JP3845616B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field-effect transistor (FET) having a metal-insulator-semiconductor (MIS) structure and a manufacturing method thereof.
[0002]
[Prior art]
Transistors have improved performance by increasing the fineness of MOS (Metal-Oxide-Semiconductor) FETs. However, as the manufacturing process has evolved, the improvement in performance due to the pursuit of fineness has begun to appear as a shadow. Transistor miniaturization is to simultaneously reduce the length and lateral size of each part of the MOSFET, such as the thickness of the gate insulating film and the gate length, but the size is approaching the atomic size. Therefore, the limit to the effect of miniaturization has begun to appear.
[0003]
For example, conventionally used SiO ₂ In the gate insulating film made of, since a tunnel current starts to flow directly when the film thickness is 2 nm or less, the gate leakage current cannot be suppressed, and problems such as an increase in power consumption cannot be avoided. For this reason, SiO ₂ Using a material with a higher dielectric constant than that (high dielectric) for the gate insulating film, ₂ While suppressing the equivalent film thickness (hereinafter also referred to as EOT (Equivalent Oxide Thickness)), it is necessary to increase the physical film thickness and suppress the leakage current.
[0004]
However, when a high dielectric gate insulating film is used, SiO ₂ Compared with the above case, there is a big problem that the characteristics of the transistor are deteriorated due to a decrease in carrier mobility due to an increase in interface state density and impurity scattering in the high dielectric film. In order to compensate for such a decrease in carrier mobility, development of a transistor using strained Si for the channel layer is underway.
[0005]
The strained Si transistor increases the carrier mobility of the channel layer by utilizing the effect that the crystal lattice of Si is distorted by being affected by the lattice spacing of another crystal in contact therewith. By forming a silicon crystal that forms the channel layer, which is the carrier movement path of the transistor, on the silicon-germanium (SiGe) layer, the Si crystal in the channel layer in contact with the SiGe layer is distorted, realizing higher carrier mobility. it can. However, to make an SGOI (SiGe on Insulator) substrate as the substrate, after depositing SiGe on the SOI (Si on Insulator) substrate, the SiGe is oxidized, the Ge is concentrated by oxidation, and then the oxide film is peeled off. It is necessary to go through a complicated process of epitaxially growing Si on the top (see, for example, Non-Patent Document 1). In addition, another method of manufacturing strained Si using SiGe is known in order to improve the mobility of a transistor by applying tensile internal stress or lattice strain to the channel layer (for example, Patent Document 1). reference).
[0006]
As described above, since the FET forming process becomes complicated and complicated, it is expected that the yield of the process is lowered and problems such as an increase in cost are caused. Further, as the strained Si layer is made thinner, the effect of scattering by Ge diffused from the SiGe layer becomes remarkable, and there is a problem that the carrier mobility is deteriorated.
[0007]
Note that in order to improve the mobility of the transistor by applying tensile internal stress or lattice distortion to the channel layer, silicon oxide or silicon nitride is used as a material for the undercoat insulating film provided under the channel layer or the gate insulating film. It is known to use (for example, refer to Patent Document 2).
[0008]
In addition, SiO on the channel layer ₂ It is known that an ultra-thin gate insulating film can be realized by epitaxially growing a single crystal Ce oxide film directly bonded to a Si substrate without forming an amorphous layer (eg, non-patent document). 2). However, this Non-Patent Document 2 does not describe that the channel layer is strained Si.
[0009]
[Non-Patent Document 1]
T. Mizuno et al., IEDM, p.934 (1999)
[Non-Patent Document 2]
Y. Nishikawa et al., Jpn. J. Appl. Phys. 41, 2480 (2002)
[Patent Document 1]
JP 2001-284558 A
[Patent Document 2]
JP 2002-176061 A
[0010]
[Problems to be solved by the invention]
As described above, now that the improvement in transistor performance due to the pursuit of fineness is beginning to appear, it is necessary to introduce a new device into the transistor structure itself like a strained Si transistor.
[0011]
However, in the method using the conventional SGOI substrate, it is expected that the FET forming process becomes complicated and complicated, resulting in a decrease in yield and problems such as an increase in cost. Further, the effect of scattering by Ge diffused from the SiGe layer becomes remarkable, and there is a problem that the carrier mobility is deteriorated.
[0012]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a field effect transistor capable of greatly improving transistor characteristics and a method for manufacturing the same.
[0013]
[Means for Solving the Problems]
A field effect transistor according to a first aspect of the present invention includes a semiconductor region formed in a substrate, a first conductivity type channel region formed in the semiconductor region, and a lattice spacing between the substrate and the substrate formed on the channel region. A gate insulating film including at least metal oxide layers made of different crystalline materials, a gate electrode formed on the gate insulating film, and a second conductivity type source formed in the semiconductor region on both sides of the gate electrode A drain region, and the lattice spacing of at least the channel region of the substrate is modulated.
[0014]
A field effect transistor according to the second aspect of the present invention is formed between a semiconductor region formed in a substrate, a first conductivity type channel region formed in the semiconductor region, and between the substrate and the channel region. An insulating film including at least a metal oxide layer made of a crystal having a lattice spacing different from that of the substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, and And a second conductivity type source / drain region formed in the semiconductor region on both sides of the gate electrode, wherein the lattice spacing of at least the channel region of the substrate is modulated.
[0015]
The metal oxide layer may be made of a rare earth oxide containing at least one kind of rare earth element.
[0016]
The metal oxide layer may contain one or more metal elements of Ce, Dy, Y, Gd, La, and Pr.
[0017]
The metal oxide layer may have a metal / oxygen composition ratio less than a stoichiometric ratio.
[0018]
The lattice spacing of the metal oxide layer may be different from the lattice spacing when the composition ratio of metal and oxygen is a stoichiometric ratio.
[0019]
A crystalline rock salt structure metal oxide may be provided between the metal oxide layer and the channel region.
[0020]
The rock salt structure metal oxide may contain one or more metal elements of Mg, Ca, Sr, and Ba.
[0021]
A field effect transistor according to the third aspect of the present invention is formed between a semiconductor region formed in a substrate, a first conductivity type channel region formed in the semiconductor region, and between the substrate and the channel region. A first insulating film including at least a first metal oxide layer made of a crystalline material having a lattice spacing different from that of the substrate; and a second insulating film formed on the channel region and made of a crystalline material having a lattice spacing different from that of the substrate. A gate insulating film including at least a metal oxide layer; a gate electrode formed on the gate insulating film; and a source / drain region of a second conductivity type formed in the semiconductor region on both sides of the gate electrode. And the lattice spacing of at least the channel region of the substrate is modulated.
[0022]
In addition, in the method for manufacturing a field effect transistor according to the fourth aspect of the present invention, an insulating film containing at least a crystalline metal oxide is formed on a substrate, and the oxygen composition ratio in the metal oxide is calculated from the stoichiometric ratio. And a step of forming a gate electrode on the insulating film and a source / drain region on the substrate on each side of the gate electrode, respectively.
[0023]
In the step of reducing the oxygen composition ratio from the stoichiometric ratio, it is preferable to perform at least one of heat treatment, laser irradiation, electron beam irradiation, and electromagnetic wave irradiation on the insulating film.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
(First embodiment)
FIG. 1 shows a cross-sectional configuration of the MISFET according to the first embodiment of the present invention. In the MISFET according to this embodiment, a channel region 5 is formed on the surface of a semiconductor substrate 1 made of Si, and a source region 11 a and a drain region 11 b having a conductivity type different from that of the channel region 5 are formed on both sides of the channel region 5. It has a configuration. A gate insulating film 7 including at least a crystalline metal oxide film is formed on the channel region 5. Since the lattice spacing of the metal oxide film constituting the gate insulating film 7 is different from Si, Si in the channel region 5 receives stress from the gate insulating film 7 and a strained Si layer is formed. A gate electrode 9 made of polysilicon is formed on the gate insulating film 7. In other words, in the present embodiment, the Si lattice spacing in the channel region 5 is configured to be different from the Si lattice spacing in the semiconductor substrate 1. Here, in the case of an n-channel MISFET, the lattice constant of the metal oxide film is made larger than that of Si, and the lattice spacing of Si in the channel layer 5 is widened by tensile stress. Thereby, the mobility of electrons in the channel layer 5 can be increased. On the other hand, in the case of a p-channel MISFET, the lattice constant of the metal oxide film is made larger or smaller than Si, and the lattice spacing of Si in the channel layer 5 is changed by tensile stress or compressive stress. Thereby, the mobility of holes in the channel layer 5 can be increased.
[0026]
Next, the manufacturing method of the MISFET according to the present embodiment will be described with reference to FIGS. 2 and 3 taking an n-channel MISFET as an example.
[0027]
First, as shown in FIG. 2A, after the element isolation region 2 is formed on the silicon substrate 1 having the (001) plane orientation, for example, SiO 50 having a thickness of 50 nm is formed. ₂ The film 4 is coated on the entire surface. Subsequently, SiO ₂ By implanting boron element ions through the film 4, a steep impurity profile is formed in the channel region 5. Subsequently, SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, dilute hydrofluoric acid treatment is performed, and the Si surface of the channel region 5 is terminated with hydrogen.
[0028]
Next, the silicon substrate 1 is introduced into an electron beam vapor deposition apparatus. The substrate temperature is set to 500 ° C., for example, and Pr ₆ O ₁₁ As a vapor deposition source ₂ O ₃ Is deposited by 5 nm to form a metal oxide film 7a (see FIG. 2B). At this time, the oxygen partial pressure is 1 × 10 ^-7 By controlling precisely to Torr, Pr ₂ O ₃ The orientation of the metal oxide film 7a made of this material was increased to improve the crystallinity. At this time, Si on the surface of the channel layer 5 is oxidized, and the channel layer 5 and Pr ₂ O ₃ Between the metal oxide films 7a made of SiO 2 having a film thickness of 0.5 nm. ₂ Layer 7b was formed. That is, the insulating film 7 has a thickness of 0.5 nm. ₂ Layer 7b and 5 nm thick Pr ₂ O ₃ It has a laminated structure composed of the layers 7a (see FIG. 2B).
[0029]
From X-ray diffraction evaluation, Pr ₂ O ₃ It was found that the layer 7a is a polycrystalline film oriented in the plane orientation (001) direction, and the lattice constant is 5.52Å (the lattice constant is 1.7% larger than Si). X-ray diffraction half-width is narrow, Pr ₂ O ₃ The layer 7a was confirmed to be a highly crystalline film strongly oriented to (001).
[0030]
Next, a polysilicon film 9 to be a gate electrode is deposited on the entire surface by using a CVD (Chemical Vapor Deposition) method (see FIG. 2C).
[0031]
Subsequently, as shown in FIG. 3A, the polysilicon film 9 and the gate insulating film 7 are patterned by using an anisotropic etching method such as RIE (Reactive Ion Etching) method, for example, on the channel region 5. A gate insulating film 7 and a gate electrode 9 are formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 7 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced.
[0032]
Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface (see FIG. 3B). Subsequently, as shown in FIG. 3C, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal film such as Al is deposited to form a metal film on the entire surface. Source / drain electrodes 15a and 15b and a gate connection portion 15c are formed to complete an n-channel MISFET.
[0033]
Next, the characteristics of the gate insulating film of the n-channel MISFET having the structure shown in FIGS. 2 and 3 will be described in detail. Usually, even if the metal oxide used as the insulating film is crystalline, the lattice constant does not affect the Si of the channel layer 5. However, this time, we are highly oriented Pr (001) and highly crystalline. ₂ O ₃ It has been found that by forming the layer 7a, tensile stress is applied to the Si of the channel layer 5 to change the lattice constant.
[0034]
FIG. 4 is an enlarged view of the insulating film 7 and the channel region 5 in the n-channel MISFET having the structure shown in FIGS. ₂ O ₃ Layer 7a, SiO ₂ 4 is a schematic diagram showing a cross-sectional structure in a layer 7b and a channel region 5. FIG. FIG. 5 shows changes in the lattice constant obtained from an electron beam diffraction image measured using a transmission electron microscope (hereinafter referred to as TEM (Transparent Electron Microscope)). What is measured here is the lattice constant in the direction parallel to the interface. The measurement point is Pr as shown in FIG. ₂ O ₃ Layer 7a, SiO ₂ Si in the vicinity of the interface between the layer 7b and the silicon substrate, Si in the silicon substrate 50 nm away from the interface, and Si in the semiconductor substrate 1 250 nm away from the interface. The change in lattice constant is shown with reference to the lattice spacing of Si 250 nm away from the interface. As can be seen from FIG. ₂ O ₃ The lattice constant of the layer 7a is increased by + 1.7% compared to the Si layer 250 nm away from the interface, and this result shows that the metal oxide Pr obtained from X-ray diffraction is obtained. ₂ O ₃ This corresponds to the lattice constant value of. Furthermore, this Pr ₂ O ₃ It was found that the Si at the interface was distorted by being pulled by the layer 7a, and the change in lattice constant was + 0.5%. Even at Si 50 nm away from the interface, the lattice constant changes, and the lattice constant increases by + 0.4%.
[0035]
From this result, it is possible to change the lattice spacing of the Si layer in the channel region 5 by using the gate insulating film 7 as the insulating film containing a metal oxide having a different lattice spacing from Si and having high crystallinity. Indicated. By increasing the crystallinity, the elastic constant of the metal oxide is increased. In other words, it is considered that the crystal is hardened qualitatively. For this reason, the lattice constant of the metal oxide has a great influence on Si, and it is considered that lattice deformation occurs even at a depth of 50 nm from the interface.
[0036]
Next, crystalline Pr having a different lattice spacing from Si according to the present embodiment. ₂ O ₃ A transistor having a gate insulating film 7 including a layer and a transistor having amorphous SiON as a gate insulating film as a comparative example were manufactured, and the characteristics of this embodiment and the comparative example were compared. FIG. 6 shows both SiO ₂ A comparative transistor having a gate insulating film made of SiON having an equivalent film thickness (EOT) of 1.5 nm, and Pr ₂ O ₃ / SiO ₂ The Id-Vg characteristic of the transistor of this embodiment which has the insulating film which has a laminated structure is shown.
[0037]
The S factor in the n-channel MISFET of the comparative example having the gate insulating film made of SiON is 92 mV / decade, and this value is SiO 2 ₂ Is considerably deteriorated as compared with a normal n-channel MOSFET having a gate insulating film as a gate insulating film. This is because nitrogen diffuses near the interface with the channel region and the interface state density increases.
[0038]
On the other hand, Pr ₂ O ₃ It can be seen that the S-factor of the n-channel MISFET of this embodiment having the gate insulating film including the layer is 75 mV / decade, which is greatly improved. In addition, it can be seen that the current driving force is also improved in this embodiment compared to the comparative example. This is because the electron mobility is improved by applying tensile strain to the Si layer of the channel layer, and further, SiO at the interface with the channel layer. ₂ This is because the interface state density can be reduced by the presence of.
[0039]
As described above, according to the present embodiment, by using an insulating film containing a metal oxide having a lattice spacing different from that of Si as a gate insulating film, tensile stress can be applied to Si in the channel region, and electron transfer By increasing the degree, the transistor characteristics can be greatly improved. Further, it is not necessary to go through complicated steps such as depositing SiGe on the SOI to generate strained Si, then oxidizing and concentrating Ge, and epitaxially growing Si thereon. Therefore, a conventional Si substrate or SOI substrate can be used as the substrate, and the cost can be greatly reduced.
[0040]
(Second Embodiment)
Next, a p-channel MISFET according to a second embodiment of the invention will be described. The p-channel MISFET according to this embodiment has substantially the same configuration as the MISFET according to the first embodiment shown in FIG. 1, but a metal having a lattice constant smaller than that of Si in order to apply compressive stress to Si of the channel layer 5. Oxide film, for example Dy ₂ O ₃ Is used. The manufacturing method is substantially the same as the method shown in FIGS. The channel layer 5 is formed by ion implantation of arsenic element. Dy ₂ O ₃ The metal oxide film 7a was formed using an electron beam evaporation method. Dy ₂ O ₃ As a vapor deposition source and metal oxide Dy ₂ O ₃ Of 5nm and Dy ₂ O ₃ A metal oxide film 7a made of is formed. At this time, the oxygen partial pressure is 1 × 10 ^-7 By controlling precisely to Torr, Dy ₂ O ₃ The crystallinity was improved by increasing the orientation of. Further, Si on the surface of the channel layer 5 is oxidized, and the channel layer 5 and Dy ₂ O ₃ Between the metal oxide film 7a made of SiO 2 having a film thickness of 0.5 nm ₂ Layer 7b is formed. That is, the insulating film 7 has a thickness of 0.5 nm of SiO. ₂ Layer 7b and Dy with a thickness of 5 nm ₂ O ₃ It has a laminated structure composed of layers 7a.
[0041]
From the X-ray diffraction evaluation, Dy ₂ O ₃ It was found that the layer 7a is a polycrystalline film oriented in the plane orientation (001) direction and has a lattice constant of 5.33 （(the lattice constant is 1.8% smaller than Si). The half width of X-ray diffraction is narrow, Dy ₂ O ₃ The layer was confirmed to be a highly crystalline film strongly oriented in the plane orientation (001). In addition, as a result of lattice constant evaluation using electron diffraction, Dy is strongly oriented in the plane orientation (001) and has high crystallinity. ₂ O ₃ By forming the layer 7a, it was confirmed that compressive stress was applied to Si of the channel layer 5 and the lattice constant was reduced. Dy ₂ O ₃ The change in the lattice constant of the layer 7a is −1.8%, and this Dy ₂ O ₃ It was found that Si at the interface was distorted accompanying the layer 7a, and the change in lattice constant was -0.5%. The lattice constant was changed even at Si 50 nm away from the interface, and the lattice constant was changed by -0.4%. From this result, it was shown that the lattice spacing of the Si layer in the channel region can be reduced by using an insulating film containing a metal oxide having a smaller lattice spacing and higher crystallinity than Si as a gate insulating film.
[0042]
Dy according to this embodiment ₂ O ₃ A transistor having the gate insulating film 7 including the layer 7a and a transistor having a gate insulating film made of amorphous SiON as a comparative example were manufactured, and the characteristics of this embodiment and the comparative example were compared. Both SiO ₂ A p-channel MISFET according to a comparative example having a gate insulating film made of SiON with an equivalent film thickness (EOT) of 1.5 nm, and Dy ₂ O ₃ / SiO ₂ When the Id-Vg characteristics of the p-channel MISFET according to the present embodiment having a gate insulating film having a laminated structure are compared, the S factor in the comparative example having the SiON gate insulating film is 120 mV / decade, and SiO 2 ₂ Compared to a normal p-channel MOSFET having a gate insulating film as a gate insulating film, it was considerably deteriorated. This is because nitrogen diffuses near the interface with the channel layer and the interface state density increases.
[0043]
On the other hand, Dy ₂ O ₃ The S-factor of the p-channel MISFET according to the present embodiment having the gate insulating film including the layer was 100 mV / decade, which was found to be greatly improved. In addition, it was confirmed that the current driving force of the present embodiment is improved as compared with the comparative example. This is because the hole mobility is improved by applying compressive stress to the Si layer of the channel layer, and further, SiO at the interface with the channel layer. ₂ This is because the interface state density can be reduced by the presence of.
[0044]
As described above, according to this embodiment, even in the p-channel MISFET, transistor characteristics can be greatly improved by using an insulating film containing a metal oxide having a lattice spacing different from that of Si as a gate insulating film. .
[0045]
In the first or second embodiment, Pr is used as the crystalline metal oxide. ₂ O ₃ Or Dy ₂ O ₃ As an example, the crystalline metal oxide is SrTiO. ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But the same effect can be obtained. Although the crystalline metal oxide is also shown in the case of a polycrystal in which the crystal orientation is oriented, it has been confirmed that a larger change in lattice constant occurs by using a single crystal metal oxide. Although the case where the electron beam evaporation method is used as the film formation method of the crystalline metal oxide is shown, other film formation methods such as a CVD method, a sputtering method, a molecular beam epitaxy (MBE) method are used as the film formation method. May be.
[0046]
Among crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one element selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film forming conditions, and can effectively change the lattice spacing of Si. Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, it is confirmed that a film having high crystallinity can be realized and a particularly high effect can be obtained. It was.
[0047]
Of the crystalline metal oxides described above, which metal oxide is selected depends on whether tensile stress or compressive stress is to be applied to Si. When an n-channel MISFET is manufactured, the mobility of electrons is improved in Si to which tensile stress is applied. Therefore, a metal oxide having a larger lattice constant than Si is selected.
[0048]
On the other hand, when a p-channel MISFET is manufactured, the mobility of holes is improved by either tensile or compressive stress, so a metal oxide having a lattice constant different from that of Si may be selected. The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be realized with a metal oxide containing only one kind of metal element, a metal oxide containing two or more kinds of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ By using this, the change in the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0049]
(Third embodiment)
Next, an n-channel MISFET according to a third embodiment of the invention will be described.
[0050]
The n-channel MISFET according to the present embodiment has substantially the same configuration as the MISFET according to the first embodiment shown in FIG. 1, but in this embodiment, in order to apply tensile stress to Si of the channel layer, the oxygen composition ratio Is a metal oxide, such as Ce oxide, which is less than the stoichiometric ratio. The manufacturing method of the n-channel MISFET in this embodiment is almost the same as the method shown in FIGS. As the substrate, Si having a (111) plane orientation is used, and the channel region is formed by ion implantation of boron element. The Ce oxide is formed using the MBE method. The Si surface of the channel region is subjected to dilute hydrofluoric acid treatment and terminated with hydrogen, and then the substrate is introduced into the MBE apparatus. The substrate temperature is set to 700 ° C., for example, and Ce is monolayer-deposited using metal Ce as an evaporation source. ₃ Alternatively, an oxygen gas is supplied to form an insulating film made of Ce oxide with a thickness of 5 nm. The oxygen partial pressure during film formation is 1 × 10 ^-8 Torr. By using such a film formation method, SiO ₂ A single crystal Ce oxide film that is directly bonded to Si and oriented in the plane orientation (111) can be epitaxially grown without forming an amorphous layer. The present inventors have already reported that an ultrathin gate insulating film can be realized using this method (Y. Nishikawa et al., Jpn. J. Appl. Phys. 41, 2480 (2002)). In addition, this document does not describe that Si is distorted, and it has become clear that Si is distorted by subsequent knowledge of the present inventors.
[0051]
Next, the characteristics of the gate insulating film of the n-channel MISFET according to the third embodiment will be described in detail. FIG. 7 is an enlarged view of the gate insulating film 8 made of Ce oxide and the channel region, and is a schematic diagram of a cross-sectional structure of the Ce oxide layer 8 and the channel region 5 made of silicon. FIG. 8 shows a change in lattice constant obtained from an electron beam diffraction image measured using TEM. What is measured here is the lattice constant in the direction parallel to the interface. As shown in FIG. 7, the measurement points are the gate insulating film 8 made of Ce oxide, Si near the Ce oxide / Si interface, Si 50 nm away from the interface, and Si 250 nm away from the interface. The change in lattice constant is shown with reference to the lattice spacing of Si 250 nm away from the interface. The lattice constant of Ce oxide is about + 0.8% larger than Si. Further, the Si at the interface is distorted by + 0.75%. Further, it was found that the lattice constant also changed in Si 50 nm away from the interface, which was a large value of + 0.65%. CeO ₂ Is directly bonded to Si, and the difference in lattice constant more directly affects the Si layer. Therefore, the Si layer is greatly strained, and the change in lattice constant is CeO. ₂ It can be seen that it is as large as layer 8.
[0052]
CeO, a bulk Ce oxide ₂ The lattice constant of is reported to be 5.411Å. That is, CeO compared to the lattice constant of Si (5.430 Å). ₂ The lattice constant of should be small. However, the results of our experiments show that the previous CeO ₂ It was found that the lattice constant of the Ce oxide was larger than that of Si, as shown in FIG. As a result of detailed studies on these causes, new findings have been obtained that the lattice constant changes as the oxygen composition ratio in the Ce oxide changes.
[0053]
FIG. 9 shows Ce oxide (CeO _x ) Shows the relationship between the oxygen composition ratio and the lattice constant. The oxygen composition ratio was measured by energy dispersive X-ray fluorescence (EDX). When the oxygen composition ratio is stoichiometric (x = 2.0), the lattice constant is 5.411Å, and the conventional Ce oxide (CeO ₂ ) Is consistent with the reported lattice constant. On the other hand, it was found that the lattice constant increases when the oxygen composition ratio is smaller than the stoichiometric ratio and x <2.0. As described above, it is considered that the lattice constant of Ce oxide greatly changes depending on the oxygen composition ratio because Ce oxide is a crystal having a strong ionic bond.
[0054]
10A and 10B are schematic diagrams of oxygen vacancies in Ce oxide. When the oxygen at the lattice position in the crystal is released, the lattice position of the Ce atom bonded to the released oxygen is displaced from the original lattice position by being pulled by the bond with other oxygen. As a result, it is considered that the average distance between the lattices increases and the lattice constant increases.
[0055]
The lattice constant of the Ce oxide shown in this embodiment is + 0.8% compared to Si, and it was found from the characteristic graph of FIG. 9 that the oxygen composition ratio is 1.77. The oxygen composition ratio decreases because the oxygen partial pressure during MBE film formation is 1 × 10. ^-8 This is because it is set low as Torr. By controlling the oxygen partial pressure, the oxygen composition ratio of the Ce oxide can be changed, and the oxygen partial pressure is reduced to 1 × 10. ^-7 When it was set to Torr, the oxygen composition ratio was 1.89.
[0056]
Next, the characteristics of an n-channel MISFET having a crystalline Ce oxide film having a lattice spacing different from that of Si as a gate insulating film and an n-channel MISFET having a gate insulating film made of amorphous SiON were compared. FIG. 11 shows SiO ₂ Converted film thickness (EOT) is 1 nm, SiON, and Ce oxides with different oxygen composition ratios (CeO _1.77 , CeO _1.89 , CeO _2.00 ) Shows an Id-Vg characteristic of an n-channel MISFET having a gate insulating film as a gate insulating film.
[0057]
The S-factor of the n-channel MISFET having a gate insulating film made of amorphous SiON is 92 mV / decade, and SiO 2 ₂ This is worse than in the case of a normal n-channel MISFET using a gate insulating film made of This is because nitrogen has diffused at the interface with the channel region and the interface state density has increased.
[0058]
When attention is paid to Ce oxide, it can be seen that as the oxygen composition ratio becomes smaller, the S factor becomes smaller and the current driving ability is further improved. When the oxygen composition ratio is the stoichiometric ratio x = 2.0, the S factor is 120 mV / decade, which is further deteriorated as compared with the case of SiON. This is presumably because the electron mobility is lowered due to impurity scattering in the Ce oxide (for example, diffusion of boron from the gate electrode). However, the S factor decreases with a decrease in the oxygen composition ratio, and is improved to 61 mV / decade at x = 1.77. This is because as the oxygen composition ratio decreases, the lattice spacing of Ce oxide increases, so that the lattice spacing of Si in the channel also increases, and the electron mobility is improved. It is considered that this is because the decrease in electron mobility due to impurity scattering in Ce oxide is compensated and the improvement in electron mobility due to the effect of strain contributes more.
[0059]
As a crystalline metal oxide, CeO ₂ As described above, the same effect can be obtained if the crystal has a high ion binding property. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But you can.
[0060]
Although the crystalline Ce oxide is shown as a single crystal, the same effect can be obtained in the case of a polycrystal with oriented crystal orientation. Although the case where the MBE method is used as the film formation method for the crystalline metal oxide is shown, other film formation methods such as a CVD method, a sputtering method, and an electron beam evaporation method may be used. Among crystalline metal oxides, rare earth elements having strong ion bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, More preferably, a rare earth oxide containing at least one element selected from Yb, Lu) is used. Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, it is confirmed that precise control of the oxygen composition ratio can be realized and a particularly high effect can be obtained. It was done.
[0061]
In the first and second embodiments, a MISFET is formed on a silicon substrate having a plane orientation of (001) and in the third embodiment on a silicon substrate having a plane orientation of (111). Any of (001) and (111) may be used. Further, the silicon substrate on which the MISFET is formed may have a surface orientation of (110) or may be slightly deviated from the above surface orientation.
[0062]
(Fourth embodiment)
Next, a p-channel MISFET according to a fourth embodiment of the invention will be described. The p-channel MISFET according to the present embodiment has substantially the same configuration as that of the MISFET according to the second embodiment. However, in this embodiment, in order to distort Si in the channel layer more effectively, crystalline metal oxidation is performed. A metal oxide having a rock salt structure is sandwiched between the object and the channel layer. The manufacturing method is almost the same as the method shown in FIGS.
[0063]
The channel region is formed by ion implantation of arsenic element. SrO as the rock salt structure metal oxide, Dy as the metal oxide film ₂ O ₃ These two types of metal oxides were formed by the MBE method. The Si surface of the channel region is subjected to dilute hydrofluoric acid treatment and terminated with hydrogen, and then the substrate is introduced into the MBE apparatus. The substrate temperature is set to 300 ° C., for example, and Sr is deposited in two atomic layers using metal Sr as an evaporation source, and then oxygen gas is supplied to form an SrO layer.
[0064]
Next, for example, the substrate temperature is set to 700 ° C., and metal Dy and oxygen gas are supplied. ₂ O ₃ A layer is formed to 5 nm. The oxygen partial pressure during film formation is 1 × 10 ^-7 Torr. By depositing SrO on Si in two atomic layers, SiO as shown in the second embodiment is obtained. ₂ Dy without layer formation ₂ O ₃ A layer was formed. This is because SrO prevents oxygen diffusion. That is, the insulating film is composed of the SrO layer 2 atomic layer and the Dy ₂ O ₃ It has a laminated structure composed of 5 nm layers. Dy formed in this way ₂ O ₃ It was confirmed from the X-ray diffraction evaluation that the orientation of the film was high and the crystallinity was good. Dy ₂ O ₃ It was found that the layer was a polycrystalline film oriented in the plane orientation (001) direction and the lattice constant was 5.33 （(the lattice constant is 1.8% smaller than Si).
[0065]
As a result of lattice constant evaluation using electron diffraction, it was confirmed that compressive stress was applied to Si of the channel layer and the lattice constant was reduced. Dy ₂ O ₃ It was found that the change in the lattice constant of -1.8% and the change in the lattice constant of Si near the interface was -0.8%. The lattice constant was changed even in Si 50 nm away from the interface, and the lattice constant was changed by -0.7%. The amount of change in the lattice constant of Si is increased to about twice that of the second embodiment in which no SrO layer is used. Amorphous SiO ₂ Since no layer was formed, the difference in lattice spacing in the metal oxide film was directly added to the Si layer, and the lattice constant of SrO was 5.12Å ₂ O ₃ This is because the effect of applying the compressive stress is further increased because the size is even smaller than the above. Here, although the thickness of the SrO layer is a diatomic layer, it has been found that the thickness of the SrO layer is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, when the thickness is further increased, the crystallinity changes with time and the characteristics deteriorate. On the other hand, if it is thinner than one atomic layer, the effect of suppressing the diffusion of oxygen cannot be obtained, and SiO 2 ₂ This is because a layer is generated.
[0066]
SrO layer and Dy as described above ₂ O ₃ The characteristics of a transistor having a gate insulating film including a layer and a transistor having amorphous SiON as a gate insulating film were compared. Both SiO ₂ A gate insulating film made of SiON having a converted film thickness (EOT) of 1.5 nm, and Dy ₂ O ₃ When comparing Id-Vg characteristics of p-channel MISFETs each having a gate insulating film having a / SrO stacked structure, the S factor in the gate insulating film made of SiON is 120 mV / decade, and SiO 2 ₂ Compared to that of a normal p-channel MOSFET having a gate insulating film as a gate insulating film, it is considerably deteriorated. This is because nitrogen diffuses near the interface with the channel layer and the interface state density increases.
[0067]
On the other hand, Dy ₂ O ₃ The p-channel MISFET having the gate insulating film including the / SrO layer according to the present embodiment has an S factor of 90 mV / decade, which is found to be greatly improved. In addition, it was confirmed that the current driving force of the present embodiment is improved as compared with the case of SiON. This is because the hole mobility is further improved by applying a large compressive stress to the Si layer of the channel layer.
[0068]
As described above, according to the present embodiment, it has been clarified that the effect of using a metal oxide having a lattice interval different from that of Si is further increased by inserting a metal oxide having a rock salt structure.
[0069]
In addition, although the case where SrO was used was shown in this embodiment, you may use the metal oxide with another rock salt structure. In particular, when a metal oxide film having a rock salt structure of SrO, MgO, CaO, or BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be greatly improved.
[0070]
When applying tensile stress to Si, it is desirable to use BaO, which is a metal oxide having a rock salt structure having a lattice constant larger than that of Si. In addition, when it is desired to apply compressive stress to Si, it is desirable to use SrO, MgO, and CaO, which are metal oxides having a rock salt structure having a lattice constant smaller than that of Si. However, the change in the lattice constant in the Si layer is mainly determined by the crystalline metal oxide having a large film thickness formed on the Si layer, and for example, sandwiching SrO having a lattice constant smaller than that of Si. Pr having a larger lattice constant than Si ₂ O ₃ In the structure in which Si is laminated, Si in the channel region is subjected to tensile stress, so that a metal oxide having a rock salt structure and a crystalline metal oxide can be arbitrarily combined.
[0071]
(Fifth embodiment)
FIG. 12 shows a cross-sectional configuration of the MISFET according to the fifth embodiment of the present invention. In the MISFET according to this embodiment, an insulating film 3 including at least a crystalline metal oxide having a lattice interval different from that of Si is embedded in a semiconductor substrate 1 made of Si. A channel region 5 is formed in the semiconductor substrate 1, and a source region 11 a and a drain region 11 b having a conductivity type different from that of the channel region 5 are formed in the semiconductor substrate 1 on both sides of the channel region 5. A gate insulating film 7 is formed on the channel region 5. Si in the channel region 5 is subjected to stress from the metal oxide to form a strained Si layer. A gate electrode 9 made of polysilicon is formed on the gate insulating film 7.
[0072]
When the MISFET according to the present embodiment is an n-channel MISFET, the lattice constant of the insulating film 3 made of a metal oxide is made larger than Si, and the lattice spacing of Si in the channel layer 5 is widened by tensile stress. Thereby, the mobility of electrons in the channel layer can be increased. On the other hand, when the MISFET according to the present embodiment is a p-channel MISFET, the lattice constant of the metal oxide is made larger or smaller than Si, and the lattice spacing of Si in the channel layer is changed by tensile stress or compressive stress. . Thereby, the mobility of holes in the channel layer can be increased.
[0073]
Next, the method for fabricating the n-channel MISFET according to the present embodiment will be explained with reference to FIGS.
[0074]
First, dilute hydrofluoric acid treatment is performed on the surface of the silicon substrate 1 having the (001) plane orientation, and the surface of the silicon substrate 1 is terminated with hydrogen. Subsequently, as shown in FIG. 13A, the silicon substrate 1 is introduced into a sputtering apparatus, the substrate temperature is set to, for example, 600 ° C., and La ₂ O ₃ As a vapor deposition source on the silicon substrate 1 with metal oxide La ₂ O ₃ Of 10 nm is deposited to form the insulating film 3. At this time, the oxygen partial pressure is 5 × 10 ^-7 By precisely controlling Torr, La ₂ O ₃ The crystallinity was improved by increasing the orientation of. In addition, Si on the surface of the silicon substrate 1 is oxidized to form the silicon substrate 1 and the metal oxide La. ₂ O ₃ Between the insulating films 3a made of SiO 2 having a film thickness of 2 nm ₂ Layer 3b was formed. From X-ray diffraction evaluation, La ₂ O ₃ The layer 3a is a polycrystalline film oriented in the (001) direction, has a lattice constant of 5.70, and is found to be 5.0% larger than that of Si. The half width of X-ray diffraction is narrow, La ₂ O ₃ It was confirmed that the layer 3a is a highly crystalline film strongly oriented in the plane orientation (001).
[0075]
Next, a channel layer 5 made of Si having a thickness of 100 nm is formed by CVD (see FIG. 13B). At this time, the metal oxide La ₂ O ₃ Between the insulating film 3a and the channel layer 5 made of SiO 2 having a film thickness of 1 nm ₂ Layer 3c was formed. That is, the insulating film 3 is made of SiO 2 having a thickness of 2 nm. ₂ Layer 3b, La with a film thickness of 10 nm ₂ O ₃ Layer 3a, 1 nm thick SiO ₂ It has a laminated structure composed of the layers 3c.
[0076]
Next, element isolation regions 2 are formed on both sides of the channel layer 5, and then, for example, SiO 50 having a thickness of 50 nm is formed. ₂ The film 4 is coated on the entire surface. Subsequently, SiO ₂ By implanting boron element ions through the film 4, a steep impurity profile is formed in the channel layer 5 (see FIG. 13C). Then SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, the silicon surface of the channel layer 5 is treated with dilute hydrofluoric acid and terminated with hydrogen.
[0077]
Next, by performing thermal oxidation, SiO ₂ A gate insulating film 7 made of, for example, 3 nm is formed. Subsequently, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by CVD (see FIG. 13D).
[0078]
Subsequently, as shown in FIG. 14A, the polysilicon film 9 and the gate insulating film 7 are patterned by using, for example, an anisotropic etching method such as RIE, and the gate insulating film 7 and the channel layer 5 are formed. A gate electrode 9 is formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 9 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced (see FIG. 14A).
[0079]
Next, SiO is formed by CVD. ₂ An interlayer insulating film 13 made of is deposited on the entire surface (see FIG. 14B). Subsequently, as shown in FIG. 14C, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode, and a metal film such as Al is deposited to form a metal film on the entire surface. Source / drain electrodes 15a and 15b and a gate electrode 15c are formed to complete an n-channel MISFET (see FIG. 14C).
[0080]
Next, the characteristics of the channel layer 5 of the n-channel MISFET having the structure shown in FIGS. 13 and 14 will be described in detail. FIG. 15 shows SiO ₂ Layer 3b / La ₂ O ₃ Layer 3a / SiO ₂ It is the enlarged view of the insulating film 3 which consists of the laminated structure of the layer 3c, and the channel layer 5, and shows a cross-sectional structure typically. FIG. 16 shows changes in the lattice constant obtained from an electron beam diffraction image measured using a TEM. What is measured here is the lattice constant in the direction parallel to the interface. As shown in FIG. ₂ A Si layer at a position 250 nm away from the interface between the layer 3b and the Si substrate 1, La ₂ O ₃ Layer 3a, Si channel layer 5 and SiO ₂ The Si layer near the interface with the layer 3c, the Si layer located 50 nm away from this interface, and the Si layer located 100 nm away from this interface (SiO 2 ₂ Si near the interface between the gate insulating film 7 and the channel layer 5).
[0081]
FIG. 16 shows SiO ₂ The change in lattice constant is shown with reference to the lattice spacing of Si at a position 250 nm away from the interface between the layer 3 b and the Si substrate 1. La ₂ O ₃ The lattice constant of the layer 3a is increased by 5.0% compared to the reference Si layer. This result shows that the metal oxide La obtained from X-ray diffraction ₂ O ₃ This corresponds to the lattice constant value of. Channel layer 5 and SiO ₂ Si of the channel layer 5 in the vicinity of the interface with the layer 3c is La ₂ O ₃ There is + 1.0% distortion associated with layer 3a. Furthermore, it was found that the lattice constant also changed in Si at a position 50 nm away from this interface, and was distorted by + 0.8%. Further, the channel layer 5 (ie, SiO 2) located 100 nm away from this interface. ₂ It was confirmed that even Si in Si near the interface between the gate insulating film 7 and the channel layer 5 was distorted by + 0.6%. From this result, it was shown that the lattice spacing of the Si layer in the channel region 5 can be increased by embedding an insulating film containing a metal oxide having a larger lattice spacing and higher crystallinity than Si in the substrate.
[0082]
According to the present embodiment, crystalline La having different lattice spacing from Si ₂ O ₃ The characteristics of the transistor in which the insulating film including the layer is embedded in the silicon substrate 1 and the strained SGOI transistor as a comparative example are compared. FIG. 17 shows a cross-sectional structure of a strained SGOI transistor which is a comparative example manufactured by a known method. In this strained SGOI transistor, in order to produce strained Si, a SiGe layer 104 is deposited on an SOI substrate including a silicon substrate 101, a SiGe layer 102, an insulating film 103, and a silicon layer (not shown), and then oxidized to form Ge. Concentrate. By this concentration, SiO generated on the SiGe layer 104 enriched with Ge is obtained. ₂ A complicated process of peeling the film and then epitaxially growing the Si layer 105 on the SiGe layer 104 is required. Thereby, the Si layer 105 becomes strained Si. SiO on the Si layer 105 ₂ A gate insulating film 107 and a gate electrode 108 are formed, and impurities are introduced into the Si layer 105 and the SiGe layer 104 on both sides of the gate electrode 108, thereby forming a source region 109a and a drain region 109b.
[0083]
On the other hand, in the method according to the present embodiment, a Si substrate can be used as the substrate, and the cost can be greatly reduced. FIG. 18 shows both cases of 3 nm SiO. ₂ An n-channel MISFET according to a comparative example having an SGOI structure having a gate insulating film, and La ₂ O ₃ The Id-Vg characteristics of the n-channel MISFET according to the present embodiment manufactured by embedding layers are compared.
[0084]
The S factor in the n-channel MISFET according to the comparative example having the strained SGOI structure is 75 mV / decade.
[0085]
In contrast, La ₂ O ₃ The S-factor of the n-channel MISFET according to the present embodiment in which the layer was embedded was 70 mV / decade, and it was confirmed that there was no inferiority as compared with the comparative example having the strained SGOI structure. Moreover, it turns out that this embodiment is improving also the current drive force compared with the comparative example. This makes it possible to apply sufficient tensile strain to the Si layer of the channel layer, improving the electron mobility, and avoiding the decrease in mobility due to Ge diffusion, which is observed when an SGOI substrate is used. It depends on what was done.
[0086]
As described above in detail, according to the present embodiment, a tensile stress can be applied to Si in the channel region by embedding an insulating film containing a metal oxide having a lattice spacing different from that of Si in the substrate. Further, according to the present embodiment, the transistor characteristics can be improved by increasing the electron mobility without going through a complicated process using a conventional strained SGOI.
[0087]
In the fifth embodiment, La is used as the crystalline metal oxide constituting the insulating film 3a. ₂ O ₃ As an example, the crystalline metal oxide is SrTiO. ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But the same effect can be obtained. Although the crystalline metal oxide is also shown in the case of a polycrystal in which the crystal orientation is oriented, it has been confirmed that a larger change in lattice constant occurs by using a single crystal metal oxide.
[0088]
In addition, although the case where the sputtering method is used as the film formation method for the crystalline metal oxide is shown, other film formation methods such as a CVD method, an electron beam evaporation method, and an MBE method may be used. .
[0089]
Among crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one element selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film forming conditions, and can effectively change the lattice spacing of Si. Among them, it was confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd was used, a film having high crystallinity could be realized and a particularly high effect was obtained. .
[0090]
In the fifth embodiment, the case of the n-channel MISFET has been described, but the p-channel MISFET can also be implemented by the same method. Of the crystalline metal oxides described above, which metal oxide is selected depends on whether tensile stress or compressive stress is to be applied to Si. When an n-channel MISFET is manufactured, the mobility of electrons is improved in Si to which tensile stress is applied. Therefore, a metal oxide having a larger lattice constant than Si is selected. On the other hand, when a p-channel MISFET is manufactured, the mobility of holes is improved by either tensile or compressive stress, so a metal oxide having a lattice constant different from that of Si may be selected.
[0091]
The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be realized with a metal oxide containing only one kind of metal element, a metal oxide containing two or more kinds of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ By using this, the change in the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0092]
(Sixth embodiment)
Next, an n-channel MISFET according to a sixth embodiment of the invention will be described. The n-channel MISFET according to the present embodiment has the same configuration as that of the n-channel MISFET according to the fifth embodiment shown in FIG. 12, but in this embodiment, in order to apply tensile stress to Si of the channel layer, insulation is performed. As the film 3, a metal oxide having a composition ratio of metal and oxygen smaller than the stoichiometric ratio, for example, Ce oxide is embedded in the substrate.
[0093]
The manufacturing method of the n-channel MISFET in this embodiment is almost the same as the method shown in FIGS. 13 and 14, but a silicon substrate having a (111) plane orientation is used as the substrate. The Ce oxide is formed using the MBE method. The Si surface of the substrate is treated with dilute hydrofluoric acid and terminated with hydrogen, and then introduced into the MBE apparatus. The substrate temperature is set to 700 ° C., for example, and Ce is monolayer-deposited using metal Ce as an evaporation source. ₃ Alternatively, oxygen gas is supplied to form an insulating film made of Ce oxide with a thickness of 5 nm. The oxygen partial pressure during film formation is 1 × 10 ^-8 Torr. By using such a film formation method, SiO ₂ A single crystal Ce oxide film that is directly bonded to Si and oriented in the (111) direction can be epitaxially grown without forming an amorphous layer. Thereafter, the same process as shown in FIGS. 13B to 14B is performed to complete the n-channel MISFET.
[0094]
According to the above method, the composition ratio of the metal and oxygen of the Ce oxide formed was 1.77, and the lattice constant was + 0.8% compared to Si. As described in the third embodiment, the oxygen composition ratio of the Ce oxide decreases because the oxygen partial pressure during MBE film formation is 1 × 10. ^-8 This is because it is set low as Torr. By controlling the oxygen partial pressure, the composition ratio between the metal and oxygen of the Ce oxide can be changed. ^-7 When it is set to Torr, the composition ratio is 1.89, and the change in lattice constant is almost 0%. The strain in the Si channel layer formed on the Ce oxide having the composition ratio x = 1.77 was + 0.75%. The strain in the Si channel layer formed on the Ce oxide having the composition ratio x = 1.89 was almost 0%.
The characteristics of a transistor in which a crystalline Ce oxide having a lattice spacing different from that of Si according to the present embodiment is embedded in a Si substrate and a strained SGOI transistor as a comparative example will be compared.
[0095]
FIG. 19 shows both cases of 3 nm SiO. ₂ An SGOI structure n-channel MISFET having a gate insulating film and a Ce oxide (CeO having a different composition ratio) _1.77 , CeO _1.89 , CeO _2.00 ) Are compared to compare the Id-Vg characteristics of n-channel MISFETs. The S factor in a strained SGOI n-channel MISFET is 75 mV / decade. When attention is paid to Ce oxide, it can be seen that as the composition ratio of metal and oxygen becomes smaller, the S factor becomes smaller and the current driving force is further improved. When the composition ratio of the metal and oxygen is the stoichiometric ratio x = 2.0, the S factor is deteriorated to 120 mV / decade. At this time, the lattice constant of Ce oxide is smaller than that of Si, and compressive strain is applied to Si of the channel layer. Therefore, the mobility of electrons decreases and the S factor deteriorates. As the composition ratio decreases, the S factor improves, and when x = 1.77, the S factor decreases to 61 mV / decade. This is because, as the composition ratio of metal and oxygen decreases, the lattice spacing of Ce oxide increases, so that the lattice spacing of Si in the channel also increases, and the electron mobility is improved. It was confirmed that the S-factor of the n-channel MISFET embedded with Ce oxide having a composition ratio x = 1.77 was not only inferior but improved compared to the strained SGOI. Further, it can be seen that the current driving force is also improved as compared with the strain SGOI. This makes it possible to apply sufficient tensile strain to the Si layer of the channel layer, improving the electron mobility, and avoiding the decrease in mobility due to Ge diffusion, which is observed when an SGOI substrate is used. It depends on what was done.
[0096]
As a crystalline metal oxide, CeO ₂ As described above, the same effect can be obtained if the crystal has a high ion binding property. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl2O with spinel structure ₄ But you can. Although the crystalline Ce oxide is shown as a single crystal, the same effect can be obtained in the case of a polycrystal with oriented crystal orientation.
[0097]
In this embodiment, the case where the MBE method is used as the film formation method for the crystalline metal oxide is shown. However, the film formation method may be another film formation method such as a CVD method, a sputtering method, or an electron beam evaporation method. A method may be used. Among crystalline metal oxides, rare earth elements having strong ion bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, More preferably, a rare earth oxide containing at least one element selected from Yb, Lu) is used. Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the composition ratio of metal to oxygen can be realized, and a particularly high effect can be obtained. It was confirmed.
[0098]
In the fifth embodiment, a MISFET is formed on a Si substrate having a plane orientation of (001) and in the sixth embodiment on a silicon substrate having a plane orientation of (111). The plane orientation is (001), Any of (111) may be sufficient. Further, the silicon substrate on which the MISFET is formed may have a surface orientation of (110) or may be slightly deviated from the above surface orientation.
[0099]
Furthermore, in the fifth and sixth embodiments, it is also effective to sandwich a metal salt having a rock salt structure between the crystalline metal oxide and the channel layer in order to more effectively distort the Si of the channel layer. There is. The effect is the same as that described in detail in the fourth embodiment, and amorphous SiO is formed at the interface with the crystalline oxide by sandwiching the metal oxide having a rock salt structure. ₂ Since no layer is formed, the difference in lattice spacing in the metal oxide film is more directly added to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, when the thickness is further increased, the crystallinity changes with time and the characteristics deteriorate. On the other hand, if it is thinner than one atomic layer, the effect of suppressing the diffusion of oxygen cannot be obtained, and amorphous SiO ₂ This is because a layer is generated. Among the oxides of rock salt structure, especially when the metal oxide film of rock salt structure of SrO, MgO, CaO, BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be greatly improved. It is.
[0100]
In addition, when applying tensile stress to Si, it is desirable to use BaO which is a metal oxide having a rock salt structure having a lattice constant larger than that of Si. In addition, when it is desired to apply compressive stress to Si, it is desirable to use SrO, MgO, and CaO, which are metal oxides having a rock salt structure having a lattice constant smaller than that of Si. However, the change in the lattice constant in the Si layer is mainly determined by a crystalline metal oxide having a large film thickness. For example, SrO having a lattice constant smaller than that of Si is sandwiched, and the lattice constant is larger than that of Si. Big Pr ₂ O ₃ In the structure in which Si is laminated, Si in the channel region is subjected to tensile stress, so that a metal oxide having a rock salt structure and a crystalline metal oxide can be arbitrarily combined.
[0101]
(Seventh embodiment)
FIG. 20 shows a cross-sectional configuration of the MISFET according to the seventh embodiment of the present invention. In the MISFET according to this embodiment, an insulating film 3 containing crystalline metal oxide having a lattice spacing different from that of Si is embedded in a semiconductor substrate 1 made of Si. A channel region 5 is formed in the semiconductor substrate 1, and a source region 11 a and a drain region 11 b having a conductivity type different from that of the channel region 5 are formed in the semiconductor substrate 1 on both sides of the channel region 5. A gate insulating film 7 including at least a crystalline metal oxide having a lattice spacing different from that of Si is formed on the channel region 5. The channel region 5 receives stress from the metal oxide contained in the insulating film 3 and the metal oxide contained in the gate insulating film 7 to form a strained Si layer. A gate electrode 9 made of polysilicon is formed on the gate insulating film 7.
[0102]
Next, the method for fabricating the p-channel MISFET according to the present embodiment will be explained with reference to FIGS. First, dilute hydrofluoric acid treatment is performed on the surface of the Si substrate 1 having the (001) plane orientation, and the surface of the Si substrate 1 is terminated with hydrogen. Subsequently, the Si substrate 1 is introduced into an electron beam vapor deposition apparatus, and the substrate temperature is set to 700 ° C., for example. ₂ O ₃ Metal oxide Y on Si substrate 1 using as a deposition source ₂ O ₃ Was deposited to 10 nm, and the metal oxide Y was deposited. ₂ O ₃ An insulating film 3 containing is formed. At this time, the oxygen partial pressure is 5 × 10 ^-7 By precisely controlling Torr, Y ₂ O ₃ The orientation of the layer 3a was increased and the crystallinity was improved. Further, Si on the surface of the Si substrate 1 is oxidized, and the Si substrate 1 and the metal oxide Y ₂ O ₃ Between the layer 3a, a 1 nm-thickness SiO ₂ A layer 3b was formed (see FIG. 21A). From X-ray diffraction evaluation, Y ₂ O ₃ It was found that the layer 3a is a polycrystalline film oriented in the plane orientation (001) direction and has a lattice constant of 5.30 （(the lattice constant is 2.4% smaller than Si). X-ray diffraction half-width is narrow, Y ₂ O ₃ It was confirmed that the layer 3a is a highly crystalline film strongly oriented in the plane orientation (001).
[0103]
Next, a Si channel layer 5 having a thickness of 100 nm is formed by CVD (see FIG. 21B). At this time, the metal oxide Y ₂ O ₃ Between the layer 3a and the channel layer 5, a 1 nm-thickness SiO ₂ Layer 3c was formed. That is, the insulating film 3 is made of SiO having a thickness of 1 nm. ₂ Layer 3b, Y with a thickness of 10 nm ₂ O ₃ Layer 3a, 1 nm thick SiO ₂ A layered structure composed of the layers 3c is formed (see FIG. 21B).
[0104]
Next, element isolation regions 2 are formed on both sides of the channel layer 5, and then, for example, a 50 nm-thickness SiO2 film is formed. ₂ The film 4 is coated on the entire surface. Subsequently, SiO ₂ By implanting boron element ions through the film 4, a steep impurity profile is formed in the channel layer 5 (see FIG. 21C). Then SiO ₂ After the film 4 is etched away with an ammonia fluoride solution, the Si surface of the channel layer 5 is treated with dilute hydrofluoric acid and terminated with hydrogen.
[0105]
Next, the Si substrate 1 is introduced into an electron beam vapor deposition apparatus, and the substrate temperature is set to 700 ° C., for example. ₂ O ₃ Is used as a deposition source to form metal oxide Y on the channel layer 5 ₂ O ₃ Is deposited by 10 nm to form the gate insulating film 7. At this time, the oxygen partial pressure is 5 × 10 ^-7 By precisely controlling Torr, Y ₂ O ₃ The orientation of the layer 7a was increased to improve the crystallinity. From X-ray diffraction evaluation, Y ₂ O ₃ It was found that the layer 7a is a polycrystalline film oriented in the plane orientation (001) direction and has a lattice constant of 5.30 （(the lattice constant is 2.4% smaller than Si). X-ray diffraction half-width is narrow, Y ₂ O ₃ The layer 7a was confirmed to be a highly crystalline film strongly oriented in the plane orientation (001). At this time, the metal oxide La contained in the gate insulating film 12 ₂ O ₃ Between the layer 7a and the channel layer 5, a 1 nm-thick SiO 2 film is formed. ₂ Layer 7b was formed. That is, the gate insulating film 7 is made of 1 nm thick SiO. ₂ Layer 7b and 10 nm thick La ₂ O ₃ A layered structure composed of the layers 7a is formed (see FIG. 21D).
[0106]
Next, a polysilicon film 9 to be a gate electrode is deposited on the entire surface by CVD (see FIG. 22A). Subsequently, as shown in FIG. 22B, the polysilicon film 9 and the gate insulating film 7 are patterned by using, for example, an anisotropic etching method such as RIE, and the gate insulating film 7 and the channel layer 5 are formed. A gate electrode 9 is formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 9 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced.
[0107]
Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface (see FIG. 23A). Subsequently, as shown in FIG. 23B, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal film such as Al is deposited to form a metal film on the entire surface. Source / drain electrodes 15a and 15b and a gate connection portion 15c are formed to complete a p-channel MISFET.
[0108]
Next, the characteristics of the channel layer of the p-channel MISFET according to this embodiment having the structure shown in FIGS. 21 to 23 will be described in detail. FIG. 24 shows SiO ₂ Layer 3c / Y ₂ O ₃ Layer 3a / SiO ₂ Insulating film 3 having a laminated structure of layer 3b, channel layer 5, Y ₂ O ₃ Layer 7a / SiO ₂ It is an enlarged view of the gate insulating film 7 which consists of a laminated structure of the layer 7b, and shows a cross-sectional structure typically. FIG. 25 shows changes in lattice constants obtained from electron diffraction images measured using TEM. What is measured here is the lattice constant in the direction parallel to the interface. As shown in FIG. ₂ Si at a position 250 nm away from the interface between the layer 3b and the Si substrate 1, Y in the insulating film 3 ₂ O ₃ Layer 3a, Si channel layer 5 and SiO ₂ Si channel layer near the interface with the layer 7b, Si channel layer at a position 50 nm away from this interface, Si channel layer at a position 100 nm away from this interface (Si near the interface of the gate insulating film 7 / Si channel layer 5), Y in the gate insulating film 7 ₂ O ₃ Layer 7a. SiO ₂ The change in lattice constant is shown with reference to the lattice spacing of Si at a position 250 nm away from the interface between the layer 3 b and the Si substrate 1. Y in insulating film 3 ₂ O ₃ The change in the lattice constant of the layer 3a is -2.4%, which is consistent with the result obtained from X-ray diffraction. Si channel layer 5 and SiO ₂ Si in the channel layer 5 in the vicinity of the interface with the layer 7b is Y ₂ O ₃ Associated with layer 7a is -1.0% distortion. Furthermore, the lattice constant also changes by -1.0% in the Si layer located 50 nm away from this interface. It was also confirmed that Si in the channel layer (Si near the interface between the gate insulating film 7 and the Si channel layer 5) located 100 nm away from this interface was also distorted by -1.0%. Y in the gate insulating film 7 ₂ O ₃ The change in the lattice constant of the layer 7a is also -2.4%, which is consistent with the result obtained from X-ray diffraction. The major feature here is that an insulating film 3 containing a crystalline metal oxide having a lattice spacing different from that of Si is embedded in the Si substrate 1, and further, a crystalline metal oxide having a lattice spacing different from that of Si. By using the gate insulating film 7 containing, it is possible to apply uniform strain to Si of the channel layer 5. That is, Si in the channel layer is similarly stressed by two crystalline metal oxides provided on the upper and lower sides, so that uniform strain occurs in the depth direction.
[0109]
According to the present embodiment, crystalline Y having different lattice spacing from Si ₂ O ₃ An insulating film including a layer is embedded in a Si substrate, and crystalline Y having a lattice spacing different from that of Si is used. ₂ O ₃ The characteristics of a transistor including a layer in a gate insulating film and a transistor having a strained SGOI structure as a comparative example are compared. FIG. 26 shows Id-Vg characteristics of the p-channel MISFET according to the present embodiment and the p-channel MISFET according to the comparative example. The S factor in the strained SGOI p-channel MISFET according to the comparative example is 81 mV / decade. On the other hand, Y according to this embodiment ₂ O ₃ The S-factor of the p-channel MISFET using the layer was 70 mV / decade, and it was confirmed that there was no inferiority as compared with the comparative example. In addition, it can be seen that the current driving force is improved in the present embodiment as compared with the case of the strain SGOI. This is sufficient for the Si layer of the channel layer, and it is possible to apply a uniform compressive strain in the depth direction, and the hole mobility is improved. Further, this is seen when an SGOI substrate is used. This is because a decrease in mobility due to Ge diffusion is avoided.
[0110]
In the seventh embodiment, Y is used as the crystalline metal oxide constituting the insulating films 3a and 7. ₂ O ₃ As an example, the crystalline metal oxide is SrTiO. ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But the same effect can be obtained.
[0111]
Although the crystalline metal oxide is also shown in the case of a polycrystal with oriented crystal orientation, it has been confirmed that the use of a single crystal metal oxide causes a larger change in lattice constant. Although the case where the electron beam method is used as a method for forming a crystalline metal oxide is shown, other film formation methods such as a CVD method, a sputtering method, and an MBE method may be used.
[0112]
Among crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one element selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film forming conditions, and can effectively change the lattice spacing of Si. Among them, it was confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd was used, a film having high crystallinity could be realized and a particularly high effect was obtained. .
[0113]
In the seventh embodiment, both the crystalline metal oxide having a lattice spacing different from that of Si embedded in the substrate and the crystalline metal oxide having a lattice spacing different from that of Si included in the gate insulating film are Y. ₂ O ₃ However, it is not always necessary to use the same metal oxide for both, and any of the above-described metal oxides can be selected depending on the direction and amount of strain required.
[0114]
Further, in the seventh embodiment, the case of the p-channel MISFET has been described, but the same effect can also be obtained for the n-channel MISFET. Of the crystalline metal oxides described above, which metal oxide is selected depends on whether tensile stress or compressive stress is to be applied to Si. When an n-channel MISFET is manufactured, the mobility of electrons is improved in Si to which tensile stress is applied. Therefore, a metal oxide having a larger lattice constant than Si is selected. On the other hand, when a p-channel MISFET is manufactured, the mobility of holes is improved by either tensile or compressive stress, so a metal oxide having a lattice constant different from that of Si may be selected.
[0115]
The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be realized with a metal oxide containing only one kind of metal element, a metal oxide containing two or more kinds of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ By using this, the change in the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0116]
Furthermore, in the seventh embodiment, in order to apply stress to Si of the channel layer, Y ₂ O ₃ However, it is also possible to use a metal oxide in which the composition ratio of metal to oxygen is less than the stoichiometric ratio. As described in detail so far, a crystal having a high ion binding property may be selected as the crystalline metal oxide. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure such as can be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But you can. The crystalline metal oxide may be a single crystal or a polycrystal having a crystal orientation oriented. As a method for forming a crystalline metal oxide, an MBE method, a method such as a CVD method, a sputtering method, or an electron beam evaporation method can be used. Among crystalline metal oxides, rare earth elements having strong ion bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, More preferably, a rare earth oxide containing at least one element selected from Yb, Lu) is used. Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the composition ratio of metal to oxygen can be realized, and a particularly high effect can be obtained. It was confirmed.
[0117]
It is necessary to use the same metal oxide for both the crystalline metal oxide with different lattice spacing from Si embedded in the substrate and the crystalline metal oxide with different lattice spacing from Si contained in the gate insulating film. It is possible to use a metal oxide having a stoichiometric ratio of metal and oxygen on one side and a metal oxide having a lower oxygen composition ratio than the stoichiometric ratio on the other side. is there. Depending on the direction and amount of strain required, any of the above metal oxides can be selected.
[0118]
In the seventh embodiment, the Si substrate having the (001) plane orientation is used, but the plane orientation may be any of (001), (111), and (110). Further, the angle may slightly deviate from the plane orientation.
[0119]
Furthermore, in the seventh embodiment, in order to more effectively distort the Si of the channel layer, a crystalline metal oxide embedded in the Si substrate, or a crystalline metal oxide included in the gate insulating film, It is also effective to sandwich a metal salt having a rock salt structure between the channel layer. The effect is the same as that described in detail in the fourth embodiment, and amorphous SiO is formed at the interface with the crystalline oxide by sandwiching the metal oxide having a rock salt structure. ₂ Since no layer is formed, the difference in lattice spacing in the metal oxide film is more directly added to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, when the thickness is further increased, the crystallinity changes with time and the characteristics deteriorate. On the other hand, if it is thinner than one atomic layer, the effect of suppressing the diffusion of oxygen cannot be obtained, and amorphous SiO ₂ This is because a layer is generated. Among the oxides of rock salt structure, especially when the metal oxide film of rock salt structure of SrO, MgO, CaO, BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be greatly improved. It is. When applying tensile stress to Si, it is desirable to use BaO, which is a metal oxide having a rock salt structure having a lattice constant larger than that of Si. In addition, when it is desired to apply compressive stress to Si, it is desirable to use SrO, MgO, and CaO, which are metal oxides having a rock salt structure having a lattice constant smaller than that of Si. However, the change in the lattice constant in the Si layer is mainly determined by a crystalline metal oxide having a large thickness. For example, SrO having a lattice constant smaller than that of Si is sandwiched, and the lattice constant is larger than that of Si. Big Pr ₂ O ₃ In the structure in which Si is laminated, Si in the channel region is subjected to tensile stress, so that a metal oxide having a rock salt structure and a crystalline metal oxide can be arbitrarily combined. In addition, a crystalline salt metal oxide with a different lattice spacing from Si embedded in the substrate, a crystalline metal oxide with a different lattice spacing from Si contained in the gate insulating film, and a rock salt structure at the interface with the channel layer There is no need to sandwich the metal oxide, and the effect can be obtained with either one.
[0120]
(Eighth embodiment)
Next, a method for manufacturing a field effect transistor according to the eighth embodiment of the present invention will be described with reference to FIGS.
[0121]
First, as shown in FIG. 27A, an element isolation region 2 is formed on a silicon substrate 1 having a (111) plane orientation, and thereafter, for example, SiO 50 having a thickness of 50 nm. ₂ The film 4 is coated on the entire surface. Subsequently, SiO ₂ A steep impurity profile is formed in the channel region 5 by performing ion implantation of both boron and indium elements through the film 4. Then SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, the surface is subjected to dilute hydrofluoric acid treatment, and the Si surface of the channel region is terminated with hydrogen.
[0122]
Next, the silicon substrate 1 is introduced into a laser ablation apparatus. The substrate temperature is set to 500 ° C., for example, and CeO ₂ As a vapor deposition source, a metal oxide made of Ce oxide is formed to a thickness of 5 nm to form a metal oxide layer 7 (see FIG. 27B). At this time, the deposited Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 Å.
[0123]
Next, only the Ce oxide layer 7 on the channel region 5 was irradiated with a laser (see FIG. 27C). When the oxygen composition ratio was measured after laser irradiation, the oxygen composition ratio was reduced to x = 1.77, and the lattice constant increased to 5.48 cm. This is because oxygen deficiency was caused by laser irradiation, and the oxygen composition ratio was reduced. By such a method, the Ce oxide layer 7A having a large lattice constant can be formed only on the channel region 5 (see FIG. 27C). In addition, although an example in which laser irradiation is performed in the step of FIG. 27C is shown, the effect of reducing the oxygen composition ratio can be obtained even when heat treatment, electron beam irradiation, or electromagnetic wave irradiation is used. It was confirmed that + 0.8% strain was applied to Si of the channel layer 5 by increasing the lattice constant of the Ce oxide layer 7A. Subsequently, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by CVD (see FIG. 27D).
[0124]
Next, as shown in FIG. 28A, the polysilicon film 9 and the insulating films 7 and 7A are patterned using an anisotropic etching method such as RIE, for example, and the gate insulating film 7A is formed on the channel region 5. And the gate electrode 9 is formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 9 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced.
[0125]
Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface (see FIG. 28B). Subsequently, as shown in FIG. 28C, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal film such as Al is deposited to form a metal film on the entire surface. The source / drain electrodes 15a and 15b and the gate connection portion 15c are formed, and the MISFET is completed (see FIG. 28C).
[0126]
As described above, according to the present embodiment, strained Si can be formed in the channel region, so that transistor characteristics can be greatly improved. Further, strained Si can be easily formed by laser irradiation or the like.
[0127]
(Ninth embodiment)
Next, a method for fabricating a field effect transistor according to the ninth embodiment of the present invention will be described with reference to FIGS.
[0128]
First, as shown in FIG. 29A, the surface of the silicon substrate 1 having the (111) orientation is subjected to dilute hydrofluoric acid treatment, and the surface of the silicon substrate 1 is terminated with hydrogen. Next, the silicon substrate 1 is introduced into a laser ablation apparatus. The substrate temperature is set to 500 ° C., for example, and CeO ₂ Is used as a vapor deposition source to form a metal oxide layer 3 made of Ce oxide with a thickness of 10 nm (see FIG. 29A). At this time, the deposited Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 Å.
[0129]
Next, the Ce oxide layer 3 was irradiated with a laser (see FIG. 29B). After the laser irradiation, the oxygen composition ratio of the Ce oxide layer 3A was measured. As a result, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48%. This is because oxygen deficiency was caused by laser irradiation, and the oxygen composition ratio was reduced. By such a method, the Ce oxide layer 3A having a large lattice constant can be produced. Here, an example in which laser irradiation is performed is shown, but the effect of reducing the oxygen composition ratio can be obtained even when heat treatment, electron beam irradiation, or electromagnetic wave irradiation is used.
[0130]
Next, the Si channel layer 5 is formed to a thickness of, for example, 100 nm using the CVD method (see FIG. 29C). At this time, it was confirmed that Si of the channel layer 5 was pulled by the lattice constant of the Ce oxide layer 3 and had a strain of + 0.8%.
[0131]
Next, element isolation regions 2 are formed on both sides of the Si channel layer 5 (see FIG. 29D). Subsequently, for example, SiO having a thickness of 50 nm ₂ The film 4 is coated on the entire surface (see FIG. 29D). Then SiO ₂ A steep impurity profile is formed in the channel region 5 by implanting boron element ions through the film 4. Subsequently, SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, the surface of the Si channel layer 5 is subjected to dilute hydrofluoric acid treatment, and the surface is terminated with hydrogen.
[0132]
Next, by thermal oxidation, SiO ₂ A gate oxide film 7 made of, for example, 3 nm is formed. Subsequently, a polysilicon film 9 to be a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 30A). Subsequently, as shown in FIG. 30B, the polysilicon film 9 and the gate insulating film 7 are patterned by using, for example, an anisotropic etching method such as the RIE method, and the gate insulating film 7 and the channel region 5 are formed. A gate electrode 9 is formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 9 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced (see FIG. 30B).
[0133]
Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface (see FIG. 30C). Subsequently, contact holes are formed on the source / drain regions 11a, 11b and the gate electrode 9, and a metal film such as Al is deposited to form a metal film on the entire surface, thereby connecting the source / drain electrodes 15a, 15b and the gate connection. The part 15c is formed, and the MISFET is completed (see FIG. 30C).
[0134]
As described above, according to the present embodiment, strained Si can be formed in the channel region, so that transistor characteristics can be greatly improved. Further, strained Si can be easily formed by laser irradiation or the like.
[0135]
(10th Embodiment)
Next, a method for manufacturing a field effect transistor according to the tenth embodiment of the present invention will be described with reference to FIGS.
[0136]
First, dilute hydrofluoric acid treatment is performed on the surface of a silicon substrate having a (111) plane orientation, and the surface of the silicon substrate is terminated with hydrogen. Next, the silicon substrate 1 is introduced into a laser ablation apparatus. The substrate temperature is set to 500 ° C., for example, and CeO ₂ As a vapor deposition source, a metal oxide layer 3 made of Ce oxide is formed to a thickness of 10 nm (see FIG. 31A). At this time, the deposited Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 Å.
[0137]
Next, the Ce oxide layer 3 was irradiated with a laser (see FIG. 31B). When the oxygen composition ratio of the Ce oxide layer 3A was measured after the laser irradiation, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48Å. This is because oxygen deficiency was caused by laser irradiation, and the oxygen composition ratio was reduced. By such a method, Ce oxide 3A having a large lattice constant can be produced. Here, an example in which laser irradiation is performed is shown, but the effect of reducing the oxygen composition ratio can be obtained even when heat treatment, electron beam irradiation, or electromagnetic wave irradiation is used.
[0138]
Next, as shown in FIG. 31C, the Si channel layer 5 is formed to a thickness of, for example, 100 nm using the CVD method. Subsequently, element isolation regions 2 are formed on both sides of the Si channel layer 5. Subsequently, for example, SiO having a thickness of 50 nm ₂ The film 4 is coated on the entire surface (see FIG. 31C). Then SiO ₂ A steep impurity profile is formed in the channel region 5 by performing ion implantation of both boron and indium elements through the film 4. Subsequently, SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, dilute hydrofluoric acid treatment is performed to terminate the Si surface of the channel layer 5 with hydrogen.
[0139]
Next, a substrate is introduced into the laser ablation apparatus. The substrate temperature is set to 500 ° C., for example, and CeO ₂ As a vapor deposition source, a metal oxide layer 7 made of Ce oxide is formed to a thickness of 5 nm (see FIG. 31D). At this time, the deposited Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 Å.
[0140]
Next, as shown in FIG. 32A, only the Ce oxide layer 7 on the channel region 5 was irradiated with laser. After the laser irradiation, the oxygen composition ratio of the Ce oxide layer 7A was measured. As a result, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48%. This is because oxygen deficiency was caused by laser irradiation, and the oxygen composition ratio was reduced. By such a method, the Ce oxide layer 7A having a large lattice constant can be formed only on the channel region 5 (see FIG. 32A). Although an example of laser irradiation is shown here, the effect of reducing the oxygen composition ratio can be obtained even when heat treatment, electron beam irradiation, or electromagnetic wave irradiation is used. It was confirmed that + 1.0% strain was uniformly applied to the Si of the channel layer 5 by increasing the lattice constants of the Ce oxide layer 3A and the Ce oxide layer 7A.
[0141]
Next, a polysilicon film 9 to be a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 32B). Subsequently, as shown in FIG. 32 (c), the polysilicon film 9 and the Ce oxide layers 7 and 7 A are patterned using an anisotropic etching method such as RIE, for example, and gate insulation is performed on the channel region 5. A film 7A and a gate electrode 9 are formed. Thereafter, ion implantation and a thermal process are performed using the gate electrode 9 as a mask, thereby forming source / drain regions 11a and 11b into which impurities are introduced. Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface. Subsequently, contact holes are formed on the source / drain regions 11a, 11b and the gate electrode 9, and a metal film such as Al is deposited to form a metal film on the entire surface, thereby connecting the source / drain electrodes 15a, 15b and the gate connection. The part 15c is formed, and the MISFET is completed (see FIG. 32C).
[0142]
As described above, according to the present embodiment, strained Si can be formed in the channel region, so that transistor characteristics can be greatly improved. Further, strained Si can be easily formed by laser irradiation or the like.
[0143]
(Eleventh embodiment)
Next, a method for manufacturing a field effect transistor according to the eleventh embodiment will be described with reference to FIGS. In the present embodiment, a method for manufacturing a MISFET having an n-type channel and a p-type channel region is shown.
[0144]
First, as shown in FIG. 33A, an element isolation region 2 is formed on a silicon substrate 1 having a (111) plane orientation, and then, for example, SiO 50 having a thickness of 50 nm is formed. ₂ The film 4 is coated on the entire surface. Subsequently, SiO ₂ By performing ion implantation of boron element and arsenic element through the film 4, a steep impurity profile is formed in the region 5a used as the p-type channel and the region 5b used as the n-type channel. Subsequently, SiO ₂ After the film 4 is removed by etching with an ammonia fluoride solution, a dilute hydrofluoric acid treatment is performed to terminate the Si surfaces of the channel regions 5a and 5b with hydrogen.
[0145]
Next, Dy ₂ O ₃ The insulating film 7 containing oxide is changed to Dy ₂ O ₃ Was formed using an electron beam evaporation method as an evaporation source. Dy ₂ O ₃ Layer 7a was deposited with a thickness of 5 nm. At this time, the oxygen partial pressure is 1 × 10 ^-7 By controlling precisely to Torr, Dy ₂ O ₃ The orientation of the layer 7a was increased to improve the crystallinity. Further, Si on the channel layer surface is oxidized to form channel layers 5a and 5b and Dy ₂ O ₃ Between the oxide layer 7a, a 0.5 nm-thickness SiO ₂ Layer 7b was formed. That is, the gate insulating film 7 has a thickness of 0.5 nm of SiO. ₂ Layer 7b and Dy with a thickness of 5 nm ₂ O ₃ It has a laminated structure composed of layers 7a. From the X-ray diffraction evaluation, Dy ₂ O ₃ The layer 7a is a polycrystalline film oriented in the (001) direction and has a lattice constant of 5.33 （(the lattice constant is 1.8% smaller than Si). The half width of X-ray diffraction is narrow, Dy ₂ O ₃ The layer 7a was confirmed to be a highly crystalline film strongly oriented to (001). As a result of lattice constant evaluation using electron diffraction, Dy is strongly oriented to (001) and has high crystallinity. ₂ O ₃ By forming the layer 7a, it was confirmed that compressive stress was applied to Si of the channel layer 5 and the lattice constant was reduced. Dy ₂ O ₃ The change in the lattice constant of the layer 7a is −1.8% compared to the lattice constant of Si, and this Dy ₂ O ₃ It was found that Si at the interface was distorted accompanying the layer 7a, and the change in the lattice constant of Si at this interface was -0.5%. The lattice constant also changed in Si at a position 50 nm away from the interface, and the lattice constant changed by -0.4%.
[0146]
Next, only the gate insulating film 7 on the n-type channel layer 5b is selectively irradiated with laser, and Dy ₂ O ₃ Thus, the gate insulating film 7A containing Dy oxide having Dy: O = 2.0: 2.5 was obtained. At this time, the lattice constant of the Dy oxide having Dy: O = 2.0: 2.5 was 0.7% larger than the lattice constant of Si. As described above, the oxygen at the lattice position in the crystal is released, so that the lattice position of the Dy atom bonded to the released oxygen is pulled from the original lattice position by being pulled by the bond with other oxygen. As a result, the average distance between the lattices increases and the lattice constant increases. Further, the Si lattice constant of the n-type channel layer 5b was increased by + 0.3%. This is because tensile stress is applied to Si of the channel layer by making the lattice spacing of Dy oxide having a strong crystallinity of Dy: O = 2.0: 2.5 larger than Si, which is strongly oriented to (001). This is because the lattice constant increases. From this result, an insulating film containing a metal oxide having a lattice spacing smaller than that of Si and having a high crystallinity is used as a gate insulating film, and local laser irradiation is performed. A tensile strain can be generated in the channel, and the performance as a CMOS can be greatly improved.
[0147]
Next, a polysilicon film 9 to be a gate electrode is deposited on the entire surface by CVD (see FIG. 33D). Subsequently, as shown in FIG. 34 (a), the polysilicon film 9 and the gate insulating films 7 and 7A containing Ce oxide are patterned by using, for example, an anisotropic etching method such as the RIE method, and the channel region 5a. 5b, a gate insulating film 7 and a gate electrode 9a, and a gate insulating film 7A and a gate electrode 9b are formed. Thereafter, using the gate electrode 9a and the gate electrode 9b as a mask, ion implantation of a boron element and an arsenic element and a thermal process are performed to form source / drain regions 11a, 11b, 12a, and 12b into which impurities are introduced. (See FIG. 34 (a)).
[0148]
Next, SiO is formed by CVD. ₂ A film 13 is deposited on the entire surface (see FIG. 34B). Subsequently, as shown in FIG. 34 (c), contact holes are opened on the source / drain regions 11a, 11b, 12a, 12b and the gate electrodes 9a, 9b, and a metal film is deposited by depositing a metal such as Al. By forming it on the entire surface, source / drain electrodes 15a, 15b, 16a, 16b and gate connection portions 15c, 16c are formed, and the MISFET is completed (see FIG. 34C).
[0149]
As described above, the transistor according to the present embodiment having an n-type channel and a p-type channel and modulating the lattice constant of the Dy oxide on the n-type channel side is compared with amorphous SiO which is a comparative example. ₂ The characteristics were compared with a transistor having a strained SGOI structure having a gate insulating film as a gate electrode. The comparison result is shown in FIG.
[0150]
As shown in FIG. ₂ SiO with an equivalent film thickness (EOT) of 8 nm ₂ CMOSFET having a gate insulating film made of (hereinafter also referred to as SGOI type CMOS), SiO ₂ Dy oxide / SiO2 with equivalent film thickness (EOT) of 8 nm ₂ The dependence of the gate delay time on the power supply voltage of the CMOSFET according to the present embodiment having an insulating film having a laminated structure (hereinafter also referred to as a lattice local modulation type CMOS) was compared. The lattice local modulation type CMOS is lower than the SGOI type CMOS over the entire voltage range, and it can be seen that the delay time can be reduced by using the lattice local modulation type CMOS. This is because the SGOI type has tensile strain applied to both the n-type and p-type, so that only the mobility of electrons is improved and the mobility of holes is not so much improved. This is because the tensile strain is applied to the mold and the compressive strain is applied to the p-type, so that the mobility of both electrons and holes is greatly improved.
[0151]
As described above, according to the present embodiment, not only the n-channel MISFET and the p-channel MISFET but also the composite CMOS thereof includes a metal oxide whose lattice spacing changes with Si by controlling the oxygen composition. By using the insulating film as the gate insulating film, the characteristics can be greatly improved. Further, the same effect can be obtained even if the above method is performed on a metal oxide embedded in a substrate. Furthermore, it is possible to achieve further improvement in performance by combining the use of a metal oxide whose lattice spacing changes with Si by controlling the oxygen composition in the substrate and using it as a gate insulating film. is there.
[0152]
Further, in the eighth to eleventh embodiments, an example in which Ce oxide and Dy oxide are used to apply stress to Si in the channel layer has been shown. However, as described in detail so far, crystalline metal oxide is used. As the product, a crystal having high ion binding property may be selected. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ An oxide having a perovskite structure such as can be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ But you can. The crystalline metal oxide may be a single crystal or a polycrystal having a crystal orientation oriented.
[0153]
As a method for forming a crystalline metal oxide, an MBE method, a method such as a CVD method, a sputtering method, or an electron beam evaporation method can be used. Among crystalline metal oxides, rare earth elements having strong ion bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, More preferably, a rare earth oxide containing at least one element selected from Yb, Lu) is used. Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, it is confirmed that precise control of the oxygen composition ratio can be realized and a particularly high effect can be obtained. did.
[0154]
In the case of the eleventh embodiment, both the crystalline metal oxide having a lattice spacing different from that of Si embedded in the substrate and the crystalline metal oxide having a lattice spacing different from that of Si included in the gate insulating film are used. It is not always necessary to use the same metal oxide for both. It is also possible to use a metal oxide whose oxygen composition ratio is a stoichiometric ratio on one side and a metal oxide whose oxygen composition ratio is lower than the stoichiometric ratio on the other side. A metal oxide can be arbitrarily selected according to the direction and amount of strain required.
[0155]
In the eighth to eleventh embodiments, the Si substrate having the (111) plane orientation is used, but the plane orientation may be any of (001), (111), and (110). Further, the angle may slightly deviate from the plane orientation.
[0156]
Furthermore, in the eighth to eleventh embodiments, in order to more effectively distort Si in the channel layer, a crystalline metal oxide embedded in the Si substrate or a crystalline metal oxide included in the gate insulating film It is also effective to sandwich a metal salt having a rock salt structure between the object and the channel layer. The effect is the same as that described in detail in the fourth embodiment, and amorphous SiO is formed at the interface with the crystalline oxide by sandwiching the metal oxide having a rock salt structure. ₂ Since no layer is formed, the difference in lattice spacing in the metal oxide film is more directly added to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, when the thickness is further increased, the crystallinity changes with time and the characteristics deteriorate. On the other hand, if it is thinner than one atomic layer, the effect of suppressing the diffusion of oxygen cannot be obtained, and amorphous SiO ₂ This is because a layer is generated. Among the oxides of rock salt structure, especially when the metal oxide film of rock salt structure of SrO, MgO, CaO, BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be greatly improved. It is. When applying tensile stress to Si, it is desirable to use BaO, which is a metal oxide having a rock salt structure having a lattice constant larger than that of Si.
[0157]
In addition, when it is desired to apply compressive stress to Si, it is desirable to use SrO, MgO, and CaO, which are metal oxides having a rock salt structure having a lattice constant smaller than that of Si. However, the change in the lattice constant in the Si layer is mainly determined by a crystalline metal oxide having a large thickness. For example, SrO having a lattice constant smaller than that of Si is sandwiched, and the lattice constant is larger than that of Si. Big Pr ₂ O ₃ In the structure in which Si is laminated, Si in the channel region is subjected to tensile stress, so that a metal oxide having a rock salt structure and a crystalline metal oxide can be arbitrarily combined. Further, in the case of the eleventh embodiment, a crystalline metal oxide having a lattice spacing different from that of Si embedded in the substrate, and a crystalline metal oxide having a lattice spacing different from that of Si included in the gate insulating film. In addition, it is not necessary to sandwich a metal oxide having a rock salt structure at both the interface with the channel layer, and the effect can be obtained with either one.
[0158]
【The invention's effect】
As described above, according to the present invention, the transistor characteristics can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a manufacturing process of the method for manufacturing the field effect transistor according to the first embodiment.
FIG. 3 is a cross-sectional view of a manufacturing process of the method for manufacturing the field effect transistor according to the first embodiment.
FIG. 4 shows Pr of the field effect transistor according to the first embodiment. ₂ O ₃ / SiO ₂ The schematic diagram which shows the cross section of / Si interface.
FIG. 5 shows Pr of the field effect transistor according to the first embodiment. ₂ O ₃ Layer, SiO ₂ The figure which shows the change of the lattice constant in / Si interface and a channel layer.
FIG. 6 is a characteristic diagram showing the relationship between the gate voltage Vg and the drain current Id of the field effect transistors according to the first embodiment and the comparative example.
FIG. 7 is a schematic view showing a cross section of a Ce oxide / Si interface of a field effect transistor according to a third embodiment of the present invention.
FIG. 8 is a diagram showing a measurement position of a Ce oxide / Si interface and a change value of a lattice constant according to a third embodiment.
FIG. 9 is a view showing the relationship between the composition ratio of metal and oxygen and the lattice constant of Ce oxide of the field effect transistor according to the third embodiment.
FIG. 10 is a schematic view showing that the Ce oxide of the field effect transistor according to the third embodiment has an oxygen deficiency due to oxygen loss and an average lattice constant of the Ce oxide is increased.
FIG. 11 is a characteristic diagram showing the relationship between the composition ratio of Ce oxide metal and oxygen, the gate voltage, and the drain current of the field effect transistors according to the third embodiment and the comparative example.
FIG. 12 is a cross-sectional view showing a configuration of a field effect transistor according to a fifth embodiment of the present invention.
FIG. 13 is a cross-sectional view of a manufacturing process of the field effect transistor according to the fifth embodiment.
FIG. 14 is a cross-sectional view of a manufacturing process of the field effect transistor according to the fifth embodiment.
FIG. 15 shows Si / SiO according to the fifth embodiment. ₂ / La ₂ O ₃ / SiO ₂ / Si / SiO ₂ The schematic diagram which shows the cross section of an interface.
FIG. 16 shows Si / SiO according to the fifth embodiment. ₂ / La ₂ O ₃ / SiO ₂ / Si / SiO ₂ The figure which shows the measurement position of an interface, and the change value of a lattice constant.
FIG. 17 is a cross-sectional view showing a structure of a field effect transistor having a strained SOI structure.
FIG. 18 is a characteristic diagram showing the relationship between the gate voltage and the drain current of the SOI field effect transistor according to the fifth embodiment and the comparative example.
FIG. 19 is a characteristic diagram showing the relationship between the gate voltage and the drain current of the SOI field effect transistor according to the sixth embodiment and the comparative example.
FIG. 20 is a sectional view showing the structure of a field effect transistor according to a seventh embodiment of the present invention.
FIG. 21 is a cross-sectional view showing the manufacturing process of the field effect transistor according to the seventh embodiment.
FIG. 22 is a cross-sectional view showing a manufacturing process of the field effect transistor according to the seventh embodiment.
FIG. 23 is a cross-sectional view showing a manufacturing step of the field effect transistor according to the seventh embodiment.
FIG. 24 shows Si / SiO of the field effect transistor according to the seventh embodiment. ₂ / Y ₂ O ₃ / SiO ₂ / Si / SiO ₂ The schematic diagram which shows the cross section of an interface.
FIG. 25 shows Si / SiO of the field effect transistor according to the seventh embodiment. ₂ / Y ₂ O ₃ / SiO ₂ / Si / SiO ₂ The figure which shows the measurement position of an interface, and the change value of a lattice constant.
FIG. 26 is a characteristic diagram showing the relationship between the gate voltage and the drain current of the SOI field effect transistor according to the seventh embodiment and the comparative example.
FIG. 27 is a manufacturing step sectional view of a method for manufacturing a field effect transistor according to the eighth embodiment of the present invention;
FIG. 28 is a manufacturing step sectional view of a method for manufacturing a field effect transistor according to the eighth embodiment of the present invention;
FIG. 29 is a manufacturing process sectional view of the method for manufacturing the field effect transistor according to the ninth embodiment of the present invention.
30 is a manufacturing process sectional view of the method for manufacturing the field effect transistor according to the ninth embodiment of the present invention; FIG.
FIG. 31 is a manufacturing step sectional view of the method for manufacturing the field effect transistor according to the tenth embodiment of the present invention;
FIG. 32 is a manufacturing step sectional view of the method for manufacturing the field effect transistor according to the tenth embodiment of the present invention;
33 is a manufacturing process sectional view of the method for manufacturing the field effect transistor according to the eleventh embodiment of the present invention; FIG.
34 is a cross-sectional view showing a manufacturing step in the method for manufacturing the field effect transistor according to the eleventh embodiment of the present invention; FIG.
FIG. 35 is a characteristic diagram showing the relationship between the drain voltage and the delay time of the field-effect transistor manufactured according to the eleventh embodiment and the transistor according to the comparative example.
[Explanation of symbols]
1 Silicon substrate
2 Device isolation region
3 Insulating film
3a Insulating film
3b SiO ₂ film
3c SiO ₂ film
5 Channel region (channel layer)
7 Gate insulation film
7a Insulating film
7b SiO ₂ film
9 Gate electrode
11a Source region
11b Drain region
13 Insulating film
15a Source electrode
15b Drain electrode
15c Gate connection

Claims (9)

A channel region of the first conductivity type formed on the surface of the silicon substrate and a crystalline material formed on the channel region and having a lattice spacing different from that of the silicon substrate, and any one of Ce, Dy, Y, La, and Pr A gate insulating film including at least a metal oxide layer having a kind of oxide, a gate electrode formed on the gate insulating film, and a second conductivity type source formed in the semiconductor region on both sides of the gate electrode -It is provided between the drain region, the metal oxide layer, and the channel region, and is an oxide of any one of Mg, Ca, Sr, and Ba, and has a film thickness of 1 to 3 atomic layers A field effect transistor comprising: a crystalline rock salt structure metal oxide, wherein a lattice spacing of the channel region is modulated. A semiconductor region including silicon formed on a substrate, a first conductivity type channel region formed on a surface of the semiconductor region, and a lattice spacing different from that of the semiconductor region formed between the substrate and the semiconductor region. An insulating film including at least a metal oxide layer made of crystalline and having any one kind of oxide of Ce, Dy, Y, La, and Pr ; a gate insulating film formed on the channel region; and the gate A gate electrode formed on the insulating film, and a source / drain region of a second conductivity type formed in the semiconductor region on both sides of the gate electrode, and the lattice spacing of the channel region is modulated A field effect transistor characterized by. A crystalline rock-salt structure metal oxide having a film thickness of 1 to 3 atomic layers, which is an oxide of any one of Mg, Ca, Sr, and Ba between the metal oxide layer and the channel region The field effect transistor according to claim 2, wherein an object is provided.   4. The field effect transistor according to claim 1, wherein the metal oxide layer has a metal / oxygen composition ratio less than a stoichiometric ratio.   5. The field effect transistor according to claim 4, wherein the lattice spacing of the metal oxide layer is different from the lattice spacing when the composition ratio of metal and oxygen is a stoichiometric ratio. A semiconductor region containing silicon formed on a substrate, a channel region of a first conductivity type formed on the surface of the semiconductor region, and a crystal formed between the substrate and the semiconductor region and having a lattice spacing different from that of the semiconductor region A first insulating film including at least a first metal oxide layer made of a material and having any one kind of oxide of Ce, Dy, Y, La, and Pr ; and the substrate formed on the channel region; A gate insulating film including at least a second metal oxide layer made of crystalline materials having different lattice spacings and having any one kind of oxide of Ce, Dy, Y, La, and Pr, and formed on the gate insulating film And a second conductivity type source / drain region formed in the semiconductor region on both sides of the gate electrode, and the lattice spacing of the channel region is modulated. Field-effect transistor according to claim.   7. The field effect transistor according to claim 6, wherein at least one of the first and second metal oxide layers has an oxygen composition ratio less than a stoichiometric ratio.   8. The field effect transistor according to claim 7, wherein the lattice spacing of at least one of the first and second metal oxide layers is different from the lattice spacing when the oxygen composition ratio is a stoichiometric ratio. A crystalline rock salt that is one kind of oxide of Mg, Ca, Sr, and Ba and has a film thickness of 1 to 3 atomic layers between the second metal oxide layer and the channel region. 9. The field effect transistor according to claim 6, wherein a structural metal oxide layer is provided.

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