JP2004213682A - Memory module - Google Patents

Memory module Download PDF

Info

Publication number
JP2004213682A
JP2004213682A JP2004030004A JP2004030004A JP2004213682A JP 2004213682 A JP2004213682 A JP 2004213682A JP 2004030004 A JP2004030004 A JP 2004030004A JP 2004030004 A JP2004030004 A JP 2004030004A JP 2004213682 A JP2004213682 A JP 2004213682A
Authority
JP
Japan
Prior art keywords
insulating substrate
terminals
substrate
plug
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004030004A
Other languages
Japanese (ja)
Other versions
JP3713034B2 (en
Inventor
Toshio Kanno
利夫 管野
Seiichiro Tsukui
誠一郎 津久井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Renesas Eastern Japan Semiconductor Inc filed Critical Hitachi Ltd
Priority to JP2004030004A priority Critical patent/JP3713034B2/en
Publication of JP2004213682A publication Critical patent/JP2004213682A/en
Application granted granted Critical
Publication of JP3713034B2 publication Critical patent/JP3713034B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory module capable of preventing wrong insertion in the case of mounting an insulation substrate to a socket. <P>SOLUTION: The memory module is provided with the rectangular insulation substrate (10) having first and third sides opposed to each other and second and fourth sides opposed to each other, a plurality of connector terminals (connector terminals) being insulated from each other and provided on the front side and the rear side of the insulation substrate along the first side, a plurality of memory ICs (20) provided on the insulation substrate and notches (12a, 12b) for mechanical key-in for preventing the wrong insertion, which is provided almost at the center of the first side of the insulation substrate. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

本発明は、IC実装技術さらには接栓端子列を有する半導体実装絶縁基板に適用して特に有効な技術に関し、例えば複数個のメモリICを高密度に搭載したソケット実装タイプのメモリモジュールに利用して有効な技術に関する。   The present invention relates to an IC mounting technology and a technology particularly effective when applied to a semiconductor mounting insulating substrate having a plug terminal row. For example, the present invention is applied to a socket mounting type memory module in which a plurality of memory ICs are mounted at high density. And effective technology.

近年、一辺に接栓端子列を有する絶縁基板上に複数個のメモリICを高密度に実装してなるメモリモジュールが、ノートパソコン等の小型電子機器向けに開発されている。従来のメモリモジュールにおける接栓端子列は、実装用絶縁基板10の表裏に銅めっきを施した後、エッチングにより図8に示すように、基板の一辺に沿って同一形状の接栓端子11a,11b………および11a’,11b’………を基板表裏にそれぞれ形成し、各接栓端子11の基端部と基板を貫通するようにドリルで穴あけを行なってスルーホール15を形成し、各接栓端子11の表面から上記スルーホール15の内面にかけて銅めっきを施すことで、基板表裏の対応する接栓端子11間を電気的に接続した構造とされていた。   In recent years, memory modules in which a plurality of memory ICs are densely mounted on an insulating substrate having a plug terminal row on one side have been developed for small electronic devices such as notebook personal computers. The plug terminal rows in the conventional memory module are formed by plating copper on the front and back of the mounting insulating substrate 10 and then etching the plug terminals 11a, 11b having the same shape along one side of the substrate as shown in FIG. , And 11a ', 11b',... Are formed on the front and back of the board, respectively, and drilled to penetrate the base end of each plug-in terminal 11 and the board to form through holes 15; By applying copper plating from the surface of the plug terminal 11 to the inner surface of the through hole 15, the corresponding plug terminal 11 on the front and back of the substrate is electrically connected.

しかしながら、上述した技術には、次のような問題のあることが本発明者らによってあきらかとされた。
すなわち、従来のソケット実装タイプのメモリモジュールでは、実装用絶縁基板に設けられる接栓端子のピッチが2.54mmあるいは1.27mmで標準化されていたため、ある大きさの基板に設けることができる接栓端子の数に制約があった。言い換えると、必要な接栓端子数を確保しようとすると、基板の外形寸法が接栓端子数によって律速されてしまうという問題点があった。
However, the inventors have clarified that the above-described technique has the following problems.
That is, in the conventional socket mounting type memory module, the pitch of the plug terminals provided on the mounting insulating substrate is standardized to be 2.54 mm or 1.27 mm, so that the plug can be provided on a board of a certain size. There were restrictions on the number of terminals. In other words, there is a problem that the outer dimensions of the board are limited by the number of plug terminals when trying to secure the required number of plug terminals.

本発明は、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができるような構造の基板を用いたモジュールを提供することを目的とする。あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができるような基板構造およびそのような構造の基板を用いたモジュールを提供することを目的とする。
本発明の前記並びにその他の目的と新規な特徴については、本明細書の記述および添付図面から明らかになるであろう。
SUMMARY OF THE INVENTION An object of the present invention is to provide a module using a substrate having a structure capable of providing twice as many plug terminals without changing the pitch on an insulating substrate having the same size as the conventional one. Alternatively, it is another object of the present invention to provide a substrate structure capable of reducing the size of an insulating substrate to about half if the number of plug terminals is the same, and a module using a substrate having such a structure.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を説明すれば、下記のとおりである。
すなわち、絶縁基板の表裏に設けられる接栓端子を、互いに電気的に絶縁された別個の接栓端子となるように形成するようにしたものである。
具体的には、互いに対向する第1及び第3の辺と、互いに対向する第2及び第4の辺とを有する矩形状の絶縁基板と、前記第1の辺に沿って前記絶縁基板の表面側及び裏面側に互いに電気的に絶縁されて設けられた複数の接栓端子と、前記絶縁基板に設けられ、複数のメモリと前記複数のメモリに共通信号を伝達するドライバとを含む複数の半導体装置と、前記絶縁基板に設けられ、前記半導体装置と前記接栓端子とを電気的に接続する配線とを備えた半導体実装装置としたものである。
The outline of a representative invention among the inventions disclosed in the present application will be described as follows.
That is, the plug terminals provided on the front and back of the insulating substrate are formed so as to be separate plug terminals electrically insulated from each other.
Specifically, a rectangular insulating substrate having first and third sides facing each other, and second and fourth sides facing each other, and a surface of the insulating substrate along the first side Plural semiconductors including a plurality of plug terminals electrically insulated from each other on a side and a back side, and a plurality of memories provided on the insulating substrate and including a plurality of memories and a driver for transmitting a common signal to the plurality of memories. According to another aspect of the present invention, there is provided a semiconductor mounting device including: a device; and a wiring provided on the insulating substrate and electrically connecting the semiconductor device and the plug terminal.

上記した手段によれば、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができ、あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができる。   According to the above-described means, it is possible to provide twice the number of plug terminals without changing the pitch on an insulating substrate of the same size as the conventional one, or if the number of plug terminals is the same, the number of plug terminals can be reduced. The size can be reduced by about half.

さらに、前記絶縁基板において、前記第1の辺に誤挿入防止のためのノッチを、前記第2及び第4の辺にそれぞれ抜け止め用のノッチを設けることが望ましい。これによって、前記絶縁基板をソケットに装着する際の誤挿入を防止できるとともに、基板装着後、基板の抜け止めを行えるようになっている。   Further, in the insulating substrate, it is preferable that a notch for preventing erroneous insertion is provided on the first side, and a notch for retaining is provided on each of the second and fourth sides. With this, it is possible to prevent erroneous insertion when the insulating substrate is mounted on the socket, and to prevent the substrate from coming off after mounting the substrate.

また、長方形の絶縁基板と、前記絶縁基板の1つの長辺に沿って前記絶縁基板の両面に電気的に互いに絶縁して設けられた複数の接栓端子と、前記絶縁基板に設けられた複数の半導体装置と、前記絶縁基板上に設けられ、前記半導体装置と前記接栓端子とを電気的に接続する配線とを備え、前記接栓端子は基板識別用の端子を含む半導体実装装置としてもよい。これによって、異なる仕様の複数種のモジュールに対して基板の標準化を可能とし、トータルコストを低減することができるようになる。   A rectangular insulating substrate; a plurality of plug terminals provided on both surfaces of the insulating substrate along one long side of the insulating substrate so as to be electrically insulated from each other; and a plurality of plug terminals provided on the insulating substrate. And a wiring provided on the insulating substrate and electrically connecting the semiconductor device and the plug terminal, wherein the plug terminal may be a semiconductor mounting device including a terminal for board identification. Good. As a result, it is possible to standardize a substrate for a plurality of types of modules having different specifications, thereby reducing the total cost.

さらに、前記絶縁基板の場合も、前記絶縁基板の長辺に誤挿入防止のためのノッチを、前記絶縁基板の2つの短辺にそれぞれ抜け止め用のノッチを設けるとよい。これによって、前記絶縁基板をソケットに装着する際誤挿入を防止できるとともに、基板装着後、基板の抜け止めを行うことができる。   Further, in the case of the insulating substrate as well, a notch for preventing erroneous insertion may be provided on a long side of the insulating substrate, and a notch for preventing slippage may be provided on each of two short sides of the insulating substrate. This can prevent erroneous insertion when the insulating substrate is mounted in the socket, and can prevent the substrate from coming off after the substrate is mounted.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記のとおりである。
すなわち、ICが実装される絶縁基板に、ピッチを変えることなく従来の2倍の数の接栓端子を設けることができ、あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができる。
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
That is, twice the number of plug terminals can be provided on the insulating substrate on which the IC is mounted without changing the pitch, or if the number of plug terminals is the same, the size of the insulating substrate can be reduced. Can be halved.

以下、本発明の好適な実施例を図面に基づいて説明する。   Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

図1〜図3には、本発明を適用したメモリモジュールの一実施例が示されている。この実施例のメモリモジュールは、絶縁基板10の表面と裏面にそれぞれ8個のメモリIC20と1個のドライバIC30が搭載されており、上記絶縁基板10の表裏には基板の一辺に沿って同一形状の接栓端子11a,11b,11c………が、等ピッチPでそれぞれ形成されている。絶縁基板10の表側の接栓端子11a,11b,11c………と、裏側の接栓端子11a’,11b’,11c’………とは、互いに電気的に絶縁されている。しかもこの実施例では、特に制限されないが、絶縁基板10の表側の接栓端子11a,11b,11c………と、裏側の接栓端子11a’,11b’,11c’………とは、図2に示すごとく、互いに位置が半ピッチP/2だけずれるように形成されている。   1 to 3 show one embodiment of a memory module to which the present invention is applied. In the memory module of this embodiment, eight memory ICs 20 and one driver IC 30 are mounted on the front and back surfaces of the insulating substrate 10, respectively, and the same shape is formed on one side of the insulating substrate 10 along one side of the substrate. Are formed at equal pitches P. The plug terminals 11a, 11b, 11c,. The plug terminals 11a, 11b, 11c on the front side of the insulating substrate 10 and the plug terminals 11a ', 11b', 11c 'on the rear side are electrically insulated from each other. Moreover, in this embodiment, although not particularly limited, the front connection terminals 11a, 11b, 11c... And the rear connection terminals 11a ′, 11b ′, 11c ′. As shown in FIG. 2, the positions are shifted from each other by a half pitch P / 2.

上記絶縁基板10は、それぞれ表面に導電層からなる配線パターンが形成されてなる複数(例えば6枚)の絶縁性基板が積層された多層構造とされている。また、この実施例では、上記絶縁基板10の材料としてFR−5と呼ばれる熱膨張率が10ppm程度の高TG材料(軟化温度の高いガラス)が使用されている。これによって、TSOP(薄型スモール・アウトライン・パッケージ)構造のメモリIC20が実装可能にされる。   The insulating substrate 10 has a multilayer structure in which a plurality of (for example, six) insulating substrates each having a wiring pattern formed of a conductive layer formed on the surface thereof are stacked. In this embodiment, a high TG material (glass having a high softening temperature) having a thermal expansion coefficient of about 10 ppm called FR-5 is used as a material of the insulating substrate 10. Thus, the memory IC 20 having a TSOP (thin small outline package) structure can be mounted.

すなわち、従来一般的に使用されていたFR−4と呼ばれるガラスエポキシ等からなる基板にあっては、熱膨張率が16ppm程度であるため、はんだ接合部の熱膨張率が5ppm程度であるTSOP(薄型スモール・アウトライン・パッケージ)構造のメモリICを使用すると、熱サイクル等によりはんだ接合部が剥がれたりするおそれがあるため、はんだ接合部の熱膨張率が10ppm程度であるSOJ構造のメモリICを実装せざるを得なかった。   That is, in the case of a substrate made of glass epoxy or the like called FR-4 which has been generally used in the past, since the coefficient of thermal expansion is about 16 ppm, the TSOP (solder joint) has a coefficient of thermal expansion of about 5 ppm. When a memory IC having a thin small outline package) structure is used, a solder joint may be peeled off due to a thermal cycle or the like. Therefore, a memory IC having an SOJ structure in which the thermal expansion coefficient of the solder joint is about 10 ppm is mounted. I had to do it.

しかるに、本実施例では、基板10の材料として熱膨張率が10ppm程度の高TG材料を使用しているため、リード端子が外側に拡がるように折曲された熱膨張率が5ppm程度のTSOP(薄型スモール・アウトライン・パッケージ)構造のメモリICを使用することができるようになった。その結果、基板に実装された状態でのICの高さが低くなって、モジュールが小型化できるようになった。   However, in this embodiment, since a high TG material having a thermal expansion coefficient of about 10 ppm is used as the material of the substrate 10, the TSOP (the thermal expansion coefficient of which is bent so that the lead terminals are spread outward) of about 5 ppm is used. A memory IC having a thin small outline package) structure can be used. As a result, the height of the IC mounted on the substrate is reduced, and the module can be reduced in size.

さらに、この実施例では、絶縁基板10の所定の位置に、互いにリード端子が逆方向に曲げられたメモリIC20がはんだ付けされている。すなわち、絶縁基板10の表側に実装されたメモリIC20は、図3に示すように、リード端子21がICの腹の側に向かって曲げられており、絶縁基板10の裏側に実装されたメモリIC20’はリード端子21’がICの背の側に向かって曲げられている。これによって、表面のICと裏面のICの信号端子が同一位置に来るようになるので、基板10の表面に形成すべき配線パターンの共用化が可能になるとともに、最短距離の配線形成が容易となる。そのため、配線パターンの設計が容易となるとともに、配線同士の交差箇所を減らすことができ、配線が簡素化されてモジュールの特性および品質が向上する。   Further, in this embodiment, memory ICs 20 whose lead terminals are bent in opposite directions are soldered to predetermined positions of the insulating substrate 10. That is, as shown in FIG. 3, the memory IC 20 mounted on the front side of the insulating substrate 10 has the lead terminals 21 bent toward the antinode of the IC, and the memory IC 20 mounted on the back side of the insulating substrate 10. In ', the lead terminal 21 ′ is bent toward the back of the IC. As a result, the signal terminals of the IC on the front surface and the signal terminals of the IC on the back surface come to the same position, so that the wiring pattern to be formed on the front surface of the substrate 10 can be shared, and the shortest distance wiring can be easily formed. Become. Therefore, the design of the wiring pattern is facilitated, the number of intersections between the wirings can be reduced, the wiring is simplified, and the characteristics and quality of the module are improved.

上記絶縁基板10の接栓端子11が形成された辺とこれに直交する2辺には、図1に示すように、それぞれノッチ12a,12bおよび13a,13bが形成されている。このうち接栓端子が形成された辺上のノッチ12aと12bは、誤挿入を防止するためのメカニカルキーイン用のノッチ(凹部)とされ、13a,13bは抜け止め用のノッチとされる。   As shown in FIG. 1, notches 12a, 12b and 13a, 13b are formed on the side of the insulating substrate 10 on which the plug terminal 11 is formed and on two sides orthogonal thereto. Of these, notches 12a and 12b on the side where the plug terminal is formed are mechanical key-in notches (recesses) for preventing erroneous insertion, and 13a and 13b are notches for retaining.

すなわち、この実施例の絶縁基板10は、図4に示されているようなソケット40に装着される適した構造とされている。   That is, the insulating substrate 10 of this embodiment has a structure suitable for being mounted on the socket 40 as shown in FIG.

次に、ソケット40の一実施例について説明する。
絶縁基板10が装着されるソケット40は、前記接栓端子11a,11b,11c………および11a,11b,11c………と11a’,11b’,11c’………の数に対応した端子ピン41a,41b,41c………を外側に有し、内側には上記ノッチ12a,12bに対応した位置にそれぞれ上記ノッチと係合可能な突起42a,42bを有している。
Next, an embodiment of the socket 40 will be described.
The socket 40 on which the insulating substrate 10 is mounted has terminals corresponding to the number of the plugging terminals 11a, 11b, 11c,... And 11a, 11b, 11c,. .. Have pins 41a, 41b, 41c... On the outside, and have projections 42a, 42b on the inside corresponding to the notches 12a, 12b, respectively, which can be engaged with the notches.

また、上記各端子ピン41a,41b,41c………には、図5に示すように、上記各接栓端子11と接触可能な弾性片からなるリード43がそれぞれ一体に形成されており、それらがソケットのハウジング44内に接栓端子のピッチPの半分のピッチP/2で保持されている。各リード43は互いに離間されているとともに、リード43は、図5に実線Aで示されているようなやや下向きのリードと二点鎖線Bで示されているようなやや上向きのリードとが交互に配置されることにより、互いに基板10の厚みとより少し狭い間隔をおいて向き合う係合部を構成している。絶縁基板10は、矢印C方向から接栓端子部を上記リード43により構成される係合部に挿入し、矢印D方向へ回動させることにより装着される。   As shown in FIG. 5, the terminal pins 41a, 41b, 41c... Are integrally formed with reeds 43 made of elastic pieces that can come into contact with the plug terminals 11, respectively. Are held in the socket housing 44 at a pitch P / 2, which is half the pitch P of the plug-in terminals. The leads 43 are spaced apart from each other, and the leads 43 alternate between a slightly downward lead as shown by a solid line A and a slightly upward lead as shown by a two-dot chain line B in FIG. , An engaging portion facing each other with a slightly smaller interval than the thickness of the substrate 10 is formed. The insulating substrate 10 is mounted by inserting the plug terminal portion into the engaging portion formed by the lead 43 in the direction of arrow C and rotating in the direction of arrow D.

ソケット40の両端には、図4に示すように、先端部にそれぞれ突起47a,47bを有する一対の保持アーム45a,45bがピン46a,46bを支点として回転自在に取り付けられており、上記リード43に上記絶縁基板10を装着した後に、上記保持アーム45a,45bを内側に回動させ、基板10の側面のノッチ13a,13bに突起47a,47bを係合させることで、基板の抜け止めを行なえるようになっている。   As shown in FIG. 4, a pair of holding arms 45a and 45b having protrusions 47a and 47b at the ends thereof are rotatably attached to both ends of the socket 40 with pins 46a and 46b as fulcrums. After the insulating substrate 10 is mounted on the substrate 10, the holding arms 45a and 45b are rotated inward, and the protrusions 47a and 47b are engaged with the notches 13a and 13b on the side surfaces of the substrate 10, thereby preventing the substrate from coming off. It has become so.

さらに、保持アーム45a,45bには内側に向けて作動片48a,48bが形成されており、上記ピン46a,46bを支点としてそれぞれ外側へ回動させたとき、上記作動片48a,48bが装着されている基板10を押し出して離脱させるように構成されている。これによって、端子密度が増大し取外しが困難になった基板10とソケット40との結合を、保持アーム45a,45bの操作によるてこの原理で簡単に外すことができるようになる。   Further, the holding arms 45a, 45b are formed with operating pieces 48a, 48b inward, and when the pins 46a, 46b are pivoted outward with the pins 46a, 46b as fulcrums, the operating pieces 48a, 48b are mounted. The substrate 10 is configured to be pushed out and separated. As a result, the connection between the substrate 10 and the socket 40, which has become difficult to remove due to an increase in terminal density, can be easily removed by leverage principle by operating the holding arms 45a and 45b.

さらに、この実施例の絶縁基板10には、基板識別用のPD端子17a,17b,17c,17dと、ジャンパーチップ接続端子18a,18b,18c,18dと、グランド端子(もしくはVcc端子)19a,19b,19c,19dが基板表面に、また上記PD端子17a,17b,17c,17dをジャンパーチップ接続端子18a,18b,18c,18dに接続するための配線パターン50が、図1に破線で示すように、内部配線層に設けられており、上記PD端子17a,17b,17c,17dおよびグランド端子(もしくはVcc端子)19a,19b,19c,19d間に、それらを短絡するための導電体(0Ωの抵抗)を有するジャンパーチップ50a,50c………が選択的に接続されるようになっている。ジャンパーチップ50a,50c………は、仕様の異なるモジュールを識別するためのコードを発生するために使用される。   Furthermore, the insulating substrate 10 of this embodiment has PD terminals 17a, 17b, 17c, 17d for board identification, jumper chip connection terminals 18a, 18b, 18c, 18d, and ground terminals (or Vcc terminals) 19a, 19b. , 19c, 19d on the surface of the substrate, and the wiring pattern 50 for connecting the PD terminals 17a, 17b, 17c, 17d to the jumper chip connection terminals 18a, 18b, 18c, 18d, as shown by broken lines in FIG. A conductor (0Ω resistance) is provided between the PD terminals 17a, 17b, 17c, 17d and the ground terminals (or Vcc terminals) 19a, 19b, 19c, 19d. ) Having jumper chips 50a, 50c... Are selectively connected. The jumper chips 50a, 50c... Are used to generate codes for identifying modules having different specifications.

すなわち、図6に示すように、ジャンパーチップ50a,50cが接続されたPD端子17a,17cはグランド電位(もしくはVcc電位)に固定され、ジャンパーチップが接続されないPD端子17b,17dはNC端子(ノオ・コネクション端子)となるため、これらのPD端子17a〜17dの状態をマイクロプロセッサが読み込むことでどのような仕様のモジュールであるか、つまりモジュールの記憶容量や電気的特性を例えば自己の保有するテーブル(メモリ)を参照することで知ることができる。上記PD端子が4個あれば16種類、n個あれば2のn乗種類のモジュールを識別することができる。   That is, as shown in FIG. 6, the PD terminals 17a and 17c to which the jumper chips 50a and 50c are connected are fixed to the ground potential (or Vcc potential), and the PD terminals 17b and 17d to which no jumper chips are connected are NC terminals (NO). Connection terminal), the microprocessor reads the state of these PD terminals 17a to 17d to determine the specification of the module, that is, the storage capacity and electrical characteristics of the module, for example, in a table held by itself. It can be known by referring to (memory). If there are four PD terminals, 16 types of modules can be identified, and if there are n PD terminals, 2 n types of modules can be identified.

図7には、上記メモリモジュールのブロック構成例を示す。この実施例のモジュールは、16個のダイナミックRAM D0〜D15(メモリIC20)と、ドライバB0〜B26とにより構成されている。上記ドライバB0〜B26は、半数ずつそれぞれ一つの半導体チップ上に形成されてIC化され、基板10上に実装される(図1のIC30)。上記ドライバB0〜B26は、複数のダイナミックRAMに共通の信号(OE,WE,CAS等)を各チップに伝達するのに使用される。   FIG. 7 shows an example of a block configuration of the memory module. The module of this embodiment includes 16 dynamic RAMs D0 to D15 (memory IC 20) and drivers B0 to B26. The drivers B0 to B26 are each formed on a single semiconductor chip in half, are formed into ICs, and are mounted on the substrate 10 (IC30 in FIG. 1). The drivers B0 to B26 are used to transmit signals (OE, WE, CAS, etc.) common to a plurality of dynamic RAMs to each chip.

このように、ドライバがモジュール側に設けられていることにより、これを駆動するCPUの側のドライバが不要となり、ユーザーはモジュールの種類ごとにドライバを設計する必要がなくなる。すなわち、仮にモジュール側にドライバがないとすると、使用するモジュールが変わるとそれを駆動するのに必要な駆動力も変わるので、いちいち最適なドライバを設計し直す必要があるが、上記実施例ではドライバがモジュール側に設けられているため、CPUの側のドライバが不要となる。   As described above, since the driver is provided on the module side, the driver on the CPU side for driving the module becomes unnecessary, and the user does not need to design a driver for each type of module. That is, if there is no driver on the module side, if the module to be used changes, the driving force required to drive the module also changes, so it is necessary to redesign the optimum driver each time. Since it is provided on the module side, a driver on the CPU side is unnecessary.

以上説明したように上記実施例は、絶縁基板の表裏に設けられる接栓端子を、互いに電気的に絶縁された別個の接栓端子となるように形成するようにしたので、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができる。あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができるという効果がある。   As described above, in the above embodiment, the plug terminals provided on the front and back sides of the insulating substrate are formed so as to be separate plug terminals electrically insulated from each other, so that the same size as the conventional one is used. Twice the number of plug terminals can be provided on the insulating substrate without changing the pitch. Alternatively, if the number of plug terminals is the same, the size of the insulating substrate can be reduced to approximately half.

さらに、絶縁基板の材料として低熱膨張率の材料を使用するとともに、TSOP(薄型スモール・アウトライン・パッケージ)構造のICとして実装させるようにしたので、SOJ構造のICに比べて絶縁基板に実装された状態でのICの高さを低くなってモジュールが小型化されるという効果がある。   Furthermore, since a material having a low coefficient of thermal expansion is used as the material of the insulating substrate, and it is mounted as an IC having a TSOP (thin small outline package) structure, it is mounted on an insulating substrate as compared with an IC having a SOJ structure. There is an effect that the height of the IC in the state is reduced and the module is downsized.

また、絶縁基板の表面側の接栓端子列と、裏面側の接栓端子列とを互いに半ピッチ分ずらして形成するようにしたので、それぞれの接栓端子列と接触するリード(コネクタ)を有するソケットを作りやすくなるという効果がある。   In addition, since the plug terminal row on the front side and the plug terminal row on the back side of the insulating substrate are formed so as to be shifted from each other by a half pitch, a lead (connector) contacting each plug terminal row is formed. This has the effect of making it easier to make a socket that has

さらに、絶縁基板の接栓端子列側の端面にノッチを設け、ソケットの対応する位置には上記ノッチに係合可能な突起を設けるようにしたので、誤った基板(モジュール)に挿入されてシステムが誤動作したり、モジュール内のICが破損されるのを防止することができる。   Further, a notch is provided on the end surface of the insulating substrate on the side of the connector terminal row, and a protrusion engageable with the notch is provided at a corresponding position of the socket, so that the system can be inserted into an incorrect substrate (module). Can be prevented from malfunctioning and the IC in the module can be prevented from being damaged.

また、絶縁基板の接栓端子列の一部に、複数の基板識別用端子(PD端子)を設けるとともに、これらの端子と電源端子間を選択的に短絡させるためのジャンパーチップを実装可能な接続端子を設けるようにしたので、異なる仕様の複数種のモジュールに対して基板の標準化を可能とし、トータルコストを低減することができるようになる。   A plurality of board identification terminals (PD terminals) are provided in a part of the connector terminal row of the insulating board, and a jumper chip for selectively short-circuiting these terminals and the power supply terminal can be mounted. Since the terminals are provided, it is possible to standardize the substrate for a plurality of types of modules having different specifications, thereby reducing the total cost.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば上記実施例では、絶縁基板の表面および裏面にそれぞれ複数のメモリICが実装されているが、複数のICが絶縁基板の表面または裏面の一方にのみ実装されたものであってもよい。   Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor. For example, in the above embodiment, a plurality of memory ICs are mounted on the front surface and the back surface of the insulating substrate, respectively, but a plurality of ICs may be mounted on only one of the front surface and the back surface of the insulating substrate.

以上の説明では主として本発明者によってなされた発明をその背景となった利用分野であるメモリモジュールに適用した場合について説明したがこの発明はそれに限定されるものでなく、メモリカードその他一枚の絶縁基板上に複数のICが実装された半導体実装基板に広く利用することができる。   In the above description, the case where the invention made by the present inventor is applied to a memory module, which is the field of application as the background, has been mainly described. However, the present invention is not limited to this case, and a memory card and other insulation It can be widely used for a semiconductor mounting substrate in which a plurality of ICs are mounted on a substrate.

本発明を適用したメモリモジュールの一実施例を示す平面図である。FIG. 3 is a plan view showing one embodiment of a memory module to which the present invention is applied. 図1のメモリモジュールの接栓端子部の拡大説明図である。FIG. 2 is an enlarged explanatory view of a plug terminal part of the memory module of FIG. 1. 図1のメモリモジュールのIC実装状態を示す拡大説明図である。FIG. 2 is an enlarged explanatory diagram illustrating an IC mounted state of the memory module in FIG. 1. 図1のメモリモジュールが装着されるソケットの一実施例を示す側面図である。FIG. 2 is a side view showing one embodiment of a socket to which the memory module of FIG. 1 is mounted. 図3のソケットの構造を示す拡大断面図である。FIG. 4 is an enlarged sectional view showing the structure of the socket of FIG. 3. PD端子とジャンパーチップとの関係を示す等化回路図である。FIG. 3 is an equalization circuit diagram illustrating a relationship between a PD terminal and a jumper chip. 図1のメモリモジュールの構成例を示すブロック図である。FIG. 2 is a block diagram illustrating a configuration example of a memory module in FIG. 1. 従来のメモリモジュールの接栓端子部の拡大説明図である。It is an enlarged explanatory view of the plug terminal part of the conventional memory module.

符号の説明Explanation of reference numerals

10 絶縁基板
11a,11b,11c 接栓端子
12a,12b メカニカルキーイン用のノッチ
13a,13b 抜け止め用のノッチ
17a〜17d PD端子
20 メモリIC
30 ドライバIC
40 ソケット
50a,50c ジャンパーチップ
DESCRIPTION OF SYMBOLS 10 Insulating board 11a, 11b, 11c Plug terminal 12a, 12b Notch for mechanical key-in 13a, 13b Notch for retaining 17a-17d PD terminal 20 Memory IC
30 Driver IC
40 socket 50a, 50c jumper chip

Claims (2)

互いに対向する第1及び第3の辺と、互いに対向する第2及び第4の辺とを有する矩形状の絶縁基板と、
前記第1の辺に沿って前記絶縁基板の表面側及び裏面側に互いに電気的に絶縁されて設けられた複数の接栓端子と、
前記絶縁基板に設けられた複数のメモリICと、
前記絶縁基板の前記第1の辺の略中央に設けられた誤挿入防止のためのメカニカルキーイン用ノッチとを備えたことを特徴とするメモリモジュール。
A rectangular insulating substrate having first and third sides facing each other and second and fourth sides facing each other;
A plurality of plug terminals provided electrically insulated from each other on the front side and the back side of the insulating substrate along the first side;
A plurality of memory ICs provided on the insulating substrate;
A memory module comprising: a mechanical key-in notch for preventing erroneous insertion, provided at a substantially center of the first side of the insulating substrate.
前記絶縁基板は、前記第1の辺に設けられた誤挿入防止のためのノッチに加えて、前記第2及び第4の辺にそれぞれ設けられた抜け止め用のノッチとを備えることを特徴とする請求項1記載のメモリモジュール。   The insulating substrate includes a notch for preventing erroneous insertion provided on the first side, and a notch for retaining provided on each of the second and fourth sides. The memory module according to claim 1, wherein:
JP2004030004A 2004-02-06 2004-02-06 Memory module Expired - Lifetime JP3713034B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004030004A JP3713034B2 (en) 2004-02-06 2004-02-06 Memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004030004A JP3713034B2 (en) 2004-02-06 2004-02-06 Memory module

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP10293237A Division JPH11195749A (en) 1993-06-25 1998-10-15 Semiconductor mounting device

Publications (2)

Publication Number Publication Date
JP2004213682A true JP2004213682A (en) 2004-07-29
JP3713034B2 JP3713034B2 (en) 2005-11-02

Family

ID=32822060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004030004A Expired - Lifetime JP3713034B2 (en) 2004-02-06 2004-02-06 Memory module

Country Status (1)

Country Link
JP (1) JP3713034B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008023839A1 (en) * 2006-08-24 2008-02-28 Polyplastics Co., Ltd. Asymmetric electronic component
US7733680B2 (en) 2006-12-29 2010-06-08 Samsung Electronics Co., Ltd. Non-volatile memory module for preventing system failure and system including the same
JP2012022463A (en) * 2010-07-13 2012-02-02 Ricoh Co Ltd Communication unit, information equipment, and information system
EP3401937A1 (en) * 2017-05-10 2018-11-14 General Electric Technology GmbH Improvements in or relating to protection relays

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4538350B2 (en) 2005-03-18 2010-09-08 富士フイルム株式会社 Photosensitive composition, image recording material, and image recording method
JP4777226B2 (en) 2006-12-07 2011-09-21 富士フイルム株式会社 Image recording materials and novel compounds
JP4860525B2 (en) 2007-03-27 2012-01-25 富士フイルム株式会社 Curable composition and planographic printing plate precursor
EP2048539A1 (en) 2007-09-06 2009-04-15 FUJIFILM Corporation Processed pigment, pigment-dispersed composition, colored photosensitive composition, color filter, liquid crystal display element, and solid image pickup element
JP2009091555A (en) 2007-09-18 2009-04-30 Fujifilm Corp Curable composition, image forming material and planographic printing plate precursor
EP2042928B1 (en) 2007-09-28 2010-07-28 FUJIFILM Corporation Negative-working photosensitive material and negative-working planographic printing plate precursor
JP4890408B2 (en) 2007-09-28 2012-03-07 富士フイルム株式会社 Polymerizable composition, lithographic printing plate precursor using the same, alkali-soluble polyurethane resin, and method for producing diol compound
WO2009116442A1 (en) 2008-03-17 2009-09-24 富士フイルム株式会社 Pigment-dispersed composition, colored photosensitive composition, photocurable composition, color filter, liquid crystal display element, and solid image pickup element
US7923197B2 (en) 2008-03-25 2011-04-12 Fujifilm Corporation Lithographic printing plate precursor
JP5444933B2 (en) 2008-08-29 2014-03-19 富士フイルム株式会社 Negative-type planographic printing plate precursor and planographic printing method using the same
JP5554106B2 (en) 2009-03-31 2014-07-23 富士フイルム株式会社 Colored curable composition, method for producing color filter, color filter, solid-state imaging device, and liquid crystal display device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008023839A1 (en) * 2006-08-24 2008-02-28 Polyplastics Co., Ltd. Asymmetric electronic component
JPWO2008023839A1 (en) * 2006-08-24 2010-01-14 ポリプラスチックス株式会社 Asymmetric electronic components
US7980897B2 (en) 2006-08-24 2011-07-19 Polyplastics Co., Ltd. Asymmetric electronic parts
JP5385609B2 (en) * 2006-08-24 2014-01-08 ポリプラスチックス株式会社 Method for producing liquid crystalline polyester composition
US7733680B2 (en) 2006-12-29 2010-06-08 Samsung Electronics Co., Ltd. Non-volatile memory module for preventing system failure and system including the same
JP2012022463A (en) * 2010-07-13 2012-02-02 Ricoh Co Ltd Communication unit, information equipment, and information system
EP3401937A1 (en) * 2017-05-10 2018-11-14 General Electric Technology GmbH Improvements in or relating to protection relays
WO2018206283A1 (en) * 2017-05-10 2018-11-15 General Electric Technology Gmbh Improvements in or relating to protection relays
US11223165B2 (en) 2017-05-10 2022-01-11 General Electric Technology Gmbh Or relating to protection relays

Also Published As

Publication number Publication date
JP3713034B2 (en) 2005-11-02

Similar Documents

Publication Publication Date Title
JP3713034B2 (en) Memory module
JP4689674B2 (en) Male / female socket / adapter
US7768796B2 (en) Die module system
EP0767495B1 (en) Surface-mounting type semiconductor device
US7508061B2 (en) Three-dimensional semiconductor module having multi-sided ground block
US7227247B2 (en) IC package with signal land pads
US20060125067A1 (en) Flex circuit constructions for high capacity circuit module systems and methods
JP2008541293A (en) Memory module system and method
US7547213B2 (en) Memory modules and methods for manufacturing memory modules
TW200822331A (en) A differential I/O spline for inexpensive breakout and excellent signal quality
US7863089B2 (en) Planar array contact memory cards
US7771206B2 (en) Horizontal dual in-line memory modules
KR20070094572A (en) Memory module having a cooling means, method for producing the memory module having a cooling means, and data processing device comprising a memory module having a cooling means
JP3099051B2 (en) Semiconductor mounting equipment
US9155194B1 (en) Memory interconnect arrangement having high data transfer speed signal integrity
JP2000031617A (en) Memory module and its manufacture
JPH09289052A (en) Packaged structure of module
US8747132B1 (en) Printed circuit board injector/ejector mechanism
JP2005166892A (en) Stack type small-sized memory card
US6837721B2 (en) Detachable connector device
JP4402806B2 (en) Semiconductor device
JPH113955A (en) Semiconductor chip mounting board
KR100353537B1 (en) Interconnection structure between rambus dram inline memory modules using bridge pcb with improved thermal emission property
JP2005166891A (en) Small-sized memory card
KR20070082136A (en) Semiconductor module having auxiliary substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040305

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20041214

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050209

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050811

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050818

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080826

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090826

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100826

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100826

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110826

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120826

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120826

Year of fee payment: 7

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120826

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120826

Year of fee payment: 7

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120826

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130826

Year of fee payment: 8

EXPY Cancellation because of completion of term