JP3713034B2 - Memory module - Google Patents

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JP3713034B2
JP3713034B2 JP2004030004A JP2004030004A JP3713034B2 JP 3713034 B2 JP3713034 B2 JP 3713034B2 JP 2004030004 A JP2004030004 A JP 2004030004A JP 2004030004 A JP2004030004 A JP 2004030004A JP 3713034 B2 JP3713034 B2 JP 3713034B2
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insulating substrate
terminals
substrate
memory
plug
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JP2004213682A (en
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利夫 管野
誠一郎 津久井
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Hitachi Ltd
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本発明は、IC実装技術さらには接栓端子列を有する半導体実装絶縁基板に適用して特に有効な技術に関し、例えば複数個のメモリICを高密度に搭載したソケット実装タイプのメモリモジュールに利用して有効な技術に関する。   The present invention relates to an IC mounting technique, and more particularly to a technique that is particularly effective when applied to a semiconductor mounting insulating substrate having a connector terminal array. Related to effective technology.

近年、一辺に接栓端子列を有する絶縁基板上に複数個のメモリICを高密度に実装してなるメモリモジュールが、ノートパソコン等の小型電子機器向けに開発されている。従来のメモリモジュールにおける接栓端子列は、実装用絶縁基板10の表裏に銅めっきを施した後、エッチングにより図8に示すように、基板の一辺に沿って同一形状の接栓端子11a,11b………および11a’,11b’………を基板表裏にそれぞれ形成し、各接栓端子11の基端部と基板を貫通するようにドリルで穴あけを行なってスルーホール15を形成し、各接栓端子11の表面から上記スルーホール15の内面にかけて銅めっきを施すことで、基板表裏の対応する接栓端子11間を電気的に接続した構造とされていた。   In recent years, a memory module in which a plurality of memory ICs are mounted at a high density on an insulating substrate having a connection terminal row on one side has been developed for small electronic devices such as notebook computers. In the conventional plug terminal array in the memory module, the front and back surfaces of the mounting insulating substrate 10 are subjected to copper plating, and then etched to have the same shape of the plug terminals 11a and 11b along one side of the substrate as shown in FIG. ... and 11a ', 11b' ......... are formed on the front and back sides of the substrate, respectively, and a through hole 15 is formed by drilling so as to penetrate the base end of each plug terminal 11 and the substrate. Copper plating was applied from the surface of the plug terminal 11 to the inner surface of the through hole 15 so that the corresponding plug terminals 11 on the front and back of the substrate were electrically connected.

しかしながら、上述した技術には、次のような問題のあることが本発明者らによってあきらかとされた。
すなわち、従来のソケット実装タイプのメモリモジュールでは、実装用絶縁基板に設けられる接栓端子のピッチが2.54mmあるいは1.27mmで標準化されていたため、ある大きさの基板に設けることができる接栓端子の数に制約があった。言い換えると、必要な接栓端子数を確保しようとすると、基板の外形寸法が接栓端子数によって律速されてしまうという問題点があった。
However, the present inventors have revealed that the above-described technique has the following problems.
That is, in the conventional socket mounting type memory module, since the pitch of the plug terminals provided on the mounting insulating substrate is standardized at 2.54 mm or 1.27 mm, the plug can be provided on a certain size of the board. There were restrictions on the number of terminals. In other words, there has been a problem that, when trying to secure the necessary number of plug terminals, the outer dimensions of the substrate are limited by the number of plug terminals.

本発明は、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができるような構造の基板を用いたモジュールを提供することを目的とする。あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができるような基板構造およびそのような構造の基板を用いたモジュールを提供することを目的とする。
本発明の前記並びにその他の目的と新規な特徴については、本明細書の記述および添付図面から明らかになるであろう。
SUMMARY OF THE INVENTION An object of the present invention is to provide a module using a substrate having a structure in which a double number of plug terminals can be provided on an insulating substrate having the same size as the conventional one without changing the pitch. Alternatively, an object of the present invention is to provide a substrate structure in which the size of an insulating substrate can be approximately halved if the number of connecting terminals is the same, and a module using the substrate having such a structure.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を説明すれば、下記のとおりである。
すなわち、絶縁基板の表裏に設けられる接栓端子を、互いに電気的に絶縁された別個の接栓端子となるように形成するようにしたものである。
具体的には、互いに対向する第1及び第3の辺と、互いに対向する第2及び第4の辺とを有する矩形状の絶縁基板と、前記第1の辺に沿って前記絶縁基板の表面側及び裏面側に互いに電気的に絶縁されて設けられた複数の接栓端子と、前記絶縁基板に設けられ、複数のメモリと前記複数のメモリに共通信号を伝達するドライバとを含む複数の半導体装置と、前記絶縁基板に設けられ、前記半導体装置と前記接栓端子とを電気的に接続する配線とを備えた半導体実装装置としたものである。
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, the plug terminals provided on the front and back of the insulating substrate are formed to be separate plug terminals that are electrically insulated from each other.
Specifically, a rectangular insulating substrate having first and third sides facing each other and second and fourth sides facing each other, and a surface of the insulating substrate along the first side A plurality of semiconductor terminals including a plurality of plug terminals electrically insulated from each other on the side and the back side, a plurality of memories provided on the insulating substrate, and a driver for transmitting a common signal to the plurality of memories The semiconductor mounting apparatus includes a device and a wiring provided on the insulating substrate and electrically connecting the semiconductor device and the plug terminal.

上記した手段によれば、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができ、あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができる。   According to the above means, it is possible to provide twice the number of plug terminals without changing the pitch on the same size insulating substrate as before, or if the number of plug terminals is the same, The size can be halved.

さらに、前記絶縁基板において、前記第1の辺に誤挿入防止のためのノッチを、前記第2及び第4の辺にそれぞれ抜け止め用のノッチを設けることが望ましい。これによって、前記絶縁基板をソケットに装着する際の誤挿入を防止できるとともに、基板装着後、基板の抜け止めを行えるようになっている。   Further, in the insulating substrate, it is preferable that notches for preventing erroneous insertion are provided on the first side, and notches for retaining are respectively provided on the second and fourth sides. As a result, it is possible to prevent erroneous insertion when the insulating substrate is mounted on the socket, and to prevent the substrate from coming off after the substrate is mounted.

また、長方形の絶縁基板と、前記絶縁基板の1つの長辺に沿って前記絶縁基板の両面に電気的に互いに絶縁して設けられた複数の接栓端子と、前記絶縁基板に設けられた複数の半導体装置と、前記絶縁基板上に設けられ、前記半導体装置と前記接栓端子とを電気的に接続する配線とを備え、前記接栓端子は基板識別用の端子を含む半導体実装装置としてもよい。これによって、異なる仕様の複数種のモジュールに対して基板の標準化を可能とし、トータルコストを低減することができるようになる。   Also, a rectangular insulating substrate, a plurality of plug terminals provided on both surfaces of the insulating substrate along one long side of the insulating substrate, and a plurality of plug terminals provided on the insulating substrate And a wiring board that is provided on the insulating substrate and electrically connects the semiconductor device and the plug terminal, and the plug terminal includes a terminal for identifying the substrate. Good. This makes it possible to standardize substrates for a plurality of types of modules with different specifications, thereby reducing the total cost.

さらに、前記絶縁基板の場合も、前記絶縁基板の長辺に誤挿入防止のためのノッチを、前記絶縁基板の2つの短辺にそれぞれ抜け止め用のノッチを設けるとよい。これによって、前記絶縁基板をソケットに装着する際誤挿入を防止できるとともに、基板装着後、基板の抜け止めを行うことができる。   Further, also in the case of the insulating substrate, it is preferable to provide a notch for preventing erroneous insertion on the long side of the insulating substrate, and a notch for preventing the slipping on the two short sides of the insulating substrate. Accordingly, it is possible to prevent erroneous insertion when the insulating substrate is attached to the socket, and it is possible to prevent the substrate from being detached after the substrate is attached.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記のとおりである。
すなわち、ICが実装される絶縁基板に、ピッチを変えることなく従来の2倍の数の接栓端子を設けることができ、あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができる。
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, it is possible to provide twice the number of conventional plug terminals on the insulating substrate on which the IC is mounted without changing the pitch, or if the number of plug terminals is the same, the size of the insulating substrate is approximately the same. Can be halved.

以下、本発明の好適な実施例を図面に基づいて説明する。   Preferred embodiments of the present invention will be described below with reference to the drawings.

図1〜図3には、本発明を適用したメモリモジュールの一実施例が示されている。この実施例のメモリモジュールは、絶縁基板10の表面と裏面にそれぞれ8個のメモリIC20と1個のドライバIC30が搭載されており、上記絶縁基板10の表裏には基板の一辺に沿って同一形状の接栓端子11a,11b,11c………が、等ピッチPでそれぞれ形成されている。絶縁基板10の表側の接栓端子11a,11b,11c………と、裏側の接栓端子11a’,11b’,11c’………とは、互いに電気的に絶縁されている。しかもこの実施例では、特に制限されないが、絶縁基板10の表側の接栓端子11a,11b,11c………と、裏側の接栓端子11a’,11b’,11c’………とは、図2に示すごとく、互いに位置が半ピッチP/2だけずれるように形成されている。   1 to 3 show an embodiment of a memory module to which the present invention is applied. In the memory module of this embodiment, eight memory ICs 20 and one driver IC 30 are mounted on the front and back surfaces of the insulating substrate 10 respectively, and the same shape is formed on the front and back of the insulating substrate 10 along one side of the substrate. Are formed at an equal pitch P. The plug terminals 11a, 11b, 11c,. The front-side plug terminals 11a, 11b, 11c,... Of the insulating substrate 10 and the back-side plug terminals 11a ', 11b', 11c ', ... are electrically insulated from each other. Moreover, in this embodiment, although not particularly limited, the front side plug terminals 11a, 11b, 11c,... And the back side plug terminals 11a ′, 11b ′, 11c ′,. As shown in FIG. 2, the positions are shifted from each other by a half pitch P / 2.

上記絶縁基板10は、それぞれ表面に導電層からなる配線パターンが形成されてなる複数(例えば6枚)の絶縁性基板が積層された多層構造とされている。また、この実施例では、上記絶縁基板10の材料としてFR−5と呼ばれる熱膨張率が10ppm程度の高TG材料(軟化温度の高いガラス)が使用されている。これによって、TSOP(薄型スモール・アウトライン・パッケージ)構造のメモリIC20が実装可能にされる。   The insulating substrate 10 has a multilayer structure in which a plurality of (for example, six) insulating substrates each having a wiring pattern formed of a conductive layer on the surface are laminated. In this embodiment, as the material of the insulating substrate 10, a high TG material (glass with a high softening temperature) called FR-5 having a thermal expansion coefficient of about 10 ppm is used. As a result, the memory IC 20 having a TSOP (thin small outline package) structure can be mounted.

すなわち、従来一般的に使用されていたFR−4と呼ばれるガラスエポキシ等からなる基板にあっては、熱膨張率が16ppm程度であるため、はんだ接合部の熱膨張率が5ppm程度であるTSOP(薄型スモール・アウトライン・パッケージ)構造のメモリICを使用すると、熱サイクル等によりはんだ接合部が剥がれたりするおそれがあるため、はんだ接合部の熱膨張率が10ppm程度であるSOJ構造のメモリICを実装せざるを得なかった。   That is, since the thermal expansion coefficient of a substrate made of glass epoxy or the like called FR-4, which has been generally used in the past, is about 16 ppm, the thermal expansion coefficient of the solder joint is about 5 ppm. If a memory IC with a thin small outline package) structure is used, the solder joint may peel off due to thermal cycling, etc., so a memory IC with an SOJ structure with a solder joint thermal expansion coefficient of about 10 ppm is mounted. I had to do it.

しかるに、本実施例では、基板10の材料として熱膨張率が10ppm程度の高TG材料を使用しているため、リード端子が外側に拡がるように折曲された熱膨張率が5ppm程度のTSOP(薄型スモール・アウトライン・パッケージ)構造のメモリICを使用することができるようになった。その結果、基板に実装された状態でのICの高さが低くなって、モジュールが小型化できるようになった。   However, in this embodiment, since a high TG material having a thermal expansion coefficient of about 10 ppm is used as the material of the substrate 10, the TSOP having a thermal expansion coefficient of about 5 ppm bent so that the lead terminal expands to the outside is used. A memory IC having a thin small outline package) structure can be used. As a result, the height of the IC when mounted on the substrate is lowered, and the module can be miniaturized.

さらに、この実施例では、絶縁基板10の所定の位置に、互いにリード端子が逆方向に曲げられたメモリIC20がはんだ付けされている。すなわち、絶縁基板10の表側に実装されたメモリIC20は、図3に示すように、リード端子21がICの腹の側に向かって曲げられており、絶縁基板10の裏側に実装されたメモリIC20’はリード端子21’がICの背の側に向かって曲げられている。これによって、表面のICと裏面のICの信号端子が同一位置に来るようになるので、基板10の表面に形成すべき配線パターンの共用化が可能になるとともに、最短距離の配線形成が容易となる。そのため、配線パターンの設計が容易となるとともに、配線同士の交差箇所を減らすことができ、配線が簡素化されてモジュールの特性および品質が向上する。   Furthermore, in this embodiment, a memory IC 20 in which lead terminals are bent in opposite directions is soldered to a predetermined position of the insulating substrate 10. That is, the memory IC 20 mounted on the front side of the insulating substrate 10 has the lead terminals 21 bent toward the antinode side of the IC, as shown in FIG. 3, and the memory IC 20 mounted on the back side of the insulating substrate 10. The lead terminal 21 'is bent toward the back side of the IC. As a result, the signal terminals of the IC on the front surface and the IC on the back surface come to the same position, so that it is possible to share the wiring pattern to be formed on the surface of the substrate 10 and to easily form the wiring with the shortest distance. Become. Therefore, the design of the wiring pattern is facilitated, the number of intersections between the wirings can be reduced, the wiring is simplified, and the characteristics and quality of the module are improved.

上記絶縁基板10の接栓端子11が形成された辺とこれに直交する2辺には、図1に示すように、それぞれノッチ12a,12bおよび13a,13bが形成されている。このうち接栓端子が形成された辺上のノッチ12aと12bは、誤挿入を防止するためのメカニカルキーイン用のノッチ(凹部)とされ、13a,13bは抜け止め用のノッチとされる。   As shown in FIG. 1, notches 12a, 12b and 13a, 13b are respectively formed on the side of the insulating substrate 10 where the plug terminal 11 is formed and on two sides orthogonal thereto. Of these, notches 12a and 12b on the side where the contact terminal is formed are mechanical key-in notches (recesses) for preventing erroneous insertion, and 13a and 13b are notches for retaining.

すなわち、この実施例の絶縁基板10は、図4に示されているようなソケット40に装着される適した構造とされている。   That is, the insulating substrate 10 of this embodiment has a suitable structure to be mounted on the socket 40 as shown in FIG.

次に、ソケット40の一実施例について説明する。
絶縁基板10が装着されるソケット40は、前記接栓端子11a,11b,11c………および11a,11b,11c………と11a’,11b’,11c’………の数に対応した端子ピン41a,41b,41c………を外側に有し、内側には上記ノッチ12a,12bに対応した位置にそれぞれ上記ノッチと係合可能な突起42a,42bを有している。
Next, an embodiment of the socket 40 will be described.
The socket 40 to which the insulating substrate 10 is attached is a terminal corresponding to the number of the plug terminals 11a, 11b, 11c... And 11a, 11b, 11c... And 11a ′, 11b ′, 11c ′. Pins 41a, 41b, 41c,... Are provided on the outer side, and projections 42a, 42b that can be engaged with the notches are provided on the inner side at positions corresponding to the notches 12a, 12b.

また、上記各端子ピン41a,41b,41c………には、図5に示すように、上記各接栓端子11と接触可能な弾性片からなるリード43がそれぞれ一体に形成されており、それらがソケットのハウジング44内に接栓端子のピッチPの半分のピッチP/2で保持されている。各リード43は互いに離間されているとともに、リード43は、図5に実線Aで示されているようなやや下向きのリードと二点鎖線Bで示されているようなやや上向きのリードとが交互に配置されることにより、互いに基板10の厚みとより少し狭い間隔をおいて向き合う係合部を構成している。絶縁基板10は、矢印C方向から接栓端子部を上記リード43により構成される係合部に挿入し、矢印D方向へ回動させることにより装着される。   Each of the terminal pins 41a, 41b, 41c,... Is integrally formed with a lead 43 made of an elastic piece that can come into contact with each of the plug terminals 11, as shown in FIG. Is held in the socket housing 44 at a pitch P / 2 which is half the pitch P of the plug terminal. The leads 43 are spaced apart from each other, and the lead 43 has a slightly downward lead as shown by a solid line A and a slightly upward lead as shown by a two-dot chain line B in FIG. By disposing, the engaging portions are opposed to each other with a slightly narrower distance from the thickness of the substrate 10. The insulating substrate 10 is mounted by inserting the plug terminal portion into the engaging portion constituted by the lead 43 from the direction of arrow C and rotating it in the direction of arrow D.

ソケット40の両端には、図4に示すように、先端部にそれぞれ突起47a,47bを有する一対の保持アーム45a,45bがピン46a,46bを支点として回転自在に取り付けられており、上記リード43に上記絶縁基板10を装着した後に、上記保持アーム45a,45bを内側に回動させ、基板10の側面のノッチ13a,13bに突起47a,47bを係合させることで、基板の抜け止めを行なえるようになっている。   As shown in FIG. 4, a pair of holding arms 45a and 45b having protrusions 47a and 47b at the tip end portions are attached to both ends of the socket 40 so as to be rotatable about the pins 46a and 46b. After attaching the insulating substrate 10 to the substrate 10, the holding arms 45 a and 45 b are rotated inward, and the protrusions 47 a and 47 b are engaged with the notches 13 a and 13 b on the side surface of the substrate 10, thereby preventing the substrate from coming off. It has become so.

さらに、保持アーム45a,45bには内側に向けて作動片48a,48bが形成されており、上記ピン46a,46bを支点としてそれぞれ外側へ回動させたとき、上記作動片48a,48bが装着されている基板10を押し出して離脱させるように構成されている。これによって、端子密度が増大し取外しが困難になった基板10とソケット40との結合を、保持アーム45a,45bの操作によるてこの原理で簡単に外すことができるようになる。   Furthermore, operating pieces 48a and 48b are formed inwardly on the holding arms 45a and 45b, and the operating pieces 48a and 48b are mounted when the pins 46a and 46b are rotated outward with the pins 46a and 46b as fulcrums, respectively. The substrate 10 is pushed out and separated. As a result, the connection between the board 10 and the socket 40, which has become difficult to remove due to an increase in the terminal density, can be easily removed based on this principle by operating the holding arms 45a and 45b.

さらに、この実施例の絶縁基板10には、基板識別用のPD端子17a,17b,17c,17dと、ジャンパーチップ接続端子18a,18b,18c,18dと、グランド端子(もしくはVcc端子)19a,19b,19c,19dが基板表面に、また上記PD端子17a,17b,17c,17dをジャンパーチップ接続端子18a,18b,18c,18dに接続するための配線パターン50が、図1に破線で示すように、内部配線層に設けられており、上記PD端子17a,17b,17c,17dおよびグランド端子(もしくはVcc端子)19a,19b,19c,19d間に、それらを短絡するための導電体(0Ωの抵抗)を有するジャンパーチップ50a,50c………が選択的に接続されるようになっている。ジャンパーチップ50a,50c………は、仕様の異なるモジュールを識別するためのコードを発生するために使用される。   Further, the insulating substrate 10 of this embodiment includes substrate identification PD terminals 17a, 17b, 17c and 17d, jumper chip connection terminals 18a, 18b, 18c and 18d, and ground terminals (or Vcc terminals) 19a and 19b. , 19c, 19d on the surface of the substrate, and a wiring pattern 50 for connecting the PD terminals 17a, 17b, 17c, 17d to the jumper chip connection terminals 18a, 18b, 18c, 18d is shown by broken lines in FIG. A conductor (0Ω resistance) for short-circuiting between the PD terminals 17a, 17b, 17c, 17d and the ground terminals (or Vcc terminals) 19a, 19b, 19c, 19d. Jumper chips 50a, 50c,. The jumper chips 50a, 50c,... Are used to generate codes for identifying modules having different specifications.

すなわち、図6に示すように、ジャンパーチップ50a,50cが接続されたPD端子17a,17cはグランド電位(もしくはVcc電位)に固定され、ジャンパーチップが接続されないPD端子17b,17dはNC端子(ノオ・コネクション端子)となるため、これらのPD端子17a〜17dの状態をマイクロプロセッサが読み込むことでどのような仕様のモジュールであるか、つまりモジュールの記憶容量や電気的特性を例えば自己の保有するテーブル(メモリ)を参照することで知ることができる。上記PD端子が4個あれば16種類、n個あれば2のn乗種類のモジュールを識別することができる。   That is, as shown in FIG. 6, the PD terminals 17a and 17c to which the jumper chips 50a and 50c are connected are fixed to the ground potential (or Vcc potential), and the PD terminals 17b and 17d to which the jumper chips are not connected are NC terminals (noon). A connection terminal), the microprocessor reads the state of the PD terminals 17a to 17d to determine what type of module it is, that is, the table of its own storage capacity and electrical characteristics, for example. This can be known by referring to (memory). If there are four PD terminals, 16 types of modules can be identified, and if n, 2 n types of modules can be identified.

図7には、上記メモリモジュールのブロック構成例を示す。この実施例のモジュールは、16個のダイナミックRAM D0〜D15(メモリIC20)と、ドライバB0〜B26とにより構成されている。上記ドライバB0〜B26は、半数ずつそれぞれ一つの半導体チップ上に形成されてIC化され、基板10上に実装される(図1のIC30)。上記ドライバB0〜B26は、複数のダイナミックRAMに共通の信号(OE,WE,CAS等)を各チップに伝達するのに使用される。   FIG. 7 shows a block configuration example of the memory module. The module of this embodiment is composed of 16 dynamic RAMs D0 to D15 (memory IC 20) and drivers B0 to B26. Each of the drivers B0 to B26 is formed on one semiconductor chip by half and formed into an IC, and mounted on the substrate 10 (IC30 in FIG. 1). The drivers B0 to B26 are used to transmit signals (OE, WE, CAS, etc.) common to a plurality of dynamic RAMs to each chip.

このように、ドライバがモジュール側に設けられていることにより、これを駆動するCPUの側のドライバが不要となり、ユーザーはモジュールの種類ごとにドライバを設計する必要がなくなる。すなわち、仮にモジュール側にドライバがないとすると、使用するモジュールが変わるとそれを駆動するのに必要な駆動力も変わるので、いちいち最適なドライバを設計し直す必要があるが、上記実施例ではドライバがモジュール側に設けられているため、CPUの側のドライバが不要となる。   As described above, since the driver is provided on the module side, a driver on the CPU side that drives the driver is unnecessary, and the user does not need to design a driver for each type of module. In other words, if there is no driver on the module side, the driving force required to drive the module changes when the module to be used changes. Therefore, it is necessary to redesign the optimum driver. Since it is provided on the module side, a driver on the CPU side becomes unnecessary.

以上説明したように上記実施例は、絶縁基板の表裏に設けられる接栓端子を、互いに電気的に絶縁された別個の接栓端子となるように形成するようにしたので、従来と同一の大きさの絶縁基板にピッチを変えることなく2倍の数の接栓端子を設けることができる。あるいは、接栓端子の数が同一ならば絶縁基板の大きさをおよそ半分にすることができるという効果がある。   As described above, in the above embodiment, the plug terminals provided on the front and back of the insulating substrate are formed so as to be separate plug terminals that are electrically insulated from each other. It is possible to provide twice as many plug terminals on the insulating substrate without changing the pitch. Alternatively, if the number of plug terminals is the same, there is an effect that the size of the insulating substrate can be halved.

さらに、絶縁基板の材料として低熱膨張率の材料を使用するとともに、TSOP(薄型スモール・アウトライン・パッケージ)構造のICとして実装させるようにしたので、SOJ構造のICに比べて絶縁基板に実装された状態でのICの高さを低くなってモジュールが小型化されるという効果がある。   In addition, a low thermal expansion material was used as the insulating substrate material, and it was mounted as an IC with a TSOP (thin small outline package) structure, so it was mounted on an insulating substrate compared to an SOJ structure IC. There is an effect that the module is miniaturized by reducing the height of the IC in the state.

また、絶縁基板の表面側の接栓端子列と、裏面側の接栓端子列とを互いに半ピッチ分ずらして形成するようにしたので、それぞれの接栓端子列と接触するリード(コネクタ)を有するソケットを作りやすくなるという効果がある。   In addition, since the plug terminal row on the front surface side and the plug terminal row on the back surface side of the insulating substrate are formed so as to be shifted from each other by a half pitch, leads (connectors) that come into contact with the respective plug terminal rows are formed. There is an effect that it is easy to make a socket having.

さらに、絶縁基板の接栓端子列側の端面にノッチを設け、ソケットの対応する位置には上記ノッチに係合可能な突起を設けるようにしたので、誤った基板(モジュール)に挿入されてシステムが誤動作したり、モジュール内のICが破損されるのを防止することができる。   Furthermore, since a notch is provided on the end surface of the insulating substrate on the side of the terminal block, and a protrusion that can be engaged with the notch is provided at a corresponding position of the socket, the system is inserted into an incorrect substrate (module). Can be prevented from malfunctioning, and the IC in the module can be prevented from being damaged.

また、絶縁基板の接栓端子列の一部に、複数の基板識別用端子(PD端子)を設けるとともに、これらの端子と電源端子間を選択的に短絡させるためのジャンパーチップを実装可能な接続端子を設けるようにしたので、異なる仕様の複数種のモジュールに対して基板の標準化を可能とし、トータルコストを低減することができるようになる。   In addition, a plurality of board identification terminals (PD terminals) are provided in a part of the plug terminal array of the insulating board, and a jumper chip for selectively short-circuiting between these terminals and the power supply terminals can be mounted. Since the terminals are provided, it is possible to standardize the board for a plurality of types of modules having different specifications, and to reduce the total cost.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば上記実施例では、絶縁基板の表面および裏面にそれぞれ複数のメモリICが実装されているが、複数のICが絶縁基板の表面または裏面の一方にのみ実装されたものであってもよい。   The invention made by the present inventor has been specifically described on the basis of the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, a plurality of memory ICs are mounted on the front and back surfaces of the insulating substrate, respectively, but a plurality of ICs may be mounted only on one of the front and back surfaces of the insulating substrate.

以上の説明では主として本発明者によってなされた発明をその背景となった利用分野であるメモリモジュールに適用した場合について説明したがこの発明はそれに限定されるものでなく、メモリカードその他一枚の絶縁基板上に複数のICが実装された半導体実装基板に広く利用することができる。   In the above description, the case where the invention made mainly by the present inventor is applied to the memory module which is the field of use as the background has been described. However, the present invention is not limited to this, and the memory card or other single insulation is used. It can be widely used for a semiconductor mounting substrate in which a plurality of ICs are mounted on a substrate.

本発明を適用したメモリモジュールの一実施例を示す平面図である。It is a top view which shows one Example of the memory module to which this invention is applied. 図1のメモリモジュールの接栓端子部の拡大説明図である。FIG. 2 is an enlarged explanatory view of a plug terminal portion of the memory module of FIG. 1. 図1のメモリモジュールのIC実装状態を示す拡大説明図である。FIG. 2 is an enlarged explanatory view showing an IC mounting state of the memory module of FIG. 1. 図1のメモリモジュールが装着されるソケットの一実施例を示す側面図である。FIG. 3 is a side view showing an embodiment of a socket in which the memory module of FIG. 1 is mounted. 図3のソケットの構造を示す拡大断面図である。It is an expanded sectional view which shows the structure of the socket of FIG. PD端子とジャンパーチップとの関係を示す等化回路図である。It is an equalization circuit diagram which shows the relationship between PD terminal and a jumper chip. 図1のメモリモジュールの構成例を示すブロック図である。FIG. 2 is a block diagram illustrating a configuration example of a memory module in FIG. 1. 従来のメモリモジュールの接栓端子部の拡大説明図である。It is an expansion explanatory view of the connection terminal part of the conventional memory module.

符号の説明Explanation of symbols

10 絶縁基板
11a,11b,11c 接栓端子
12a,12b メカニカルキーイン用のノッチ
13a,13b 抜け止め用のノッチ
17a〜17d PD端子
20 メモリIC
30 ドライバIC
40 ソケット
50a,50c ジャンパーチップ
DESCRIPTION OF SYMBOLS 10 Insulation board | substrate 11a, 11b, 11c Plug terminal 12a, 12b Notch 13a, 13b for mechanical key-in Notch 17a-17d for retaining prevention PD terminal 20 Memory IC
30 Driver IC
40 Socket 50a, 50c Jumper chip

Claims (2)

互いに対向する第1及び第3の辺と、互いに対向する第2及び第4の辺とを有する矩形状の絶縁基板と、
前記第1の辺に沿って前記絶縁基板の表面側及び裏面側に互いに電気的に絶縁されて設けられた複数の接栓端子と、
前記絶縁基板の表面と裏面にそれぞれ設けられた複数のメモリICと前記複数のメモリICに共通信号を伝達するドライバICとを含む複数の半導体装置と、
前記絶縁基板の前記第1の辺の略中央に設けられた誤挿入防止のためのメカニカルキーイン用ノッチとを備え
前記絶縁基板の表面に設けられたメモリICと前記絶縁基板の裏面に設けられたメモリICの対応する外部端子同士が、前記絶縁基板に形成された共通の配線パターンを介して前記絶縁基板の表面側または裏面側の接栓端子のいずれか一つの接栓端子に接続されてなることを特徴とするメモリモジュール。
A rectangular insulating substrate having first and third sides facing each other and second and fourth sides facing each other;
A plurality of plug terminals provided to be electrically insulated from each other on the front side and the back side of the insulating substrate along the first side;
A plurality of semiconductor devices including a plurality of memory ICs provided on the front surface and the back surface of the insulating substrate , respectively, and a driver IC that transmits a common signal to the plurality of memory ICs;
A mechanical key-in notch for preventing erroneous insertion provided in the approximate center of the first side of the insulating substrate ;
Corresponding external terminals of the memory IC provided on the surface of the insulating substrate and the memory IC provided on the back surface of the insulating substrate are connected to the surface of the insulating substrate via a common wiring pattern formed on the insulating substrate. A memory module characterized by being connected to any one of the plug terminals on the side or back side .
前記絶縁基板は、前記第1の辺に設けられた誤挿入防止のためのノッチに加えて、前記第2及び第4の辺にそれぞれ設けられた抜け止め用のノッチとを備えることを特徴とする請求項1記載のメモリモジュール。
The insulating substrate includes notches for preventing erroneous insertion provided on the first side and retaining notches provided on the second and fourth sides, respectively. The memory module according to claim 1.
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