JP2004200688A - Dram cell having mos capacitor, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DRAM cell having a MOS capacitor that prevents a leakage current loss and its manufacturing method. <P>SOLUTION: The DRAM cell includes a MOS capacitor 4 composed of a plate node electrode, a storage node electrode 114 and insulator membranes 110 and 111, and a cell transistor 3 comprising a gate insulating membrane 110, a gate electrode 112, and a source/drain 118 formed on the top surface of an active region. A structure on which the MOS capacitor 4 and the transistor 3 are formed has an interlayer insulating membrane 120, and a contact electrode 126 connects the source/drain 118 of the cell transistor 3 or the storage node electrode 114 of the MOS capacitor 4. A wiring 128 connects the drain and the storage node electrode 114 through contact electrodes 122 and 124. A bit line 130 connects the source through the contact electrode 126. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a DRAM cell and a method of manufacturing the same, and more particularly, to a DRAM cell having a MOS capacitor suitable for an electronic device such as a CD-R / W or a game device requiring a small amount of memory, and a method of manufacturing the same. It is.

  2. Description of the Related Art In general, a memory device refers to a device that can store data so that the data can be retrieved and viewed when needed. The memory device mainly includes a semiconductor memory centered on a DRAM (Dynamic Random Access Memory), a magnetic disk, an optical disk, and the like. There are various types. Among them, the semiconductor memory has advantages that it is compact, has high reliability, is inexpensive and can be manufactured, and can operate at a relatively high speed. Therefore, it is widely used as a main memory located in a computer, a built-in memory in a microprocessor, and a cache memory.

  A DRAM unit cell is connected to a word line driven by a row address, a bit line driven by a column address, a cell transistor having a drain connected to the bit line and a gate connected to the word line, and a source connected to the cell transistor. Consists of a capacitor.

  Reading / writing of such a DRAM cell operates as follows. When a word line is activated, a cell transistor connected to the word line is turned on, and charges are stored in a storage node electrode of a capacitor while a voltage of a bit line is applied through a drain of the cell transistor. At this time, 0V or Vdd (drive voltage) is supplied as a voltage applied to the bit line. A constant power supply voltage is supplied to the plate node electrode of the capacitor. However, the power supply voltage is about half of the drive voltage (Vdd) as a whole.

  On the other hand, when a MOS (Metal-Oxide-Silicon) capacitor is used in a DRAM cell, there is an advantage that a logic process can be used as it is as compared with a general stacked capacitor.

  FIG. 1 is a vertical sectional view showing a DRAM cell structure having a MOS capacitor according to the prior art. Referring to FIG. 1, a vertical sectional structure of a DRAM cell includes a semiconductor substrate 10, a well 12, an element isolation film 14, a gate insulating film 16 deposited on the entire surface of the substrate, and a gate insulating film 16 Through the gate electrode 18 of the cell transistor 3 and the plate node electrode 20 of the MOS capacitor 4, the source / drain 24 of the cell transistor 3 formed in the substrate, and the contact electrode 28 of the interlayer insulating film 26. It comprises a bit line 30 connected to a source / drain 24.

  In FIG. 1, the storage node electrode of the MOS capacitor 4 is a region of the well 12 located below the plate node electrode 20, and an insulator film between these electrodes is a gate insulating film 16. The gate electrode 18 of the cell transistor 3 is used as a word line.

  The DRAM cell having such a configuration is stored in the well 12 of the storage node of the MOS capacitor 4 connected to the source of the cell transistor 3 transmitting a signal. However, although the DRAM cell having the MOS capacitor has the advantage that the logic process can be used as it is in comparison with the stacked capacitor, data is stored in the well 12 used as a storage node. There is a problem that the refresh time is shortened.

  An object of the present invention to solve the problems of the prior art is to use a plate node electrode as an active region of a substrate and a storage node electrode as a T-shaped conductive pattern in a DRAM cell using a MOS capacitor. Accordingly, it is an object of the present invention to provide a DRAM cell having a MOS capacitor capable of increasing the capacitance of the MOS capacitor and preventing a leakage current loss when the storage node electrode is used in an active region.

  Another object of the present invention is to form a T-shaped storage node electrode in a trench in a substrate using a plate node electrode of a MOS capacitor as an active region of a substrate, thereby activating the storage node electrode while increasing the capacitance of the MOS capacitor. It is an object of the present invention to provide a method of manufacturing a DRAM cell having a MOS capacitor capable of preventing a leakage current loss occurring when used in a region.

  In order to achieve the above object, a DRAM cell having a MOS capacitor according to the present invention is driven by a word line driven by a row address and a column address in a DRAM cell having a cell transistor and a capacitor. A bit line, a cell transistor having a source connected to the bit line and a gate electrode connected to the word line, and a plate node formed on an active region of the semiconductor substrate having a storage node electrode connected to a drain of the cell transistor. An electrode, and a MOS capacitor having an insulating thin film between the storage node electrode and the plate node electrode.

  Here, the storage node electrode may have a T-shaped structure through a trench of the active region.

  Preferably, a power line to which a power voltage is supplied is connected to the plate node electrode.

  In order to achieve another object of the present invention, a DRAM cell having a MOS capacitor according to the present invention is a DRAM cell having a cell transistor and a capacitor, wherein an active region of a semiconductor substrate and a plate node which is a part of the active region are provided. An electrode, a storage node electrode having a T-shaped structure through the trench of the active region, a MOS capacitor comprising an insulating thin film between the plate node electrode and the storage node electrode, and a gate formed on an upper surface of the active region An insulating film and a gate electrode, a cell transistor including a source / drain formed in the active region, an interlayer insulating film deposited on the structure where the MOS capacitor and the cell transistor are formed, and an interlayer insulating film. Through the contact hole, the source of the cell transistor A contact electrode connected to the storage node electrode of the MOS capacitor, a wiring connecting the drain to the storage node electrode through the contact electrode, and a bit line connected to the source through the contact electrode. Features.

  Here, the MOS capacitor may further include a filling layer filling a lower portion of the trench with an insulating material.

  Also, a power supply line to which a power supply voltage is supplied through another contact electrode of the interlayer insulating film may be connected to the plate node electrode.

  Further, it is preferable that the trench of the MOS capacitor is a bent trench connected to at least one or more.

  The storage node electrode of the MOS capacitor and the gate electrode of the cell transistor preferably further include a side well spacer on a side wall.

  According to another aspect of the present invention, there is provided a method of manufacturing a DRAM cell having a MOS capacitor, comprising: forming a trench in a part of an active region of a semiconductor substrate in the method of manufacturing a DRAM cell having a cell transistor and a capacitor; Performing a step of implanting impurities into the active region, forming an insulating thin film and forming a gate insulating film on the entire surface of the substrate on which the trench is formed, and embedding the trench in the resultant. Depositing a conductive film and patterning the same to form a storage node electrode having the T-shaped structure and forming a gate electrode of the cell transistor; and implanting impurities into the resultant to form the cell. Forming a source / drain of the transistor and forming an interlayer insulating film on the entire surface of the resultant structure; Forming a contact hole in the interlayer insulating film, burying a conductive film in the contact hole to form a contact electrode connected to a source / drain of the cell transistor or a storage node electrode of the MOS capacitor; Depositing a conductive film on top of the substrate, patterning the conductive film, and forming a bit line connecting the source and a line connecting the drain and the storage node electrode through the contact electrode. .

  Here, it is preferable that the trench of the MOS capacitor is formed by a bent trench that connects at least one or more.

  In addition, before injecting impurities into the active region, it is preferable to further form a filling film for filling a lower portion of the trench with an insulating material.

  Preferably, the filling film is formed in a trench in a storage node region of the MOS capacitor or in a trench in an element isolation region of the semiconductor substrate.

  Further, it is preferable that the filling film formed in the trench in the storage node region of the MOS capacitor is buried to an upper surface or a certain portion of the trench.

  Preferably, before forming the source / drain of the cell transistor, a side well spacer is further formed on a sidewall of the storage node electrode of the MOS capacitor and a gate electrode of the cell transistor.

  Further, when depositing a conductive film on the interlayer insulating film and patterning the conductive film, a power supply line for supplying a power supply voltage to the plate node electrode through another contact electrode of the interlayer insulating film may be formed. preferable.

  According to the present invention, a plate node electrode to which power is supplied in a DRAM cell using a MOS capacitor is used as an active region of a substrate having a large parasitic resistance and capacitance, that is, a well, so that a signal speed can be improved.

  Further, according to the present invention, by using the storage node electrode of the MOS capacitor as the conductive film on the active region, it is possible to prevent the leakage current loss that occurs when the storage node electrode is used in the active region in the conventional DRAM cell. In addition, the cell read / write time can be reduced.

  In addition, according to the present invention, by forming a trench in a MOS capacitor region to manufacture a storage node electrode having a T-shaped structure, the capacitance of the MOS capacitor can be increased.

  Further, according to the present invention, the logic process can be used as it is, and the process time can be reduced.

  Hereinafter, the best mode for carrying out the present invention (hereinafter, referred to as an example) will be described with reference to the drawings.

  FIG. 2 is a layout diagram of a DRAM cell having a MOS capacitor according to the present invention. Referring to FIG. 2, a DRAM cell layout according to the present invention includes a word line (gate electrode) 112 driven by a row address, a bit line 130 driven by a column address, and a source 118 connected to a bit line 113. And a cell transistor connected to the gate electrode 112. The storage node electrode 114 is connected to the drain 118 of the cell transistor. In addition, in the DRAM cell of the present invention, the well 102 in the active region of the semiconductor substrate is used as a plate node electrode to which a power supply voltage is supplied, thereby forming a MOS capacitor. In the present invention, a power supply line 134 to which a power supply voltage is supplied through a contact electrode 132 is connected to a plate node electrode of the well 102.

  In the layout diagram, reference numerals 122, 124 and 126 indicate contact electrodes. Reference numeral 11 denotes a mask region used for removing a film filling the lower part of the trench when forming the trench of the MOS capacitor.

  In the DRAM cell of the present invention, the MOS capacitor uses a plate node electrode to which a power supply voltage is supplied as a well and uses a storage node electrode 114 in which signal charges are stored as a conductive film on an active region. At the time of read / write operation as compared with the case where the electrode is used as the active region, the leakage current loss flowing through the substrate is eliminated and the data access time is shortened.

  FIG. 3 is a vertical sectional view taken along line AA 'in FIG. 2, and FIG. 4 is a vertical sectional view taken along line BB' in FIG.

  Referring to these drawings, the DRAM cell of the present invention includes a storage node electrode 114 having a T-shaped structure through a well 102 of an active region of a semiconductor substrate 100 and a trench 106 of the active region 102, a plate node electrode and a storage node. The MOS capacitor 4 including the insulator thin films 110 and 111 between the node electrodes 114 is formed. The cell transistor 3 has a gate insulating film 110 and a gate electrode 112 formed on the upper surface of the active region, and has a source / drain 118 formed in the active region.

  In addition, an interlayer insulating film 120 is deposited on the structure on which the MOS capacitor 4 and the cell transistor 3 are formed, and the source / drain 118 of the cell transistor 3 or the storage of the MOS capacitor 4 is formed through the contact hole of the interlayer insulating film 120. A contact electrode 122, 124, 126 connected to the node electrode 114 and a wiring 128 connecting the drain and the storage node electrode 114 through the contact electrodes 122, 124 are formed, and a bit line 130 connected to the source through another contact electrode 126. Is formed.

  In the DRAM cell of the present invention, the MOS capacitor 4 is further formed with a filling film 108 filling the lower portion of the trench 106 with an insulating material. At this time, the mask 11 of FIG. Use. Side well spacers 116 made of an insulating material are formed on the sidewalls of the storage node electrode 114 of the MOS capacitor 4 and the gate electrode 112 of the cell transistor 3 to insulate the side of the structure.

  As shown in FIG. 4, the storage node electrode 114 of the MOS capacitor 4 according to the present invention is formed by a bent trench in which at least one trench in which a lower film is buried is connected, and a stacked MOS capacitor formed on a plane. , A higher capacitance can be secured.

  In the DRAM cell of the present invention having the above-described structure, when a data signal is supplied to the bit line 130 during a write operation, a high level voltage is supplied to the gate electrode 112 of the word line, and the cell transistor 3 is turned on. Become. Signal charges are accumulated in the storage node electrode 114 of the MOS capacitor through the drain 118 of the cell transistor 3.

  On the other hand, during a read operation, when a high level voltage is supplied to the gate electrode 112 of the word line and the cell transistor 3 is turned on, the bit line 130 through the source for transmitting the signal stored in the storage node electrode 114 through the source. Conveyed to.

  5A to 5I are process diagrams sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. In this embodiment, the manufacturing process of a DRAM cell will be described mainly on the manufacturing process of a MOS capacitor.

  First, as shown in FIG. 5A, a pad oxide film 103a and a hard mask film 103b are sequentially stacked on a silicon substrate as a semiconductor substrate 100, and a photoresist pattern 105 defining a MOS capacitor trench region is formed thereon.

  Then, as a dry etching process using the photoresist pattern 105, the substrate 100 is etched to a predetermined depth while patterning the hard mask film 103b and the pad oxide film 103a to form a trench 106 as shown in FIG. 5B. Then, the photoresist pattern 105, the hard mask film 103b and the pad oxide film 103a are removed. At this time, the trench 106 of the MOS capacitor according to the present invention may be formed by at least one bent trench connected to increase the capacitance of the capacitor.

  Subsequently, as shown in FIG. 5C, a high temperature low pressure dielectric (HLD) film is deposited on the resultant material as a gap-fill layer 108, and the film is planarized and the trench 106 is filled with an insulating material. In the process of manufacturing the trench and the filling film 108 of the MOS capacitor, the process of manufacturing the device isolation film of the DRAM cell, for example, a shallow trench device isolation film may be performed.

  Subsequently, an impurity implantation process, for example, a p-well process, is performed in the semiconductor substrate 100 to form a well 102 used as a plate node electrode of a MOS capacitor as an active region of a cell in the substrate. Then, an impurity ion is additionally implanted into the substrate by performing an n-channel process, adjusting a threshold voltage, and the like in the well.

  Meanwhile, it is preferable that the filling film 108 buried in the trench in the MOS capacitor region is buried up to the upper surface or a certain portion of the trench, or buried in a certain portion of the trench to increase the MOS capacitor capacity. . For this purpose, the following steps are performed.

  As shown in FIG. 5D, a thin insulating film 110a is deposited on the entire surface of the semiconductor substrate, and a photoresist pattern 113 for opening a MOS capacitor trench region is formed thereon. Then, the insulating thin film 110a on the filling film 108 opened by the photoresist pattern 113 is removed by etching. After that, the photoresist pattern 113 is removed. At this time, although not shown in the drawings, the photoresist pattern 113 defines not only a trench region but also a MOS capacitor region and a gate insulating film region of a cell transistor. Accordingly, during the etching process using the photoresist pattern 113, both the insulating thin film and the gate insulating film of the MOS capacitor can be patterned. Accordingly, as shown in FIG. 5E, the insulating thin film 110 of the MOS capacitor and the gate insulating film (not shown) of the cell transistor are patterned.

  Subsequently, the exposed filling film 108 is selectively etched to fill a part of the trench, and then a side well spacer 111 made of an insulating material is formed on a sidewall of the trench. At this time, the side well spacer is used as an insulator thin film of the MOS capacitor.

  Subsequently, as shown in FIG. 5f, polysilicon is deposited on the resultant structure as a conductive film 114a, and partially fills the trench, and partially covers the insulating thin film 110 and the gate insulating film of the MOS capacitor. Evaporate so that the thickness remains. Then, as shown in FIG. 5g, a photoresist pattern 115 defining a storage node electrode of the MOS capacitor and a gate electrode region of the cell transistor is formed on the conductive film 114a.

  Subsequently, the conductive film 114a opened by the photoresist pattern 115 is dry-etched to form a storage node electrode 114 of a MOS capacitor having a T-shaped structure as shown in FIG. I do. Then, the photoresist pattern 115 is removed.

  Next, as shown in FIG. 5I, an insulating layer is deposited on the resultant structure and dry-etched, and side well spacers 116 are formed on sidewalls of the storage node electrode 114 of the MOS capacitor and the gate electrode 112 of the cell transistor. Form. The source / drain 118 of the cell transistor is formed by implanting impurities using the side well spacers as a mask, and an interlayer insulating layer 120 is formed on the entire surface of the resultant structure and planarized. Subsequently, after forming a contact hole in the interlayer insulating film 120, a conductive film is embedded in the contact hole. Accordingly, contact electrodes 122 and 124 connected to the source / drain 118 of the cell transistor or the storage node electrode 114 of the MOS capacitor are formed.

  Subsequently, a conductive film is deposited on the interlayer insulating film 120 and then patterned to form a wire 128 connecting the drain 118 and the storage node electrode 114 through the contact electrodes 122 and 124 and to form another contact electrode ( A bit line (not shown) is formed to connect the source 118 of the cell transistor through a not shown (not shown).

  On the other hand, although not shown in FIG. 5i, in the manufacturing process of the wiring 128 and the bit line, a power supply line for supplying a power supply voltage to the well 102 of the plate node electrode through another contact electrode of the interlayer insulating film 120 is connected. Form.

  On the other hand, the present invention is not limited to the embodiments described above, and various modifications can be made by those skilled in the art within the technical concept and the scope of the present invention described in the claims described below.

FIG. 2 is a vertical sectional view showing a DRAM cell structure having a MOS capacitor according to the related art. FIG. 2 is a layout diagram of a DRAM cell having a MOS capacitor according to the present invention. FIG. 3 is a vertical sectional view taken along line AA ′ in FIG. 2. FIG. 3 is a vertical sectional view taken along line BB ′ in FIG. 2. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention. FIG. 3 is a process diagram sequentially illustrating a process of manufacturing a DRAM cell having a MOS capacitor according to an embodiment of the present invention.

Explanation of reference numerals

  Reference Signs List 100 semiconductor substrate, 103a pad oxide film, 103b hard mask, 105 photoresist pattern, 106 trench, 108 filling film, 112 gate electrode, 114 storage node electrode, 130 bit line.

Claims (15)

In a DRAM cell having a cell transistor and a capacitor,
A word line driven by a row address;
A bit line driven by a column address;
A cell transistor having a source connected to the bit line and a gate electrode connected to the word line;
A storage node electrode connected to a drain of the cell transistor, the plate node electrode being formed in an active region of a semiconductor substrate, and a MOS capacitor having an insulating thin film between the storage node electrode and the plate node electrode. A DRAM cell having a MOS capacitor.   2. The DRAM cell having a MOS capacitor according to claim 1, wherein the storage node electrode has a T-shaped structure through a trench of the active region.   The DRAM cell of claim 1, wherein a power supply line to which a power supply voltage is supplied is connected to the plate node electrode. In a DRAM cell having a cell transistor and a capacitor,
An active region of the semiconductor substrate;
A plate node electrode that is a part of the active region, a storage node electrode having a T-shaped structure through a trench of the active region, a MOS capacitor including an insulating thin film between the plate node electrode and the storage node electrode,
A cell transistor including a gate insulating film and a gate electrode formed on an upper surface of the active region, and a source / drain formed in the active region;
An interlayer insulating film deposited on the structure on which the MOS capacitor and the cell transistor are formed;
A contact electrode connected to a source / drain of the cell transistor or a storage node electrode of the MOS capacitor through a contact hole of the interlayer insulating film;
A wiring connecting the drain and the storage node electrode through the contact electrode;
A DRAM cell having a MOS capacitor, comprising a bit line connected to the source through the contact electrode.   5. The DRAM cell of claim 4, wherein the MOS capacitor further comprises a filling layer filling a lower portion of the trench with an insulating material.    5. The DRAM cell having a MOS capacitor according to claim 4, wherein a power supply line to which a power supply voltage is supplied through another contact electrode of the interlayer insulating film is connected to the plate node electrode.   The DRAM cell having a MOS capacitor according to claim 4, wherein the trench of the MOS capacitor is a bent trench connected to at least one or more.   5. The DRAM cell according to claim 4, wherein the storage node electrode of the MOS capacitor and the gate electrode of the cell transistor further include a side well spacer on a side wall thereof. In a method of manufacturing a DRAM cell having a cell transistor and a capacitor,
Forming a trench in a portion of the active region of the semiconductor substrate;
Implanting impurities into the active region;
Forming an insulating thin film over the entire surface of the substrate on which the trench is formed, and forming a gate insulating film;
Depositing a conductive film so that a trench is buried in the resultant, patterning the conductive film to form a storage node electrode having the T-shaped structure, and forming a gate electrode of the cell transistor;
Implanting impurities into the resultant to form a source / drain of the cell transistor;
After forming an interlayer insulating film on the entire surface of the resultant structure and forming a contact hole in the interlayer insulating film, a conductive film is buried in the contact hole to form a source / drain of the cell transistor or a storage node electrode of the MOS capacitor. Forming a connected contact electrode;
Depositing a conductive film on the interlayer insulating film, patterning the conductive film, and forming a wiring connecting the drain and the storage node electrode and a bit line connecting the source through the contact electrode. A method for manufacturing a DRAM cell having a MOS capacitor.   The method of claim 9, wherein the trench of the MOS capacitor is formed as a bent trench connected to at least one or more.   10. The method of claim 9, further comprising forming a filling layer filling the lower portion of the trench with an insulating material before implanting impurities into the active region.   12. The DRAM cell having a MOS capacitor according to claim 11, wherein the filling film is formed in a trench in a storage node region of the MOS capacitor or in a trench in an element isolation region of the semiconductor substrate. Manufacturing method.   13. The method of claim 12, wherein the filling film formed in the trench in the storage node region of the MOS capacitor is buried to an upper surface or a predetermined portion of the trench.   10. The MOS capacitor according to claim 9, further comprising, before forming a source / drain of the cell transistor, a side well spacer on a side wall of a storage node electrode of the MOS capacitor and a gate electrode of the cell transistor. A method for manufacturing a DRAM cell having:   When depositing a conductive film on the interlayer insulating film and patterning the conductive film, a power line for supplying a power voltage to the plate node electrode through another contact electrode of the interlayer insulating film is formed. A method for manufacturing a DRAM cell having the MOS capacitor according to claim 9.

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