KR20040053844A - DRAM cell including MOS capacitor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A DRAM(Dynamic Random Access Memory) cell having an MOS(Metal Oxide Semiconductor) capacitor and a manufacturing method thereof are provided to increase the capacitance and prevent the leakage current by using a plate node electrode as an active region of a semiconductor substrate and a storage node electrode as a 'T' shaped conductive pattern. CONSTITUTION: A DRAM cell having an MOS capacitor is provided with word lines driven by a row address, bit lines(130) driven by a column address, and a cell transistor for being connected with the bit line through its source(118) and the word line through its gate electrode(112). The DRAM cell further includes an MOS capacitor. The MOS capacitor includes a storage node electrode(114) connected with a drain of the cell transistor, a plate node electrode(102) formed at the active region of a semiconductor substrate, and a thin film for insulation between the storage node electrode and the plate node electrode.

Description

Dram cell with MOS capacitor and method for manufacturing the same {DRAM cell including MOS capacitor and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell and a method for manufacturing the same, and more particularly, to a DRAM cell having a MOS capacitor suitable for an electronic device such as a CD-R / W or a game device that requires a small memory, and a method for manufacturing the same. .

Generally, a semiconductor memory device refers to a device that can store data and read out data when needed. The semiconductor memory device mainly includes various types of semiconductor disks, such as magnetic disks and optical disks, mainly from DRAM (Dynamic Random Access Memory). Among them, semiconductor memory is compact, has high reliability, and can be manufactured at low cost, and has the advantage of relatively high speed operation. Therefore, the main memory located inside the computer, the buried memory in the microprocessor, and the cache memory type It is widely used.

Meanwhile, a DRAM unit cell structure includes a word line driven by a row address, a bit line driven by a column address, and a drain connected to the bit line. And a cell transistor having a gate connected to the line, and a capacitor connected to the source of the cell transistor.

The read / write of such DRAM cells is operated as follows. When any word line is activated, the cell transistor connected to the word line is turned on and the voltage of the bit line is applied through the drain of the cell transistor to store charge in the storage node electrode of the capacitor. . At this time, the voltage applied to the bit line is supplied with 0V or Vdd (driving voltage). A fixed power supply voltage is supplied to the plate node electrode of the capacitor, which is usually about half of the driving voltage Vdd.

On the other hand, when using a metal-oxide-silicon (MOS) capacitor in a DRAM cell, there is an advantage that a logic process can be used as it is compared to a general stack type capacitor.

1 is a vertical cross-sectional view showing a DRAM cell structure having a MOS capacitor according to the prior art. Referring to FIG. 1, a vertical cross-sectional structure of a DRAM cell includes a semiconductor substrate 10, a well 12, a device isolation film 14, a gate insulating film 16 deposited over the substrate, and a gate insulating film. (16) the gate electrode 18 of the cell transistor 2 and the plate node electrode 20 of the MOS capacitor 4 formed on top of each other, the source / drain 24 of the cell transistor 2 formed in the substrate, The bit line 30 is connected to the drain 24 through the contact electrode 28 of the interlayer insulating layer 26.

In the figure, the storage node electrode of the MOS capacitor 4 is the well 12 region located below the plate node electrode 20, and the insulator film between these electrodes becomes the gate insulating film 16. The gate electrode 18 of the cell transistor 2 is used as a word line.

The DRAM cell having such a configuration is stored in the well 12 which is a storage node of the MOS capacitor 4 connected to the source of the cell transistor 2. However, despite the advantage that DRAM cells with MOS capacitors can use the logic process as it is compared to stacked capacitors, because the data is stored in the well 12 used as a storage node, a large amount of leakage current flows to refresh the DRAM cells. There was a problem that the time (refresh time) is shortened.

An object of the present invention is to increase the MOS capacitor capacity by using the plate node electrode as the active region of the substrate and the storage node electrode as the T-shaped conductive pattern in the DRAM cell using the MOS capacitor in order to solve the problems of the prior art. The present invention provides a DRAM cell having a MOS capacitor that can prevent the loss of the liquid current when the storage node electrode is used as an active region.

Another object of the present invention is to form a liquefied current when the storage node electrode is used as an active region while increasing the capacity of the MOS capacitor by forming a T-shaped storage node electrode in a trench in the substrate as the active region of the substrate. Disclosed is a method for fabricating a DRAM cell having a MOS capacitor capable of preventing loss.

1 is a vertical sectional view showing a DRAM cell structure having a MOS capacitor according to the prior art,

2 is a layout diagram of a DRAM cell having a MOS capacitor according to the present invention;

3 is a vertical cross-sectional view taken along the line AA ′ of FIG. 2;

4 is a vertical cross-sectional view taken along the line B-B 'in FIG.

5A-5I are process flow diagrams sequentially illustrating a DRAM cell fabrication process with MOS capacitors in accordance with one embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 103a pad oxide film

103b: hard mask 105: photoresist pattern

106: trench 108: filling film

112: gate electrode 114: storage node electrode

130: bit line

In order to achieve the above object, the present invention provides a DRAM cell having a cell transistor and a capacitor, comprising: a word line driven by a row address, a bit line driven by a column address, and a source in the bit line; Is connected to a gate electrode connected to a word line, a storage node electrode is connected to a drain of the cell transistor, and a plate node electrode formed in an active region of the semiconductor substrate, and an insulator thin film between the storage node electrode and the plate node electrode. A MOS capacitor is provided.

In order to achieve the above object, the present invention provides a DRAM cell having a cell transistor and a capacitor, the active region of the semiconductor substrate, a plate node electrode which is a part of the active region, a storage node electrode having a T-shaped structure through the trench of the active region, A cell transistor comprising a MOS capacitor comprising an insulator thin film between a plate node electrode and a storage node electrode, a gate insulating film and a gate electrode formed on an upper surface of an active region, a source / drain formed in the active region, and a MOS capacitor and a cell transistor. An interlayer insulating film deposited on the formed structure, a contact electrode connected to a source / drain of a cell transistor or a storage node electrode of a MOS capacitor through a contact hole of the interlayer insulating film, a wiring to which a drain and a storage node electrode are connected through a contact electrode; Source connected via contact electrode Provided with a bit line.

In order to achieve the above object, the present invention provides a method of manufacturing a DRAM cell having a cell transistor and a capacitor, the method comprising the steps of forming a trench in a portion of the active region of the semiconductor substrate, implanting impurities into the active region, Forming an insulator thin film on the entire surface of the formed substrate, and simultaneously forming a gate insulating film; depositing and patterning a conductive film to fill the trench in the resultant, forming a storage node electrode having a T-shape, and simultaneously forming a gate electrode of the cell transistor. Forming a source / drain of the cell transistor by injecting impurities into the resultant, forming an interlayer insulating film on the entire surface of the resultant, forming a contact hole in the interlayer insulating film, and then filling the conductive film in the contact hole. Storage node electrodes of the source / drain or MOS capacitors A contact electrode; and a conductive film is deposited on the interlayer insulation film to form an upper and by patterning them and forming a wiring line and a bit line connected to the source and the drain and the storage node electrode is connected through the contact electrode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a layout diagram of a DRAM cell having a MOS capacitor according to the present invention. Referring to FIG. 2, the DRAM cell layout of the present invention is a source line of a word line (gate electrode) 112 driven by a row address, a bit line 130 driven by a column address, and a bit line 113. A cell transistor 118 is connected and a gate electrode 112 is connected to a word line. The storage node electrode 114 is connected to the drain 118 of the cell transistor. In addition, in the DRAM cell of the present invention, the well 102, which is an active region of the semiconductor substrate, is used as a plate node electrode to which a power supply voltage is supplied, thereby forming a MOS capacitor. In the present invention, a power supply line 134 to which a power supply voltage is supplied through a contact electrode 132 is connected to a plate node electrode which is a well 102.

Reference numerals 122, 124, and 126, which are not described in the layout diagram, indicate contact electrodes. In addition, reference numeral 11 denotes a mask region used to remove a film filled in the lower portion of the trench when forming the trench of the MOS capacitor.

In the DRAM cell of the present invention, a MOS capacitor uses a plate node electrode supplied with a power supply voltage as a well and a storage node electrode 114 storing signal charges as a conductive layer on the active region, thereby making the storage node electrode an active region. There is no loss of liquid current to the substrate during read / write operations and shorter data access time.

3 is a vertical cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 4 is a vertical cross-sectional view taken along the line B-B ′ of FIG. 2. Referring to these figures, the DRAM cell vertical cross section of the present invention is as follows.

An insulator between the well node 102, which is an active region of the semiconductor substrate, and the storage node electrode 114 having a T-shape through the trench 106 of the active region 102, and the plate node electrode and the storage node electrode 114. The MOS capacitor 4 which consists of the thin films 110 and 111 is formed. A cell transistor 2 having a gate insulating layer 110 and a gate electrode 112 formed on an upper surface of the active region and a source / drain 118 formed in the active region is provided. In addition, an interlayer insulating layer 120 is deposited on the structure where the MOS capacitor 4 and the cell transistor 2 are formed, and the source / drain 118 or the MOS capacitor of the cell transistor 2 is formed through the contact hole of the interlayer insulating layer 120. Contact electrodes 122, 124, and 126 to which the storage node electrode 114 of (4) is connected, and a wiring 128 to which the drain and the storage node electrode 114 are connected to each other through the contact electrodes 122 and 124. The bit line 130 is connected to the source through another contact electrode 126.

In the DRAM cell of the present invention, the MOS capacitor 4 is further formed with a filling film 108 filling the lower portion of the trench 106 with an insulating material, in which the filling film 108 to leave only the trench in FIG. The mask 11 is used. In addition, sidewall spacers 116 made of an insulating material are formed on sidewalls of the storage node electrode 114 of the MOS capacitor 4 and the gate electrode 112 of the cell transistor 2 to insulate the side of the structure.

As shown in FIG. 3, the storage node electrode 114 of the MOS capacitor 4 of the present invention is composed of curved trenches formed by curved trenches formed by at least one or more trenches in which a lower layer is embedded. Higher capacitance can be obtained than capacitors.

In the DRAM cell of the present invention having the structure as described above, when a data signal is supplied to the bit line 130 during a write operation, a high level voltage is supplied to the gate electrode 112 which is a word line, thereby providing the cell transistor 2. Is turned ON. Signal charge is stored at the storage node electrode 114 of the MOS capacitor through the drain 118 of the cell transistor 2.

On the contrary, when a high level voltage is supplied to the gate electrode 112 which is a word line during a read operation, and the cell transistor 2 is turned on, the signal charge stored in the storage node electrode 114 is discharged from the drain. Is transmitted to the bit line 130.

5A-5I are process flow diagrams sequentially illustrating a DRAM cell fabrication process with MOS capacitors in accordance with one embodiment of the present invention. This embodiment will describe a DRAM cell manufacturing process centering on the manufacturing process of the MOS capacitor.

First, as shown in FIG. 5A, a photoresist pattern 105 for sequentially depositing a pad oxide film 103a and a hard mask film 103b on a silicon substrate as a semiconductor substrate 100 and defining a MOS capacitor trench region thereon. To form.

The substrate 100 is etched to a predetermined depth by patterning the hard mask layer 103b and the pad oxide layer 103a by a dry etching process using the photoresist pattern 105 to form the trench 106 as shown in FIG. 5B. do. The photoresist pattern 105, the hard mask film 103a, and the pad oxide film 103a are removed. At this time, the trench 106 of the MOS capacitor according to the present invention may be formed of at least one curved trenches to increase the capacitor capacity.

Subsequently, as shown in FIG. 5C, a high temperature low pressure dielectric (HLD) film is deposited on the resultant as a gap-fill layer 108 and planarized to fill the trench 106 with an insulating material. . In the process of manufacturing the trench and the filling film 108 of the MOS capacitor, the device isolation film of the DRAM cell, for example, the shallow trench device isolation film may also be processed.

Subsequently, an impurity implantation process, for example, a p-well process, is performed in the semiconductor substrate 100 to form a well 102 in the substrate, which is an active region of a cell and used as a plate node electrode of a MOS capacitor. Further, n-channel process, threshold voltage control, and the like are performed in the well to implant additional impurity ions into the substrate.

On the other hand, the filling film 108 buried in the trench of the MOS capacitor region is buried to the trench upper surface or a predetermined portion, it is preferable to fill the trench to a predetermined portion to increase the MOS capacitor capacity. To do this, proceed as follows.

As shown in FIG. 5D, a thin insulator thin film 110a is deposited on the entire surface of the semiconductor substrate, and a photoresist pattern 113 is formed thereon to open the MOS capacitor trench region. The photoresist pattern 113 is removed after the insulator thin film 110a on the filling film 108 exposed by the photoresist pattern 113 is removed by etching. Although not shown in the drawing, the photoresist pattern 113 defines not only the trench region but also the MOS capacitor region and the gate insulating layer region of the cell transistor. As a result, the insulator thin film and the gate insulating film of the MOS capacitor may be patterned together during the etching process using the photoresist pattern 113. Accordingly, as shown in FIG. 5E, the insulator thin film 110 of the MOS capacitor and the gate insulating film (not shown) of the cell transistor are patterned.

Subsequently, the exposed filling layer 108 is selectively etched to fill a portion of the trench, and then sidewall spacers 111 made of an insulating material are formed on the sidewalls of the trench. In this case, the side well spacer is used as an insulator thin film of the MOS capacitor.

Subsequently, as shown in FIG. 5F, polysilicon is deposited as the conductive film 114a on the resultant, but a portion of the thickness is left over the insulator thin film 110 and the gate insulating film of the MOS capacitor while completely filling the trench. do. As shown in FIG. 5G, a photoresist pattern 115 is formed on the conductive layer 114a to define the storage node electrode of the MOS capacitor and the gate electrode region of the cell transistor.

Subsequently, the conductive film 114a exposed by the photoresist pattern 115 is dry-etched to form the storage node electrode 114 of the MOS capacitor having a T-shape as shown in FIG. 5H and at the same time the gate electrode of the cell transistor ( 112). The photoresist pattern 115 is removed.

Next, as shown in FIG. 5I, an insulating film is deposited on the resultant and dry-etched to form sidewall spacers 116 on sidewalls of the storage node electrode 114 of the MOS capacitor and the gate electrode 112 of the cell transistor. Form. The source / drain 118 of the cell transistor is formed by implanting impurities into the side well spacer using a mask, and then the interlayer insulating layer 120 is formed on the entire surface of the resultant cell and planarized. Subsequently, after forming contact holes in the interlayer insulating layer 120, contact electrodes 122 and 124 to which the source / drain 118 of the cell transistor or the storage node electrode 114 of the MOS capacitor are connected by filling a conductive film in the contact hole are formed. ).

Subsequently, a conductive film is deposited on the interlayer insulating film 120 and patterned to form a wiring 128 to which the drain 118 and the storage node electrode 114 are connected through the contact electrodes 122 and 124. A bit line (not shown) to which the source 118 of the cell transistor is connected is formed through another contact electrode (not shown).

Although not shown in FIG. 5I, a power line for supplying a power voltage to the well 102, which is a plate node electrode, is formed through another contact electrode of the interlayer insulating layer 120 during the wiring 128 and the bit line manufacturing process. do.

As described above, the present invention uses a plate node electrode supplied with power in a DRAM cell using a MOS capacitor as an active region, that is, a well, of a substrate having a large parasitic resistance and a capacitance, thereby improving signal speed.

In addition, by using the storage node electrode of the MOS capacitor as the conductive layer on the active region, the present invention can prevent the loss of the liquefaction current that occurs when the storage node electrode is used as the active region in a conventional DRAM cell and the read / write time of the cell. This can shorten the effect.

In addition, the present invention can increase the MOS capacitor capacity by forming a trench in the MOS capacitor region to produce a T-shaped storage node electrode.

In addition, the present invention can use the logic process as it is there is an advantage of shortening the process time.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (15)

In a DRAM cell having a cell transistor and a capacitor, A word line driven by a row address; A bit line driven by a column address; A cell transistor having a source connected to the bit line and a gate electrode connected to the word line; And A MOS capacitor comprising a MOS capacitor having a storage node electrode connected to the drain of the cell transistor and a plate node electrode formed in an active region of the semiconductor substrate, and an insulator thin film between the storage node electrode and the plate node electrode. Having a DRAM cell. The DRAM cell of claim 1, wherein the storage node electrode has a T-shape through a trench in the active region. The DRAM cell of claim 1, wherein a power line to which a power voltage is supplied is connected to the plate node electrode. In a DRAM cell having a cell transistor and a capacitor, An active region of the semiconductor substrate; A MOS capacitor comprising a plate node electrode which is a part of the active region, a storage node electrode having a T-shape through a trench of the active region, and an insulator thin film between the plate node electrode and the storage node electrode; A cell transistor including a gate insulating film and a gate electrode formed on an upper surface of the active region, and a source / drain formed in the active region; An interlayer insulating film deposited on the structure in which the MOS capacitor and the cell transistor are formed; A contact electrode connected to a source / drain of the cell transistor or a storage node of the MOS capacitor through a contact hole of the interlayer insulating layer; A wiring connecting the drain and the storage node electrode through the contact electrode; And And a bit line connected to the source through the contact electrode. The DRAM cell of claim 4, wherein the MOS capacitor further comprises a filling layer filling the lower portion of the trench with an insulating material. The DRAM cell of claim 4, wherein a power line to which a power voltage is supplied to the plate node electrode is connected through another contact electrode of the interlayer insulating layer. 5. The DRAM cell of claim 4 wherein the trench of the MOS capacitor is at least one successive curved trench. The DRAM cell of claim 4, wherein sidewall spacers are added to sidewalls of the storage node of the MOS capacitor and the gate electrode of the cell transistor. In the method of manufacturing a DRAM cell having a cell transistor and a capacitor, Forming a trench in a portion of the active region of the semiconductor substrate; Implanting impurities into the active region; Forming an insulator thin film on the entire surface of the substrate on which the trench is formed and simultaneously forming a gate insulating film; Depositing and patterning a conductive layer to fill the trench in the resultant, thereby forming a storage node electrode having the T-shaped structure and simultaneously forming a gate electrode of the cell transistor; Implanting impurities into the resultant to form a source / drain of the cell transistor; Forming an interlayer insulating film on the entire surface of the resultant, forming a contact hole in the interlayer insulating film, and filling a conductive film in the contact hole to form a contact electrode connected to a source / drain of the cell transistor or a storage node electrode of the MOS capacitor; ; And And depositing a conductive layer on the interlayer insulating layer and patterning the conductive layer to form a wiring through which the drain and the storage node are connected and a bit line through which the source is connected through the contact electrode. DRAM cell manufacturing method. 10. The method of claim 9, wherein the trench of the MOS capacitor is formed of at least one successive curved trenches. 10. The method of claim 9, further comprising forming a filling film filling the lower portion of the trench with an insulating material before implanting impurities into the active region. 12. The method of claim 11, wherein the filling layer is formed in a trench of a storage node region of the MOS capacitor or in a trench of an isolation region of the semiconductor substrate. 13. The method of claim 12, wherein the filling film formed in the trench of the storage node region of the MOS capacitor is embedded in the trench upper surface or a predetermined portion. 10. The DRAM of claim 9, wherein sidewall spacers are further formed on sidewalls of the storage node of the MOS capacitor and the gate electrode of the cell transistor before forming the source / drain of the cell transistor. Cell manufacturing method. The MOS capacitor of claim 9, wherein when a conductive film is deposited on the interlayer insulating layer and patterned thereon, a MOS capacitor is formed in which a power line is supplied to the plate node electrode through another contact electrode of the interlayer insulating layer. DRAM cell manufacturing method.