JP2004180333A - Analog/digital converter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital converter circuit which comprises a subtraction amplifier circuit that can operate at a low voltage and whose noise is reduced. <P>SOLUTION: In a differential amplifier 111, an inverting input terminal of an operational amplifier 1 is connected to a node Na and a non-inverting input terminal is connected to a node Nb. An inverting output terminal of the operational amplifier 1 is connected to a node NO1 and a non-inverting output terminal is connected to a node NO2. The node Na is connected to a node N11 through a capacitor 3a and connected to a node N12 through a capacitor 4a. The node Nb is connected to a node N21 through a capacitor 3b and connected to a node N22 through a capacitor 4b. A switch SW13 is connected between the node NO1 and the node NO2. An output of the front stage differential amplifier 111 and an input of the post stage differential amplifier 111 are connected without using a changing-over switch. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to an analog-digital conversion circuit including a subtraction amplifier circuit.

  2. Description of the Related Art In recent years, with the progress of video signal digital processing technology, demand for an analog-to-digital converter (A / D converter) for video signal processing has increased. Conventionally, a two-step flash (two-step parallel) system has been widely used because an analog-to-digital converter for video signal processing requires a high-speed conversion operation.

  However, with the increase in the number of conversion bits, it has become impossible to obtain sufficient conversion accuracy with the two-step flash method. Therefore, an analog-digital conversion circuit having a multi-stage pipeline (step flash) configuration has been developed.

  In the analog-digital conversion circuit having the multi-stage pipeline configuration, each stage includes an A / D converter (digital-analog converter), a D / A converter (digital-analog converter), and a difference amplifier.

  In each stage, the number of bits (bit configuration) n of the A / D converter and the D / A converter are set to be the same. The A / D converter in each stage is called a sub A / D converter to distinguish it from the whole analog-digital conversion circuit. For the sub A / D converter, an all-parallel comparison (flash) method capable of high-speed conversion operation is used.

  In this analog-digital conversion circuit, first, A / D conversion is performed on an analog input signal using a first-stage sub A / D converter. Next, the A / D conversion result of the first-stage A / D converter is input to the first-stage D / A converter, and D / A conversion is performed. Subsequently, the D / A conversion result of the first stage D / A converter and the analog input signal are input to the first stage differential amplifier, and the difference therebetween is amplified.

  The output of the first-stage differential amplifier is subjected to A / D conversion using a second-stage sub A / D converter. Next, the A / D conversion result of the second-stage sub A / D converter is input to the second-stage D / A converter, and D / A conversion is performed. Subsequently, the D / A conversion result of the second-stage D / A converter and the output of the first-stage differential amplifier are input to the second-stage differential amplifier, and the difference therebetween is amplified. Thereafter, the same operation is sequentially performed in each stage.

  However, the last stage is composed of only the sub A / D converter, and A / D converts the output of the preceding stage differential amplifier.

  For example, when the number of bits (bit configuration) of the sub-A / D converters of the first to third stages in the three-stage pipeline configuration are a, b, and c, respectively, The digital output of the middle b bits from the second sub-A / D converter and the lower c bits from the third sub-A / D converter is obtained.

  In this manner, if a multi-stage pipeline configuration is employed, in each stage, the difference between the analog input signal or the output of the preceding stage difference amplifier and the D / A conversion result of the digital output of that stage is determined by the difference amplifier of that stage. Amplified. Therefore, even if the number of conversion bits increases and the LSB (Least Significant Bit) decreases, the resolution of each comparator constituting the sub A / D converter can be substantially improved, and sufficient conversion accuracy can be obtained. can get.

  A subtraction amplifier circuit is used as a differential amplifier of each stage of the analog-digital conversion circuit having such a multi-stage pipeline configuration.

  FIG. 15 is a circuit diagram showing an example of a conventional subtraction amplifier circuit. FIG. 16 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

  In FIG. 15, the inverting input terminal of the operational amplifier 1 is connected to the node nb, and the non-inverting input terminal is grounded. The output terminal of the operational amplifier 1 is connected to the node no and is connected to the inverting input terminal via the capacitor 2. The switch SW1 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier 1, and the capacitor 3 is connected between the node nb and the node na. The node na is connected to the node n1 via the switch SW2, and is connected to the node n2 via the switch SW3.

Is voltages V ₁ is input to the node n1, the voltage V ₂ is input to the node n2, the voltage V _O output from the node no.

Here, the operation of the subtraction amplifier circuit of FIG. 15 will be described with reference to FIG. Incidentally, the capacitance value of the capacitor 2 is C, a capacitance value of the capacitor 3 and KC, the ground potential V _G. K is a constant.

First, the switch SW1 and the switch SW2 are turned on, and the switch SW3 is turned off. Thereby, the voltage of the node na becomes V _1. Further, the voltage of the node no becomes 0. At this time, the charge Qa of the node nb is as follows.

_{Qa = (V G -V 1)} KC
Next, after the switch SW1 is turned off, the switch SW2 is turned off and the switch SW3 is turned on. Thereby, the voltage of the node na becomes V _2. Further, the voltage of the node no becomes V _O. At this time, since the node nb is virtually grounded, the charge Qb of the node nb is expressed by the following equation.

_{Qb = (V G -V 2)} KC + (V G -V O) C
Since the node nb has no path through which the charges escape, Qa = Qb according to the law of conservation of charges. Therefore, the following equation is established.

_{(V G -V 1) KC =} (V G -V 2) KC + (V G -V O) C
From the above equation, the voltage VO at the node no is as follows.

_{V O = V G + (V} 1 -V 2) K
In this way, the voltage V ₂ from the voltages V ₁ is subtracted, the subtraction value is amplified by K times.

In the above-described conventional subtraction amplifier circuit, as described above, the switches SW2 and SW3 are required to switch the voltages V ₁ and V ₂ input to the node na. These switches SW2 and SW3 are usually constituted by CMOS switches composed of CMOS (complementary metal oxide semiconductor) field effect transistors.

  This CMOS switch has a characteristic that it cannot be reliably turned on and off at the time of low voltage operation. In particular, an intermediate level between the power supply voltage and the ground voltage is difficult to pass or cannot pass. Therefore, it is difficult to reduce the voltage of the analog-digital conversion circuit.

Further, since the voltages V ₁ and V ₂ , which are analog input signals, are input to the capacitor 3 via the switches SW2 and SW3, when an unspecified analog signal is input, the analog input signal is reduced to the analog input signal level. Dependent switch noise is generated.

  As a result, a high-precision analog-to-digital conversion circuit that can operate at low voltage and cannot be realized.

  An object of the present invention is to provide an analog-to-digital conversion circuit including a subtraction amplifier circuit that can operate at a low voltage and has reduced noise.

  2. The analog-to-digital converter according to claim 1, comprising at least two stages including an analog-to-digital converter, a digital-to-analog converter, and a subtraction amplifier, wherein the output of the previous stage amplification amplifier and the input of the subsequent stage amplification amplifier are provided. Are connected without a switch for switching an input voltage, and the subtraction amplifier circuit has a first and a second capacitor connected in parallel to one input terminal of an operational amplifier, and the other of the operational amplifier A third capacitor connected in parallel to the input terminal, and in a subtraction amplifier circuit at a subsequent stage, the first and second input voltages are respectively applied to input terminals of the first and third capacitors. During the application, an arbitrary first set voltage is applied to the input terminals of the second and fourth capacitors, respectively, and an arbitrary second set voltage is applied to the input terminals of the first and third capacitors. Is applied, the third and fourth input voltages are applied to the input terminals of the second and fourth capacitors, respectively, so that the difference between the first input voltage and the second input voltage is increased. The gist of the present invention is to perform subtraction and amplification of a first differential input voltage which is a differential input voltage and a second differential input voltage which is a difference between the third input voltage and the fourth input voltage.

According to a second aspect of the present invention, in the first aspect, the input terminals of the first and third capacitors are connected to an inverted output and a non-inverted output of a preceding subtraction amplifier circuit. Is the gist.
The analog-to-digital conversion circuit according to claim 3 is the invention according to claim 1 or 2, wherein the third and fourth inputs use a voltage equalized from an output of a previous stage subtraction amplifier circuit as the first set voltage. The gist of the invention is to use the inverted output and the non-inverted output of the preceding subtraction amplifier circuit as the voltage.

  It is possible to provide an analog-digital conversion circuit including a subtraction amplifier circuit capable of low-voltage operation and having reduced noise.

  FIG. 1 is a circuit diagram of a subtraction amplifier circuit according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

  In FIG. 1, the inverting input terminal of the operational amplifier 1 is connected to the node NB, and the non-inverting input terminal is grounded. The output terminal of the operational amplifier 1 is connected to the node NO, and is connected to the inverting input terminal via the capacitor 2. A switch SW1 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier 1. Node NB is connected to node N1 via capacitor 3 and to node N2 via capacitor 4.

The node N1 is input voltage changes from V ₁ to V _A, the node N2 voltage changes from V _A to V ₂ are inputted. _VA is an arbitrary set voltage. The voltage V _O is output from the node NO.

Next, the operation of the subtraction amplifier circuit of FIG. 1 will be described with reference to FIG. Here, the capacitance value of the capacitor 2 is C, and the capacitance values of the capacitors 3 and 4 are KC. K is a constant. In addition, the ground potential and V _G.

First, the switch SW1 is turned on. Then, enter the voltages V ₁ to the node N1, and inputs the set voltage V _A at the node N2. Node NO is set to the ground potential V _G. At this time, the charge Qa of the node NB is as follows.

_{Qa = (V G -V 1)} KC + (V G -V A) KC
Next, the switch SW1 is turned off. Then, enter the set voltage V _A at the node N1, and inputs the voltage V ₂ to the node N2. The voltage at the node NO becomes V _O. At this time, the charge Qb of the node NB is as follows.

_{Qb = (V G -V A)} KC + (V G -V 2) KC + (V G -V O) KC
Since there is no path for the charge to escape from the node NB, Qa = Qb according to the law of conservation of charge, and the following equation holds.

_{(V G -V 1) KC +} (V G -V A) KC = (V G -V A) KC + (V G -V 2) KC + (V G -V O) KC
From the above equation, the voltage VO at the node NO is as follows.

_{V O = V G + (V} 1 -V 2) K
As described above, the voltage V _O output from the subtraction amplifier circuit of FIG. 1 is equal to the voltage V _O output from the conventional subtraction amplifier circuit of FIG.

In the subtraction amplifier circuit of the present embodiment, the voltages V ₁ and V ₂ , which are analog input signals, are input to the nodes N 1 and N 2 without passing through a switch, and the set voltage _VA can be set arbitrarily. Noise can be reduced and low-voltage operation can be performed.

  FIG. 3 is a circuit diagram of a subtraction amplifier circuit according to the second embodiment of the present invention. FIG. 4 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

  The difference between the subtraction amplifier circuit of FIG. 3 and the subtraction amplifier circuit of FIG. 1 is as follows. Node NB is connected to node N1 via capacitor 3, connected to node N21 via capacitor 4A, and connected to node N22 via capacitor 4B. That is, in the subtraction amplifier circuit of the present embodiment, the capacitor 4 in the subtraction amplifier circuit of FIG. 1 is divided into two capacitors 4A and 4B.

The node N1 is input voltage changes from V ₁ to V _A, is input voltage changes from V _A to V _T is the node N21, the voltage changes from V _A to V _B is inputted to the node N22 You.

Next, the operation of the subtraction amplifier circuit of FIG. 3 will be described with reference to FIG. Here, the capacitance value of the capacitor 2 is C, the capacitance value of the capacitor 3 is KC, and the capacitance values of the capacitors 4A and 4B are each KC / 2. K is a constant. Further, as shown in FIG. 4 (a), a _{V 2 = (V T -V B} ) / 2.

First, the switch SW1 is turned on. Then, enter the voltages V ₁ to the node N1, and inputs the setting voltage V _A at the node N21, and inputs the set voltage V _A at the node N22. Node NO is set to the ground potential V _G. At this time, the charge Qa of the node NB is as follows.

Qa = (VG -V1) KC + (V G -V A) × (KC / 2) × 2
Next, the switch SW1 is turned off. Then, enter the set voltage V _A at the node N1, and the input voltage V _T to node N21, and inputs the voltage V _B to the node N22. The voltage at the node NO becomes V _O. At this time, the charge Qb of the node NB is as follows.

_{Qb = (V G -V A)} KC + (V G -V T) × (KC / 2) + (V G -V B) × (KC / 2) + (V G -V O) C
Since there is no path for the charge to escape from the node NB, Qa = Qb from the charge conservation law, and the following equation holds.

_{V O = V G + {V} 1 - (V T + V B) / 2} K = V G + (V 1 -V 2) K
As described above, the voltage V _O output from the subtraction amplification circuit in FIG. 3 becomes equal to the voltage V _O output from the subtraction amplification circuit in FIG. That is, a capacitor connected to the node NB by bisecting, it can be set voltage V ₂ to the midpoint between the voltage V _T and the voltage V _B. As shown in FIG. 5 when divided into four capacitor connected to the node NB, it is possible to set the voltage V ₂ to one of the 4 division point between the voltage V _T and the voltage V _B .

Similarly, it can be set to any voltage between the voltage V ₂ and the voltage V _T and the voltage V _B by dividing the capacitor connected to the node NB to any number.

In these cases, it is possible to use an external voltage as the voltage V _T and the voltage V _B. Therefore, it is possible to generate a voltage V ₂ with the external voltage.

  FIG. 6 is a circuit diagram of a subtraction amplifier circuit according to the third embodiment of the present invention. FIG. 7 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. This subtraction amplifier circuit is a fully differential subtraction amplifier circuit.

  In FIG. 6, the inverting input terminal of the operational amplifier 1 is connected to the node Na, and the non-inverting input terminal is connected to the node Nb. The inverting output terminal of the operational amplifier 1 is connected to the node NO1 and to the inverting input terminal via the capacitor 2a. The non-inverting output terminal is connected to the node NO2 and to the non-inverting input terminal via the capacitor 2b.

  Node Na is grounded via switch SW11, and node Nb is grounded via switch SW12. The node Na is connected to the node N11 via the capacitor 3a, and is connected to the node N12 via the capacitor 4a. Node Nb is connected to node N21 via capacitor 3b, and to node N22 via capacitor 4b. The switch SW13 is connected between the nodes NO1 and NO2. The switch SW13 operates at the same timing as the switches SW11 and SW12.

_A voltage that changes from V ₁ (+) to V _A is input to the node N11, and a voltage that changes from V _A to V ₂ (+) is input to the node N12. _A voltage that changes from V ₁ (−) to V _A is input to the node N21, and a voltage that changes from V _A to V ₂ (−) is input to the node N22. _VA is an arbitrary set voltage. Voltage V _O (+) is outputted from the node NO1, the voltage from the node NO2 V _O (-) is output. The difference voltage ΔV _O between the nodes NO1 and NO2 is expressed by the following equation.

ΔV _O = V _O (+) − V _O (−)
Next, the operation of the subtraction amplifier circuit of FIG. 6 will be described with reference to FIG. Here, the capacitance values of the capacitors 2a and 2b are each C, and the capacitance values of the capacitors 3a, 3b, 4a and 4b are each KC. K is a constant. In addition, the ground potential and V _G.

First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, the voltage V ₁ (+) is input to the node N11, the set voltage _VA is input to the node N12, the voltage V ₁ (−) is input to the node N21, and the set voltage _VA is input to the node N22. Node NO1, NO2 becomes the ground potential V _G. At this time, the charge QAA of the node Na is expressed by the following equation.

_{QAA = {V G -V 1 (} +)} KC + (V G -V A) KC
The charge QAB at the node Nb is expressed by the following equation.

_{QAB = {V G -V 1 (} -)} KC + (V G -V A) KC
Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, enter the set voltage V _A at the node N11, and the input voltage V ₂ (+) to the node N12, and inputs the setting voltage V _A at the node N21, the voltage V ₂ to the node N22 - enter a (). The voltages at the nodes NO1 and NO2 become V _O (+) and V _O (−), respectively. At this time, the charge QBA of the node Na is expressed by the following equation.

_{QBA = (V G -V A)} KC + {V G -V 2 (+)} KC + {V G -V O (+)} C
The charge QBB at the node Nb is expressed by the following equation.

_{QBB = (V G -V A)} KC + {V G -V 2 (-)} KC + (V G -V O (-)) C
Since the nodes Na and Nb do not have a path through which the charge escapes, QAA = QBA and QAB = QBB according to the law of conservation of charge, and the following equation holds.

V _O (+) = V _G + ｛V ₁ (+)-V ₂ (+)｝ K
V _O (−) = V _G + ｛V ₁ (−) − V ₂ (−)｝ K
Therefore, the differential voltage ΔV _O is expressed by the following equation.

ΔV _O = V _O (+) − V _O (−)
_{= {V 1 (+) -} V 1 (-)} K- {V 2 (+) - V 2 (-)} K
= (ΔV ₁ −ΔV ₂ ) K
It should be noted that ΔV ₁ = V ₁ (+) − V ₁ (−) and ΔV ₂ = V ₂ (+) − V ₂ (−).

Thus, in the subtraction amplifier circuit of the present embodiment, it is possible to perform subtraction and amplification of the difference voltage ΔV ₁ and the difference voltage ΔV ₂ .

Also in this subtraction amplifier circuit, the voltages V ₁ (+) and V ₂ (+) are input to the nodes N11 and N12 without passing through the switch, and the voltages V ₁ (−) and V ₂ (−) are not passed through the switch. Since the voltage is input to the nodes N21 and N22 and the set voltage _VA can be set arbitrarily, noise can be reduced and low-voltage operation can be performed.

  FIG. 8 is a circuit diagram of a subtraction amplifier circuit according to the fourth embodiment of the present invention. FIG. 9 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. The subtraction amplification circuit in FIG. 8 is also a fully differential subtraction amplification circuit.

The difference between the subtraction amplifier circuit of FIG. 8 and the subtraction amplifier circuit of FIG. 6 is that the voltage that changes from V ₁ (+) to V _A1 is input to the node N11 and the voltage changes from V _A2 to V ₂ (+) at the node N12. This is the point where a voltage that changes from V ₁ (−) to V _A1 is input to the node N21, and a voltage that changes from V _A2 to V ₂ (−) is input to the node N22. _VA1 and _VA2 are arbitrary set voltages, respectively. Other configurations are the same as those shown in FIG.

Next, the operation of the subtraction amplifier circuit of FIG. 8 will be described with reference to FIG. Here, the capacitance values of the capacitors 2a and 2b are respectively C, and the capacitance values of the capacitors 3a, 3b, 4a and 4b are each KC. K is a constant. In addition, the ground potential and V _G.

First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, the voltage V ₁ (+) is input to the node N11, the set voltage V _A2 is input to the node N12, the voltage V ₁ (−) is input to the node N21, and the set voltage V _A2 is input to the node N22. Node NO1, NO2 is respectively ground potential V _G.

Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, enter the set voltage V _A1 to the node N11, and the input voltage V ₂ (+) to the node N12, and inputs the setting voltage V _A1 to the node N21, the voltage V ₂ to the node N22 - enter a (). The voltages at the nodes NO1 and NO2 are V _O (+) and V _O (−), respectively.

When the voltages V _O (+) and V _O (−) of the nodes NO1 and NO2 are obtained by the charge conservation law in the same manner as in the third embodiment, the following expression is obtained.

V _O (+) = V _G + ΔV ₁ (+) − V ₂ (+) ΔK + (V _A1 −V _A2 ) K
V _O (−) = V _G + ΔV ₁ (−) − V ₂ (−) ΔK + (V _A1 −V _A2 ) K
Therefore, the differential voltage ΔV _O is expressed by the following equation.

ΔV _O = V _O (+) − V _O (−)
_{= {V 1 (+) -} V 1 (-)} K- {V 2 (+) - V 2 (-)} K
= ΔV ₁ −ΔV ₂
Thus, in the subtracting amplifier circuit of the present embodiment, it is possible to perform a subtraction and amplification of the differential voltage [Delta] V ₁ and the differential voltage [Delta] V ₂ even if unequal arbitrary set voltage V _A1 and V _A2.

Further, the voltages V ₁ (+) and V ₂ (+) can be input to the nodes N11 and N12 without using a switch, and the voltages V ₁ (−) and V ₂ (−) can be input to the nodes N21 and N21, respectively. Since the voltage can be input to N22 without using a switch and the set voltages V _A1 and V _A2 can be set arbitrarily, noise can be reduced and low-voltage operation can be performed.

  FIG. 10 is a block diagram showing a configuration of an analog-to-digital conversion circuit according to the fifth embodiment of the present invention. The analog-digital conversion circuit of FIG. 10 has a 10-bit 4-stage pipeline configuration.

  10, the analog-to-digital conversion circuit 101 includes a sample-and-hold circuit 102, a first-stage circuit 103, a second-stage circuit 104, a third-stage circuit 105, a fourth-stage circuit 106, and a plurality of latch circuits 107. And an output circuit 108.

  The first-stage (first-stage) to third-stage circuits 103 to 105 include a sub A / D converter 109, a D / A converter 110, and a difference amplifier 111. As described later, the subtraction amplifier circuit of the fourth embodiment is used as the difference amplifier 111. The circuit 106 at the fourth stage (final stage) includes only the sub A / D converter 109.

  The first-stage circuit 103 has a 4-bit configuration, and the second to fourth-stage circuits 104 to 106 each have a 2-bit configuration. In the circuits 103 to 105 of the first to third stages, the number of bits (bit configuration) n of the sub A / D converter 109 and the D / A converter 110 are set to be the same.

  Next, the operation of the analog-digital conversion circuit 101 will be described. The sample hold circuit 102 samples the analog input signal Vin and holds it for a certain period of time. The analog input signal Vin output from the sample and hold circuit 102 is transferred to the first stage circuit 3.

In the first-stage circuit 103, the sub-A / D converter 109 performs A / D conversion on the analog input signal Vin. Upper 4-bit digital output is A / D conversion result of the sub-A / D converter 109 (2 ^9, 2 ^8, 2 ^7, 2 ^6), while being transferred to the D / A converter 110, four latch circuits The signal is transferred to the output circuit 108 via the switch 107. The difference amplifier 111 amplifies the difference between the D / A conversion result of the D / A converter 110 and the analog input signal Vin. The output of the difference amplifier 111 is transferred to the circuit 104 in the second stage.

In the circuit 104 of the second stage, the same operation as that of the circuit 103 of the first stage is performed on the output of the differential amplifier 111 of the circuit 103 of the first stage. In the third-stage circuit 105, the same operation as that of the first-stage circuit 103 is performed on the output of the difference amplifier 111 of the second-stage circuit 104. Then, a digital output (2 ⁵ , 2 ⁴ ) of middle and lower 2 bits is obtained from the second stage circuit 104, and a digital output (2 ³ , 2 ² ) of middle and lower 2 bits is obtained from the third stage circuit 105. Can be

In the circuit 106 of the fourth stage, the sub-A / D converter 109 performs A / D conversion on the output of the differential amplifier 111 of the circuit 105 of the third stage, and outputs the lower 2 bits of digital output (2 ¹ , 2). ⁰ ) is obtained.

  The digital outputs of the circuits 103 to 106 of the first to fourth stages reach the output circuit 108 via the respective latch circuits 107 at the same time. That is, each latch circuit 107 is provided to synchronize the digital output of each of the circuits 103 to 106.

The output circuit 108 if necessary digital output D _out 10 bits of the analog input signal Vin is after digital correction processing parallel output.

  As described above, in the analog-digital conversion circuit 101, in each of the circuits 103 to 105, the analog input signal Vin or the output of the difference amplifier 111 of the preceding circuits 103 and 104 and the digital output of the circuits 103 to 105 of that stage are output. The difference between the output and the D / A conversion result is amplified by the difference amplifier 111.

  Therefore, even if the number of conversion bits increases and the LSB decreases, the resolution of each comparator constituting the sub A / D converter 109 can be substantially improved, and sufficient conversion accuracy can be obtained.

  FIG. 11 is a circuit diagram of the difference amplifier 111 in the analog-digital conversion circuit 101 of FIG. The difference amplifier 111 in FIG. 11 has the same configuration as the subtraction amplifier circuit in FIG.

  The differential amplifier 111 is supplied with the analog input signal Vin or the output of the differential amplifier 111 of the preceding circuits 103 to 105 as a differential voltage ΔVi. ΔVi = Vi (+) − Vi (−). The difference amplifier 111 is supplied with the D / A conversion result of the D / A converter 110 in the same stage as the difference voltage ΔVDA.

  ΔVDA = VDA (+) − VDA (−).

A voltage that changes from Vi (+) to V _A1 is input to the node N11, a voltage that changes from V _A2 to VDA (+) is input to the node N12, and a voltage that changes from Vi (−) to V _A1 is input to the node N21. varying voltage is input, the node N22 from V _A2 VDA (-) voltage that varies inputted.

Next, the operation of the difference amplifier 111 of FIG. 11 will be described with reference to FIG. First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, enter the voltage Vi (+) to the node N11, and inputs the setting voltage V _A2 to node N12, the voltage Vi at node N21 (-) inputs, and inputs the set voltage V _A2 to the node N22. Thereby, nodes NO1, NO2 becomes the ground potential V _G.

Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, enter the set voltage V _A1 to the node N11, and the input voltage VDA (+) to the node N12, and inputs the setting voltage V _A1 to the node N21, the voltage VDA at node N22 - enter a (). Thereby, the voltages of the nodes NO1 and NO2 become V _O (+) and V _O (−), respectively.

When the difference voltage ΔV _O is obtained in the same manner as in the subtraction amplifier circuit of FIG. 8, the following expression is obtained.

ΔV _O = V _O (+) − V _O (−)
= {Vi (+)-Vi (-)} K- {VDA (+)-VDA (-)} K
= (ΔVi-ΔVDA) K
As described above, the difference amplifier 111 of FIG. 11 performs subtraction and amplification of the difference voltage ΔVi given from the preceding stage and the difference voltage ΔVDA given from the D / A converter 110 in the same stage.

In this case, the set voltages V _A1 and V _A2 can be set arbitrarily. Therefore, the voltage at the time of equalizing (equalizing) the output of the sample-hold circuit 102 at the preceding stage or the output of the difference amplifier 111 can be used as the set voltage V _A1 . Further, an external voltage can be used as the set voltage _VA2 .

  As described above, since the voltages Vi (+) and Vi (-), which are analog input signals, can be input to the nodes N11 and N21 without passing through the switches, noise can be reduced and low-voltage operation can be performed. Become. Therefore, the voltage and accuracy of the analog-to-digital conversion circuit 101 can be reduced.

  FIG. 13 is a circuit diagram of the sub-A / D converter 109 and the D / A converter 110 in the analog-digital conversion circuit 101 of FIG. The sub A / D converter 109 in FIG. 13 is an all-parallel comparison (flash) type sub A / D converter, and the D / A converter 110 is a capacitance array type D / A converter.

  The sub A / D converter 109 includes n resistors R and n comparators D1 to Dn. All resistors R have the same resistance value, and are connected in series between node N31 receiving high-potential-side reference voltage VRT and node N32 receiving low-potential-side reference voltage VRB. Here, the potentials of the nodes N41 to N4n between the n resistors R between the node N32 and the node N31 are denoted by VR (1) to VR (n), respectively.

  The input signal VI (analog input signal Vin or the output of the differential amplifier 111 of the preceding circuits 103 to 105) is input to the positive input terminals of the comparators D1 to Dn. The potentials VR (1) to VR (n) of the nodes N41 to N4n are applied to the negative input terminals of the comparators D1 to Dn, respectively.

  As a result, the outputs of the comparators D1 to Dn become high level when the input signal VI is higher than the potentials VR (1) to VR (n), respectively, and the input signals VI become the potentials VR (1) to VR (n). When it is lower than (n), it becomes low level.

  The D / A converter 110 includes n switches E1 to En, F1 to Fn, G1 to Gn, H1 to Hn, n positive capacitors B1 to Bn, and n negative capacitors connected in an array. It is composed of capacitors C1 to Cn.

  The capacitors B1 to Bn and C1 to Cn all have the same capacitance value c. A differential positive output voltage VDA (+) is generated from one terminal (hereinafter, referred to as an output terminal) of the capacitors B1 to Bn, and is different from one terminal (hereinafter, referred to as an output terminal) of the capacitors C1 to Cn. The negative output voltage VDA (−) is generated. The other terminals of the capacitors B1 to Bn and C1 to Cn are called input terminals.

  One terminal of each of the switches E1 to En is connected to the node N31, and the other terminal is connected to input terminals of the capacitors B1 to Bn. One terminal of each of the switches F1 to Fn is connected to the node N31, and the other terminal is connected to input terminals of the capacitors C1 to Cn. One terminal of each of the switches G1 to Gn is connected to the node N32, and the other terminal is connected to input terminals of the capacitors B1 to Bn. One terminal of each of the switches H1 to Hn is connected to the node N32, and the other terminal is connected to input terminals of the capacitors C1 to Cn.

  Each of the switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn is a switch having the same number and constitutes a quad switch. For example, the switches E1, F1, G1, and H1 are connected in series and the switches En, Fn, Gn, and Hn are also connected in series. The switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn are turned on and off according to the output levels of the comparators D1 to Dn, respectively. For example, when the output of the comparator Dn is at a high level, the switches En and Hn are turned on, and the switches Gn and Fn are turned off. Conversely, when the output of the comparator Dn is at a low level, the switches En and Hn are turned off and the switches Gn and Fn are turned on.

  The output of the comparator D1 constituting the sub A / D converter 109 is open. Further, the switches E1 and F1 are fixed to an on state at a predetermined timing, and the switches G1 and H1 are fixed to an off state at a predetermined timing.

  The voltage range of the input signal VI of the sub-A / D converter 109 is from the high-potential-side reference voltage VRT to the low-potential-side reference voltage VRB. That is, the input signal VI of the sub-A / D converter 109 does not fall below the low potential side reference voltage VRB. Therefore, the output of the comparator D1 always goes to the high level. Therefore, the OFF state of each of the switches E1, G1, F1, and H1 can be fixed at a predetermined timing regardless of the output of the comparator D1.

  Next, the operation of the D / A converter 110 will be described. In the initial condition, the potentials of the input terminals and the output terminals of the capacitors B1 to Bn are both 0 V, and the switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn are all off. Therefore, in the initial condition, the electric charge (electric quantity) Q1 = 0 stored in all the capacitors B1 to Bn and C1 to Cn.

  Here, when the m outputs of the n comparators D1 to Dn become high level, m of the switches E1 to En are turned on and (nm) switches are turned off, and each of the switches G1 is turned off. Of (Gn), (nm) are on and m are off. According to the on / off operations of the switches E1 to En and G1 to Gn, the electric charge Q2 stored in all the capacitors B1 to Bn is represented by the following equation (A1).

Q2 = m (VRT-VDA (+)) c + (nm) (VRB-VDA (+))
c ... (A1)
According to the law of conservation of charge, Q1 = Q2. Therefore, the differential positive output voltage VDA (+) is expressed by the following equation (A2).

VDA (+) = VRB + m (VRT-VRB) / n (A2)
On the other hand, when the m outputs of the n comparators D1 to Dn become high level, m of the switches H1 to Hn are turned on and (nm) switches are turned off, and the switches F1 to Fn are turned off. Of the Fn, (nm) are turned on and m are turned off. According to the on / off operations of the switches H1 to Hn and F1 to Fn, the electric charge Q3 stored in all the capacitors C1 to Cn is represented by the following equation (A3).

Q2 = (nm) (VRT-VDA (-)) c + m (VRB-VDA (-))
c ... (A3)
According to the law of conservation of charge, Q1 = Q3. Therefore, the differential negative output voltage VDA (-) is represented by the following equation (A4).

VDA (−) = VRB− (m−1) (VRT−VRB) / n (A4)
Therefore, from the above equations (A2) and (A4), the difference voltage ΔVDA is expressed by equation (A5).

ΔVDA = VDA (+) − VDA (−)
= VRB-VRT + (m-1) (VRT-VRB) / n- (VRT-VRB)
/N...(A5)
FIG. 14 is a circuit diagram showing a specific configuration of the D / A converter 110 and the difference amplifier 111 when the subtraction amplifier circuit of the fourth embodiment is used for the difference amplifier 111 of the analog-digital conversion circuit 101 of FIG. is there.

In FIG. 14, a node N30 of the D / A converter 110 is connected to input terminals of capacitors B1 to Bn via switches S1 to Sn, respectively. The node N30 is connected to input terminals of capacitors C1 to Cn via switches T1 to Tn, respectively. The node N30 is input set voltage V _A2, the high reference voltage VRT is inputted to the node N31, the node N32 lower reference voltage VRB is inputted. Output terminals of the capacitors B1 to Bn are connected to a node Na of the difference amplifier 111, and output terminals of the capacitors C1 to Cn are connected to a node Nb of the difference amplifier 111.

  The node Na of the difference amplifier 111 is connected to the node N11 via the capacitor 3a, and the node Nb is connected to the node N21 via the capacitor 3b. The voltage Vi (+) is input to the node N11, and the voltage Vi (-) is input to the node N21.

  The capacitance values of the capacitors 2a and 2b are respectively C, and the capacitance values of the capacitors 3a and 3b are KC. The capacitance values of the capacitors B1 to Bn and C1 to Cn are respectively KC / n. K is a constant.

  Next, the operation of the D / A converter 110 and the difference amplifier 111 in FIG. 14 will be described.

First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, the switches S1 to Sn and T1 to Tn are turned on. As a result, the set voltage V _A2 is input to the input terminals of the capacitors B1 to Bn and C1 to Cn. Further, the voltage Vi (+) is input to the node N11, and the voltage Vi (-) is input to the node N21. Thereby, nodes NO1 and NO2 are set to the ground potential.

  Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, the switches S1 to Sn and T1 to Tn are turned off. Each of the switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn is turned on or off according to the output level of each of the comparators D1 to Dn in FIG. 13, respectively, and connected to the input terminals of the capacitors B1 to Bn and C1 to Cn, respectively. A voltage is applied.

At this time, the voltage inputted to the node N11, N21 Vi (+), Vi (-) , as shown in FIG. 12, are equalized in both voltage equal V _A1. As a result, the differential voltage ΔV _O between the nodes NO1 and NO2 is expressed by the following equation, as described with reference to FIG.

ΔV _O = V _O (+) − V _O (−) = ΔVi−ΔVDA
Thus, it is possible to use the output of the preceding differential amplifier 111 as a set voltage VA1 input to node N11, N21, and inputs the voltage Vi (+) and the set voltage V _A1 without using a switch node N11 The voltage Vi (−) and the set voltage V _A1 can be input to the node N21 without using a switch.

Further, an arbitrary voltage can be used as the set voltage V _A2 input to the node N30. For example, it is also possible to use a high-potential reference voltage VRT or lower reference voltage VRB as the set voltage V _A2.

Further, these set voltages V _A1 and V _A2 can be set near the power supply voltage or the ground voltage. This enables low-voltage operation even when using a CMOS switch.

  As a result, a high-precision analog-to-digital conversion circuit capable of reducing switch noise and operating at a low voltage is realized.

FIG. 2 is a circuit diagram of a subtraction amplifier circuit according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining an operation of the subtraction amplifier circuit of FIG. 1. FIG. 9 is a circuit diagram of a subtraction amplifier circuit according to a second embodiment of the present invention. FIG. 4 is a diagram for explaining an operation of the subtraction amplifier circuit of FIG. 3. It is a figure showing other examples of capacity division. FIG. 11 is a circuit diagram of a subtraction amplifier circuit according to a third embodiment of the present invention. FIG. 7 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. 6. FIG. 14 is a circuit diagram of a subtraction amplifier circuit according to a fourth embodiment of the present invention. FIG. 9 is a diagram for explaining the operation of the subtraction amplifier circuit in FIG. 8. FIG. 15 is a block diagram illustrating a configuration of an analog-to-digital conversion circuit having a multi-stage pipeline configuration according to a fifth embodiment of the present invention. FIG. 11 is a circuit diagram of a differential amplifier in the analog-to-digital converter of FIG. 10. FIG. 12 is a diagram for explaining the operation of the differential amplifier in FIG. FIG. 11 is a circuit diagram of a sub-A / D converter and a D / A converter in the analog-digital conversion circuit of FIG. FIG. 11 is a circuit diagram of a D / A converter and a difference amplifier when the subtraction amplification circuit according to the fifth embodiment is used as a difference amplifier of the analog-digital conversion circuit of FIG. FIG. 9 is a circuit diagram illustrating an example of a conventional difference amplifier. FIG. 16 is a diagram for explaining the operation of the differential amplifier in FIG.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Operational amplifier 2, 2a, 2b, 3a, 3b, 4a, 4b, B1 to Bn, C1 to Cn Capacitor 101 Analog-digital conversion circuit 102 Sample hold circuit 103 to 106 First to fourth stage circuit 109 Sub-A / D converter 110 D / A converter 111 Difference amplifier SW1, SW11-SW12, E1-En, G1-Gn, S1-Sn, F1-Fn, H1-Hn, T1-Tn Switches

Claims (3)

At least two stages including an analog-to-digital converter, a digital-to-analog converter, and a subtraction amplification circuit are provided, and an output of a preceding-stage subtraction amplification circuit and an input of a subsequent-stage subtraction amplification circuit form a switch for switching an input voltage. Connected without any intervention
The subtraction amplifier circuit has a configuration in which first and second capacitors are connected in parallel to one input terminal of an operational amplifier, and third and fourth capacitors are connected in parallel to the other input terminal of the operational amplifier. Has,
In the latter stage of the subtraction amplifier circuit, while the first and second input voltages are respectively applied to the input terminals of the first and third capacitors, an arbitrary input terminal of the second and fourth capacitors is provided. While the first set voltage is applied, and the arbitrary second set voltage is applied to the input terminals of the first and third capacitors, the second and fourth capacitors are connected to the input terminals of the second and fourth capacitors. The third input voltage and the fourth input voltage, respectively, provide a first differential input voltage that is a difference between the first input voltage and the second input voltage, and a third input voltage and a fourth input voltage. An analog-to-digital conversion circuit for performing subtraction and amplification with a second difference input voltage that is a difference from a voltage. 2. The analog-digital conversion circuit according to claim 1, wherein input terminals of said first and third capacitors are connected to an inverted output and a non-inverted output of a preceding stage subtraction amplifier circuit. The inverting output and the non-inverting output of the preceding subtraction amplifier circuit are used as the first and second input voltages, and the voltage equalized from the output of the preceding subtraction amplifier circuit is used as the second setting voltage. The analog-to-digital conversion circuit according to claim 1 or 2, wherein

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