JP2006033304A - Switched capacitor circuit and pipe line a/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the sampling period of a switched capacitor circuit for sampling and holding an analog differential signal. <P>SOLUTION: The switched capacitor circuit includes a capacitor C1 connected to the input terminal 3a of a differential amplifier 30; a capacitor C3 connected to the input terminal 3b of the differential amplifier 30; a comparator 31 for detecting level inversions of analog differential signals A<SB>i</SB><SP>p</SP>, A<SB>i</SB><SP>m</SP>; and a signal replacing circuit PX for supplying one of the signals A<SB>i</SB><SP>p</SP>, A<SB>i</SB><SP>m</SP>to the capacitor C1, supplying the other to the capacitor C3, and replacing these signals based on the output of the comparator 31. Changes in amounts of the electric charge of the capacitors C1, C3 are suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a switched capacitor circuit and a pipeline A / D converter. More specifically, the present invention relates to an improved switched capacitor circuit that controls charging / discharging of a capacitor using a switching element and samples and holds an analog differential signal. In addition, the present invention relates to an improvement in a pipeline A / D converter using a switched capacitor circuit.

  A pipeline method is conventionally known as an A / D conversion processing method that achieves both conversion rate and conversion accuracy and is relatively easy to integrate (for example, Patent Document 1). The pipeline method is a method that includes a plurality of stages for converting an analog signal into a low-resolution digital signal, and sequentially performs A / D conversion processing in each stage to generate a high-resolution digital signal. An A / D converter adopting such a pipeline system is called a pipeline A / D converter.

FIG. 17 is a block diagram showing a schematic configuration example of a conventional pipeline A / D converter. The pipeline A / D converter includes a plurality of conversion stages 11 to 15 are serially connected, the plurality of delay circuits 16, is constituted by an adder 17, and converts the analog signal A ₁ into a digital signal D _out be able to.

The analog signal A ₁ is converted into a 1.5-bit digital signal D ₁ in the first stage 11. At this time, the amplitude of the signal component that has not been digitally converted is amplified by a factor of ₂ , and is output to the second stage 12 as an analog signal A2. Similarly, in the second to fourth stages 12 to 14, the analog signals A _{2 to} A ₄ input from the immediately preceding stage are converted into 1.5-bit digital signals D _{2 to} D ₄ and unconverted components. Is amplified by a factor of 2 and output as analog signals A _{3 to} A ₅ to the next stage. In the fifth stage 15 is the final stage, which converts the analog signal A ₅ input from the fourth stage 14 of 2-bit digital signal D _5.

In each stage 11 to 14 except the last stage 15, a sampling period of the analog signal _A 1 to A ₄ is input, and a holding period for outputting an analog signal _A 2 to A _5, are alternately repeated. Further, the adjacent stages 11 to 14 are controlled so that if one is a sampling period, the other is a hold period. Here, it is assumed that the sampling period and the hold period are switched every half cycle (half clock) of the clock signal. In this case, the analog signal A ₁ is sequentially propagated between the stages 11 to 15 as analog signals A _{2 to} A ₅ while being delayed by half a clock, and the digital signals D _{1 to} D ₅ are transmitted in half. It is sequentially generated as a signal having a clock time delay.

The delay circuit 16 is a latch circuit that delays the digital signal by a half clock, and synchronizes the digital signals D _{1 to} D ₅ output from the stages 11 to 15 and inputs them to the adder circuit 17. In the adder circuit 17, these digital signals D _{1 to} D ₅ are added in order by shifting by 1 bit to obtain a 6-bit digital signal D _out .

FIG. 18 is a block diagram showing a configuration example of the i-th stage (i = 2 to 4) in FIG. Each stage includes a sub A / D converter 20, a sub D / A converter 21, an S / H (Sample & Hold) processing unit 22, an amplification processing unit 23, and an arithmetic processing unit 24. The analog signal A _i is input from the previous stage during the sampling period. Based on the analog signal A _i , the analog signal A _{i + 1} is output to the subsequent stage and the digital signal D _i is output to the delay circuit 16 during the hold period.

Sub A / D converter 20, an analog input signal _{A i} and digital conversion, and generates a 1.5-bit digital signal _{D i.} For example, if the variation range of the analog input signal _{A i} is -Vref～Vref, comparing the voltage level ± 1 / a (4 × Vref), one of the digital signals _{D i} of 10,01 or 00 generates Is done. This digital signal _Di is held by the sub A / D converter 20 during the hold period.

The sub D / A converter 21 converts the digital signal _Di into the analog signal _Ad again and outputs it to the arithmetic processing unit 24. The analog signal A _d is twice the digital signal D _i corresponds to the analog-converted signal, either Vref, 0 or -Vref is output as an analog signal A _d.

The S / H processing unit 22 samples the analog signal A _i input during the sampling period and holds it until the next hold period ends. The analog signal A _{i being held} is amplified by the amplification processing unit 23 and input to the arithmetic processing unit 24. Processing unit 24 is an analog subtracting means for subtracting the analog signal A _d from the amplified signal, the difference signal obtained is outputted as an analog signal A _{i + 1.}

  The S / H processing unit 22, the amplification processing unit 23, and the arithmetic processing unit 24 described above are realized as a switched capacitor circuit 25. The switched capacitor circuit 25 is an analog circuit including a capacitor and a switching element that controls charging / discharging of the capacitor, and these blocks 22 to 24 schematically show the functions of the switched capacitor circuit 25. .

FIG. 19 is a circuit diagram showing a configuration example of the switched capacitor circuit 25 of FIG. The switched capacitor circuit 25 includes a differential amplifier 30, capacitors C1 to C4, and switching elements S11 to S14 and S21 to S24. The analog signal A _i in FIG. _18, A i + _1, A _d are both differential signal formed from a set of non-inverted signal and an inverted signal, 19, is the sign at the end of the non-inverted signal "p ", And" m "is added to the end of the sign of the inverted signal.

  The switching elements S11 to S14 are circuits that make two terminals conductive during the sampling period and open during the hold period based on the clock signal. On the other hand, the switching elements S21 to S24 are circuits that open between two terminals during the sampling period and conduct during the hold period based on the clock signal.

Capacitors C1, C2 connected to the first input terminal 3a of the differential amplifier 30 during the sampling period, the non-inverted signal _A ^{i p} is applied via the respective switching elements S11, S12. On the other hand, during the hold period, the non-inverted signal A _d ^p is applied to the capacitor C1 via the switching element S21, and the capacitor C2 is connected to the first output terminal 30c of the differential amplifier 30 via the switching element S22. The In this case, if the capacitors C1 and C2 have the same capacitance, (2A _i ^p −A _d ^p ) is output as the non-inverted signal A _{i + 1} ^p during the hold period.

The operation on the inverted signal side is exactly the same as the operation on the non-inverted signal side. That is, if the capacitance of the capacitor C3, C4 are the same, during the hold period, the inverted signal _{^{A i + 1 m (2A i}} m -A d m) is output.
JP 2000-201054 A

In the pipeline A / D converter of FIG. 17, if attention is paid to the analog signal A ₁ at a certain time point, the analog signal A ₁ is input to the first stage 11, and then the digital signal D _out as the conversion result is obtained. 2.5 clocks are required to get it. However, since the processes in the stages 11 to 15 are executed in parallel with each other, A / D conversion can be performed on the analog signal A ₁ that is different for each clock cycle. For this reason, the pipeline A / D converter can achieve both the conversion rate and the conversion accuracy.

In such a pipeline A / D converter, in order to achieve a higher conversion rate, it is necessary to shorten the clock cycle and shorten the processing time in each stage 11-15. However, if the charging / discharging period of the capacitors C1 to C4 is not ensured, the conversion accuracy is significantly reduced. Therefore, charging and discharging time of the capacitor C1~C4 when the analog signal A _i input to each stage 11-14 is changed greatest were not define the limits of the conversion rate of the pipelined A / D converter .

  The present invention has been made in view of the above circumstances, and an object thereof is to shorten a sampling period in a switched capacitor circuit that samples and holds an analog differential signal. It is another object of the present invention to improve the conversion rate of a pipeline A / D converter using a switched capacitor circuit.

  A switched capacitor circuit according to a first aspect of the present invention includes a differential amplifier having a first input terminal and a second input terminal, a first capacitor having a first electrode connected to the first input terminal of the differential amplifier, and a differential A second capacitor having a first electrode connected to the second input terminal of the amplifier, an inversion detection circuit for detecting level inversion of the analog differential signal, and an analog difference supplied to the second electrodes of the first and second capacitors And a first signal replacement circuit that performs signal replacement on the motion signal.

  The first signal replacement circuit is a circuit that supplies one signal constituting an analog differential signal to the second electrode of the first capacitor and supplies the other signal to the second electrode of the second capacitor; Based on the output of the inversion detection circuit, the one and other signals are exchanged and supplied to the first and second capacitors.

  When the analog differential signal largely fluctuates, the voltage level of the non-inverted signal and the inverted signal is reversed. The inversion detection circuit detects this level inversion, and the first signal replacement circuit replaces the non-inversion signal and the inversion signal supplied to the first and second capacitors, thereby charging and discharging the first and second capacitors. Can be shortened. That is, the sampling time when used as a sampling hold circuit can be shortened.

  In the switched capacitor circuit according to a second aspect of the present invention, in addition to the above configuration, the first signal switching circuit supplies a non-inverted signal of the analog differential signal to the second electrode of the first capacitor. A second switching element that supplies an inverted signal of the analog differential signal to the second electrode of the first capacitor; a third switching element that supplies the non-inverted signal to the second electrode of the second capacitor; And a fourth switching element for supplying the inverted signal to the second electrode of the second capacitor. With this configuration, the first signal replacement circuit can be realized.

  According to a third aspect of the present invention, in addition to the above configuration, the switched capacitor circuit according to the third aspect of the present invention is configured so that the first signal switching circuit connects the first and second switching elements to the second electrode of the first capacitor. A switching element; and a sixth switching element that connects the third and fourth switching elements to the second electrode of the second capacitor.

  With such a configuration, the number of switching elements connected to the second electrodes of the first and second capacitors can be suppressed. For this reason, it can suppress that the capacity | capacitance of a 1st and 2nd capacitor fluctuates by adding a signal switching circuit.

  According to a fourth aspect of the present invention, in addition to the above-described configuration, the inversion detection circuit includes a comparator that compares the non-inversion signal and the inversion signal that constitute the analog differential signal. With such a configuration, an inversion detection circuit can be realized.

  In a switched capacitor circuit according to a fifth aspect of the present invention, a third capacitor having a first electrode connected to the first input terminal of the differential amplifier, and a first electrode connected to the second input terminal of the differential amplifier. The fourth capacitor, the second electrode of the third capacitor connected to the first output terminal of the differential amplifier, the seventh switching element forming a feedback circuit, and the second electrode of the fourth capacitor An eighth switching element that is connected to the second output terminal of the differential amplifier and forms a feedback circuit, and a second signal that performs signal replacement for the analog differential signal supplied to the second electrodes of the third and fourth capacitors And a replacement circuit.

  The second signal replacement circuit is a circuit that supplies one signal constituting an analog differential signal to the second electrode of the third capacitor and supplies the other signal to the second electrode of the fourth capacitor; Based on the output of the inversion detection circuit, the one and other signals are exchanged and supplied to the third and fourth capacitors. With such a configuration, the charge / discharge time of the third and fourth capacitors can be shortened.

  A pipeline A / D converter according to a sixth aspect of the present invention is obtained by serially connecting a plurality of conversion stages each having a switched capacitor circuit for sampling and holding an analog differential signal and performing digital conversion in each conversion stage. A pipeline A / D converter that generates a high-resolution digital signal based on a low-resolution digital signal, and performs level inversion of the analog differential signal input to the switched capacitor circuit of the n-th conversion stage. An inversion detection circuit for detecting, and a signal replacement circuit for exchanging one and the other of the analog differential signals input to the switched capacitor circuit of the nth conversion stage based on the output of the inversion detection circuit. Composed. Note that n is an arbitrary natural number.

  With such a configuration, level inversion of the analog differential signal input to the nth conversion stage is detected, and signal replacement is performed for the analog differential signal input to the switched capacitor circuit of the conversion stage. The charge / discharge time of the capacitor in the switched capacitor circuit can be shortened. That is, the sampling time in the nth stage can be shortened.

  In addition to the above configuration, the pipeline A / D converter according to the seventh aspect of the present invention receives the (n + 1) th conversion stage from the nth conversion stage based on the output of the inversion detection circuit. The sub-A / D converter converts the analog differential signal into a digital signal. With such a configuration, even when the signal replacement of the analog differential signal is performed in the nth stage, the digital conversion can be correctly performed in the n + 1th stage.

  Further, in the pipeline A / D converter according to the eighth aspect of the present invention, in addition to the above configuration, the inversion detection circuit detects level inversion of the analog differential signal input to the first conversion stage, The signal replacement circuit is configured to perform signal replacement of the analog differential signal input to the switched capacitor circuit of the first conversion stage based on the output of the inversion detection circuit. Since the stage where the sampling time shortage most affects the conversion accuracy is the first stage, a pipeline A / D converter with high conversion accuracy can be realized with such a configuration.

  The pipeline A / D converter according to the ninth aspect of the present invention has a switched capacitor circuit for sampling and holding in addition to the above-described configuration, and the analog differential signal being held is supplied to the first conversion stage. An input sampling circuit is provided, and the inversion detection circuit detects level inversion of the analog differential signal input to the first conversion stage based on an input signal to the switched capacitor circuit of the input sampling circuit. Configured as follows. With such a configuration, level inversion detection can be performed before an analog differential signal is input to the first stage, so that the sampling period can be further shortened.

  In the pipeline A / D converter according to the tenth aspect of the present invention, the signal replacement circuit switches an input signal to the switched capacitor circuit of the input sampling circuit, and the input sampling circuit switches to the first conversion stage. It is configured to supply an analog differential signal after signal replacement. With this configuration, the analog differential signal is switched before the analog differential signal is input to the first stage, and the analog differential signal after the signal replacement is supplied to the first stage. can do. Therefore, the sampling period can be further shortened.

  According to the present invention, a sampling period in a switched capacitor circuit that samples and holds an analog differential signal can be shortened. In addition, the conversion rate can be improved by shortening the sampling time of each stage constituting the pipeline A / D converter.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration example of a switched capacitor circuit according to the first embodiment of the present invention. This switched capacitor circuit includes a differential amplifier 30, a comparator 31, four capacitors C1 to C4, and twelve switching elements S11 to S14, S21 to S24, and S31 to S34.

The switched capacitor circuit receives analog differential signals A _i and A _d and outputs an analog differential signal A _{i + 1} . These analog differential signals are both composed of a non-inverted signal and an inverted signal. The non-inverted signal has “p” at the end of the sign, and the inverted signal has “m” at the end of the sign. . Similarly to the conventional switched capacitor circuit (FIG. 19), a clock signal (not shown) defining a sampling period and a hold period is input to the switched capacitor circuit, and the sampling period and the hold period are alternately repeated.

  The differential amplifier 30 is an amplifier circuit that amplifies an analog differential signal. A non-inverted signal is input to the first input terminal 3a, and the amplified signal is output from the first output terminal 3c. The inverted signal is input to the second input terminal 3b, and the amplified signal is output from the second output terminal 3d.

  The first electrodes of the capacitors C1 and C2 are both connected to the first input terminal 3a of the differential amplifier 30. The second electrode of the capacitor C1 is connected to the switching elements S11, S21, and S31, and the second electrode of the capacitor C2 is connected to the switching elements S12, S22, and S32.

  Similarly, the first electrodes of the capacitors C3 and C4 are both connected to the second input terminal 3b of the differential amplifier 30. The second electrode of the capacitor C3 is connected to the switching elements S13, S23, and S33, and the second electrode of the capacitor C4 is connected to the switching elements S14, S24, and S34.

The comparator 31 compares the voltage level of the non-inverted signal A _i ^p and the inverted signal A _i ^m, and outputs a comparison signal CP _i indicating the comparison result. In general, a non-inverted signal and an inverted signal constituting an analog differential signal are composed of an in-phase component and an anti-phase component. That is, the non-inverted signal is composed of the sum of the in-phase component and the anti-phase component, and the inverted signal is composed of the difference between them. For this reason, if the sign of the anti-phase component changes, the voltage levels of both signals are reversed. In the present specification, this inversion of the voltage level is referred to as “level inversion” of the analog differential signal. The comparator 31 is an inversion detection circuit that detects level inversion of the analog differential signal A _i , and a comparison signal CP _i is generated as an inversion detection result.

  The switching elements S11 to S14, S21 to S24, and S31 to S34 are well-known circuits that can control conduction and opening between two terminals, for example, switching circuits made of MOS. Hereinafter, in the present specification, the reference symbol S1x is used as a generic term for the switching elements S11 to 14, the reference symbol S2x is used as a generic term for the switching elements S21 to S24, and the reference symbol S3x is used as a generic term for the switching elements S31 to S34.

The switching element S2x is controlled based on the clock signal, and is open during the sampling period and is conductive during the hold period. On the other hand, the switching elements S1x and S3x are controlled based on the clock signal and the comparison signal CP _i and are in a conductive state only during the sampling period. Specifically, the switching element S1x during the hold period, S3x are both open, during the sampling period, based on the comparison signal CP _i, one conduction state of the switching device S1x and the switching element S3x And the other is open.

Switching element S11,12 is a non-inverted signal _A ^{i p} a circuit for applying respectively to the second electrode of the capacitor C1, C2. The switching element S31,32 is a circuit for applying respective inverted signals _A ^{i m} to the second electrode of the capacitor C1, C2. That is, the capacitors C1, C2 during the sampling period, based on the comparison signal CP _i, either the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m} is applied.

Similarly, the switching element S13,14 is a circuit for applying respective inverted signals _A ^{i m} to the second electrode of the capacitor C3, C4. The switching element S33,34 is a non-inverted signal _A ^{i p} a circuit for applying respectively to the second electrode of the capacitor C3, C4. Therefore, the capacitor C3, C4 during the sampling period, among the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m,} the signal is not applied to the capacitor C1, C2 is applied.

Signal replacement circuit PX shown by the broken line in the figure, the switching element S1x, is constituted by S3x, switches the transmission path of the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m,} it is supplied to the capacitor C1~C4 This is a circuit for switching the signals A _i ^p and A _i ^m . That is, the input signal to the capacitor C1 is input by the switching elements S11 and S31, the input signal to the capacitor C2 is input by the switching elements S12 and S32, and the input signal to the capacitor C3 is input by the switching elements S13 and S33 to the input signal to the capacitor C4. Are switched by switching elements S14 and S34, respectively. This switching operation is performed on the basis of a comparison signal CP _i, one of the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m} is supplied to the capacitor C1, C2, the other is supplied to the capacitor C3, C4. In this specification, such replacement processing between a non-inverted signal and an inverted signal is referred to as “signal replacement” of an analog differential signal.

The switching element S21 is a circuit for applying the non-inverted signal A _d ^p to the second electrode of the capacitor C1 during the hold period. The switching element S23 is in the hold period, a circuit for applying the inverted signal A _d ^m to the second electrode of the capacitor C3.

  The switching element S22 is a circuit for connecting the first output terminal 3c of the differential amplifier 30 to the second electrode of the capacitor C2. That is, during the hold period, the capacitor C2 is connected between the first input terminal 3a and the first output terminal 3c of the differential amplifier 30, and a feedback loop is formed.

  Similarly, the switching element S24 is a circuit for connecting the second output terminal 3d of the differential amplifier 30 to the second electrode of the capacitor C4. That is, during the hold period, the capacitor C4 is connected between the second input terminal 3b and the second output terminal 3d of the differential amplifier 30, and a feedback loop is formed.

FIG. 2 is a timing chart showing an example of the operation of the switched capacitor circuit of FIG. In the figure, (a) is a clock signal, (b) is an analog differential signal A _i , (c) is a comparison signal CP _i of the comparator 31, and (d) to (f) are states of the switching elements S1x, S3x, S2x. , (G) is the charge amount of the capacitors C1 and C2, and (h) is the charge amount of the capacitors C3 and C4.

In this switched capacitor circuit, during the sampling period when the clock signal is at a low level, one of the switching elements S1x and S3x is conducted, and the capacitors C1 to C4 are charged and discharged. On the other hand, during the hold period in which the clock signal is at a high level, the switching element S2x conducts, and a predetermined analog differential signal A _{i + 1} is output from the differential amplifier 30. For example, when C1 = C2 and C3 = C4, (2A _i −A _d ) is output as the analog differential signal A _{i + 1} .

The comparator 31 has a non-inverting signal _A ^{i p} and the voltage level of the inverted signal _A ^{i m} which constitutes the analog differential signals _{A i may} output the _A ^{i p} ≧ _A ⁱ if ^m of low level comparison signal CP _i If A _i ^p <A _i ^m , a high level comparison signal CP _i is output. Then, during the sampling period, the comparison signal CP _i is equal at a low level to conduct the switching element S1x is, the switching element S3x is conductive if a high level. Therefore, among the signals _A ⁱ _{p, A} ^{i _m,} high-level signal is always supplied to the capacitor C1, C2, the low level signal is always supplied to the capacitor C3, C4.

In (g) and (h) in the figure, the operation of the switched capacitor circuit (FIG. 1) according to the present embodiment is shown by a solid line, and the operation of the conventional switched capacitor circuit (FIG. 19) is shown by a one-dot chain line as a comparative example. Is shown. In this embodiment, when the analog differential signals A _i varies greatly by utilizing the fact with level inversion, by performing replacement signal of the analog differential signals A _i at level inversion, capacitors C1~C4 The fluctuation of the charge amount is suppressed.

In conventional switched capacitor circuit in response to the analog differential signals A _i, the charge amount of the capacitor C1~C4 also vary, if analog differential signal A _i is changed greatly, long charge and discharge time of the capacitor C1~C4 Become. In contrast, in the switched capacitor circuit according to this embodiment, if the analog differential signals A _i is level inversion, the signal replacement circuit PX is interchanged non-inverted signal A _i ^p and the inverted signal A _i ^p, each capacitor It supplies to C1-C4. For this reason, the charge / discharge time when the level of the analog signal _Ai is inverted does not become longer than the maximum charge / discharge time when the level is not inverted.

  That is, the signal replacement circuit PX can reduce the maximum charge / discharge charge amount for the capacitors C1 to C4 to ½, and can greatly shorten the maximum charge / discharge time of the capacitors C1 to C4. Since the sampling period of the switched capacitor circuit is determined by the maximum charge / discharge time of the capacitors C1 to C4, if the maximum charge / discharge time is shortened, the sampling time can be shortened, and the switched capacitor circuit is operated at high speed. Can do.

Embodiment 2. FIG.
In the first embodiment, an example of a switched capacitor circuit in which two switching elements are connected to the second electrodes of the capacitors C1 to C4, respectively, to perform signal replacement has been described. This switched capacitor circuit increases the parasitic capacitance of the capacitors C1 to C4 and increases the error of the analog differential signal A _{i + 1} compared to the conventional switched capacitor circuit (FIG. 19). Therefore, in this embodiment, a switched capacitor circuit in which the parasitic capacitance is suppressed will be described.

  FIG. 3 is a diagram showing a configuration example of the switched capacitor circuit according to the second embodiment of the present invention. The switched capacitor circuit includes a differential amplifier 30, a comparator 31, four capacitors C1 to C4, and twelve switching elements S11 to S14, S21 to S24, S41, S42, S51, and S52. . In addition, code | symbol S4x is used as a general term for switching element S41,42, and code | symbol S5x is used as a generic term for switching element S51, S52.

  The operation of the switching elements S1x and S2x is the same as that of the conventional switched capacitor circuit. That is, the switching element S1x is in a conductive state during the sampling period and is in an open state during the hold period. The switching element S2x is in an open state during the sampling period and is in a conductive state during the hold period.

The switching elements S11 and S12 have one terminal connected to the second electrodes of the capacitors C1 and C2, the other terminal connected to each other, and the connection point connected to the switching elements S41 and S51. The switching element S41 is a circuit for supplying a non-inverted signal A _i ^p to the connection point, the switching element S51 is a circuit for supplying an inverted signal A _i ^m to the connection point. That is, the signal _A ⁱ p to the capacitor _C1, the supply of the _A ^{i m} are both performed through the switching device S11, the signal _A ⁱ _{p, A} ⁱ the supply of ^m are each switching device S12 to the capacitor C2 Is done through.

In exactly the same manner, switching elements S13 and S14 have one terminal connected to the second electrode of capacitors C3 and C4, the other terminal connected to each other, and the connection point connected to switching elements S42 and S52. ing. The switching element S42 is a circuit for supplying a non-inverted signal A _i ^p to the connection point, the switching element S52 is a circuit for supplying an inverted signal A _i ^m to the connection point. That is, the application of the signal _A ⁱ _{p, A} ^{i m} for capacitor C3 are all performed through the switching device S13, the signal _A ⁱ _{p, A} ⁱ the application of ^m are each switching device S14 to the capacitor C4 Is done through.

Signal replacement circuit PX shown by the broken line in the figure, the switching element S4x, is constituted by S5x, by switching the propagation path of the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m,} it is supplied to the capacitor C1~C4 This is a circuit for exchanging signals A _i ^p and A _i ^m . That is, the input signals to the capacitors C1 and C2 are both switched by the switching elements S41 and S51, and the input signals to the capacitors C3 and C4 are both switched by the switching elements S42 and S52. This switching operation is performed on the basis of a comparison signal CP _i, one of the non-inverted signal _A ^{i p} and the inverted signal _A ^{i m} is supplied to the capacitor C1, C2, the other is supplied to the capacitor C3, C4.

FIG. 4 is a timing chart showing an example of the operation of the switched capacitor circuit of FIG. In the figure, (a) is a clock signal, (b) is an analog differential signal A _i , (c) is a comparison signal CP _i of the comparator 31, and (d) to (g) are switching elements S1x, S2x, S4x, S5x. It is a state.

According to the present embodiment, the signal replacement circuit PX for performing the signal replacement of the analog differential signal A _i without increasing the number of switching elements connected to the second electrodes of the capacitors C1 to C4 is switched capacity. Can be introduced into a data circuit.

If the number of switching elements connected to the second electrodes of the capacitors C1 to C4 increases, the parasitic capacitance increases, and it becomes difficult to set the capacitances of the capacitors C1 to C4 to a desired value. Since the amplification factor of the switched capacitor circuit is determined based on the capacitances of the capacitors C1 to C4, the capacitance error of the capacitors C1 to C4 appears as an error of the analog signal _{Ai + 1} . On the other hand, in the switched capacitor circuit according to the present embodiment, the sampling time can be shortened without increasing the error of the analog signal A _{i + 1} .

Embodiment 3 FIG.
FIG. 5 is a block diagram showing a configuration example of the pipeline A / D converter according to the third embodiment of the present invention. FIG. 6 is a block diagram showing a configuration example of the i-th stage (i = 2 to 4) in FIG.

  Each of the stages 12 to 14 includes a sub A / D converter 20N, a sub D / A converter 21N, and a switched capacitor circuit 25N.

For example, the circuit shown in FIG. 1 or 3 is used as the switched capacitor circuit 25N. That is, in addition to the S / H unit 22, amplification processing unit 23 and the arithmetic processing unit 24 performs a comparator 31 for detecting the level inversion of the analog differential signals A _i, a replacement signal of the analog differential signals A _i signal and a circuit PX replacement, on the basis of the analog differential signals _{a i,} and generates an analog differential signals _{a i + 1} and the comparison signal CP _i.

The analog differential signal A _i is input from the (i−1) th stage, and the analog differential signal A _{i + 1} is output to the (i + 1) th stage. The comparison signal CP _i is output to each stage subsequent to the i-th stage. The comparison signal CP _i is delayed by half a clock by a delay circuit (not shown) and sequentially input to each stage.

The sub A / D converter 20N converts the analog differential signal A _i into a digital signal D _i based on the comparison signals CP _{1 to} CP _i−1 generated in each stage preceding the i-th stage. Yes. If replacement signal in a more previous stage has been performed, the analog differential signals A _i input to the i-th stage, the non-inverted signal A _i ^p and the inverted signal A _i ^m are interchanged. Therefore, the sub-A / D converter 20N, first, after the digital signal digitally converted analog differential signals _{A i} were determined _{D d,} based on the comparison signal _{CP 1 ~CP i-1,} the digital signal It corrected dd, seeking the correct digital signal _{D i.}

Sub D / A converter 21N, based on the comparison signal CP _i of the comparator 31, a digital signal _{D d} before correction analog conversion, and generates an analog differential signal _{A d.} When signal replacement is performed in the i-th stage signal replacement circuit PX, the input signal from the amplification processing unit 23 to the arithmetic processing unit 24 is a signal after signal replacement. Therefore, the sub D / A converter 21N also based on the comparison signal CP _i, is performed replacement signal of the analog differential signals _{A d.} Incidentally, D / A converter 21N is constitutively by the switching circuit for selectively outputting one of a plurality of reference voltages, generating the analog differential signals A _d after replacement signal is easily realized be able to.

FIG. 7 is a block diagram showing a configuration example of the first stage in FIG. Since the first stage 11 does not receive a comparison signal from the previous stage, a conventional sub A / D converter 20 is used instead of the sub A / D converter 20N, and the sub D / A converter 21N includes digital signal _{D 1} is input. Other configurations are the same as those of the stages 12 to 14.

Incidentally, the fifth stage is the final stage is constituted by only the sub A / D converter 20 N, a digital signal D _d before correction is not used.

According to the present embodiment, each of the stages 11 to 14 (excluding the final stage 15) constituting the pipeline A / D converter has the switched capacitor circuit 25N that samples and holds the analog differential signal. ing. These stages 11 to 14, a comparator 31 for detecting the level inversion of the analog differential signals A _i, based on the output of the comparator 31, the signal replacement circuit for performing replacement signal of the analog differential signals A _i PX.

  Therefore, in each stage 11 to 14, the level inversion of the analog differential signal is detected, the signal is switched for the analog differential signal input to the switched capacitor circuit 25N in the stage, and the switched capacitor circuit 25N is changed. The charging / discharging time of the capacitor which comprises can be shortened. Therefore, the sampling time in each stage can be shortened and the conversion rate can be improved.

Embodiment 4 FIG.
In the third embodiment, an example of a pipeline A / D converter that enables signal replacement in each stage 11 to 14 has been described. However, the configuration is such that signal replacement is possible in one or more arbitrary stages. Also good. In the present embodiment, an example of a pipeline A / D converter in which signal replacement is performed in the first stage 11 will be described.

  FIG. 8 is a block diagram showing a configuration example of a pipeline A / D converter according to the fourth embodiment of the present invention. FIG. 9 is a block diagram showing a configuration example of the i-th stage (i = 2 to 4) in FIG.

The first stage 11 includes a comparator 31 and Embodiment 3 the circuit of Figure 7 having a signal replacement circuit PX is adopted, at the time the level inversion of the analog differential signals A ₁ signal replacement is performed. On the other hand, later stage of each stage 12-15 is constructed without providing the comparator 31 and the signal replacement circuit PX, the sub A / D converter 20 N, a digital conversion of the analog signal _{A i} on the basis of a comparison signal CP ₁ The sub A / D converter 21 converts the digital signal D _d before correction into an analog signal _Ad .

  In the present embodiment, an example of a pipeline A / D converter in which signal replacement is performed in the first stage 11 has been described. However, some stages constituting the pipeline A / D converter include one or more stages. It is also possible to configure so that level inversion detection and signal replacement of an input analog differential signal can be performed at any stage. In that case, a conventional circuit (FIG. 18) is used for a stage preceding the stage where signal replacement is performed first.

  In this way, any stage can be configured to be able to replace the signal, and the A / D conversion is performed in consideration of the signal replacement in the stage subsequent to the stage, thereby simplifying the circuit configuration of the subsequent stage. The circuit scale of the pipeline A / D converter can be reduced.

  In the case of a pipeline A / D converter, the influence of the sampling time shortage at each stage on the conversion accuracy becomes greater as the previous stage. For this reason, when signal replacement is performed in any one of the stages 11 to 14, it is particularly desirable to perform signal replacement in the first stage 11.

Embodiment 5. FIG.
In the fourth embodiment, an example of a pipeline A / D converter in which both level inversion detection and signal replacement are performed during the sampling period of the first stage 11 has been described. On the other hand, in the present embodiment, a pipeline A / D converter that can further shorten the sampling period by performing level inversion detection prior to the sampling period of the first stage 11 will be described.

  FIG. 10 is a block diagram showing a configuration example of a pipeline A / D converter according to the fifth embodiment of the present invention. In this pipeline A / D converter, a plurality of stages 11 to 15 are serially connected, and an input sampling circuit 10 is provided before the first stage 11.

The input sampling circuit 10, an analog input signal A ₀ and the reference voltage V _R is inputted. The analog input signal _A0 is an external input signal to be A / D converted, and is a single-ended signal. Reference voltage V _R is the external input voltage to provide a reference voltage of the analog input signal A _0.

The input sampling circuit 10, for the analog input signal A _0, convert to analog differential signals, comprising a switched capacitor circuit which performs the sampling and hold output signal of the switched capacitor circuit comprises first as an analog differential signal A ₁ 1 stage 11 is supplied. The sampling period and hold period of the input sampling circuit 10 are alternately repeated based on the clock signal, and if one of the input sampling circuit 10 and the first stage 11 is the sampling period, the other is the hold period. Be controlled.

The input sampling circuit 10 includes a comparator for comparing the analog input signal A ₀ and the reference voltage V _R to the sampling period, the analog differential signals A ₁ to be output to the first stage 11 to the next hold period, the level Inversion detection is performed. The comparison signal CP ₀ which is the level inversion detection result is delayed by half a clock by the delay circuit 16 and is sequentially input to the stages 11 to 15. That is, the for the first stage 11 instructs the replacement signal of the analog differential signals _{A 1,} also, for the other stages 12-15, the signal replacement for analog differential signals _A 2 to A ₅ A / D conversion is taken into consideration.

In the first stage 11, by an analog differential signals _{A 1} to convert A / D, the digital signal _{D 1} is obtained. Further, the signal exchange of the analog differential signal A ₁ is performed based on the comparison signal CP ₀ . In other stages 12-15, the comparison signal on the basis of the CP ₀ is performed A / D conversion, the digital signal _D 2 to D ₅ are determined.

FIG. 11 is a diagram showing a configuration example of the first stage 11 of FIG. The first stage 11 is different from the case of FIG. 7 (Embodiment 3) in that the switched capacitor circuit 25N ′ does not include the comparator 31. Signal replacement circuit PX and the sub D / A converter 21N are operating on the basis of a comparison signal CP ₀ from the input sampling circuit 10.

The other stages 12 to 15 are the same as those in the fourth embodiment except that the comparison signal CP ₀ is input instead of the comparison signal CP ₁ , and thus the description thereof is omitted.

  FIG. 12 is a diagram showing a configuration example of the input sampling circuit 10 of FIG. The input sampling circuit 10 includes a differential amplifier 32, four capacitors C5 to C8, and seven switching elements S61 to S64 and S71 to S73. The switching elements S63 and S64 are switching circuits that connect and open three terminals. Further, the reference symbol S6x is used as a generic term for the switching elements S61 to 64, and the reference symbol S7x is used as a generic term for the switching elements S71 to 73.

The first electrodes of the capacitors C5 and C7 are both connected to the first input terminal 3a of the differential amplifier 32, and the second electrodes of the capacitors C5 and C7 are connected to the switching elements S61 and S72, respectively. The switching element S61 is a circuit for supplying an analog input signal _{A 0} to the capacitor C5. The switching element S72 is a circuit for connecting the first output terminal 3c of the differential amplifier 32 to the capacitor C7, and when conducting, a feedback loop between the first input terminal 3a and the first output terminal 3c of the differential amplifier 30. Is formed.

The first electrodes of the capacitors C6 and C8 are both connected to the second input terminal 3b of the differential amplifier 32, and the second electrodes of the capacitors C6 and C8 are connected to the switching elements S62 and S73, respectively. The switching element S62 is a circuit for supplying a reference voltage _{V R} to the capacitor C6. The switching element S73 is a circuit for connecting the second output terminal 3c of the differential amplifier 32 to the capacitor C8. When conducting, the switching element S73 is a feedback loop between the second input terminal 3b and the second output terminal 3d of the differential amplifier 30. Is formed.

The switching element 63, the input terminals 3a of the differential amplifier 32 is a circuit for applying a reference voltage _{V 0} to 3b, the switching element 64, both output terminals 3c of the differential amplifier 32, a reference voltage _{V 0} to 3d It is a circuit to apply. The reference voltage V ₀ becomes an in-phase component of the analog differential signal A ₁ . The switching element S71 is a circuit for short-circuiting the second electrodes of the capacitors C5 and C6.

During the sampling period, the switching means S6x is in a conducting state and the switching means S7x is in an open state. At this time, the capacitor C5, C6, analog input signal _{A 0,} the reference voltage _{V R} is applied, respectively. Further, the reference voltage V ₀ is applied to the input / output terminals 3a to 3d of the differential amplifier. On the other hand, during the hold period, the switching means S6x is opened, the switching means S7x is rendered conductive, non-inverted signals A ₁ ^p and the inverted signal A ₁ ^m constitute the analog differential signals A ₁ is output.

The comparator 33 compares the voltage level of the analog input signal A ₀ and the reference voltage V _R, and outputs a comparison signal CP ₀ indicating the comparison result. In other words, the level of the analog differential signals A ₁ inverted output to the first stage to the next hold period is detected based on an analog input signal A ₀ and the reference voltage V _R during the sampling period.

According to the present embodiment, the input sampling circuit 10 is provided before the first stage 11, and the level inversion of the analog differential signal A ₁ is detected based on the input signal of the input sampling circuit 10. Therefore, prior to the analog differential signals A ₁ is input to the first stage 11, the level inversion detection can be performed in, compared with the case of the fourth embodiment, to shorten the sampling period be able to.

Incidentally, by providing the input sampling circuit 10, the first stage 11, and held from the analog differential signal A ₁ is input, the sub-A / D converter 20 and the switched-capacitor circuit of the first stage 11 The error of the analog differential signal A _{i + 1} caused by the difference in the operation timing of 25N ′ can also be suppressed.

Embodiment 6 FIG.
In the fifth embodiment, the input sampling circuit 10 has been described for an example of a pipelined A / D converter that performs level inversion detection of the analog differential signals A _1. In contrast, in the present embodiment, in the input sampling circuit 10 will be described pipelined A / D converter level inversion detection and the signal of the analog differential signals A ₁ replacement is performed.

FIG. 13 is a diagram showing a configuration example of the input sampling circuit 10 according to the sixth embodiment of the present invention. Compared to FIG. 12, the difference is that switching elements S81 and S82 are further provided. The switching element S81 is a circuit for applying a reference voltage _{V R} to the second electrode of the capacitor C5. The switching element S82 is a circuit for applying an analog input signal A ₀ to the second electrode of the capacitor C6.

Signal replacement circuit PX shown by the broken line in the figure, is constituted by the switching elements S61,62,81 and 82, by switching the propagation path of the analog input signal _{A 0} and the reference voltage _{V R,} supplied to the capacitor C5, C6 a circuit for switching the signal _a 0, _{V R} being. The signal switching by the signal replacement circuit PX, it is possible to replace the non-inverted signal A _i ^p and the inverted signal A _i ^m of the analog differential signals A _1.

The input signal to the capacitor C5 is switched by switching elements S61 and S81, and the input signal to the capacitor C6 is switched by switching elements S62 and S82, respectively. These switching elements are controlled based on the clock signal and the comparison signal CP ₀ , and both switching elements are opened during the hold period, and during the sampling period, based on the comparison signal CP ₀ , the switching elements S 61, One of S62 and switching elements S81 and S82 is in a conductive state, and the other is in an open state.

According to this embodiment, the input sampling circuit 10 that performs sampling and holding at the preceding stage than the first stage 11, level inversion detection and signal of the analog differential signals A ₁ replacement is both performed. Therefore, before the start of the sampling period of the first stage 11, the replacement level inversion detection and the signal of the analog differential signal A _i is completed. Therefore, the sampling period can be further shortened compared to the case of the fifth embodiment.

  Further, as described above, when parasitic capacitance is added to the capacitors C1 and C3 in the stages 11 to 15, it appears as an output error of the stage. On the other hand, in the input sampling circuit 10, even if parasitic capacitance is added to the capacitors C5 and C6, the output error of the input sampling circuit 10 does not occur and the conversion accuracy of the pipeline A / D converter is not affected. For this reason, by providing the signal replacement circuit PX in the input sampling circuit 10, it is possible to suppress a decrease in conversion accuracy due to parasitic capacitance, compared to the case where the signal replacement circuit PX is provided in the stages 11 to 15.

In the input sampling circuit 10, the switching element S71 is turned on during the hold period to short-circuit the second electrodes of the capacitors C5 and C6. Therefore, if the same capacity capacitor C5, C6 is, be interchanged these capacitors C5, C6 analog input signal is input to the A ₀ and the reference voltage V _R, there is no effect on the charge and discharge time.

Embodiment 7 FIG.
In the sixth embodiment, an example of a pipeline A / D converter in which A / D conversion is performed in consideration of signal replacement by the input sampling circuit 10 in each stage 11 to 15 has been described. In contrast, in the present embodiment, after adding the digital signal D _i determined at each stage 11 to 15, it will be described pipelined A / D converter to perform correction processing in consideration of replacement the signal.

  FIG. 14 is a block diagram showing a configuration example of a pipeline A / D converter according to the seventh embodiment of the present invention. The input sampling circuit 10 includes the circuit shown in FIG. 13 in which level inversion detection and signal replacement are performed. Each stage 11-15 consists of the same circuit as the stage which comprises the conventional pipeline A / D converter.

The correction circuit 18 is an arithmetic circuit that corrects the digital signal D _out of the addition circuit 17 based on the comparison signal CP ₀ and generates a correct digital signal D _out ′ taking into account signal replacement in the input sampling circuit 10.

The comparison signal CP ₀ and the digital signals D _{1 to} D ₅ are sequentially generated as signals having a time delay of a half clock. The digital signals D _{1 to} D ₅ are synchronized by the delay circuit 16 and then added by the adding circuit 17 to generate a digital signal D _out . Further, the delay circuit 16 synchronizes the comparison signal CP ₀ with the digital signal D _out and inputs these signals to the correction circuit 18. In the correction circuit 18, for each bit of the output signal D _out, compared exclusive OR of the signal CP ₀ is determined, the correct digital signal considering signal replacement D _{out 'is} generated.

  Each of the pipeline A / D converters described above can be realized as one integrated circuit, and the analog circuit and the digital circuit are arranged separately on the silicon substrate. That is, the input sampling circuit 10 and the stages 11 to 15 that are analog circuits are laid out in the analog area, and the delay circuit 16 and the adder circuit 17 that are digital circuits are laid out in the digital area.

Pipelined A / D converter of FIG. 10 in Embodiment 5, while delaying the comparison signal CP ₀ by the delay circuit 16, and is propagated between the input sampling circuit 10 and each stage 11-15. That is, the comparison signal CP _0, since propagating between analog circuits via a digital circuit, it is necessary to analog domain and the digital domain route reciprocating, a problem that the wiring length becomes longer is generated. In contrast, in the pipelined A / D converter 14, so as not to propagate a comparison signal CP ₀ to each stage 11 to 15, it is possible to shorten the wiring length, is possible to improve the integration degree of the integrated circuit it can.

Embodiment 8 FIG.
In the seventh embodiment, in the pipelined A / D converter signal replacement is performed in the input sampling circuit 10, it has been described an example in the case of performing the correction processing in consideration of replacement the signal after the addition of the digital signal D _i . On the other hand, in the present embodiment, a case where the same correction processing is performed in a pipeline A / D converter in which signal replacement is performed in the first stage 11 will be described.

FIG. 15 is a block diagram showing a configuration example of a pipeline A / D converter according to the eighth embodiment of the present invention. If this pipeline A / D converter is compared with the case of FIG. 14 (Embodiment 7), the input sampling circuit 10 is not provided, and the comparison signal CP ₁ from the first stage 11 is supplied to the correction circuit 18. It is different in that is entered.

The comparison signal CP ₁ is delayed by the delay circuit 16 and input to the correction circuit 18 in synchronization with the digital signal D _out from the addition circuit 17. In the correction circuit 18, based on the comparison signal CP _1, correction processing of the digital signal _{D out} it is performed. That is, for each bit of the digital signal D _out, obtains an exclusive OR of the comparison signal CP _1, the signal replacement is correct digital signal D _{out 'in} consideration of the generated.

In this case, the digital signal D _i to be inputted to the adder 17 must be both signals requiring a correction process (signal uncorrected). That is, the comparison signal CP ₁ is high level, when the signal replacement is performed in the first stage 11, all of the digital signal D _i to be added by the adding circuit 17, an analog signal after replacement signal The signal must be A / D converted.

As a stage 12-15, by employing conventional circuit (FIG. 18), from each stage 12-15 is output digital signal _D 2 to D ₅ uncorrected. However, as the first stage 11, by adopting a circuit (Embodiment 3) of FIG. 7, so that the correct digital signal D ₁ does not require correction processing from the first stage 11 is output. Therefore, the first stage 11 of Figure 15 converts this correct digital signal to a digital signal uncorrected, is configured to output as a digital signal D _1.

  FIG. 16 is a diagram showing a configuration example of the first stage 11 of FIG. If this first stage is compared with the case of FIG. 7 (Embodiment 3), instead of the sub A / D converter 20 and the sub D / A converter 21N, the sub A / D converter 20N and the sub D / D The difference is that an A converter 21 is provided.

Sub A / D converter 20N, based on the comparison signal CP ₁ generated by the comparator 31 in the same stage, which converts the analog differential signals A ₁ to a digital signal D _1. Analog signal _{A 1} input to the sub A / D converter 20N is an input signal of the signal replacement circuit PX, the sub A / D converter 20N as a digital signal _{D 1,} the output of the signal replacement circuit PX A signal obtained by digitally converting the signal is generated. That is, the sub A / D converter 20N, first, an analog differential signal A ₁ to digital conversion, to produce the correct digital signals. Then, based on the comparison signal CP _1, the digital signal is inversely corrected, and generates a digital signal D ₁ of the uncorrected.

The digital signal D ₁ generated by the sub A / D converter 20N are the signals in consideration of replacement signal by the signal replacement circuit PX, the sub D / A converter 21, the conventional D / A sub The same circuit as the converter can be used.

According to this embodiment, even pipelined A / D converter does not have an input sampling circuit 10, without propagating the comparison signal CP ₁ between the respective stages 11 to 15, a replacement signal of the analog signal It can be carried out. For this reason, as in the case of the seventh embodiment, the number of wirings that reciprocate between the analog region and the digital region can be reduced, the wiring length can be shortened, and the degree of integration of the integrated circuit can be improved.

It is the figure which showed one structural example of the switched capacitor circuit by Embodiment 1 of this invention. 2 is a timing chart showing an example of the operation of the switched capacitor circuit of FIG. 1. It is the figure which showed one structural example of the switched capacitor circuit by Embodiment 2 of this invention. 4 is a timing chart showing an example of the operation of the switched capacitor circuit of FIG. 3. It is the block diagram which showed one structural example of the pipeline A / D converter by Embodiment 3 of this invention. FIG. 6 is a block diagram illustrating a configuration example of an i-th stage (i = 2 to 4) in FIG. 5. FIG. 6 is a block diagram illustrating a configuration example of a first stage in FIG. 5. It is the block diagram which showed one structural example of the pipeline A / D converter by Embodiment 4 of this invention. FIG. 9 is a block diagram illustrating a configuration example of an i-th stage (i = 2 to 4) in FIG. 8. It is the block diagram which showed one structural example of the pipeline A / D converter by Embodiment 5 of this invention. It is the figure which showed the example of 1 structure of the 1st stage 11 of FIG. It is the figure which showed one structural example of the input sampling circuit 10 of FIG. It is the figure which showed one structural example of the input sampling circuit 10 by Embodiment 6 of this invention. It is the block diagram which showed one structural example of the pipeline A / D converter by Embodiment 7 of this invention. It is the block diagram which showed one structural example of the pipeline A / D converter by Embodiment 8 of this invention. FIG. 16 is a diagram illustrating a configuration example of a first stage 11 in FIG. 15. It is the block diagram which showed the example of schematic structure of the conventional pipeline A / D converter. FIG. 18 is a block diagram illustrating a configuration example of an i-th stage (i = 2 to 4) in FIG. 17. FIG. 19 is a circuit diagram illustrating a configuration example of the switched capacitor circuit 25 in FIG. 18.

Explanation of symbols

A ₀ analog input signal _A 1 _~A 5, _{A i} analog differential signals C1~C8 capacitor S11~S82 switching element 10 input sampling circuit 11 to 15 stage 16 delay circuit 17 addition circuit 18 correction circuit 20,20N sub A / D Converters 21, 21N Sub-D / A converters 25, 25N Switched capacitor circuits 30, 32 Differential amplifier 30a First input terminal 30b Second input terminal 30c First output terminal 30d Second output terminals 31, 33 Comparator CP ₀ to CP ₄ and CP _i comparison signals D _{1 to} D ₅ , D _i and D _d digital signals (low resolution)
D _out , D _out 'Digital signal (high resolution)
PX signal replacement circuit

Claims (10)

A differential amplifier having a first input terminal and a second input terminal;
A first capacitor having a first electrode connected to a first input terminal of the differential amplifier;
A second capacitor having a first electrode connected to a second input terminal of the differential amplifier;
An inversion detection circuit for detecting level inversion of the analog differential signal;
One signal constituting the analog differential signal is supplied to the second electrode of the first capacitor, and the other signal is supplied to the second electrode of the second capacitor, based on the output of the inversion detection circuit. A switched capacitor circuit, comprising: a first signal switching circuit for switching the one and the other signals. The first signal replacement circuit includes:
A first switching element for supplying a non-inverted signal of the analog differential signal to the second electrode of the first capacitor;
A second switching element for supplying an inverted signal of the analog differential signal to the second electrode of the first capacitor;
A third switching element for supplying the non-inverted signal to the second electrode of the second capacitor;
The switched capacitor circuit according to claim 1, further comprising: a fourth switching element that supplies the inverted signal to the second electrode of the second capacitor. The first signal replacement circuit includes:
A fifth switching element connecting the first and second switching elements to the second electrode of the first capacitor;
The switched capacitor circuit according to claim 2, further comprising a sixth switching element that connects the third and fourth switching elements to a second electrode of the second capacitor.   2. The switched capacitor circuit according to claim 1, wherein the inversion detection circuit comprises a comparator that compares a non-inversion signal and an inversion signal constituting the analog differential signal. A third capacitor having a first electrode connected to a first input terminal of the differential amplifier;
A fourth capacitor having a first electrode connected to a second input terminal of the differential amplifier;
A seventh switching element that connects the second electrode of the third capacitor to the first output terminal of the differential amplifier and forms a feedback circuit;
An eighth switching element that connects the second electrode of the fourth capacitor to the second output terminal of the differential amplifier and forms a feedback circuit;
One signal constituting the analog differential signal is supplied to the second electrode of the third capacitor, and the other signal is supplied to the second electrode of the fourth capacitor, based on the output of the inversion detection circuit. The switched capacitor circuit according to claim 1, further comprising a second signal replacement circuit that replaces the one and the other signals. Multiple conversion stages with switched capacitor circuits that sample and hold analog differential signals are connected in series, and high-resolution digital signals are generated based on low-resolution digital signals obtained by digital conversion at each conversion stage. In a pipeline A / D converter
an inversion detection circuit for detecting level inversion of the analog differential signal input to the switched capacitor circuit of the nth conversion stage;
A pipeline comprising: a signal replacement circuit for replacing one and the other of the analog differential signals input to the switched capacitor circuit of the nth conversion stage based on the output of the inversion detection circuit A / D converter.   The (n + 1) th conversion stage includes a sub A / D converter that converts an analog differential signal input from the nth conversion stage into a digital signal based on the output of the inversion detection circuit. The pipeline A / D converter according to claim 6. The inversion detection circuit detects the level inversion of the analog differential signal input to the first conversion stage,
7. The signal replacement circuit according to claim 6, wherein the signal replacement circuit performs signal replacement of an analog differential signal input to a switched capacitor circuit of a first conversion stage based on an output of the inversion detection circuit. Pipeline A / D converter. A switched capacitor circuit that performs sampling and holding, and an input sampling circuit that supplies an analog differential signal being held to the first conversion stage,
9. The inversion detection circuit detects level inversion of an analog differential signal input to a first conversion stage based on an input signal to a switched capacitor circuit of the input sampling circuit. A pipeline A / D converter described in 1. The signal replacement circuit switches an input signal to the switched capacitor circuit of the input sampling circuit;
10. The pipeline A / D converter according to claim 9, wherein an analog differential signal after signal replacement is supplied from an input sampling circuit to a first conversion stage.

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