JPH05175787A - Switched capacitor integrator stabilizing chopper at sampling rate - Google Patents

Abstract

PURPOSE: To remove a flicker noise or a low frequency fault at the amplifier of switched capacitor integrator without using any continuous-time integrator before a discrete time integrator. CONSTITUTION: A switched capacitor integrator 10 is formed by providing an output 26 for receiving sampling and a chopper stabilization amplifier 12 to be intermitted at a frequency higher than or practically equal with its output sampling frequency. This integrator is functioned as a double sample integrator by sampling an input (VIN) in the respective chopping phases of amplifier 12 and transferring that sampled input to a feedback capacitor 14. The output of integrator is sampled at the end of respective cycles of chopping signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to analog-to-digital converters, and more particularly to discrete-time analog-to-digital converters using chopper-stabilized amplifiers.

[0002]

Discrete time filters using switched capacitor integrators are used in a variety of applications. One of such applications is an analog loop filter used in a modulator of a delta-sigma type analog-digital converter. However, the amplifier used in the integrator produces flicker (1 / f) noise and low frequency disturbances that degrade the converter's performance in the first stage of the loop filter of the delta-sigma converter. One of the methods used in the past for attenuating flicker noise and low frequency disturbances of switched capacitor filters is to stabilize the integrator amplifier with a chopper. This method uses a circuit that modulates flicker noise and low frequency disturbances by a chopper stabilization method and removes them from the bandwidth in question.

In other similar discrete-time circuits, the chopping or modulation frequency is typically limited to a value below the circuit's Nyquist rate, which is half the sampling frequency. In such a circuit, it is not efficient to chop at a frequency higher than this frequency, because the noise, once sampled, will fold into the Nyquist band due to aliasing. However, delta-
In sigma converters, tones can occur when chopper-stabilizing a discrete-time converter at half or less of the sampling frequency.

However, there are various applications in which all discrete-time loop filters have certain advantages over continuous-time filters or a combination of continuous-time and discrete-time loop filters. Therefore, it can be seen that a switched capacitor integrator that performs chopper stabilization at the sampling rate is desirable.

[0005]

In accordance with one aspect of the present invention, there is an output that is sampled and a chopper stabilizing amplifier at a frequency above or substantially equal to the sampling frequency of the output. Flicker noise and internal low frequency disturbances are attenuated by the switched capacitor integrator that is interrupted.

According to yet another feature of the invention, the integrator has a first working phase and a second working phase and comprises an input capacitor and a feedback capacitor.
In this first phase, the amplifier is in the first chopping state. This first phase is further divided into first and second partial phases. In the first partial phase, the input capacitor is charged by the input signal and the feedback capacitor is isolated from the input capacitor. And in the second partial phase,
Since the input capacitor is isolated from the input signal but coupled to the feedback capacitor, the input voltage sampled during the first partial phase is transferred to the feedback capacitor during the second partial phase. In the second phase of the integrator,
The amplifier is in the second chopping state and the first and second sub-phases of the first phase are repeated. At the end of the second phase, the output of the integrator is sampled.

In accordance with the method of the present invention, an input signal is sampled and the sampled signal is fed to a feedback capacitor coupled between the output of the operational amplifier and its first input by the operational amplifier. Transferred when in the chopping state. The input signal is sampled again and the sampled signal is transferred to the feedback capacitor when the amplifier is in the second chopping state. The operational amplifier cycles between the first and second chopping states, but its output is periodically sampled to obtain the filtered output signal. This output is periodically sampled at a frequency substantially equal to FCHOP / N (N is a positive integer, FCHOP is the repetition rate of the first and second chopping states).

[0008]

[Example] If it seems appropriate to clarify the explanation,
The same reference numbers are used throughout the figures to indicate corresponding parts. In addition, the timing signals shown in the attached drawings are
It should be understood that the timing of the preferred embodiment of the present invention is not necessarily to scale to more clearly indicate the timing.

In a preferred embodiment of the present invention, a switched capacitor integrator that provides chopper stabilization at a sampling rate includes a chopper differential amplifier having first and second feedback capacitors, and first and second input capacitors. , + And-differential input signals (VINP and VINM) to provide positive and negative filtered output signals, and four switches around each input capacitor.

The + and-input signals are coupled to each input capacitor via separate switches. Two switches are located on opposite sides of each of the first and second input capacitors, one connected to ground, the other to the first and second inputs of the amplifier, respectively, and
And one terminal of the second feedback capacitor. The other terminals of the first and second feedback capacitors are respectively connected to the first and second terminals of the amplifier.
Connected to the output of. The output of the amplifier is sampled to form the positive and negative outputs of the integrator.

In operation, the amplifier is discontinuous in response to the square wave signal FCHOP at a frequency equal to the sampling signal FSAMPLE. Therefore, this FCHOP signal has first and second phases.

In this first phase, the amplifier is in a first chopping state, in which state its first input is a positive input, its second input is a negative input, and its first output is a negative output. , The second output is a positive output. In this first phase, the switch around the input capacitor is opened and closed twice to form two partial phases. In the first partial phase,
The switch charges the first input capacitor to VINP while the first feedback capacitor is isolated from the first input capacitor, and the second feedback capacitor is connected to the second input capacitor while isolated from the second input capacitor. The second input capacitor is set to the position to charge to VINM. In the second partial phase, the switch is set to a position that transfers charge on VINM from the first input capacitor to the first feedback capacitor and charge on VINP from the second input capacitor to the second feedback capacitor. ing.

Thus, in this first partial phase, the input capacitor is charged to the input signal and the feedback capacitor is isolated from the input capacitor. In the second partial phase, the input capacitors transfer their charge for the opposite input signal to the feedback capacitors. Also, in this first phase, noise from the amplifier is sampled and stored in the first and second feedback capacitors along with the input signal.

In the second phase of the FCHOP signal, the amplifier is in the second chopping state, in which the input and output polarities of the amplifier are such that the first input is the negative input and the second input is positive. The inputs and outputs are opened and closed so that the first output is a positive output and the second output is a negative output. First of the second phase
And a second partial phase (referred to herein as the third and fourth partial phases), with respect to the switch of the input capacitor, the FCH
It is the same as the first and second partial phases of the first phase of the OP signal.

In the second phase of FCHOP, the input signal is again applied to the feedback capacitor, but this first
The noise of the low frequency amplifier accumulated during the second phase is subtracted from the noise accumulated during the second phase. Thus, flicker noise and low frequency interference are subtracted by this double sample integrator, in contrast to other prior art circuits that modulate low frequency interference and flicker noise to remove it from the band of interest. The output of the amplifier is FC
It is sampled when the second phase of the HOP signal is complete.

Although the output sampling frequency and the chopping frequency are equal to each other in the preferred embodiment, flicker noise and low frequency impairments are attenuated even when the chopping frequency is substantially equal to N times the output sampling frequency (N is a positive integer). .. For example, if N equals 2, then FCHOP is twice FSAMPLE and the frequency of each input sample (ie, the frequency of each of the four subphases) is four times FSAMPLE.

Referring to the accompanying drawings, FIG. 1A is a schematic diagram of a single-ended switched capacitor integrator according to the present invention. As shown in FIG. 1A, the switched-capacitor integrator 10 comprises a chopper-stabilized differential operational amplifier 12 and a feedback capacitor 14 coupled between its output 16 and a first input 18. The two inputs 20 are coupled to signal ground. The amplifier has a signal input FCHOP and its complement logic signal, the inverted FCHOP on lines 22 and 23, respectively, which are generated by circuitry not shown.

The output of amplifier 12 on line 16 is sampled by the signal FSAMPLE represented by switch 24 to provide output signal VOUT on terminal 26. Switched capacitor integrator 10 receives input signal VIN at input terminal 28 which is coupled to node 32 via first switch 30. Node 32 is switch 3
4 to the signal ground. Node 32
Is connected to one terminal of the input capacitor 36 and the other terminal is connected to another node 38. Node 3
8 is coupled to signal ground via switch 40. This node 38 is coupled to the input 18 of the amplifier 12 via another switch 42. Switches 30 and 4
0 is controlled by the timing signal ΦA, and the switches 34 and 42 are controlled by the timing signal ΦB signal.

FIG. 1B is a schematic diagram of the chopper amplifier 12 of FIG. As shown in FIG. 1B, the input 18 is FC
It is coupled to the negative input of operational amplifier 42 via switch 43 controlled by HOP and to the positive input of operational amplifier 42 via switch 43 'controlled by inverting FCHOP. Input 20 is coupled to the negative input of operational amplifier 42 via switch 44 'controlled by inverting FCHOP and to the positive input of operational amplifier 42 via switch 44 controlled by FCHOP. The output of the operational amplifier 42 is the non-inverting amplifier 45 and the FCHO.
It is coupled to the output 16 of the chopper amplifier 12 via a switch 47 controlled by P and via a switch 47 'controlled by an inverting amplifier 46 and an inverting FCHOP.

In operation, the chopper amplifier 12 has the first and second chopping states. In the first chopping state, when FCHOP is at a high level and inverted FCHOP is at a low level, the switches 43, 44 and 47 are in the closed state, but the switch 4
3 ', 44' and 47 'are open. In this first chopping state, input 18 is coupled to the negative input of operational amplifier 42, input 20 is coupled to the positive input of operational amplifier 42, and the output of operational amplifier 42 is coupled to output 16. In the second chopping state, FCHOP is low level, inverted F
When CHOP is high, the switches 43,44,
47 is open, and switches 43 ', 44
'And 47' are closed. In this second chopping state, input 18 is coupled to the positive input of operational amplifier 42, input 20 to the negative input of operational amplifier 42, and the output of operational amplifier 42 is inverted and coupled to output 16.

FIG. 1C is a timing diagram of the circuit shown in FIG. 1A. As shown in FIG. 1C, for each sample of the output shown as FSAMPLE, there are two phases of the FCHOP and inverted FCHOP signals and four subphases of the ΦA and ΦB signals. 2A is a schematic diagram of FIG. 1A during partial phase 1, FIG. 2B is a schematic diagram of FIG. 1A during partial phase 2, FIG. 2C is a schematic diagram during partial phase 3, and FIG. 2B is a partial phase 4. It is a schematic diagram in between.

The operation of the amplifier shown in FIG. 1A will be described with reference to FIGS. 1B and 2A, 2B, 2C, and 2D. Figure 2
During partial phase 1 shown in A, amplifier 12 has a negative input at input 18, a positive input at input 20, and an output 16
Has a positive output at, switches 30 and 40 are closed and switches 34 and 42 are open. In this first subphase, the input signal VIN is sampled on the input capacitor 36, while the feedback capacitor 14 stores the voltage from the subphase 4 of the previous cycle. During the partial phase 2 (shown in FIG. 2B), the input terminals 18, 20 and the output terminal 16 of the amplifier 12 are unchanged in polarity, the switches 34, 42 are closed and the switches 30, 40 are closed.
Is open. During this sub-phase, the sampled input on capacitor 36 is sent to feedback capacitor 14. Also, during this partial phase, Vn in FIG.
The amplifier noise represented by is sampled and subtracted from the feedback capacitor 14.

During partial phase 3 shown in FIG. 2C, input 18 of amplifier 12 is a positive input, input 20 is a negative input and output 16 is a negative output. This is because the signals FCHOP and inverted FCHOP change polarity. Also, at this time, the switches 30, 34, 38, 40 are in the same positions as during the partial phase 1. Thus, during the third partial phase, the input signal VIN is sampled on the input capacitor 36, while the voltage on the feedback capacitor 14 remains unchanged.

During partial phase 4 (shown in FIG. 2D), amplifier 1
The inputs 18, 20 and the output 16 of 2 are unchanged from the third partial phase, the switches 30, 34, 40, 42 being the partial phase 2
It has been switched to the same position as it was in. This 4th
During the sub-phase of, the input sampled on the input capacitor 36 is applied (transferred) to the feedback capacitor 14. The inverted signal of the noise of the amplifier 12 is sampled and subtracted from the feedback capacitor 14. In this way, low frequency disturbances and flicker noise of amplifier 12 are removed from the output signal at output terminal 26.

In the preferred embodiment, the output of switched capacitor integrator 10 is sampled during the first partial phase by closing switch 24. However, as shown below, the output of the integrator 10 is the same during the fourth partial phase and the first partial phase of the next cycle, so sampling may occur during the fourth partial phase. ..

The switched capacitor integrator of FIG. 1A is a double sample integrator because each phase of the chopping clock has two sub-phases (FCHOP and inverted FCHOP). Since the chopping clock FCHOP and the inverted FCHOP have the same frequency as the sampling signal FSAMPLE, the input signal VIN is the output sample FS.
It is sampled at twice the frequency of AMPLE.

FIG. 3A is a plot of the input reference transfer function of the amplifier shown in FIG. 1A and FIG. 3B is a plot of the noise input reference transfer function of the amplifier of FIG. 1A. These two curves sum the voltage applied to the feedback capacitor 14 for each of the four sub-phases and add it to the voltage present in the fourth sub-phase of the previous cycle and the resulting output voltage Can be obtained by taking the Z transformation of Thus, the terminal voltage of sample n is equal to the terminal voltage of sample n-1, the voltage of the terminal end of the first partial phase (n-3 / 4), and the voltage of the terminal end of the second partial phase (n-1 / 2) voltage and the end of the third partial phase (n-1
/ 4) plus the final (n) cumulative voltage of the fourth partial phase. In partial phase 1,

[0028]

[Equation 1] In partial phase 2,

[0029]

[Equation 2] In partial phase 3,

[0030]

[Equation 3] In partial phase 4,

[0031]

[Equation 4] In the above equation, Vn is the sampled amplifier noise.

When the Z conversion of the equation (4) is taken, the following equation is obtained.

[0033]

[Equation 5] Therefore, the input transfer function is:

[0034]

[Equation 6] The transfer function of noise is as follows.

[0035]

[Equation 7]

Of the input and noise transfer functions

[Equation 8] The term is a well known discrete-time integrator. The numerator of these transfer functions determines their input reference response. Their steady-state responses are shown in Figures 3A and 3B, respectively. Note that the noise transfer function is zero at DC.

FIG. 4A is a fully differential schematic diagram of the switched capacitor integrator shown in FIG. 1A. This fully differential type, which uses a fully differential chopper amplifier 48, is the preferred embodiment of the present invention. The circuit shown in FIG. 4A is shown in FIG.
It operates on the same principle as described with respect to the circuit shown in FIG. 4, and the timing of the switches in FIG. 4A is the same as the timing shown in FIG. 1C. More specifically, in the partial phase 1,

[0038]

[Equation 9] In partial phase 2,

[0039]

[Equation 10] In partial phase 3,

[0040]

[Equation 11] In partial phase 4,

[0041]

[Equation 12] The Z transformation of equation (12) is as follows.

[0042]

[Equation 13] Thus, the input transfer function is

[0043]

[Equation 14] The noise transfer function is the same as equation (7). FIG. 5 shows FIG.
3 is a plot of the input reference input transfer function of the circuit shown in A. The curve shown in FIG. 3B also applies to the circuit shown in FIG. 4A.

FIG. 4B is a schematic diagram of the chopper amplifier 48 shown in FIG. 4A. As shown in FIG. 4B, operational amplifier 49 has negative and positive inputs, which are opened and closed in the same manner as the chopper amplifier shown in FIG. 1B. Amplifier 4
The positive and negative outputs of 9 are opened and closed by switches 50, 51 controlled by the FCHOP signal and by switches 50 ', 51' controlled by the inverted FCHOP signal.

FIG. 4C is another embodiment of the fully differential switched capacitor integrator according to the present invention. In the embodiment of FIG. 4C, the first terminals of the input capacitors CI are not respectively between the one input signal and the other input signal as shown in FIG. 4A, but rather the input signal (VINP or VI).
NM) and signal ground alternately.

FIG. 6 is a block diagram of a delta-sigma converter 52 having a switched capacitor integrator according to the present invention. As shown in FIG. 6, the input signal VIN is connected to the positive input of the adder circuit 53. The output of the adder circuit is connected to the input of the switched capacitor integrator 10. The output of switched capacitor integrator 10 is connected to the input of block 54 of a conventional switched capacitor integrator to form the remainder of the analog loop filter. Block 54 of conventional switched capacitor integrator
Is connected to the input of quantizer 55, the output of which provides the digital output signal DOUT. This DOUT signal is connected to the input of the digital-analog converter 56,
The output of this converter is connected to the negative input of summing circuit 50.

To explain the operation, the input signal VIN
Is added to the analog signal from the digital-to-analog converter 56 of the adder circuit 53, and this sum is coupled to the input of the switched capacitor integrator 10. Since the integrator in the latter stage does not contribute to the generation of significant low frequency noise, only the integrator 10 in the first stage is a double sample type. As mentioned above, this switched capacitor integrator 10 is used in amplifier 1
2 effectively attenuates the low frequency noise impairments, and because the double sample integrator 10 is interrupted at the modulator sampling rate, the tone mechanism that occurs when the integrator is interrupted at half the sampling rate frequency is introduced. Absent.

The output of switched capacitor integrator 10 is filtered by conventional switched capacitor integrator block 54, and the output of switched capacitor integrator block 54 is quantized by quantizer 55 to provide output signal DOUT. The output of the quantizer 55 is converted into an analog signal in the digital-analog converter 56. The output signal DOUT is typically coupled to the input of a digital decimation filter which converts the oversampled serial bit stream of DOUT into a regular digital signal and also filters DOUT.

FIG. 7 is a block diagram of an instrumentation amplifier using the present invention. As shown in FIG. 7, two differential input signals AINP and AINM are respectively connected to the positive inputs of two chopper stabilized differential amplifiers 60 and 62.
The inverting inputs of the amplifiers 60 and 62 are connected together by a resistor 64, and the output of the amplifier 60 is a feedback resistor 6
It is connected to the inverting input via 6. Operational amplifier 62
Is connected to its inverting input via feedback resistor 68. The output of amplifier 60 is connected to the AIN + input of differential double sample delta-sigma converter 70.

The amplifier 62 is a delta-sigma converter 7
0 connected to the AIN- input. Amplifier 60, 62
Are interrupted at the sampling frequency of the delta-sigma converter 70. The chopper stabilizing amplifiers 60 and 62 modulate flicker noise and low frequency interference into odd harmonics of the same chopping frequency as the sampling frequency, and also delta-
The switched-capacitor integrator of the first filter stage of the sigma converter 70 has this modulated noise and since the input reference transfer function of this integrator has a zero at the odd harmonics of the sampling frequency as shown in FIG. 3A. Control obstacles. Amplifiers 60 and 62 also provide high input impedance for input signals AINP and AINM.

Although the first stage of the delta-sigma converter 70 is chopper stabilized in the preferred embodiment of FIG. 7, the present invention is based on the example of FIG. 7 where neither stage of the delta-sigma converter 70 is chopper stabilized. Is also available. That is, the modulated noise is such that the sampling frequency of delta-sigma converter 70 is equal to the chopping frequency of chopper stabilized differential amplifiers 60, 62 (or equal to the chopping frequency divided by a positive integer).
When the input sampling frequency of the delta-sigma converter 70 is twice the chopping frequency of the chopper-stabilized differential amplifiers 60 and 62, the delta-sigma converter 70 suppresses the sampling frequency.

FIG. 8 is a block diagram of the delta-sigma converter 70 shown in FIG. As shown in FIG. 8, the input signal AIN is connected to the positive input of the adder circuit 78. It should be appreciated that the input AIN of FIG. 8 represents the differential input signals AIN + and AIN- of FIG. The output of adder 78 is connected to the input of first integration stage 80, and the output of that integration stage is connected to the positive input of second adder 82. The output of the adder 82 is connected to the input of the second integrator 84, and the output of the integrator is connected to the input of the third integrator 86. The output of integrator 86 is coupled to the input of feedback element 88, labeled B. The output of feedback element 88 is connected to the negative input of adder 82. The output of the integrator 80 is connected to the input of the feedforward element 90 indicated by A1. The output of the integrator 84 is connected to the input of the second feedforward element 92 designated A2.

The output of the integrator 86 is connected to the input of the third feedforward element 94 indicated by A3.
The outputs from the three feedforward elements 90, 91, 92 are added in an adder 96, the output of which is connected to the positive input of a quantizer or comparator 98. The negative input of comparator 98 is shown connected to signal ground in this block diagram of the preferred embodiment. The output of the comparator 98 is the output signal DOUT
give. The output of the comparator 98 is also the adder 78.
Used to control a switch 100 that selects between a positive reference voltage VREF + and a negative reference voltage VREF-, which are connected to the negative input of the.

The delta-sigma modulator 70 shown in FIG.
It is a third-order modulator that operates according to principles well known in the delta-sigma modulator art.

9 and 10 show the delta-value shown in FIG.
6 is a schematic diagram of a sigma modulator 70. FIG. As shown in FIG.
The input signals AIN + and AIN- are cross-coupled in front of the first capacitor element in the manner shown in FIG. 4A.
These are cross-coupled by the switches shown in block 102. The operational amplifiers 104 and 10 of FIGS.
Reference numerals 6 and 108 form the active elements of the integrators 80, 84 and 86 shown in FIG. The feedback element 88 of FIG. 8 is a differential feedback element shown as elements 88 'and 88 "in FIG. 10. Similarly, the feedforward elements 90, 92, 94 are elements 90', 90", respectively in FIG. 92 ', 92 ", 94',
It is shown as 94 ".

FIG. 11 is a timing diagram of the switches shown in FIGS. 9 and 10. Arrows indicate signals S1-S4, SA
-Shows a switching sequence at the SD phase boundary. The signal FCHOP is a chopping signal used for chopping or chopping the inputs and outputs of the operational amplifier 104 and the instrumentation amplifiers 60 and 62.

It can be seen that integrator 80 is a discrete time integrator whose operational amplifier 104 is interrupted at the sampling frequency. This discrete time circuit can be intermittently operated at the sampling rate by the timing signals S1 to S4 which double-sample the input signal at twice the sampling rate of the modulator. Thus, this circuit has the advantage of eliminating flicker noise and low frequency disturbances in a chopper-stabilized amplifier without introducing tones or requiring a continuous-time integrator before the discrete-time integrator. Have.

FIG. 12 is a circuit diagram of the chopper amplifier 1 shown in FIG.
Figure 4 is a schematic diagram of a preferred embodiment of 04. As shown in FIG. 12, the differential input signals INP and INM are the timing signals C.
It is switched at the input of the amplifier 104 by H3 and CH4. The differential output of amplifier 104 is also switched by timing signals CH1 and CH2. In the amplifier itself, B1-B6 are bias voltages, and B1C
A design well known in the art, where M is a bias voltage driven by a common mode amplifier (not shown) that receives VOUTP and VOUTN as input signals. B1CM is the common mode output of the amplifier VDD
To maintain substantially half the level between V and VSS. FIG. 13 shows the timing relationship of CH1-CH4 related to FCHOP shown in FIG.

[Brief description of drawings]

FIG. 1A is a schematic diagram of a switched capacitor integrator according to the present invention. FIG. 1B is a schematic diagram of the chopper amplifier shown in FIG. 1A. FIG. 1C is a timing diagram of the switched capacitor integrator shown in FIG. 1A.

2A, 2B, 2C, 2D are schematic diagrams of the switched capacitor integrator of FIG. 1A in each of four sub-phases of cycle integrator operation over one sampling period.

3A is a plot of the input transfer function of the switched capacitor integrator of FIG. 1A. Figure 3B
2 is a plot of the noise transfer function of the switched capacitor integrator of FIG. 1A.

FIG. 4A is a schematic diagram of a fully differential switched capacitor integrator according to the present invention. FIG. 4B is a schematic diagram of the chopper amplifier shown in FIG. 4A. FIG. 4C is a schematic diagram of another embodiment of a fully differential switched capacitor integrator according to the present invention.

FIG. 5 is a plot of the input transfer function of the switched capacitor integrator shown in FIG. 4A.

FIG. 6 is a block diagram of a delta-sigma converter including a switched capacitor integrator according to the present invention.

FIG. 7 is a block diagram of an embodiment of the present invention with a delta-sigma converter having a switched capacitor integrator according to the present invention.

FIG. 8 is a block diagram of the delta-sigma converter shown in FIG. 7.

FIG. 9 is a schematic diagram of the delta-sigma converter shown in FIG.

FIG. 10 is a schematic diagram of the delta-sigma converter shown in FIG.

FIG. 11 is a timing diagram of the switches shown in FIGS. 9 and 10.

FIG. 12 is a schematic diagram of the chopper amplifier shown in FIG. 9.

FIG. 13 is a timing diagram of the chopper amplifier shown in FIG. 12.

[Explanation of symbols]

 10 Switched Capacitor Integrator 12 Chopper Stabilized Differential Operational Amplifier 14 Feedback Capacitor 36 Input Capacitor 42,43 Operational Amplifier 45 Non-Inverted Amplifier 46 Inverted Amplifier 48 Fully Differential Chopper Stabilized Amplifier 49 Operational Amplifier 53 Summing Circuit 55 Quantizer 56 Digital-Analog Converter 60,62 Chopper Stabilized Differential Amplifier 70 Delta-Sigma Converter

Claims (18)

[Claims] 1. A switched capacitor circuit having an output to be sampled and a chopper stabilizing amplifier, said amplifier being discontinuous at a frequency greater than or substantially equal to the sampling frequency of the output. 2. The switched capacitor circuit according to claim 1, wherein the switched capacitor circuit is an integrator circuit. 3. The switched capacitor circuit of claim 2, wherein the integrator is a double sample integrator. 4. The switched capacitor circuit according to claim 1, wherein the switched capacitor circuit is a fully differential type. 5. A switched capacitor circuit which receives an input signal at an input terminal and provides an output signal, comprising: (a) first and second inputs and outputs, and first and second chopping states. An amplifier with a chopper configured as described above, (b) a feedback capacitor coupled between the output of the amplifier and the first input of the amplifier, and (c) the first terminal being the input terminal and the signal ground. An input capacitor selectively coupled to the first input of the amplifier and a second terminal of which is selectively coupled to signal ground; (d) the capacitors alternating; (i) the input. Charged to the signal at the terminal and (ii) transferred to the feedback capacitor during each chopping state of the amplifier by being coupled to the first input of the amplifier, and (e) the output of the amplifier is increased. Switched capacitor circuits or lower than the chopping frequency of the vessel or it and is sampled at a frequency substantially equal, characterized in that providing said output signal. 6. The first and second input terminals each have a first
And (a) a switched capacitor circuit for receiving a first input signal and a second output signal, respectively, and (a) having first and second inputs and first and second outputs, A chopper amplifier configured to have first and second chopping states; (b) a first feedback capacitor coupled between the first output of the amplifier and the first input; and A second coupled between the second output and the second input
(C) a first terminal is selectively coupled to the first input terminal and the second input terminal, and a second terminal is connected to the first input of the amplifier and the signal ground. A first input capacitor selectively coupled to: (d) the first capacitor is alternating; (i) the first input capacitor;
Is charged to the signal at the input terminal of the amplifier and (ii) the first of the amplifiers
Input to the first input capacitor and the second input terminal to transfer its charge to the first feedback capacitor during each chopping state of the amplifier, where (e) the first terminal is connected to the first input terminal. A second input capacitor selectively coupled to the second input terminal, the second terminal selectively coupled to the second input terminal of the amplifier and signal ground. , (F) the second capacitors are alternating, (i) the second capacitors
Is charged with the signal at the input terminal of the amplifier and (ii) the second amplifier
Of the charge to the second feedback capacitor during each chopping state of the amplifier by being coupled to the input of the amplifier and the first input terminal, and (g) the first and second outputs of the amplifier are A switched capacitor circuit which is sampled at a frequency lower than or substantially equal to the chopping frequency of 1 to provide the first and second output signals, respectively. 7. The first and second input terminals each have a first
And a second input signal to receive first and second output signals at the first and second output terminals, respectively, comprising: (a) first and second inputs and first and second A chopper amplifier having a second output and configured to have first and second chopping states; and (b) coupling between the first output and the first input of the amplifier. And a second feedback capacitor coupled between the second output of the amplifier and the second input, and (c) a first terminal to the first input terminal and signal ground. A first input capacitor that is selectively coupled and has a second terminal that is selectively coupled to the first input of the amplifier and signal ground; and (d) the first input capacitor is alternating. , (I) of the first input terminal (Ii) is coupled to the first input of the amplifier to transfer its charge to a first feedback capacitor during each chopping state of the amplifier; Two input terminals and a second input capacitor selectively coupled to the signal ground and a second terminal selectively coupled to the second input of the amplifier and the signal ground; Two input capacitors are alternately charged (i) to the signal at the second input terminal and (ii) coupled to the second input of the amplifier to transfer its charge during each chopping state of the amplifier. A second feedback capacitor, and (g) the first and second outputs of the amplifier are sampled at a frequency below or substantially equal to the chopping frequency of the amplifier to produce the first and second outputs. A switched capacitor circuit characterized by giving a force signal. 8. A series-coupled discrete-time integration stage, wherein at least one integration stage is chopper-stabilized at a frequency above or substantially equal to the sampling frequency of the remaining integration stages. Analog filter. 9. The analog filter of claim 8, wherein the at least one integration stage is the first integration stage of the plurality of series coupled discrete time integration stages. 10. The analog filter of claim 9, wherein the first integration stage is a double sample integrator. 11. A plurality of series-coupled discrete-time integrators of analog-to-digital modulators, wherein at least one of said integrators is chopper-stabilized at a frequency above or substantially equal to the sampling frequency of the remaining integrators. An integrator, comprising an amplifier to be integrated. 12. The integrator according to claim 1, wherein the at least one integrator is a first integrator of the plurality of serially coupled discrete time integrators. 13. An adder circuit coupled to an analog loop filter, the output of which is coupled to a quantizer, the output of which is coupled to a digital-to-analog converter, the output of which is coupled to one input of the adder circuit. A second input of the adder circuit receives an analog input signal, the analog loop filter comprises a plurality of series coupled discrete time integrators, and a first of the integrators is of the remaining integrators. An analog-to-digital modulator characterized in that it is chopper-stabilized at a frequency higher than or substantially equal to the sampling frequency. 14. The analog-to-digital modulator of claim 13, wherein the first integrator is a double sample integrator. 15. An amplifier having an input terminal and an output terminal, comprising: (a) a first chopper stabilizing circuit coupled to the input terminal for generating undesired noise at a chopping frequency; and (b) the first chopper stabilizing circuit. A switched capacitor circuit coupled between the output of the first chopper stabilizing circuit and the output terminal, wherein the input of the switched capacitor circuit is twice the chopping frequency of the first chopper stabilizing circuit. Sampled at a frequency M times the output sampling frequency of the switched capacitor circuit, M being a positive integer greater than or equal to 2, thus effectively attenuating unwanted noise from the first chopper stabilization circuit. An amplifier characterized in that a noise transfer function is obtained. 16. A chopper stabilizing amplifier in which the switched capacitor circuit is discontinuous at a frequency substantially equal to the first chopper stabilizing circuit and at a frequency substantially equal to an output sampling frequency of the switched capacitor circuit. The amplifier of claim 15 including: 17. A method of filtering an input signal, comprising: (a) sampling the input signal and storing the sampled signal in an input capacitor; and (b) outputting the sampled signal to an output of a chopper amplifier. To a feedback capacitor coupled between the input and the first input when the amplifier is in the first chopping state, (c) repeating step (a), and (d) sampling the signal to the chopper. A forwarded amplifier to the feedback capacitor coupled between the output and the first input when the amplifier is in the second chopping state, and (e) sampling the output of the amplifier and filtering it. Providing an output signal, wherein the output is a repetition rate and an actual value of the first and second chopping states. A method characterized by being sampled at qualitatively equal frequencies. 18. A method for filtering an input signal, comprising: (a) sampling the input signal and storing the sampled signal in an input capacitor; and (b) outputting the sampled signal to an output of a chopper amplifier. To a feedback capacitor coupled between the input and the first input when the amplifier is in the first chopping state, (c) repeating step (a), and (d) the sampled signal. To the feedback capacitor coupled between the output of the differential amplifier and the first input when the amplifier is in the second chopping state, and (e) steps (a) to (d) are sequentially And (f) periodically sampling the output of the amplifier to provide a filtered output signal, Force is sampled at fchop / N substantially equal frequency, N is a positive integer, wherein the fchop is a repeat rate of the first and second chopping state.