JP3530349B2 - Subtraction amplification circuit and analog-digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is, subtracting amplifier circuit Oyo
Beauty analog with the same - to digital converter.

[0002]

2. Description of the Related Art In recent years, with the progress of digital processing technology for video signals, the demand for analog-to-digital conversion circuits (A / D converters) for processing video signals has been increasing. Conventionally, a two-step flash (two-step parallel) system has been widely used because an analog-to-digital converter for video signal processing requires a high-speed conversion operation.

However, with the increase in the number of conversion bits, sufficient conversion accuracy cannot be obtained with the two-step flash method. Therefore, an analog-to-digital conversion circuit having a multi-stage pipeline (step flash) configuration has been developed.

In the analog-digital conversion circuit having the multi-stage pipeline configuration, each stage includes an A / D converter (digital-analog converter), a D / A converter (digital-analog converter), and a difference amplifier.

In each stage, an A / D converter and D
The number of bits (bit configuration) n of the / A converter is set to be the same. The A / D converter in each stage has a sub-A converter for distinguishing from the entire analog-digital conversion circuit.
It is called a / D converter. For the sub A / D converter, an all-parallel comparison (flash) method capable of high-speed conversion operation is used.

In this analog-to-digital conversion circuit, first, A / D conversion is performed on an analog input signal using a first-stage sub A / D converter. Next, the first stage A
The A / D conversion result of the / D converter is input to the first stage D / A converter to perform D / A conversion. Subsequently, the D / A conversion result of the first stage D / A converter and the analog input signal are input to the first stage differential amplifier, and the difference therebetween is amplified.

With respect to the output of the first-stage differential amplifier,
A / D conversion is performed using the second-stage sub A / D converter. Next, the A / D conversion result of the second-stage sub A / D converter is input to the second-stage D / A converter, and D / A conversion is performed. Subsequently, the D / A conversion result of the second-stage D / A converter and the output of the first-stage differential amplifier are input to the second-stage differential amplifier, and the difference therebetween is amplified. Thereafter, the same operation is sequentially performed in each stage.

However, the last stage is composed of only the sub-A / D converter, and A / D-converts the output of the preceding-stage differential amplifier.

For example, when the number of bits (bit configuration) of the sub-A / D converters of the first to third stages in the three-stage pipeline configuration are a, b, and c, respectively, the first-stage sub-A / D converter , A middle b bit from the second sub-A / D converter and a lower c-bit digital output from the third sub-A / D converter.

As described above, in the multistage pipeline configuration, in each stage, the difference between the analog input signal or the output of the preceding stage differential amplifier and the D / A conversion result of the digital output of the stage is determined by the difference of the stage. It is amplified by a difference amplifier. Therefore, the number of conversion bits increases and LSB (Least
Even if the Significant Bit is reduced, the resolution of each comparator constituting the sub A / D converter can be substantially improved, and sufficient conversion accuracy can be obtained.

A subtraction amplifier circuit is used as a differential amplifier at each stage of the analog-digital conversion circuit having such a multi-stage pipeline configuration.

FIG. 15 is a circuit diagram showing an example of a conventional subtraction amplifier circuit. FIG. 16 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

In FIG. 15, the inverting input terminal of the operational amplifier 1 is connected to the node nb, and the non-inverting input terminal is grounded. The output terminal of the operational amplifier 1 is connected to the node no.
And via a capacitor 2 to an inverting input terminal. The switch SW1 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier 1, and the capacitor 3 is connected between the node nb and the node na. Node na is connected to node n1 via switch SW2, and connected to node n via switch SW3.
2 are connected.

[0014] voltages V ₁ to the node n1 is input, the voltage V ₂ is input to the node n2, the voltage V _O output from the node no.

Here, the operation of the subtraction amplifier circuit of FIG. 15 will be described with reference to FIG. Incidentally, the capacitance value of the capacitor 2 is C, a capacitance value of the capacitor 3 and KC, the ground potential V _G. K is a constant.

First, the switch SW1 and the switch SW
2 is turned on and the switch SW3 is turned off. Thereby, the voltage of the node na becomes V _1. Also, the node no
Becomes zero. At this time, the charge Qa of the node nb is as follows.

[0017] _{Qa = (V G -V 1)} KC Then, after turning off the switch SW1, the switch SW2
Is turned off, and the switch SW3 is turned on. Thereby, the voltage of the node na becomes V _2. Node n
The voltage of o becomes V _O. At this time, since the node nb is virtually grounded, the charge Qb of the node nb is expressed by the following equation.

[0018] Since the _{Qb = (V G -V 2)} KC + (V G -V O) C node no route charge exits the nb, the Qa = Qb by the charge conservation law. Therefore, the following equation is established.

[0019] _{(V G -V 1) KC =} (V G -V 2) KC
+ (V _G −V _O ) C From the above equation, the voltage V _{O at the} node no is as follows.

V _O = V _G + (V ₁ −V ₂ ) K In this manner, the voltage V ₂ is subtracted from the voltage V ₁ , and the subtracted value is amplified by a factor of K.

[0021]

In the above-described conventional subtraction amplifier circuit, as described above, the switches SW2 and S2 are used to switch the voltages V ₁ and V ₂ input to the node na.
W3 is required. These switches SW2, SW3
Is usually constituted by a CMOS switch composed of a CMOS (complementary metal oxide semiconductor) field effect transistor.

This CMOS switch has a characteristic that it cannot be reliably turned on and off at the time of low voltage operation.
In particular, it is difficult to pass the intermediate level between the power supply voltage and the ground voltage,
Or can not pass. Therefore, it is difficult to reduce the voltage of the analog-digital conversion circuit.

The voltage V ₁ , which is an analog input signal,
Since V ₂ is input to the capacitor 3 via the switch SW2, SW3, if unspecified analog signal is inputted, switches the noise which depends on the analog input signal level to the analog input signal is generated.

As a result, a high-precision analog-to-digital conversion circuit that can operate at a low voltage and cannot be realized.

An object of the present invention is to provide a subtraction amplifier circuit capable of operating at a low voltage and reducing noise, and an analog-to-digital conversion circuit including the same.

It is another object of the present invention to provide a method of operating a subtraction amplifier circuit capable of operating at a low voltage and reducing noise.

[0027]

Means for Solving the Problems and Effects of the Invention (1)
1st invention The subtraction amplifier circuit according to the 1st invention is one of the operational amplifiers.
A first capacitor is connected between the input terminal and the output terminal, and
The second and third capacitors are connected to one input terminal of the operational amplifier.
Connected to one input terminal of the operational amplifier and the other
Short-circuited to the input terminal and the second capacitor
Input voltage is applied to the input terminal of the
After an arbitrary set voltage is applied to one end, one of the operational amplifiers
Between the input terminal and the other input terminal is open
At the same time, the set voltage is applied to the input terminal of the second capacitor.
And the second input voltage is applied to the input terminal of the third capacitor.
It is what is done.

[0028]

[0029]

[0030]

[0031]

In the subtraction amplifier circuit according to the present invention, the first input voltage and the second input voltage are interposed via the set voltage without switching between the first and second input voltages using a switch.
Is subtracted, and the subtracted value is amplified.

In this case, the first
And the second input voltage can be input and the set voltage can be arbitrarily set, so that noise can be reduced and low-voltage operation can be performed.

(2) Second Invention In the subtraction amplifier circuit according to the second invention, in the configuration of the subtraction amplifier circuit according to the first invention, the third capacitor is connected in parallel to one input terminal of the operational amplifier. Including a plurality of connected capacitors, a plurality of input voltages are respectively applied to input terminals of the plurality of capacitors when an open state is established between one input terminal and the other input terminal of the operational amplifier. .

In this case, by dividing the third capacitor into a plurality of capacitors, it is possible to set the second input voltage using an arbitrary plurality of input voltages.

[0036]

[0037]

[0038]

[0039]

(3) Third Invention A subtraction amplifier circuit according to a third invention is characterized in that the first and second capacitors are respectively provided between one and the other input terminals of the operational amplifier and the one and the other output terminals. The third and fourth capacitors are connected in parallel to one input terminal of the operational amplifier, and the fifth and sixth capacitors are connected to the other input terminal of the operational amplifier.
Are connected in parallel, one and the other input terminals of the operational amplifier are connected to a predetermined reference potential, and the first and second input voltages are applied to the input terminals of the third and fifth capacitors, respectively. And an arbitrary first set voltage is applied to the input terminals of the fourth and sixth capacitors, respectively,
One and the other input terminals of the operational amplifier are cut off from the reference potential, an arbitrary second set voltage is applied to the input terminals of the third and fifth capacitors, respectively, and the input terminals of the fourth and sixth capacitors are The third and fourth input voltages are respectively supplied to the input terminals.

In the subtraction amplifier circuit according to the present invention, the first and third input voltages are not switched by using the switch, and the first and third input voltages are not switched by using the switch. The difference voltage between the first and third input voltages and the difference voltage between the second and fourth input voltages are subtracted via the second set voltage and the second set voltage, and the subtracted value is amplified.

In this case, the first, second, third, and fourth input voltages can be input without using a switch, and the first and second set voltages can be arbitrarily set. In addition, noise can be reduced and low-voltage operation can be performed.

(4) Fourth Invention In the subtraction amplifier circuit according to the fourth invention, in the configuration of the subtraction amplifier circuit according to the third invention, the fourth and sixth capacitors are:
A plurality of capacitors respectively connected in parallel to one and the other input terminals of the operational amplifier, and a plurality of capacitors connected to the input terminals of the plurality of capacitors when one and the other input terminals of the operational amplifier are cut off from the reference potential; The input voltages are respectively given.

In this case, it is possible to set the third and fourth input voltages by respectively applying arbitrary plural input voltages to the input terminals of plural capacitors.

(5) Fifth Invention The analog-to-digital conversion circuit according to the fifth invention has a multi-stage pipeline configuration including a plurality of stages, and each stage has an analog-to-digital converter, a digital-to-analog converter, and Each of the differential amplifiers includes a differential amplifier according to any one of the first to fourth inventions.

In the analog-to-digital converter according to the present invention, since each differential amplifier comprises the subtraction amplifier according to any one of the first to eighth aspects, noise is reduced and low-voltage operation is possible. It becomes. Therefore, a high-precision analog-to-digital conversion circuit having a large number of bits, high resolution, low-voltage operation, and a high accuracy is realized.

[0047] (8) analog according to the sixth aspect sixth invention - digital conversion circuit, fifth
In the configuration of the analog-digital conversion circuit according to the invention, the output of the preceding stage is used as the set voltage of the differential amplifier of each stage.

In this case, since a switch or circuit for applying the set voltage is not required, noise is further reduced and the circuit configuration is simplified.

(7) Seventh Invention The analog-to-digital conversion circuit according to the seventh invention has a fifth
Alternatively, in the configuration of the analog-to-digital conversion circuit according to the sixth invention, the analog-to-digital converter in each stage is a flash method having a plurality of comparators, and the digital-to-analog converter in each stage includes a plurality of switches and a plurality of switches. It is characterized by a capacity array system in which capacitors are connected in an array.

In this case, a high-precision analog-digital conversion circuit capable of high-speed conversion operation, having a large number of bits and high resolution, and capable of low-voltage operation is realized.

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

FIG. 1 is a circuit diagram of a subtraction amplifier circuit according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

In FIG. 1, the inverting input terminal of the operational amplifier 1 is connected to the node NB, and the non-inverting input terminal is grounded. The output terminal of the operational amplifier 1 is connected to the node NO, and is connected to the inverting input terminal via the capacitor 2. A switch SW1 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier 1. Node NB is connected to node N1 via capacitor 3 and to node N2 via capacitor 4.

_A voltage that changes from V ₁ to V _A is input to node N 1, and a voltage that changes from V _A to V ₂ is input to node N ₂ . _VA is an arbitrary set voltage. The voltage V _O is output from the node NO.

Next, the operation of the subtraction amplifier circuit of FIG. 1 will be described with reference to FIG. Here, the capacitance value of the capacitor 2 is C, and the capacitance values of the capacitors 3 and 4 are KC
And K is a constant. In addition, the ground potential and V _G.

First, the switch SW1 is turned on. Then, enter the voltages V ₁ to the node N1, and inputs the set voltage V _A at the node N2. Node NO is set to the ground potential V _G. At this time, the charge Qa of the node NB is as follows.

[0062] _{Qa = (V G -V 1)} KC + (V G -V A) KC Next, turn off the switch SW1. And node N
Enter the set voltage V _A to 1, to input the voltage V ₂ to the node N2. The voltage at the node NO becomes V _O. At this time, the charge Qb of the node NB is as follows.

[0063] _{Qb = (V G -V A)} KC + (V G -
Since _{V 2) KC + (V G} -V O) no route charge exits the KC node NB, Qa = Qb, and the following equation is established by the charge conservation law.

[0064] _{(V G -V 1) KC +} (V G -V A) KC
_{= (V G -V A) KC} + (V G -V 2) KC + (V G -
V _O ) KC From the above equation, the voltage V _{O at the} node NO is as follows.

V _O = V _G + (V ₁ -V ₂ ) K As described above, the voltage V output from the subtraction amplifier circuit of FIG.
_O becomes equal to the voltage V _O output from the conventional subtraction amplifier circuit of FIG.

In the subtraction amplifier circuit of this embodiment, the voltages V ₁ and V ₂ , which are analog input signals, are inputted to the nodes N 1 and N 2 without passing through a switch, and the set voltage _VA can be set arbitrarily. Therefore, noise can be reduced and low-voltage operation can be performed.

FIG. 3 is a circuit diagram of a subtraction amplifier circuit according to a second embodiment of the present invention. FIG. 4 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG.

The difference between the subtraction amplifier circuit of FIG. 3 and the subtraction amplifier circuit of FIG. 1 is as follows. Node NB is connected to node N1 via capacitor 3, connected to node N21 via capacitor 4A, and connected to node N22 via capacitor 4B. That is, in the subtraction amplifier circuit of the present embodiment, the capacitor 4 in the subtraction amplifier circuit of FIG. 1 is divided into two capacitors 4A and 4B.

V is applied to node N1.₁To V_AChange into electricity
Is input to the node N21. _ATo V_TChange to
Voltage is input to the node N22._ATo V_BStrange
Is input.

Next, the operation of the subtraction amplifier circuit of FIG. 3 will be described with reference to FIG. Here, the capacitance value of the capacitor 2 is C, the capacitance value of the capacitor 3 is KC, and the capacitance values of the capacitors 4A and 4B are each KC / 2. K
Is a constant. Also, as shown in FIG. 4A, V ₂ =
(V _T + V _B ) / 2 .

First, the switch SW1 is turned on. Then, enter the voltages V ₁ to the node N1, and inputs the setting voltage V _A at the node N21, and inputs the set voltage V _A at the node N22. Node NO is set to the ground potential V _G. At this time,
The charge Qa of the node NB is as follows.

[0072] _{Qa = (V G -V 1)} KC + (V G -
V _A ) × (KC / 2) × 2 Next, the switch SW1 is turned off. And node N
Enter the set voltage V _A to 1, enter the voltage V _T to node N21, and inputs the voltage V _B to the node N22. Node N
The voltage of _O becomes V _O. At this time, the charge Q of the node NB
b becomes as follows.

[0073] _{Qb = (V G -V A)} KC + (V G -
_{V T) × (KC / 2} ) + (V G -V B) × (KC / 2)
+ (V _G −V _O ) C Since there is no path for the charge to escape from the node NB, Qa = Qb from the charge conservation law, and the following equation holds.

V _O = V _G + ｛V _1- (V _T + V _B ) /
_{2} K = V G + (} V 1 -V 2) K Thus, the voltage V output from the subtracting amplifier circuit of FIG. 3
_O becomes equal to the voltage V _O output from the subtraction amplifier circuit of FIG. That is, by bisecting the capacitor connected to the node NB, the voltage a voltage V ₂ V _T and the voltage V
It can be set at an intermediate point with _B. As shown in FIG. 5 when divided into four capacitor connected to the node NB, it is possible to set the voltage V ₂ to one of the 4 division point between the voltage V _T and the voltage V _B .

[0075] In the same manner, it can be set to any voltage between the voltage V ₂ and the voltage V _T and the voltage V _B by dividing the capacitor connected to the node NB to any number.

[0076] In these cases, it is possible to use an external voltage as the voltage V _T and the voltage V _B. Therefore, it is possible to generate a voltage V ₂ with the external voltage.

FIG. 6 is a circuit diagram of a subtraction amplifier circuit according to a third embodiment of the present invention. FIG. 7 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. This subtraction amplifier circuit is a fully differential subtraction amplifier circuit.

In FIG. 6, the inverting input terminal of the operational amplifier 1 is connected to the node Na, and the non-inverting input terminal is connected to the node N.
b. The inverting output terminal of the operational amplifier 1 is connected to the node NO1 and to the inverting input terminal via the capacitor 2a. The non-inverting output terminal is connected to the node NO2 and to the non-inverting input terminal via the capacitor 2b.

Node Na is grounded via switch SW11, and node Nb is grounded via switch SW12. The node Na is connected to the node N11 via the capacitor 3a, and is connected to the node N12 via the capacitor 4a. Node Nb is connected to node N21 via capacitor 3b, and to node N22 via capacitor 4b. The switch SW13 is connected between the nodes NO1 and NO2. This switch SW13 is connected to the switch SW1
1, and operate at the same timing as SW12.

_A voltage that changes from V ₁ (+) to V _A is input to the node N11, and a voltage from V _A to V ₂ is input to the node N12.
A voltage that changes to (+) is input. _A voltage that changes from V ₁ (−) to V _A is input to the node N21, and a voltage that changes from V _A to V ₂ (−) is input to the node N22. _VA is an arbitrary set voltage. Voltage V _O from node NO1 (+) is output, the voltage V _O from node NO2
(-) Is output. The difference voltage ΔV _O between the nodes NO1 and NO2 is expressed by the following equation.

ΔV _O = V _O (+) − V _O (−) Next, the operation of the subtraction amplifier circuit of FIG. 6 will be described with reference to FIG. Here, the capacitance values of the capacitors 2a and 2b are each C, and the capacitance values of the capacitors 3a, 3b, 4a and 4b are each KC. K is a constant. In addition, the ground potential and V _G.

First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, the voltage V ₁ (+) is input to the node N11, the set voltage _VA is input to the node N12, and the voltage V ₁ is input to the node N21.
₁ (−) is input, and the set voltage _VA is input to the node N22. Node NO1, NO2 becomes the ground potential V _G. At this time, the charge QAA of the node Na is expressed by the following equation.

[0083] _{QAA = {V G -V 1 (} +)} KC + (V
_G− V _A ) KC The charge QAB of the node Nb is expressed by the following equation.

[0084] _{QAB = {V G -V 1 (} -)} KC + (V
_G− V _A ) KC Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, the set voltage _VA is input to the node N11, and the voltage V
₂ (+) is input, the set voltage _VA is input to the node N21, and the voltage V ₂ (−) is input to the node N22. The voltages at nodes NO1 and NO2 are V _O (+) and V _{O, respectively.}
(-). At this time, the charge QBA of the node Na is expressed by the following equation.

[0085] _{QBA = (V G -V A)} KC + {V G -V
_{2 (+)} KC + {} V G -V O (+)} C The charge QBB node Nb is as follows.

QBB = (V _G -V _A ) KC + ΔV _G -V
₂ (−)｝ KC + (V _G −V _O (−)) C Since there is no path for the charge to escape from the nodes Na and Nb,
According to the law of conservation of charge, QAA = QBA and QAB = QBB, and the following equation holds.

V _O (+) = V _G + ｛V ₁ (+) − V ₂ (+)｝ K V _O (−) = V _G + ｛V ₁ (−) − V ₂ (−)｝ K , And the differential voltage ΔV _O is given by the following equation.

ΔV _O = V _O (+) − V _O (−) = ｛V ₁ (+) − V ₁ (−)｝ K− ｛V ₂ (+) − V ₂ (−)｝ K = (ΔV ₁₋ ΔV ₂ ) K Note that ΔV ₁ = V ₁ (+) − V ₁ (−), ΔV ₂ = V ₂
(+) − V ₂ (−).

As described above, in the subtraction amplifier circuit of the present embodiment, it is possible to perform subtraction and amplification of the difference voltage ΔV ₁ and the difference voltage ΔV ₂ .

In this subtraction amplifier circuit, the voltage V
₁ (+) and V ₂ (+) are input to the nodes N11 and N12 without passing through the switches, and the voltages V ₁ (−) and V
₂ (−) indicates that the nodes N21 and N
22 and the set voltage _VA can be arbitrarily set, so that noise can be reduced and low-voltage operation can be performed.

FIG. 8 is a circuit diagram of a subtraction amplifier circuit according to a fourth embodiment of the present invention. FIG. 9 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. The subtraction amplification circuit in FIG. 8 is also a fully differential subtraction amplification circuit.

The difference between the subtraction amplifier circuit of FIG. 8 and the subtraction amplifier circuit of FIG. 6 is that a voltage that changes from V ₁ (+) to V _A1 is input to the node N11 and V _A2 to V A
₂ A voltage that changes to (+) is input, and V
₁ A voltage that changes from (−) to V _A1 is input, and the node N
22 is that a voltage that changes from V _A2 to V ₂ (−) is input. _VA1 and _VA2 are arbitrary set voltages, respectively. Other configurations are the same as those shown in FIG.

Next, the operation of the subtraction amplifier circuit of FIG. 8 will be described with reference to FIG. Here, the capacitors 2a, 2
b, and the capacitors 3a, 3b,
The capacitance values of 4a and 4b are each represented by KC. K is a constant. In addition, the ground potential and V _G.

First, the switches SW11 and SW12 are turned on. At this time, the switch SW13 is also turned on. Then, the voltage V ₁ (+) is inputted to the node N11, the set voltage V _A2 is inputted to the node N12, and the voltage V ₁ is inputted to the node N21.
₁ (−) is input, and the set voltage V _A2 is input to the node N22. Node NO1, NO2 is respectively ground potential V _G.

Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, the set voltage V _A1 is input to the node N11, and the node N11
12, the voltage V ₂ (+) is input, the set voltage V _A1 is input to the node N21, and the voltage V ₂ (−) is input to the node N22. The voltages at nodes NO1 and NO2 are V
_O (+) and V _O (-).

In the same manner as in the third embodiment, the voltages V _O (+) and V _O (−) of the nodes NO1 and NO2 are calculated according to the law of conservation of electric charge.
Is obtained as follows.

V _O (+) = V _G + ｛V ₁ (+) − V
₂ (+)｝ K + (V _A1 −V _A2 ) K V _O (−) = V _G + ｛V ₁ (−) − V ₂ (−)｝ K +
(V _A1 −V _A2 ) K Therefore, the difference voltage ΔV _O is expressed by the following equation.

ΔV _O = V _O (+) − V _O (−) = ｛V ₁ (+) − V ₁ (−)｝ K− ｛V ₂ (+) − V ₂ (−)｝ K = ΔV ₁ -ΔV ₂ As described above, in the subtraction amplifier circuit of the present embodiment, the subtraction and amplification of the difference voltage ΔV ₁ and the difference voltage ΔV ₂ can be performed even when the arbitrary set voltages V _A1 and V _A2 are not equal. .

Further, the voltages V ₁ (+) and V ₂ (+) can be inputted to the nodes N11 and N12 without using a switch, and the voltages V ₁ (−) and V ₂ (−) can be respectively inputted. Since the signals can be input to the nodes N21 and N22 without using a switch, and the set voltages V _A1 and V _A2 can be set arbitrarily, noise can be reduced and low-voltage operation can be performed.

FIG. 10 is a block diagram showing a configuration of an analog-to-digital converter according to a fifth embodiment of the present invention. The analog-digital conversion circuit of FIG. 10 has a 10-bit 4-stage pipeline configuration.

In FIG. 10, the analog-digital conversion circuit 101 includes a sample-hold circuit 102, a first-stage circuit 103, a second-stage circuit 104, and a third-stage circuit 10.
The circuit includes fifth and fourth stage circuits 106, a plurality of latch circuits 107, and an output circuit 108.

First-stage (initial-stage) to third-stage circuits 103-1
05 includes a sub A / D converter 109, a D / A converter 110, and a difference amplifier 111. As described later, the subtraction amplifier circuit of the fourth embodiment is used as the difference amplifier 111. The circuit 106 at the fourth stage (final stage) includes only the sub A / D converter 109.

The first-stage circuit 103 has a 4-bit configuration,
The fourth-stage circuits 104 to 106 each have a 2-bit configuration. In the first to third circuits 103 to 105, the sub A / D converter 109 and the D / A converter 110
Are set to be the same.

Next, the analog-digital conversion circuit 101
Will be described. The sample hold circuit 102 samples the analog input signal Vin and holds it for a certain period of time. The analog input signal Vin output from the sample and hold circuit 102 is transferred to the first stage circuit 3.

In the first-stage circuit 103, the sub A / D
The converter 109 converts the analog input signal Vin into A /
Perform D conversion. Upper 4 bits of digital output (2 ⁹ ,
2 ⁸ , 2 ⁷ , 2 ⁶ ) are transferred to the D / A converter 110 and are also transferred to the output circuit 108 via the four latch circuits 107. The difference amplifier 111 has a D / A
The difference between the D / A conversion result of the converter 110 and the analog input signal Vin is amplified. The output of the difference amplifier 111 is transferred to the circuit 104 in the second stage.

In the second-stage circuit 104, the same operation as that of the first-stage circuit 103 is performed on the output of the difference amplifier 111 of the first-stage circuit 103. In the third-stage circuit 105, the same operation as that of the first-stage circuit 103 is performed on the output of the difference amplifier 111 of the second-stage circuit 104. Then, a digital output (2 ⁵ , 2 ⁴ ) of the middle and upper 2 bits is obtained from the second stage circuit 104,
From the circuit 105 at the stage, a digital output (2 ³ , 2 ² ) of middle and lower 2 bits is obtained.

In the circuit 106 at the fourth stage, the output of the differential amplifier 111 of the circuit 105 at the third stage is
The / D converter 109 performs A / D conversion, and a digital output (2 ¹ , 2 ⁰ ) of lower 2 bits is obtained.

The digital outputs of the circuits 103 to 106 of the first to fourth stages pass through the respective latch circuits 107 and are simultaneously output to the output circuit 10.
Reach 8. That is, each latch circuit 107 is provided to synchronize the digital output of each of the circuits 103 to 106.

The output circuit 108 outputs a 10-bit digital output Dout of the analog input signal Vin and outputs it in parallel after digital correction processing.

As described above, in the analog-digital conversion circuit 101, in each of the circuits 103 to 105, the analog input signal Vin or the preceding circuits 103, 1
04, the output of the differential amplifier 111 and the circuit 103 at that stage.
The difference between the D / A conversion result of the digital output and the D / A conversion result is amplified by the difference amplifier 111.

Therefore, the number of conversion bits increases and LSB
Is smaller, the resolution of each comparator constituting the sub A / D converter 109 can be substantially improved, and sufficient conversion accuracy can be obtained.

FIG. 11 is a circuit diagram of the difference amplifier 111 in the analog-digital conversion circuit 101 of FIG.
The difference amplifier 111 in FIG. 11 has the same configuration as the subtraction amplifier circuit in FIG.

[0113] The difference amplifier 111, the output of the differential amplifier 111 of the analog input signal Vin or upstream circuit 103 to 105 is supplied as differential voltage [Delta] V _i. ΔV
_i = V _i (+) - a - V _i (). The difference amplifier 111 has a D / A converter 110 of the same stage.
The / A conversion result is given as a difference voltage ΔVDA. ΔVDA = VDA (+) − VDA (−).

A voltage that changes from V _i (+) to V _A1 is input to the node N11, and a voltage from V _A2 to V D2 is input to the node N12.
A voltage that changes to A (+) is input, a voltage that changes from V _i (−) to V _A1 is input to the node N21, and a voltage that changes from V _A2 to VDA (−) is input to the node N22. You.

Next, the operation of the difference amplifier 111 of FIG. 11 will be described with reference to FIG. First, switch SW1
1, SW12 is turned on. At this time, the switch SW1
Also turn on 3. Then, the voltage V is applied to the node N11.
_i (+), the set voltage V _A2 is input to the node N12, the voltage V _i (−) is input to the node N21, and the node N
The set voltage V _A2 is input to 22. Thereby, the node N
O1, NO2 becomes the ground potential V _G.

Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, the set voltage V _A1 is input to the node N11, and the node N11
Enter the voltage VDA (+) to 12, enter the set voltage V _A1 to the node N21, the voltage VDA at node N22 - enter a (). Thereby, the voltages of the nodes NO1 and NO2 become V _O (+) and V _O (−), respectively.

When the difference voltage ΔV _O is obtained in the same manner as in the subtraction amplifier circuit of FIG. 8, the following equation is obtained.

ΔV _O = V _O (+) − V _O (−) = ｛V _i (+) − V _i (−)｝ K− ｛VDA (+) − VDA (−)｝ K = (ΔV _i − ΔVDA) K Thus, the difference amplifier 111 of FIG. 11, subtraction and amplification of the differential voltage DerutaVDA provided from D / a converter 110 of the same stage and the differential voltage [Delta] V _i supplied from the preceding stage is carried out.

In this case, the set voltages V _A1 and V _A2 can be set arbitrarily. Therefore, the voltage at the time of equalizing (equalizing) the output of the sample-hold circuit 102 at the preceding stage or the output of the difference amplifier 111 can be used as the set voltage V _A1 . Further, an external voltage can be used as the set voltage _VA2 .

As described above, the voltages V _i (+) and V _i (−), which are analog input signals, can be input to the nodes N11 and N21 without passing through the switches. Voltage operation becomes possible. Therefore, the voltage and accuracy of the analog-to-digital conversion circuit 101 can be reduced.

FIG. 13 is a circuit diagram of the sub A / D converter 109 and the D / A converter 110 in the analog-to-digital converter 101 of FIG. A sub-A / D converter 109 shown in FIG. 13 is an all-parallel comparison (flash) type sub-A / D converter.
Reference numeral 0 denotes a capacitance array type D / A converter.

The sub-A / D converter 109 comprises n resistors R and n comparators D1 to Dn. All resistors R have the same resistance value, and are connected in series between node N31 receiving high-potential-side reference voltage VRT and node N32 receiving low-potential-side reference voltage VRB. Here, n between the node N32 and the node N31
The potentials of the nodes N41 to N4n between the resistors R are denoted by VR (1) to VR (n), respectively.

The input signal VI (analog input signal Vin or the output of the differential amplifier 111 of the preceding circuits 103 to 105) is input to the positive input terminals of the comparators D1 to Dn. Negative input terminals of the comparators D1 to Dn are respectively connected to potentials VR (1) to VR4 of nodes N41 to N4n.
VR (n) is applied.

As a result, the output of each of the comparators D1 to Dn is determined by the input signal VI corresponding to the potential VR (1) to VR (1).
When the input signal VI is higher than (n), the input signal VI is at a high level. When the input signal VI is lower than the potentials VR (1) to VR (n), the input signal VI is at a low level.

The D / A converter 110 has n switches E1 to En, F1 to F1 connected in an array.
n, G1 to Gn, H1 to Hn, n positive-side capacitors B
1 to Bn and n negative-side capacitors C1 to Cn.

The capacitors B1 to Bn and C1 to Cn all have the same capacitance value c. A differential positive output voltage VDA (+) is generated from one terminal (hereinafter, referred to as an output terminal) of the capacitors B1 to Bn, and is different from one terminal (hereinafter, referred to as an output terminal) of the capacitors C1 to Cn. The negative output voltage VDA (−) is generated. Note that each capacitor B
The other terminals of 1 to Bn and C1 to Cn are called input terminals.

One terminal of each of switches E1 to En is connected to node N31, and the other terminal is connected to capacitors B1 to B2.
n input terminals. Each switch F1 to Fn
Is connected to the node N31, and the other terminal is connected to the input terminals of the capacitors C1 to Cn. One terminal of each of the switches G1 to Gn is connected to the node N32, and the other terminal is connected to input terminals of the capacitors B1 to Bn. One terminal of each of the switches H1 to Hn is connected to the node N32, and the other terminal is connected to the capacitor C1.
To Cn.

Each of the switches E1 to En, F1 to Fn, G1
To Gn and H1 to Hn are switches of the same number, respectively.
Construct a continuous switch. For example, switches E1, F1,
G1 and H1 are connected in series, and switches En, Fn, Gn,
Hn is also one. Then, each of the switches E1 to En, F
1 to Fn, G1 to Gn, and H1 to Hn turn on and off according to the output levels of the comparators D1 to Dn, respectively. For example, when the output of the comparator Dn is at a high level, the switches En and Hn are turned on, and the switches Gn and Fn are turned on.
Turns off. Conversely, when the output of the comparator Dn is at low level, the switches En and Hn are turned off and the switch G
n and Fn are turned on.

The output of the comparator D1 constituting the sub A / D converter 109 is open. Further, the switches E1 and F1 are fixed to an ON state at a predetermined timing, and the switches G1 and H1 are fixed to an OFF state at a predetermined timing.

Input signal V of sub A / D converter 109
The voltage range of I is from the high potential side reference voltage VRT to the low potential side reference voltage VRB. That is, the input signal VI of the sub-A / D converter 109 does not fall below the low potential side reference voltage VRB. Therefore, the output of the comparator D1 always goes to the high level. Therefore, the comparator D1
Switch E1, G1, F1, H1
Can be fixed at a predetermined timing.

Next, the operation of the D / A converter 110 will be described. In the initial condition, the potentials of the input terminals and the output terminals of the capacitors B1 to Bn are both 0 V, and the switches E1 to En, F1 to Fn, G1 to Gn, and H1 to Hn are all off. Therefore, in the initial condition, the electric charge (electric quantity) Q1 = 0 stored in all the capacitors B1 to Bn and C1 to Cn.

Here, when the outputs of m of the n comparators D1 to Dn become high level, m of the switches E1 to En are turned on and (nm) switches are turned off, Of the switches G1 to Gn, (nm) switches are on and m switches are off. These switches E1 to En, G1 to
According to the on / off operation of Gn, all the capacitors B1
The electric charge Q2 stored in Bn is represented by the following equation (A1).

Q2 = m (VRT−VDA (+)) c + (nm) (VRB−VDA (+)) c (A1) According to the law of conservation of charge, Q1 = Q2. Therefore, the differential positive output voltage VDA (+) is expressed by the following equation (A2).

VDA (+) = VRB + m (VRT−VRB) / n (A2) On the other hand, when m outputs of the n comparators D1 to Dn become high level, among the switches H1 to Hn, m switches on, (nm) switches off, and each switch F
(Nm) of 1 to Fn are turned on and m are turned off. According to the on / off operations of the switches H1 to Hn and F1 to Fn, the electric charge Q3 stored in all the capacitors C1 to Cn is represented by the following equation (A3).

Q2 = (nm) (VRT−VDA (−)) c + m (VRB−VDA (−)) c (A3) According to the law of conservation of charge, Q1 = Q3. Therefore, the differential negative output voltage VDA (-) is represented by the following equation (A4).

VDA (−) = VRB− (m−1) (VRT−VRB) / n (A4) Therefore, according to the above equations (A2) and (A4), the difference voltage Δ
VDA is represented by equation (A5).

ΔVDA = VDA (+) − VDA (−) = VRB−VRT + (m−1) (VRT−VRB) / n− (VRT−VRB) / n (A5) FIG. 14 shows a fourth embodiment. D / A converter 110 and difference amplifier 11 when the subtraction amplification circuit shown in FIG.
1 is a circuit diagram showing a specific configuration of FIG.

In FIG. 14, D / A converter 110
Is connected to input terminals of capacitors B1 to Bn via switches S1 to Sn, respectively.
The node N30 is connected to input terminals of capacitors C1 to Cn via switches T1 to Tn, respectively. The set voltage V _A2 is input to the node N30, the high-potential-side reference voltage VRT is input to the node N31, and the low-potential-side reference voltage VRB is input to the node N32.
Output terminals of the capacitors B1 to Bn are connected to a node Na of the difference amplifier 111, and output terminals of the capacitors C1 to Cn are connected to a node Nb of the difference amplifier 111.

The node Na of the difference amplifier 111 is connected to the node N11 via the capacitor 3a, and the node Nb is connected to the node N21 via the capacitor 3b. Voltage V _i (+) is inputted to the node N11, the node N21 voltage V _i (-) is input.

The capacitance value of each of the capacitors 2a and 2b is C, and the capacitance value of each of the capacitors 3a and 3b is KC. The capacitance values of the capacitors B1 to Bn and C1 to Cn are respectively KC / n. K is a constant.

Next, the operation of the D / A converter 110 and the difference amplifier 111 in FIG. 14 will be described.

First, the switches SW11 and SW12 are turned on.
To At this time, the switch SW13 is also turned on. So
Then, the switches S1 to Sn and T1 to Tn are turned on.
Thereby, the inputs of the capacitors B1 to Bn and C1 to Cn
Set voltage V to terminal_A2Is entered. Also, the node N11
Voltage V_i(+) Is input and the voltage V is applied to the node N21. _i
(-) Is input. As a result, the nodes NO1, NO
2 is the ground potential.

Next, the switches SW11 and SW12 are turned off. At this time, the switch SW13 is also turned off. Then, the switches S1 to Sn and T1 to Tn are turned off.
Each switch E1 to En, F1 to Fn, G1 to Gn, H1
To Hn are the comparators D1 to Dn in FIG.
ON or OFF according to the output level of the capacitor B
Voltages are applied to input terminals 1 to Bn and C1 to Cn, respectively.

At this time, the voltages V _i (+) and V _i (−) input to the nodes N11 and N21 are equalized to the same voltage V _A1 as shown in FIG. As a result, the difference voltage ΔV _O between the nodes NO1 and NO2 becomes
As described with reference to FIG. 12, the following expression is obtained.

ΔV _O = V _O (+) − V _O (−) = ΔV _i −ΔVDA Thus, the output of the preceding-stage differential amplifier 111 can be used as the set voltage V _A1 input to the nodes N11 and N21. because, the voltage V _i without using a switch voltage V _i (+) and can enter the set voltage V _A1, and a node N21 without using the switch node N11 - enter and set voltage V _A1 () can do.

The set voltage V input to the node N30 is
Any voltage can be used as _A2 . For example, it is also possible to use a high-potential reference voltage VRT or lower reference voltage VRB as the set voltage V _A2.

Further, these set voltages V _A1 and V _A2 can be set near the power supply voltage or the ground voltage. This allows
Even if a CMOS switch is used, low-voltage operation is possible.

As a result, a high-precision analog-to-digital conversion circuit capable of low-voltage operation while reducing switch noise is realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a subtraction amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. 1;

FIG. 3 is a circuit diagram of a subtraction amplifier circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining an operation of the subtraction amplifier circuit of FIG. 3;

FIG. 5 is a diagram showing another example of the capacity division.

FIG. 6 is a circuit diagram of a subtraction amplifier circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. 6;

FIG. 8 is a circuit diagram of a subtraction amplifier circuit according to a fourth embodiment of the present invention.

FIG. 9 is a diagram for explaining the operation of the subtraction amplifier circuit of FIG. 8;

FIG. 10 is a block diagram showing a configuration of an analog-digital conversion circuit having a multi-stage pipeline configuration according to a fifth embodiment of the present invention.

11 is a circuit diagram of a difference amplifier in the analog-to-digital conversion circuit of FIG.

FIG. 12 is a diagram for explaining the operation of the differential amplifier in FIG. 11;

13 is a circuit diagram of a sub-A / D converter and a D / A converter in the analog-to-digital converter of FIG.

FIG. 14 illustrates a case where the subtraction amplifier circuit of the fifth embodiment is used as a difference amplifier of the analog-to-digital conversion circuit of FIG. 10;
FIG. 3 is a circuit diagram of an / A converter and a differential amplifier.

FIG. 15 is a circuit diagram showing an example of a conventional difference amplifier.

FIG. 16 is a diagram for explaining the operation of the differential amplifier in FIG.

[Explanation of symbols]

1 operational amplifiers 2, 2a, 2b, 3a, 3b, 4a, 4b, B1 to B
n, C1 to Cn Capacitor 101 Analog-digital conversion circuit 102 Sample hold circuit 103 to 106 First to fourth stage circuit 109 Sub A / D converter 110 D / A converter 111 Difference amplifiers SW1, SW11 to SW12, E1 En, G1 to G
n, S1 to Sn, F1 to Fn, H1 to Hn, T1 to Tn
switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88 G09G 7/00

Claims (7)

(57) [Claims] A first capacitor connected between one input terminal and an output terminal of the operational amplifier; a second capacitor and a third capacitor connected in parallel to the one input terminal of the operational amplifier; The one input terminal and the other input terminal of the operational amplifier are short-circuited, a first input voltage is applied to an input terminal of the second capacitor, and After an arbitrary setting voltage is applied to the input terminal, the connection between the one input terminal and the other input terminal of the operational amplifier is opened, and the setting terminal is connected to the input terminal of the second capacitor. A subtraction amplifier circuit to which a voltage is applied and a second input voltage is applied to an input terminal of the third capacitor. 2. The method according to claim 1, wherein the third capacitor includes a plurality of capacitors connected in parallel to the one input terminal of the operational amplifier, and includes a plurality of capacitors connected between the one input terminal and the other input terminal of the operational amplifier. 2. The subtraction amplifier circuit according to claim 1 , wherein a plurality of input voltages are respectively applied to input terminals of the plurality of capacitors when the gap is opened. 3. A first and a second capacitor are respectively connected between one and the other input terminals of the operational amplifier and the one and the other output terminals, and a third and a third capacitor are respectively connected to the one input terminal of the operational amplifier. A fourth capacitor is connected in parallel, a fifth and a sixth capacitor are connected in parallel to the other input terminal of the operational amplifier, and the one and other input terminals of the operational amplifier are set to a predetermined reference potential. Connected and the third and fifth
Given the first and second input voltage to the input terminal of the capacitor, respectively, and after the fourth and first specified voltage for any input terminal of the sixth capacitor is al provided respectively, the operational amplifier Is disconnected from the reference potential, and the third and fifth input terminals are
Subtraction amplification characterized in that an arbitrary second set voltage is applied to the input terminal of the first capacitor and third and fourth input voltages are applied to the input terminals of the fourth and sixth capacitors, respectively. circuit. 4. The fourth and sixth capacitors each include a plurality of capacitors respectively connected in parallel to the one and the other input terminals of the operational amplifier, and the one and the other inputs of the operational amplifier. 4. The subtraction amplifier circuit according to claim 3 , wherein a plurality of input voltages are respectively applied to input terminals of the plurality of capacitors when a terminal is cut off from the reference potential. 5. A multi-stage pipeline configuration comprising a plurality of stages, each stage including an analog-to-digital converter, a digital-to-analog converter, and a differential amplifier, wherein each differential amplifier is
An analog-digital conversion circuit comprising the subtraction amplifier circuit according to claim 1 . 6. The analog-to-digital conversion circuit according to claim 5 , wherein an output of a preceding stage is used as said set voltage of said differential amplifier of each stage. 7. The analog-to-digital converter of each stage is of a flash type having a plurality of comparators, and the digital-to-analog converter of each stage is a capacitor in which a plurality of switches and a plurality of capacitors are connected in an array. 7. The analog-to-digital conversion circuit according to claim 5 , wherein the analog-to-digital conversion circuit is an array type.