JP2004179325A - Tape carrier for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device which can improve a yield when a product is conveyed to next step by eliminating a warp at a copper wiring pattern layer forming time and a warp at a heat curing time of a thermosetting type solder resist, and which can improve the working efficiency of a product processing treatment in next step and the dimensional quality of the product. <P>SOLUTION: The tape carrier for the semiconductor device is constituted by adhering a reinforcing tape 6 having a plurality of through holes 6a to the lower surface of an insulating film 2 in a constitution having a copper layer 1 formed on the insulating film 2. The plurality of the holes 6a are arrayed on a substantially straight line along the tape width, and are disposed downward under the region in which the part of the copper layer 1 is eliminated by patterning at the copper wiring pattern layer forming time from the copper layer 1 or are disposed in the lower vicinity region. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device tape carrier for mounting a semiconductor chip to form a semiconductor package, and more particularly to a semiconductor device tape carrier having a bendability called COF (Chip on Film).
[0002]
[Prior art]
In a process of manufacturing a TAB (Tape Automated Bonding) tape, which is a conventional tape carrier for a semiconductor device having a bendability called COF, when the thickness of a copper-containing insulating film having a two-layer structure is reduced to about 40 μm, a perforation hole ( When the insulating film is wrinkled or partially broken at the time of transport to the next step with the support of the perforated holes, it has been difficult to transport the TAB tape.
[0003]
Therefore, as shown in the cross-sectional view of the TAB tape in the width direction of FIG. 8A, in the configuration in which the copper layer 1 serving as the copper wiring pattern layer is formed on the insulating film 2, the lower surface of the insulating film 2 The reinforcing tape 3 is attached. Next, a photoresist (not shown) is coated and baked, exposed and developed, and the copper layer 1 is etched to form a copper wiring pattern layer 1a as shown in FIG. 8B. Then, tin plating for flip-chip connection of the LSI is performed, the photoresist is removed, and then tin plating is baked to form a tin plating layer 4 as shown in FIG. 8C. The solder resist 5 is applied by printing, and the solder resist 5 is cured by heat treatment. That is, in order to eliminate wrinkles and partial breakage of the insulating film 2, the reinforcing tape 3 is applied to enhance the entire TAB tape. (For example, refer to Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-223795
[Problems to be solved by the invention]
However, in the conventional TAB tape, as shown in FIG. 9A, when the copper layer 1 is etched to form the copper wiring pattern layer 1a, part of the copper layer 1 is lost. Due to the difference in the thermal expansion and contraction amount of each layer, the balance of the force acting between the layers is lost, and the TAB tape is warped. When such warpage occurs, it is difficult to carry the product to the next process, and there is a problem that the yield of products is reduced.
[0006]
Further, as shown in FIG. 9B, a thermosetting solder resist 5 is formed on the copper wiring pattern layer 1a and the insulating film 2 via the tin plating layer 4, and the solder resist 5 is cured by heat treatment. In this case, there is a problem that warpage due to heat occurs, making it difficult to convey to the next step, and lowering the work efficiency of TAB tape processing in the next step and the dimensional quality of the TAB tape.
[0007]
The present invention has been made in view of such a point, and eliminates the warpage at the time of forming a copper wiring pattern layer and the warpage at the time of thermosetting of a thermosetting solder resist, so that the yield at the time of transporting a product to the next step is improved. It is an object of the present invention to provide a semiconductor device tape carrier capable of improving the work efficiency and the dimensional quality of a product in the next step.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a tape carrier for a semiconductor device of the present invention is a tape carrier for a semiconductor device in which a copper layer for forming a copper wiring pattern is formed on an insulating film. And a reinforcing tape having a penetrated hole formed thereon is attached.
[0009]
Further, a plurality of the holes are arranged on a substantially straight line along the tape width.
[0010]
Further, the hole is arranged below or in the vicinity of a region where a part of the copper layer has disappeared by patterning at the time of forming the copper wiring pattern.
[0011]
The thickness of the copper layer is 0.2 μm to 25 μm.
[0012]
Further, the reinforcing tape has a heat resistance that does not deform at 180 ° C. × 2 hours or more.
[0013]
Further, the present invention is characterized in that tin plating is applied on the copper wiring pattern.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0015]
(Embodiment)
1A and 1B show a configuration of a TAB tape according to an embodiment of the present invention, in which FIG. 1A is a partial plan view between perforation holes of the TAB tape, and FIG. It is sectional drawing at the time of cutting.
[0016]
This TAB tape is characterized in that in the configuration in which the copper layer 1 is formed on the insulating film 2, a reinforcing tape 6 having a plurality of through holes 6 a formed on the lower surface of the insulating film 2 is attached. Have. However, FIG. 1 shows a portion inside a perforation hole provided at both ends of the TAB tape, that is, a portion having a tape width B1 used for actually mounting a semiconductor chip to form a semiconductor package. .
[0017]
The holes 6a are formed at the center of the tape width B1 and at positions on both sides separated by a predetermined distance from the center, and are formed at predetermined intervals along the longitudinal direction of the TAB tape in such an arrangement in the width B1 direction. Have been. Each hole 6a is formed in the reinforcing tape 6 in advance.
[0018]
By attaching the reinforcing tape 6 having the holes 6a to the lower surface of the insulating film 1, the warping of the TAB tape, which has conventionally been a problem, can be eliminated. The reason will be described.
[0019]
As shown in FIG. 2, in general, a curvature change 1 / R of a cantilever type bimetal in which two metal plates 11 and 12 are bonded can be represented by 1 / R ≒ 2D / L ² . Here, D is the tip deviation amount, and L is the length of the bent portion.
[0020]
As shown in FIG. 3A, in the configuration in which the copper layer 1 and the insulating film 2 are attached, the thickness ratio between the copper layer 1 (referred to as index 1) and the insulating film 2 (referred to as index 2) is determined. If m = h1 / h2, the elastic modulus ratio is n = E1 / E2, and the total thickness is h = h1 + h2, the curvature change is
1 / R = {6 (α1-α2) (1 + m) ² A} / h {3 (1 + m) ² + (1 + mn) (m ² + 1 / mn)}
It becomes. Here, α is a coefficient of thermal expansion, and A is a coefficient of thermal contraction.
[0021]
Here, it is assumed that the copper layer 1 has a thickness h = 8 μm, an elastic coefficient E = 80000, a thermal expansion coefficient α = 16 ppm / ° C., and a thermal shrinkage A = 0%. In addition, Kapton EN manufactured by Sumitomo Metal Mining was used for the insulating film 2. The Kapton EN layer 2 had a thickness h = 38 μm, an elastic coefficient E = 5000, a thermal expansion coefficient α = 16 ppm / ° C., and a thermal shrinkage rate A = −. Assume that it is 0.02%.
[0022]
In this case, the distortion thermal stress σ due to the thermal contraction of both 1 and 2 is
σ1 = E1 (ε-A1 × B)
σ2 = E2 (ε-A2 × B)
It becomes. Here, ε is the thermal expansion amount, and B is the tape width.
[0023]
As shown in FIG. 3B, in the case of the above characteristics, since the Kapton EN layer 2 is extremely small as the heat shrinkage A = −0.02%, it shrinks by heating and slightly warps.
[0024]
On the other hand, as shown in FIG. 4A, when a non-perforated reinforcing tape 16 is attached to the lower surface of the Kapton EN layer 2, the reinforcing tape 16 has a thickness h = 57 μm, an elastic coefficient E = 4000, thermal expansion coefficient α = 17 ppm / ° C., and thermal shrinkage A = −2.0%. However, in this case, since the same characteristics of the copper layer 1 and the Kapton EN layer 2 as described above are close to each other, they are considered to be integrated. In this case, as shown in FIG. 4B, since the reinforcing tape 16 has a large thermal shrinkage A of -2.0%, the reinforcing tape 16 contracts by heating and is excessively warped.
[0025]
In this case, if the reinforcing tape 6 shown in FIG. 1 is the reinforcing tape 16 having no hole 6a, the reinforcing tape substantial width B2 is the same as the tape width B1, so that the entire TAB tape is warped (curvature ratio). ) Is B2 / B1 = 1.0.
[0026]
Further, the reinforcing tape 6 having the holes 6a shown in FIG. 1, wherein the reinforcing tape substantial width B2 = B2a + B2b + B2c + B2d obtained by subtracting the length of the hole 6a from the tape width B1 on a substantially straight line in the tape width direction, If it is 50% of the whole, the warpage of the entire TAB tape becomes as small as B2 / B1 = 0.5.
[0027]
If the reinforcing tape substantial width B2 is 40% of the whole, the warpage of the entire TAB tape is as small as B2 / B1 = 0.4. Assuming that the substantial width B2 of the reinforcing tape is 20% of the whole, the warpage of the entire TAB tape is further reduced to B2 / B1 = 0.2.
[0028]
From this, as shown in FIG. 5A, even when a part of the copper layer 1 is lost when the copper layer 1 is etched to form the copper wiring pattern layer 1a, the lower part or the lower part of the lost area. If there is a hole 6a in the vicinity area, it is the same as the absence of the reinforcing tape 6 below or below the vicinity area, so that the balance of the forces acting between the layers of the TAB tape is not lost, and the TAB tape is warped. Will not occur.
[0029]
Further, as shown in FIG. 5B, a thermosetting solder resist 5 is formed on the copper wiring pattern layer 1a and the insulating film 2 via the tin plating layer 4, and the solder resist 5 is cured by heat treatment. Conventionally, warpage due to heat has occurred. However, in the present embodiment, as described above, since the holes 6a exist below or in the vicinity of the region where the copper layer 1 has been partially removed by the etching, the balance of the force acting between the layers of the TAB tape is thermal. As a result, the TAB tape does not warp.
[0030]
Therefore, the yield in transporting the TAB tape to the next step can be improved, and the work efficiency of the TAB tape processing in the next step and the dimensional quality of the TAB tape can be improved.
[0031]
Further, it is preferable that the reinforcing tape 6 has heat resistance that does not deform at 180 ° C. × 2 hours or more. This is because the solder resist 5 can withstand the heat treatment.
[0032]
The thickness of the copper layer 1 is preferably 0.2 μm to 25 μm. The reason for this is that, in the insulating film 2 with Cu having a two-layer structure, the thickness of the copper layer 1 of 0.2 μm is the minimum film thickness by sputtering. Further, the thickness of 25 μm is the limit of forming a fine wiring pitch of 60 μm (copper wiring width: 30 μm, space: 30 μm). When the thickness is 25 μm or more, when forming a fine wiring pitch of 60 μm, defects such as chipping, thinning, and thickening of the wiring are small, and it is impossible to form the wiring with good yield.
[0033]
Next, a first embodiment in which a TAB tape is actually formed based on such a principle will be described.
[0034]
38 μm thick Kapton EN manufactured by Sumitomo Metal Mining is used for the insulating film 2, 8 μm thick copper plated product is used for the copper layer 1, and FANUC 50 μm thick NT-50 (product name) is used for the reinforcing tape 6 Was used. It is assumed that each width is 540 mm.
[0035]
First, holes 6a were continuously formed in the reinforcing tape NT-50 using a mold as described above. Next, after a copper-plated product was bonded to Kapton EN using a roll laminator, a reinforcing tape NT-50 having a hole 6a was bonded to Kapton EN and cut to a width of 105 mm to be used.
[0036]
Next, a perforation hole is opened, a photoresist is coated and baked, then exposed and developed, and a copper plated product is etched to form a copper wiring pattern layer 1a, and tin plating for flip-chip connection of LSI is performed. gave. During the etching, no warping of the TAB tape occurred.
[0037]
Here, for the sake of comparison, as a result of performing the same processing using the reinforcing tape NT-50 having no hole 6a, the TAB tape was slightly warped, but could be conveyed to the next step.
[0038]
Next, after removing the photoresist, tin plating is baked to form a tin plating layer 4, a thermosetting solder resist 5 is applied by printing, and the solder resist 5 is heat-treated (150 ° C. × 1 hour). Cured. No warpage of the TAB tape occurred even in this heat treatment. As a result, the yield in transporting the TAB tape to the next step can be improved, and the work efficiency of the TAB tape processing in the next step and the dimensional quality of the TAB tape can be improved.
[0039]
On the other hand, in the case of using the reinforcing tape NT-50 in which the hole 6a for comparison was not formed, a cylindrical deformation occurred, and the transfer became impossible.
[0040]
Next, as a second embodiment, 25 μm Iupirex S manufactured by Sumitomo Metal Mining was used for the insulating film 2, a copper plated product having a thickness of 8 μm was used for the copper layer 1, and 50 μm manufactured by Kawamura Sangyo was used for the reinforcing tape 6. A heat resistant backing product name KT-508ZZ was used. It is assumed that each width is 540 mm.
[0041]
First, the holes 6a were continuously formed in the reinforcing tape KT-508ZZ using a mold as described above. Next, after a copper-plated product was bonded to Upilex S by a roll laminator, a reinforcing tape KT-508ZZ having a hole 6a was bonded to Upilex S, and cut to a width of 105 mm to be used.
[0042]
Next, a perforation hole was opened, a photoresist was coated, baked, exposed and developed, and a copper plated product was etched to form a copper wiring pattern layer 1a, which was tin-plated. During the etching, no warping of the TAB tape occurred.
[0043]
Here, for the sake of comparison, as a result of performing the same processing using the reinforcing tape NT-50 having no hole 6a, the TAB tape was warped, which adversely affected the transport to the next step.
[0044]
Next, after removing the photoresist, tin plating is baked to form a tin plating layer 4, a thermosetting solder resist 5 is applied by printing, and the solder resist 5 is heat-treated (150 ° C. × 1 hour). Cured. No warpage of the TAB tape occurred even in this heat treatment. As a result, the yield in transporting the TAB tape to the next step can be improved, and the work efficiency of the TAB tape processing in the next step and the dimensional quality of the TAB tape can be improved.
[0045]
On the other hand, in the case of using the reinforcing tape KT-508ZZ in which the hole 6a for comparison was not formed, the cylindrical shape was deformed, and the conveyance became impossible.
[0046]
As another application example, as shown in FIG. 6, even if a reinforcing tape 6 in which holes 6b and 6c having large and small elliptical diameters are randomly opened is used, the same effect as in the above embodiment can be obtained.
[0047]
When the copper wiring pattern layer 1a is left near the perforation hole 8 of the TAB tape as shown in FIGS. 7A and 7B, the copper wiring pattern is formed as shown in FIGS. 7C and 7D. In the case where the pattern layer 1a is not left, the same effect as in the above embodiment can be obtained in any case.
[0048]
【The invention's effect】
As described above, according to the present invention, in a tape carrier for a semiconductor device in which a copper layer for forming a copper wiring pattern is formed on an insulating film, a through hole is formed on a lower surface of the insulating film. The formed reinforcing tape was stuck. A plurality of holes were arranged on a substantially straight line along the tape width, and were arranged below or in the vicinity of the region where a part of the copper layer was lost by patterning when forming the copper wiring pattern layer.
[0049]
Thereby, even if a part of the copper layer is lost when the copper layer is etched to form the copper wiring pattern, if there is a hole in the lower or lower vicinity area of the lost area, the lower or lower vicinity area may have a hole. Is the same as the absence of the reinforcing tape, so that the balance of the forces acting between the layers of the tape is not lost, and the tape does not warp. In addition, when a thermosetting solder resist is formed on a copper wiring pattern and an insulating film via a tin plating layer, and the solder resist is cured by heat treatment, warpage due to heat has conventionally occurred. In the present invention, since holes are present below or in the vicinity of the region where a part of the copper layer has disappeared, the balance of the forces acting between the layers of the tape is not broken by heat, and the tape does not warp. Therefore, the yield in transporting the tape to the next step can be improved, and the work efficiency of tape processing in the next step and the dimensional quality of the tape can be improved.
[Brief description of the drawings]
1A and 1B show a configuration of a TAB tape according to an embodiment of the present invention, wherein FIG. 1A is a partial plan view between perforation holes of the TAB tape, and FIG. It is sectional drawing at the time of cutting.
FIG. 2 is a diagram for explaining a curvature change of a cantilever type bimetal in which two general metal plates are bonded together.
FIG. 3 is a diagram for explaining warpage of a TAB tape when a copper layer is formed on an insulating film.
FIG. 4 is a diagram for explaining warpage of a TAB tape when a reinforcing tape is stuck under an insulating film on which a copper layer is formed.
FIG. 5A is a cross-sectional view of a state in which a reinforcing tape having a plurality of holes formed below an insulating film on which a copper wiring pattern layer is formed is bonded, and FIG. FIG. 3 is a cross-sectional view when a tin plating layer is formed on a wiring pattern layer and a thermosetting solder resist is formed thereon.
FIG. 6 is a diagram showing a configuration of a TAB tape in which a reinforcing tape having large and small elliptical holes formed under an insulating film is adhered.
FIGS. 7A and 7B are diagrams showing a case where a copper layer is left near a perforation hole, and FIGS. 7C and 7D are diagrams showing a case where a copper layer is not left.
FIG. 8 is a cross-sectional view showing a configuration at the time of manufacturing a TAB tape to which a conventional reinforcing tape is attached.
FIG. 9 is a view for explaining warpage of a TAB tape when a conventional copper wiring pattern layer is formed and when a thermosetting solder resist is thermoset.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Copper layer 1a Copper wiring pattern layer 2 Insulating film 4 Tin plating layer 5 Thermosetting solder resist 3,6,16 Reinforcement tape 6a, 6b, 6c Hole 8 Perforation hole 11,12 Metal plate

Claims (6)

In a semiconductor device tape carrier in which a copper layer for forming a copper wiring pattern is formed on an insulating film,
A tape carrier for a semiconductor device, wherein a reinforcing tape having a through-hole is formed on a lower surface of the insulating film. The tape carrier for a semiconductor device according to claim 1, wherein a plurality of the holes are arranged on a substantially straight line along a tape width. 2. The semiconductor device tape according to claim 1, wherein the hole is arranged below or in a region near a region where a part of the copper layer has disappeared by patterning at the time of forming the copper wiring pattern. 3. Career. 2. The tape carrier for a semiconductor device according to claim 1, wherein the thickness of the copper layer is 0.2 μm to 25 μm. 3. 2. The tape carrier for a semiconductor device according to claim 1, wherein the reinforcing tape has heat resistance that does not deform at 180 ° C. × 2 hours or more. 3. 2. The tape carrier for a semiconductor device according to claim 1, wherein tin plating is applied on the copper wiring pattern.

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