JP2004179012A - Chip type surge absorber showing durability for long time in miniaturization - Google Patents
Chip type surge absorber showing durability for long time in miniaturization Download PDFInfo
- Publication number
- JP2004179012A JP2004179012A JP2002344760A JP2002344760A JP2004179012A JP 2004179012 A JP2004179012 A JP 2004179012A JP 2002344760 A JP2002344760 A JP 2002344760A JP 2002344760 A JP2002344760 A JP 2002344760A JP 2004179012 A JP2004179012 A JP 2004179012A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- chip
- trigger
- surge absorber
- discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】
【発明の属する技術分野】
この発明は、小寸化しても雷サージや異常電流による電撃に対してすぐれた耐久性を長期に亘って発揮するチップ型サージアブソーバに関するものである。
【０００２】
【従来の技術】
従来、一般に、電話機、ファクシミリ、およびモデムなどの通信機器用電子機器における通信線と接続する部分や、ＣＲＴ駆動回路などの雷サージや静電気などの異常電流（サージ電流）による電撃を受け易い部分に、これらを電気的損傷や熱的損傷、発火などの破壊から防止する目的でサージアブソーバが取りつけられている。
また、サージアブソーバには各種の構造のものが提案されているが、これらの中で、中央部に放電ギャップが形成されたトリガ電極と、前記トリガ電極の長さ方向両端部に連続して形成された主放電電極が内部に封入されたチップ本体の両側端部に、前記主放電電極と接続して端子電極を形成してなる構造のチップ型サージアブソーバが知られている（例えば、特許文献１、２参照）。
上記の構造のチップ型サージアブソーバにおいては、トリガ電極間にサージ電流が印加されると、放電ギャップ間で初期グロー放電がトリガされ（以下、トリガ放電という）、このトリガ放電がＡｒガスなどの放電制御ガスが封入された空間内を主放電電極まで瞬時に進展して、前記主放電電極間でグロー放電、アーク放電することにより前記サージ電流が吸収されるものであり、したがって前記トリガ電極は前記サージ電流の印加によって強い電撃（トリガ放電）に曝されることになる。
【０００３】
【特許文献１】
特開２００１−０３５６３３号公報
【特許文献２】
特開２００１−０３５６３４号公報
【０００４】
【発明が解決しようとする課題】
一方、近年の通信機器用電子機器に対するさらに一段の小型化および軽量化の要求は強く、これに伴い、これに組み込まれるサージアブソーバにも小寸化が強く求められているが、上記の従来チップ型サージアブソーバの場合、これを小寸化すればするほどトリガ電極の放電ギャップ間での初期トリガ放電面積、すなわちトリガ電極の放電ギャップ間の対向面積（幅および厚さ）が小さくなり、この結果前記放電ギャップ間におけるサージ電流によって発生する電撃（トリガ放電）が一段と烈しくなり、この強いトリガ放電によって放電ギャップ形状が短時間で著しく変形する結果、極端な場合には短絡・導通してしまう等してサージ電流の吸収を満足に行なうことができなくなり、比較的短時間で使用寿命に至るのが現状である。
【０００５】
【課題を解決するための手段】
そこで、本発明者等は、上述のような観点から、特にトリガ電極の放電ギャップ形状がサージ電流によって発生する電撃（トリガ放電）に対して、すぐれた耐久性を長期に亘って発揮するチップ型サージアブソーバを開発すべく研究を行った結果、チップ型サージアブソーバのチップ本体を酸化アルミニウム（以下、Ａｌ２Ｏ３で示す）で構成すると共に、トリガ電極および主放電電極を、いずれも化学蒸着形成された、窒化チタン（以下、ＴｉＮで示す）の導電性薄層とＡｌ２Ｏ３の保護薄層の一体積層で構成すると、前記ＴｉＮ薄層は、高い導電性を有し、かつ高融点高硬度を有することから、放電に対してきわめて安定した特性を発揮し、このＴｉＮ薄層のもつすぐれた特性は、導電性がないので放電による影響を全く受けず、さらに化学的熱的安定性にすぐれ、かつ高温硬さおよび耐熱性にもすぐれたＡｌ２Ｏ３薄層の一体積層によって保護され、さらに前記ＴｉＮ薄層の前記Ａｌ２Ｏ３薄層およびＡｌ２Ｏ３製チップ本体に対する高い密着性と相俟って、トリガ電極の放電ギャップ形状がサージ電流で発生するトリガ放電によってほとんど影響されることがなくなり、この現象は小寸化によっても変らず維持され、この結果放電ギャップ形状の経時的変形が著しく小さなものとなり、前記放電ギャップ間に安定した初期トリガ放電が確保されるようになることから、変らぬアーク放電特性が保持され、長期に亘っての使用が可能となる、という研究結果を得たのである。
【０００６】
この発明は、上記の研究結果に基づいてなされたものであって、
中央部に電極長手方向に対して直角方向に放電ギャップが形成されたトリガ電極と、前記トリガ電極の長さ方向両端部に連続して形成された主放電電極が内部に封入されたチップ本体の両側端部に、前記主放電電極と接続して端子電極を形成してなるチップ型サージアブソーバにおいて、
上記チップ本体をＡｌ２Ｏ３で構成すると共に、上記トリガ電極および主放電電極を、いずれも化学蒸着形成された、ＴｉＮの導電性薄層、望ましくは０．０１〜１０μｍ、さらに望ましくは０．１〜１μｍの平均層厚を有するＴｉＮの導電性薄層と、Ａｌ２Ｏ３の保護薄層、望ましくは０．０１〜０．５μｍ、さらに望ましくは０．０２〜０．１μｍの平均層厚を有するＡｌ２Ｏ３の保護薄層の一体積層で構成してなる、小寸化にもすぐれた耐久性を長期に亘って発揮するチップ型サージアブソーバに特徴を有するものである。
【０００７】
【発明の実施の形態】
つぎに、この発明のチップ型サージアブソーバを実施例により具体的に説明する。
図１，２に製造工程（ａ）〜（ｉ）［ただし、図１の（ａ）〜（ｅ）は単位区画を示す］が概略斜視図で示される通り、
（１）それぞれ表１に示される純度、並びに横：６０ｍｍ×縦：４９．５ｍｍ×厚さ：０．５ｍｍの全体寸法、さらにＲａ：０．３μｍの表面粗さを有し、かつ表面が細溝により横：３．０ｍｍ×縦：１．４８ｍｍの寸法で区画（単位区画という）されたＡｌ２Ｏ３製基板素材を用意する。
（２）上記基板素材を、アセトン中で超音波洗浄し、乾燥した状態で、通常の化学蒸着装置に装入し、
ガス組成−容量％で、ＴｉＣｌ４：４％、Ｎ２：４０％、Ｈ２：残り、
反応雰囲気温度：１０００℃、
反応雰囲気圧力：２０ｋＰａ、
の条件で、図１（ａ）に示される通り、全面にＴｉＮからなり、かつそれぞれ表１に示される平均層厚を有する導電性薄層を蒸着形成する。
（３）同じく上記の化学蒸着装置にて、上記導電性薄層の表面に、
ガス組成−容量％で、ＡｌＣｌ３：２％、ＣＯ２：６％、ＨＣｌ：２％、Ｈ２：残り、
反応雰囲気温度：１０００℃、
反応雰囲気圧力：５ｋＰａ、
の条件で、図１（ｂ）に示される通り、Ａｌ２Ｏ３からなり、かつそれぞれ表１に示される平均層厚を有する保護薄層を一体積層形成する。
（４）上記の導電性薄層と保護薄層の一体積層にマスキングを施し、アンモニア（ＮＨ４）と過酸化水素水（Ｈ２Ｏ２）の質量比で１：１のエッチング液を用い、前記エッチング液を８５℃に加熱した状態で、基板素材に対してエッチング処理を行うことにより前記一体積層を図１（ｃ）に示される形状とする。
（５）図１（ｄ）に示される通り、レーザー刻印装置を用いて、上記のエッチング処理後の導電性薄層と保護薄層の一体積層の中央部に、同じく表１に示される寸法の放電ギャップを形成する。
（６）単位区画毎に取り付けられるＡｌ２Ｏ３製蓋材の取り付け位置に、ガラスペーストを用いて、スクリーン印刷により図１（ｅ）に示される形状に３０μｍの厚さで印刷し、ついで温度：１５０℃に１０分間保持して乾燥した後、温度：５５０℃に１０分間保持の条件で焼成を行なって接着用ガラス枠を形成する。
（７）上記の単位区画毎に、それぞれトリガ電極および主放電電極と同じ作用を有する導電性薄層と保護薄層の一体積層、放電ギャップ、および接着用ガラス枠を形成したＡｌ２Ｏ３製基板素材を区分細溝に沿って分割して図２（ｆ）に示される基板素子とする。
（８）図２（ｇ）に示される通り、上記の基板素子に、９７質量％の純度を有するＡｌ２Ｏ３製蓋材を載置し、Ａｒ雰囲気で、温度：５５０℃に１０分間保持し、接着用ガラス枠溶融による封止を行い、さらに図２（ｈ）に示される通り、研削加工を施して、チップ本体を形成する。
（９）図２（ｉ）に示される通り、上記のチップ本体の長さ方向両端部に、Ａｇ粉末ペーストを用いて、２０μｍの厚さに塗布した後、温度：５５０℃に１０分間保持の条件で焼成して、端子電極を形成する。
以上（１）〜（９）の工程により本発明チップ型サージアブソーバ（以下、本発明サージアブソーバという）１〜１０をそれぞれ製造した。
【０００８】
また、比較の目的で、図３，４に製造工程（ａ´）〜（ｉ´）［ただし、図１の（ａ´）〜（ｅ´）は単位区画を示す］が概略斜視図で示される通り、
（１）それぞれ表１に示される純度、並びに横：６０ｍｍ×縦：４９．５ｍｍ×厚さ：０．５ｍｍの全体寸法、さらにＲａ：０．３μｍの表面粗さを有し、かつ表面が細溝により１区画（単位区画）が横：３．０ｍｍ×縦：１．４８ｍｍの寸法に区分されたＡｌ２Ｏ３製基板素材を用意する。
（２）上記基板素材表面に、Ａｇ−５質量％Ｐｄ合金粉末のペーストを用いてスクリーン印刷により図３（ａ´）に示される形状に印刷し、ついで温度：１５０℃に１０分間保持して乾燥した後、温度：８５０℃に昇温して１０分間保持の条件で焼成を行い、それぞれ表２に示される平均層厚の１次主放電電極を単位区画毎に形成する。
（３）両側部にそれぞれ形成された上記の１次主放電電極に接続（ブリッジ）して、中央部に純度：９９質量％のＡｌ粉末のペーストを用いてスクリーン印刷により図３（ｂ´）に示される形状に印刷し、ついで同じく温度：１５０℃に１０分間保持後、温度：６１０℃に１０分間保持の条件で焼成して、同じく表２に示される平均層厚のトリガ電極を形成する。
（４）上記１次主放電電極に重ねて、同じくＡｇ−０．５質量％Ｐｄ合金粉末のペーストを用いてスクリーン印刷により図３（ｃ´）に示される形状に印刷し、ついで温度：１５０℃に１０分間保持後、温度：５５０℃に１０分間保持の条件で焼成して、同じく表２に示される平均層厚の２次主放電電極を形成する。
（５）レーザー刻印装置を用いて、図３（ｄ´）に示される上記トリガ電極の中央部に、同じく表２に示される寸法の放電ギャップを形成する。
（６）単位区画毎に取り付けられるＡｌ２Ｏ３製蓋材の取り付け位置に、ガラスペーストを用いて、スクリーン印刷により図３（ｅ´）に示される形状に３０μｍの厚さで印刷し、ついで温度：１５０℃に１０分間保持後、温度：５５０℃に１０分間保持の条件で焼成を行なって接着用ガラス枠を形成する。
（７）上記の単位区画毎に、それぞれ１次主放電電極、トリガ電極、２次主放電電極、放電ギャップ、および接着用ガラス枠を形成したＡｌ２Ｏ３製基板素材を区分細溝に沿って分割して図４（ｆ´）に示される基板素子とする。
（８）図４（ｇ´）に示される通り、上記の基板素子に、９７質量％の純度を有するＡｌ２Ｏ３製蓋材を載置し、Ａｒ雰囲気で、温度：５５０℃に１０分間保持し、接着用ガラス枠溶融による封止を行い、さらに図４（ｈ´）に示される通り、研削加工を施して、チップ本体を形成する。
（９）上記のチップ本体の長さ方向両端部の図４（ｉ´）に示される個所を、Ａｇ粉末ペーストを用いて、塗布した後、温度：５５０℃に１０分間保持の条件で焼成して、厚さ：２０μｍの端子電極を形成する。
以上（１）〜（９）の工程より従来チップ型サージアブソーバ（以下、従来サージアブソーバという）１〜１０をそれぞれ製造した。
【０００９】
ついで、この結果得られた本発明サージアブソーバ１〜１０および従来サージアブソーバ１〜１０の耐久性を評価する目的で、これをそれぞれサージ発生装置に装着し、前記サージ発生装置の容量、抵抗、および電圧を、それぞれ容量：５００μＦ、抵抗：１００Ω、電圧：２５ｋＶとした条件で、前記サージアブソーバに繰り返しのアーク放電を発生させ、１０回のサージ電流印加毎に前記サージアブソーバの放電開始電圧を測定し、前記繰り返しのサージ電流印加後のサージアブソーバの放電開始電圧が１５０Ｖに低下するに至る迄のアーク放電回数を測定した。これらの測定結果をサージアブソーバ：１０個の平均値で表１，２に示した。
【００１０】
【表１】
【表２】
【発明の効果】
表１，２に示される結果から、本発明サージアブソーバ１〜１０は、いずれも小寸化によって放電ギャップの寸法、すなわち放電ギャップにおける導電性薄層の対向面積（幅および厚さ）が小さくなっても、長期に亘って安定した初期トリガ放電を示し、サージ印加回数が２００回を越えても放電開始電圧が１５０Ｖを下回らないのに対して、従来サージアブソーバ１〜１０は、これを小寸化、すなわち放電ギャップの寸法が小さくなればなるほど、強いトリガ放電によって放電ギャップ形状が短期間で著しく変形し、サージ電流の吸収を満足に行なうことができなくなることから、サージ印加回数１００回未満で使用寿命に至ることが明かである。
上述のように、この発明のチップ型サージアブソーバは、従来チップ型サージアブソーバにおけるトリガ電極および主放電電極を、いずれも化学蒸着形成された、ＴｉＮの導電性薄層とＡｌ２Ｏ３の保護薄層の一体積層で構成することにより、小寸化しても放電ギャップ形状の経時的変形がきわめて少なく、前記放電ギャップ間に安定した初期トリガ放電が確保され、すぐれた耐久性を長期に亘って発揮するものであるから、各種の通信機器用電子機器の一段の小型化および軽量化に寄与するものである。
【図面の簡単な説明】
【図１】本発明チップ型サージアブソーバの製造工程（ａ）〜（ｉ）の前半工程（ａ）〜（ｅ）を単位区画で示す概略斜視図である。
【図２】本発明チップ型サージアブソーバの製造工程（ａ）〜（ｉ）の後半工程（ｆ）〜（ｉ）を示す概略斜視図である。
【図３】従来チップ型サージアブソーバの製造工程（ａ´）〜（ｉ´）の前半工程（ａ´）〜（ｅ´）を単位区画で示す概略斜視図である。
【図４】従来チップ型サージアブソーバの製造工程（ａ´）〜（ｉ´）の後半工程（ｆ´）〜（ｉ´）を示す概略斜視図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip-type surge absorber that exhibits excellent durability over a long period against lightning surges and electric shocks caused by abnormal currents even if the size is reduced.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in general, a portion to be connected to a communication line in an electronic device for a communication device such as a telephone, a facsimile, and a modem, and a portion to be easily damaged by an abnormal current (surge current) such as a lightning surge or static electricity such as a CRT drive circuit. Surge absorbers are mounted for the purpose of preventing them from being damaged by electrical damage, thermal damage, fire, and the like.
In addition, various types of surge absorbers have been proposed. Among them, a trigger electrode having a discharge gap formed at the center and a trigger electrode formed continuously at both ends in the length direction of the trigger electrode are proposed. There is known a chip-type surge absorber having a structure in which terminal electrodes are formed by connecting the main discharge electrodes to both side ends of a chip body in which the main discharge electrodes are sealed (for example, see Patent Document 1). 1, 2).
In the chip-type surge absorber having the above structure, when a surge current is applied between the trigger electrodes, an initial glow discharge is triggered between discharge gaps (hereinafter, referred to as a trigger discharge), and this trigger discharge is caused by discharge of Ar gas or the like. The surge gas is instantaneously developed in the space filled with the control gas to the main discharge electrode, and the surge current is absorbed by glow discharge and arc discharge between the main discharge electrodes. The application of the surge current results in exposure to strong electric shock (trigger discharge).
[0003]
[Patent Document 1]
JP 2001-035633 A [Patent Document 2]
Japanese Patent Application Laid-Open No. 2001-035634
[Problems to be solved by the invention]
On the other hand, there is a strong demand for further downsizing and weight reduction of electronic devices for communication devices in recent years, and accordingly, there is a strong demand for downsizing of a surge absorber incorporated therein. In the case of the type surge absorber, the smaller the size, the smaller the initial trigger discharge area between the discharge gaps of the trigger electrode, that is, the area (width and thickness) between the discharge gaps of the trigger electrode, and as a result, The electric shock (trigger discharge) generated by the surge current between the discharge gaps is further increased, and the shape of the discharge gap is significantly deformed in a short time due to the strong trigger discharge. At present, it is impossible to satisfactorily absorb the surge current, and the service life is reached in a relatively short time.
[0005]
[Means for Solving the Problems]
In view of the above, the inventors of the present invention have developed a chip type that exhibits excellent durability over a long period of time, especially against electric shock (trigger discharge) in which the discharge gap shape of the trigger electrode is generated by a surge current. As a result of conducting research to develop a surge absorber, the chip body of the chip-type surge absorber was made of aluminum oxide (hereinafter, referred to as Al 2 O 3 ), and both the trigger electrode and the main discharge electrode were formed by chemical vapor deposition. When a thin layer of titanium nitride (hereinafter referred to as TiN) and a thin protective layer of Al 2 O 3 are integrally laminated, the thin layer of TiN has high conductivity and high melting point. Due to its hardness, it exhibits extremely stable characteristics against electric discharge. The excellent characteristic of this thin TiN layer is not affected by electric discharge at all because it has no conductivity. The excellent chemical and thermal stability, and also protected by integral lamination of good Al 2 O 3 thin layer high temperature hardness and heat resistance, further the Al 2 O 3 thin layer of the TiN thin layer and Al 2 O I 3 made chip high adhesion coupled with respect to the body, no longer to be most affected by the trigger discharge the discharge gap shape of the trigger electrode is generated in a surge current, this phenomenon will be maintained did not vary by small Sunka As a result, the time-dependent deformation of the discharge gap shape becomes extremely small, and a stable initial trigger discharge is secured between the discharge gaps. The research results show that it can be used.
[0006]
The present invention has been made based on the above research results,
A trigger electrode in which a discharge gap is formed in a central portion in a direction perpendicular to the electrode longitudinal direction, and a main body of a chip in which a main discharge electrode formed continuously at both ends in the longitudinal direction of the trigger electrode are enclosed. In both ends, a chip-type surge absorber formed by connecting to the main discharge electrode to form a terminal electrode,
The chip body is made of Al 2 O 3 , and the trigger electrode and the main discharge electrode are both formed by chemical vapor deposition. A thin conductive layer of TiN, preferably 0.01 to 10 μm, and more preferably 0.1 to 10 μm. A conductive thin layer of TiN having an average layer thickness of 1 to 1 μm and a protective thin layer of Al 2 O 3 , preferably 0.01 to 0.5 μm, more preferably 0.02 to 0.1 μm This is characterized by a chip-type surge absorber that is formed by integrally laminating a protective thin layer of Al 2 O 3 having the following characteristics and that exhibits excellent durability over a long period of time even in miniaturization.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the chip-type surge absorber of the present invention will be specifically described with reference to examples.
1 and 2, manufacturing steps (a) to (i) [however, (a) to (e) in FIG. 1 indicate a unit section] are shown in schematic perspective views,
(1) Purity shown in Table 1 and overall dimensions of width: 60 mm × length: 49.5 mm × thickness: 0.5 mm, Ra: surface roughness of 0.3 μm, and fine surface A substrate material made of Al 2 O 3 is prepared which is sectioned by a groove (unit: section) with a size of 3.0 mm in width × 1.48 mm in length.
(2) The above-mentioned substrate material is ultrasonically cleaned in acetone, and in a dried state, charged into a normal chemical vapor deposition apparatus;
Gas composition - in volume%, TiCl 4: 4%, N 2: 40%, H 2: remainder,
Reaction atmosphere temperature: 1000 ° C.
Reaction atmosphere pressure: 20 kPa,
Under the condition (1), as shown in FIG. 1 (a), a conductive thin layer composed entirely of TiN and having an average layer thickness shown in Table 1 is formed by vapor deposition.
(3) Similarly, on the surface of the conductive thin layer,
Gas composition - in volume%, AlCl 3: 2%, CO 2: 6%, HCl: 2%, H 2: remainder,
Reaction atmosphere temperature: 1000 ° C.
Reaction atmosphere pressure: 5 kPa,
As shown in FIG. 1 (b), a protective thin layer made of Al 2 O 3 and having an average layer thickness shown in Table 1 is integrally laminated under the conditions (1) and ( 2 ).
(4) Masking is performed on the integrated lamination of the conductive thin layer and the protective thin layer, and an etching solution having a mass ratio of ammonia (NH 4 ) and hydrogen peroxide solution (H 2 O 2 ) of 1: 1 is used. While the etching solution is heated to 85 ° C., an etching process is performed on the substrate material to form the integrated laminate into the shape shown in FIG.
(5) As shown in FIG. 1 (d), using a laser engraving device, the conductive thin layer and the protective thin layer after the above-described etching treatment were placed at the center of the integrally laminated layer having the dimensions shown in Table 1 also. A discharge gap is formed.
(6) A glass paste is used to screen-print the shape shown in FIG. 1 (e) with a thickness of 30 μm on the mounting position of the Al 2 O 3 lid material mounted on each unit section, and then temperature. After holding at 150 ° C. for 10 minutes and drying, baking is performed under the condition of holding at a temperature of 550 ° C. for 10 minutes to form an adhesive glass frame.
(7) For each of the above-described unit sections, an integrated laminate of a conductive thin layer and a protective thin layer each having the same action as the trigger electrode and the main discharge electrode, a discharge gap, and an Al 2 O 3 formed with a bonding glass frame are formed. The substrate material is divided along the narrow section grooves to obtain the substrate element shown in FIG.
(8) As shown in FIG. 2 (g), a cover made of Al 2 O 3 having a purity of 97% by mass is placed on the above-mentioned substrate element, and the temperature is kept at 550 ° C. for 10 minutes in an Ar atmosphere. Then, sealing is performed by melting the glass frame for bonding, and further, as shown in FIG. 2 (h), grinding is performed to form a chip body.
(9) As shown in FIG. 2 (i), an Ag powder paste was applied to both ends of the chip body in the longitudinal direction to a thickness of 20 μm, and then kept at a temperature of 550 ° C. for 10 minutes. By firing under the conditions, a terminal electrode is formed.
The chip-type surge absorbers of the present invention (hereinafter, referred to as surge absorbers of the present invention) 1 to 10 were manufactured by the above steps (1) to (9).
[0008]
For the purpose of comparison, FIGS. 3 and 4 show manufacturing steps (a ′) to (i ′) (where (a ′) to (e ′) in FIG. 1 indicate unit sections) in schematic perspective views. As you can see,
(1) Purity shown in Table 1 and overall dimensions of width: 60 mm × length: 49.5 mm × thickness: 0.5 mm, Ra: surface roughness of 0.3 μm, and fine surface An Al 2 O 3 substrate material is prepared in which one section (unit section) is divided by the groove into a dimension of 3.0 mm in width × 1.48 mm in length.
(2) Using the paste of Ag-5 mass% Pd alloy powder on the surface of the above-mentioned substrate material, screen printing was used to print the shape shown in FIG. 3 (a '), and then the temperature was kept at 150 [deg.] C. for 10 minutes. After drying, firing is performed under the condition of raising the temperature to 850 ° C. and holding for 10 minutes to form a primary main discharge electrode having an average layer thickness shown in Table 2 for each unit section.
(3) Connected (bridged) to the primary main discharge electrodes formed on both sides, respectively, and screen printed using a paste of Al powder having a purity of 99% by mass at the center by screen printing (FIG. 3B ′). And then fired at the same temperature: 150 ° C. for 10 minutes and then fired at the temperature: 610 ° C. for 10 minutes to form a trigger electrode having the average layer thickness also shown in Table 2. .
(4) Overlaid on the primary main discharge electrode, printed in the shape shown in FIG. 3 (c ') by screen printing using the same paste of Ag-0.5 mass% Pd alloy powder, and then temperature: 150 After holding at 10 ° C. for 10 minutes, baking is performed under the condition of holding at a temperature of 550 ° C. for 10 minutes to form a secondary main discharge electrode having an average layer thickness also shown in Table 2.
(5) Using a laser marking device, a discharge gap having the same dimensions as shown in Table 2 is formed at the center of the trigger electrode shown in FIG.
(6) Using a glass paste, screen printing is used to print the shape shown in FIG. 3 (e ') with a thickness of 30 μm at the mounting position of the Al 2 O 3 lid material mounted for each unit section, and then. After holding at a temperature of 150 ° C. for 10 minutes, baking is performed at a temperature of 550 ° C. for 10 minutes to form a bonding glass frame.
(7) For each of the above-mentioned unit sections, the primary main discharge electrode, the trigger electrode, the secondary main discharge electrode, the discharge gap, and the substrate material made of Al 2 O 3 on which the bonding glass frame is formed are formed along the narrow section grooves. To obtain a substrate element shown in FIG.
(8) As shown in FIG. 4 (g ′), a lid member made of Al 2 O 3 having a purity of 97% by mass is placed on the above substrate element, and the temperature is set to 550 ° C. for 10 minutes in an Ar atmosphere. The chip body is held, sealed by melting the glass frame for bonding, and further subjected to a grinding process as shown in FIG. 4 (h ′) to form a chip body.
(9) The portions shown in FIG. 4 (i ') at both ends in the longitudinal direction of the chip body are applied using an Ag powder paste, and then baked at a temperature of 550 ° C. for 10 minutes. Then, a terminal electrode having a thickness of 20 μm is formed.
Conventional chip-type surge absorbers (hereinafter, referred to as conventional surge absorbers) 1 to 10 were manufactured from the above steps (1) to (9).
[0009]
Then, for the purpose of evaluating the durability of the
[0010]
[Table 1]
[Table 2]
【The invention's effect】
From the results shown in Tables 1 and 2, in each of the
As described above, in the chip-type surge absorber of the present invention, the trigger electrode and the main discharge electrode in the conventional chip-type surge absorber are both formed by chemical vapor deposition to form a conductive thin layer of TiN and a protective layer of Al 2 O 3 . Even if the size is reduced, deformation of the discharge gap shape with the passage of time is extremely small, so that a stable initial trigger discharge is secured between the discharge gaps, and excellent durability is exhibited over a long period of time. Therefore, it contributes to further reduction in size and weight of electronic devices for various communication devices.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view showing, in unit sections, first half steps (a) to (e) of manufacturing steps (a) to (i) of a chip type surge absorber of the present invention.
FIG. 2 is a schematic perspective view showing the second half of steps (f) to (i) of the steps (a) to (i) for manufacturing the chip type surge absorber of the present invention.
FIG. 3 is a schematic perspective view showing, in unit sections, first half steps (a ′) to (e ′) of manufacturing steps (a ′) to (i ′) of a conventional chip-type surge absorber.
FIG. 4 is a schematic perspective view showing the latter half steps (f ′) to (i ′) of the manufacturing steps (a ′) to (i ′) of the conventional chip type surge absorber.
Claims (1)
上記チップ本体を酸化アルミニウムで構成すると共に、上記トリガ電極および主放電電極を、いずれも化学蒸着形成された、窒化チタンの導電性薄層と酸化アルミニウムの保護薄層の一体積層で構成したこと、
を特徴とする小寸化にもすぐれた耐久性を長期に亘って発揮するチップ型サージアブソーバ。A trigger body in which a discharge gap is formed at a central portion in a direction perpendicular to the electrode longitudinal direction, and a chip body in which a main discharge electrode formed continuously at both ends in the longitudinal direction of the trigger electrode are enclosed. In both ends, a chip-type surge absorber formed by connecting to the main discharge electrode to form a terminal electrode,
The chip body is made of aluminum oxide, and the trigger electrode and the main discharge electrode are both formed by chemical vapor deposition, and are formed by integrally laminating a conductive thin layer of titanium nitride and a protective thin layer of aluminum oxide.
A chip-type surge absorber that exhibits excellent durability over a long period of time, even in miniaturization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002344760A JP4122510B2 (en) | 2002-11-28 | 2002-11-28 | Chip-type surge absorber with long-lasting durability with excellent miniaturization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002344760A JP4122510B2 (en) | 2002-11-28 | 2002-11-28 | Chip-type surge absorber with long-lasting durability with excellent miniaturization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004179012A true JP2004179012A (en) | 2004-06-24 |
| JP4122510B2 JP4122510B2 (en) | 2008-07-23 |
Family
ID=32706110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002344760A Expired - Fee Related JP4122510B2 (en) | 2002-11-28 | 2002-11-28 | Chip-type surge absorber with long-lasting durability with excellent miniaturization |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4122510B2 (en) |
-
2002
- 2002-11-28 JP JP2002344760A patent/JP4122510B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP4122510B2 (en) | 2008-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7570473B2 (en) | Surge absorber | |
| JP4140173B2 (en) | Chip-type surge absorber and manufacturing method thereof | |
| CN101015101A (en) | Surge absorber | |
| JP3528655B2 (en) | Chip type surge absorber and method of manufacturing the same | |
| US7733622B2 (en) | Surge absorber and production method therefor | |
| JP4122510B2 (en) | Chip-type surge absorber with long-lasting durability with excellent miniaturization | |
| JP2007317541A (en) | Surge suppressor | |
| JP4544255B2 (en) | Electronic component enclosure | |
| TW478229B (en) | Chip type surge absorbing device and its manufacturing method | |
| JP5304997B2 (en) | surge absorber | |
| JP4292935B2 (en) | Chip-type surge absorber and manufacturing method thereof | |
| JP2005251458A (en) | Chip type surge absorber, and manufacturing method of the same | |
| JP7320198B2 (en) | Surge protective element and manufacturing method thereof | |
| JP3508565B2 (en) | Chip type surge absorber and method of manufacturing the same | |
| JP3596266B2 (en) | Nonlinear dielectric element | |
| JP2615221B2 (en) | Gas input / discharge arrester | |
| JP4363180B2 (en) | surge absorber | |
| JP2006049064A (en) | Surge absorber | |
| JP3777886B2 (en) | Chip type surge absorber (1) | |
| JP3969098B2 (en) | surge absorber | |
| JP5218769B2 (en) | surge absorber | |
| JP4265321B2 (en) | surge absorber | |
| JP4123981B2 (en) | Chip-type surge absorber and manufacturing method thereof | |
| JP4407259B2 (en) | Surge absorber and manufacturing method thereof | |
| JP3777885B2 (en) | Chip type surge absorber (2) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050318 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071214 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080123 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080407 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080420 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110516 Year of fee payment: 3 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080123 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110516 Year of fee payment: 3 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110516 Year of fee payment: 3 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110516 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120516 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120516 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130516 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130516 Year of fee payment: 5 |
|
| LAPS | Cancellation because of no payment of annual fees |