JP2004173081A - A/d conversion circuit, a/d conversion control method, and a/d conversion program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion circuit, an A/D conversion control method, and an A/D conversion program, which can increase the number of effective bits. <P>SOLUTION: A clock signal generation circuit 1 generates a clock signal with a frequency f<SB>S</SB>, which is used as a reference signal at PLL (2), where the frequency f<SB>S</SB>is increased n times to be f<SB>R</SB>to make a reference signal R(t) synchronous in phase with the reference signal and send it out. An adder 3 adds a received signal I(t) to the reference signal R(t). An A/D converter 5 receives an added signal X(t) and the clock signal with the frequency f<SB>S</SB>, sampling the signal X(t) at the sampling frequency f<SB>S</SB>and holding the sampled signal. A jitter detecting section 7 receives a digital signal Rk, calculating aperture times and sending them out. A no-uniform sampling BRF(8) receives a digital signal xk and aperture times input, calculates filter factors, filters the digital signal xk by means of non-uniform sampling to eliminate interference waves, thus outputs a desired signal wave. <P>COPYRIGHT: (C)2004,JPO

Description

ただし、式（１）において
・Ａ_０は参照信号Ｒ（ｔ）の振幅より算出可
・ｆ_Ｒ／ｆ_ｓ＝ｎ
・τｋは瞬時変動（平均値０のガウス分布に近似可）
であることから、ジッタ検出部７は、τ_ｋの平均化（狭域帯フィルタ）によりτ_ｋ→０となることからφ０を算出し、さらに、この算出したφ０を式（１）に代入して、各ｋに対するアパーチャ時間τ_ｋを算出する。また同様にしてτ_{ｋー ｐ}を算出する。
【００２０】
不均一サンプリングＢＰＦ・８は、ＡＤＣ・５、ジッタ検出部７と接続されており、ＡＤＣ・５が出力したデジタル信号ｘｋ及びジッタ検出部７が出力したＮ個のアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）の入力を受けて、アパーチャ時間τ_{ｋー ｐ}（ｐ≠０）、τ_ｋに基づいて、フィルタ係数ｈ_０〜ｈ_ｐを算出し、これらのフィルタ係数をセットして、デジタル信号ｘｋに対して、不均一サンプリングを行い、参照信号Ｒ（ｔ）を含む干渉波を除去し希望波ｙｋを出力する。
ここで、フィルタ係数ｈ_ｐは次式（２）より求められる。
【数２】

ただし、式（２）においてｈは既知のフィルタ係数である。
【００２１】
デジタル信号ｘｋは次式（３）で表される。
【数３】

ただし、式（３）においてｘは、既知の信号値である。これら算出されたフィルタ係数とデジタル信号ｘｋとを畳み込むと希望波ｙｋは次式（４）で表される。
【数４】

【００２２】
不均一サンプリングＢＰＦ・８は、具体的には例えば図２に示すように、ｐ個の遅延素子Ｄｔ−１〜Ｄｔ−ｐと（ｐ＋１）個の乗算器１０−０〜乗算器１０−ｐ、加算器１１、ＲＡＭ１２、フィルタ係数演算部１３から構成される。
乗算器１０−０は、不均一サンプリングＢＰＦ・８のＡＤＣ・５側の入力端子、加算器１１と接続されており、ＡＤＣ・５からのデジタル信号ｘｋとフィルタ係数ｈ０（フィルタ係数演算部１３が各サンプル毎に上述の式に基づいて算出し、ＲＡＭ１２に書き込んだフィルタ係数ｈ_０が乗算器１０−０に毎回セットされる。）とを乗算して、加算器１１に出力する。
【００２３】
また乗算器１０−ｉ（１≦ｉ≦ｐ）は、遅延素子Ｄｔ−ｉ、加算器１１と接続されており、遅延素子Ｄｔ−ｉのデジタル信号ｘ_ｋ−ｉとフィルタ係数ｈ_ｉとを乗算して、加算器１１に出力する。ここで、フィルタ係数ｈ_ｉはフィルタ係数演算部１３が各サンプル毎に上述の式に基づいて算出し、この算出値がＲＡＭ１２に書き込まれて、フィルタ係数ｈ_ｉが乗算器１０−ｉに毎回セットされる。
【００２４】
遅延素子Ｄｔ−１は、不均一サンプリングＢＰＦ・８のＡＤＣ・５側の入力端子、遅延素子Ｄｔ−２、乗算器１０−１と接続されており、ＡＤＣ・５からのデジタル信号ｘｋを所定時間だけ遅延させたデジタル信号ｘ_ｋー１を遅延素子Ｄｔ−２、乗算器１０−１に出力する。また。遅延素子Ｄ_ｔ−ｊ（２≦ｊ≦ｐー１）は、遅延素子Ｄ_{ｔ−ｊ−１}、遅延素子Ｄ_{ｔ−ｊ＋１}、乗算器１０−ｊと接続されており、遅延素子Ｄ_{ｔ−ｊ−１}からのデジタル信号ｘ_{ｋ−ｊ＋１}を所定時間だけ遅延させたデジタル信号ｘ_{ｋー ｊ}を遅延素子Ｄ_{ｔ−ｊ＋１}、乗算器１０−ｊに出力する。また。遅延素子Ｄ_ｔ−ｐは、遅延素子Ｄ_{ｔ−ｐ−１}、乗算器１０−ｐと接続されており、遅延素子Ｄ_{ｔ−ｐ−１}からのデジタル信号ｘ_{ｋー ｐ ＋１}を所定時間だけ遅延させたデジタル信号ｘ_ｋ−ｐを乗算器１０−ｊに出力する。
【００２５】
加算器１１は、入力されるｐ＋１個の加算信号ｈ_０ｘ_ｋ、ｈ_１ｘ_ｋ−１、…、ｈ_ｐｘ_ｋ―ｐをすべて加算した希望信号ｙｋを出力する。
ＲＡＭ１２は、半導体メモリ等の一時記憶部であって、フィルタ係数演算部１３が算出した乗算器１０−０〜乗算器１０−ｐにセットされるフィルタ係数ｈ_０〜ｈ_ｐが格納されている。なお、このフィルタ係数ｈ_０〜ｈ_ｐはワンサンプルごとにフィルタ係数演算部１３によって更新された値が書き込まれる。
フィルタ係数演算部１３は、アパーチャ時間τ_ｋ〜τ_{ｋー ｐ}の入力を受けて、上述の式によりアパーチャ時間τ_ｋ〜τ_{ｋー ｐ}ワンサンプルごとに、つまり各ｋに対してフィルタ係数ｈ_０〜ｈ_ｐを算出し、ＲＡＭ１２にこれを書き込む。
【００２６】
以下、本実施形態のＡ／Ｄ変換回路の動作について説明する。
アンテナにおいて受信された受信信号が本実施形態のＡ／Ｄ変換回路に入力されると、ＢＰＦ・４を経由して加算器３に受信信号Ｉ（ｔ）が入力される。
加算器３は、この受信信号Ｉ（ｔ）と、ＰＬＬ・２が出力した周波数ｆ_Ｒの参照信号Ｒ（ｔ）の入力を受けて、これら信号を加算し、加算信号Ｘ（ｔ）をＡＤＣ・５に出力する。
ＡＤＣ・５は、クロック信号発生回路１から出力された周波数ｆｓのクロック信号と加算器３から出力された加算信号Ｘ（ｔ）の入力を受けて、加算信号Ｘ（ｔ）をサンプリング周波数ｆｓで標本化し、標本化されたデジタル値を保持する。
次に、ＡＤＣ・５は、このデジタル値をデジタル信号ｘｋとしてＬＰＦ・６及び不均一サンプリングフィルタ８それぞれに出力する。ここで、Ａ／Ｄ変換後のデジタル信号ｘｋは周波数ｆ_Ｓのサンプリングクロックが、もともとアパーチャジッタによる誤差を含んでいるため、雑音が発生し、等価的にＡ／Ｄ変換のＥＮｏＢを劣化させる。
【００２７】
一方、このアパーチャジッタによる雑音は、各サンプル点が時間ずれτ_Ｋを持つ不均一サンプリングだと解釈すれば、雑音成分は生じていない。そこで、τ_Ｋを用いて、不均一サンプリングＢＰＦ・８のフィルタ係数を算出し、不均一サンプリングを行う。
すなわち、まずデジタル信号ｘｋは、ＬＰＦ・６において、デジタル信号Ｉｋが除去され、デジタル信号Ｒｋのみがジッタ検出部７に入力される。ジッタ検出部７は、デジタル信号Ｒｋの入力を受けて、上述の式（２）を用いて、デジタル信号Ｒｋと参照信号Ｒ（ｔ）の周波数ｆ_Ｒ又はクロック信号の周波数ｆｓからアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）をＮ個すべて算出し、不均一サンプリングＢＰＦ・８に出力する。
【００２８】
不均一サンプリングＢＰＦ・８は、ＡＤＣ・５が出力したデジタル信号ｘｋ及びジッタ検出部７が出力したＮ個のアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）の入力を受けて、アパーチャ時間τ_{ｋー ｐ}（ｐ≠０）、τ_ｋに基づいて、フィルタ係数ｈ_０〜ｈ_ｐを算出し、このフィルタ係数をセットして、デジタル信号ｘｋに対して、不均一サンプリングを行い、参照信号Ｒ（ｔ）を含む干渉波を除去し希望波ｙｋを出力する。
なお、フィルタリング後は、希望波ｙｋのみであるため、均一サンプリングに戻しても必要なＳＮＲは十分確保することができる。
【００２９】
したがって、本実施形態のＡ／Ｄ変換回路によれば、Ａ／Ｄ変換時のアパーチャジッタによる雑音を減少させ、等価的にＡ／Ｄ変換回路全体のＥＮｏＢを増大することができる効果が得られる。
【００３０】
次に本発明のＡ／Ｄ変換回路の第２の実施形態について説明する。本実施形態が第１の実施形態と異なる点は、ＡＤＣ・５より後段部分の処理がすべてソフトウェアを用いてＣＰＵやＤＳＰ等（図示せず）の演算部により実行される点にある。すなわち、本実施形態のＡ／Ｄ変換回路は、ＬＰＦ・６、ジッタ検出部７、不均一サンプリングＢＰＦ・８の代わりにＣＰＵ等の演算部、ＲＯＭ、ＲＡＭ等の記憶部をさらに有することで構成される。
ＣＰＵ等の演算部は、ＲＯＭに記憶された雑音処理プログラム、ジッタ検出処理プログラム、不均一サンプリング処理プログラムを読み出して、これを実行する。
【００３１】
雑音処理プログラムとは、デジタル信号ｘｋに含まれる希望波の周波数帯域、具体的にはデジタル信号Ｉｋの周波数帯を阻止し、デジタル信号ｘｋからデジタル信号Ｉｋを除去する処理をＣＰＵに実行させるためのプログラムである。
また、ジッタ検出処理プログラムとは、上述の式（１）を用いて、デジタル信号Ｒｋと参照信号Ｒ（ｔ）の周波数ｆ_Ｒ又はクロック信号の周波数ｆ_ｓからアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）をＮ個算出する処理をＣＰＵに実行させるためのプログラムである。
また、不均一サンプリング処理プログラムとは、上述の式（２）〜式（４）を用いて、雑音処理プログラムによって処理されたデジタル信号ｘｋ及びジッタ検出処理プログラムが算出したＮ個のアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）の入力を受けて、アパーチャ時間τ_{ｋー ｐ}（ｐ≠０）、τ_ｋに基づいて、フィルタ係数ｈ_０〜ｈ_ｐを算出し、これらのフィルタ係数をセットして、デジタル信号ｘｋに対して、不均一サンプリング処理を行い、参照信号Ｒ（ｔ）を含む干渉波を除去し希望波ｙｋを出力する処理をＣＰＵに実行させるためのプログラムである。
ＲＡＭは、半導体メモリ等の一時記憶部であり、上述のＲＡＭ１２と同様の構成である。
【００３２】
以下、本実施形態のＡ／Ｄ変換回路の動作について、第１の実施形態と異なる点について説明し、共通する点については説明を省略する。
ＣＰＵは、ＲＯＭに記憶された雑音処理プログラム、ジッタ検出処理プログラム、不均一サンプリング処理プログラムを読み出して、これを実行する。すなわち、ＣＰＵは、ＡＤＣ・５から出力されたデータ信号ｘｋ（＝デジタル信号ｘｋ）の入力を受けて、雑音処理プログラムによるプロセスにしたがって、データ信号ｘｋよりデータ信号Ｉｋ（＝デジタル信号Ｉｋ）を除去し、デ−タ信号Ｒｋ（＝デジタル信号Ｒｋ）のみをジッタ検出処理プログラムによるプロセスに渡す。
【００３３】
ＣＰＵは、データ信号Ｒｋがジッタ検出処理プログラムのプロセスに渡されたことを受けて、上述の式（２）を用いて、データ信号Ｒｋと参照信号Ｒ（ｔ）の周波数ｆ_Ｒ又はクロック信号の周波数ｆｓからアパーチャ時間データτ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）をＮ個すべて算出し、ＲＡＭに書き込む。そして、Ｎ個すべてのアパーチャ時間データτ_{ｋー ｐ}を不均一サンプリング処理プログラムのプロセスに対して渡す。
【００３４】
ＣＰＵは、ジッタ検出処理プログラムからのＮ個のアパーチャ時間τ_{ｋー ｐ}が不均一サンプリング処理プログラムのプロセスに対して渡されたことを受けて、アパーチャ時間τ_{ｋー ｐ}（ｐ≠０）、τ_ｋに基づいて、フィルタ係数データｈ_０〜ｈ_ｐを算出し、ＲＡＭに書き込む。
次に、ＣＰＵは、ＡＤＣ・５が出力したデータ信号ｘｋの入力を受けて、デジタル信号ｘｋに対して、セットされたフィルタ係数を用いて不均一サンプリングを行い、参照信号Ｒ（ｔ）を含む干渉波部分のデータを除去し希望波部分のデータｙｋを上位のアプリケーションに出力する。
【００３５】
したがって、本実施形態のＡ／Ｄ変換回路によれば、Ａ／Ｄ変換時のアパーチャジッタによる雑音を減少させ、等価的にＡ／Ｄ変換回路全体のＥＮｏＢを増大することができる効果が得られる。また、ＣＰＵによりソフトウェアによる制御を行うので、回路変更等が必要な場合でも、ＲＯＭ等にインストールされるプログラムを更新することで、変更を実現できるなど、変更・改良作業の効率を上げることができる効果が得られる。
【００３６】
次に本発明の第３の実施形態について、図面を参照して説明する。図３は、本実施形態のＡ／Ｄ変換回路の構成を示す全体構成図である。本実施形態のＡ／Ｄ変換回路は、クロック信号発生回路３１と、ＢＰＦ・３２と、分周器・３３と、加算器３と、ＢＰＦ・４と、ＡＤＣ・５と、ＬＰＦ・６と、ジッタ検出部７と、不均一サンプリングＢＰＦ８とから構成される。
すなわち、本実施形態のＡ／Ｄ変換回路が第１の実施形態のＡ／Ｄ変換回路と異なる点は、周波数ｆ_Ｓのクロック信号を発生するクロック信号発生回路１の代わりに、周波数ｆ_Ｒのクロック信号を発生するクロック信号発生回路３１を設け、ＰＬＬ・２の代わりに、参照信号Ｒ（ｔ）を出力するＢＰＦ・３２を設け、さらに、クロック信号発生回路３１の発生するクロック信号の周波数を１／ｎ倍した周波数ｆ_ｓのクロックを発生する分周器・３３を設けた点である。
【００３７】
クロック信号発生回路３１は、ＢＰＦ・３２と分周器・３３と接続されており、上述の周波数ｆ_Ｒのアパーチャジッタ特性を持つクロック信号を発生し、ＢＰＦ・３２、分周器・３３それぞれに出力する。
ＢＰＦ・３２は、加算器３と接続されており、周波数ｆ_Ｒの持つクロック信号の入力を受けて、ＡＤＣ・５のサンプリング周波数に対してエイリアスの発生しない帯域のみ信号を通過させるフィルタ特性、すなわち、ＡＤＣ・５のサンプリング周波数（分周器・３３から入力されるクロック信号の周波数ｆ_ｓ）の２分の１以上の周波数帯を阻止するフィルタ特性のアナログフィルタであって、加算器３に参照信号Ｒ（ｔ）を出力する。
【００３８】
分周器・３３は、ループ内の発振器からの出力との位相差が一定となるように、ループ内の発振器にフィードバックをかけて発振させる発振回路である。具体的には、クロック信号発生回路３１とＡＤＣ・５と接続されており、クロック信号発生回路３１が発生する周波数ｆ_Ｒのクロック信号の入力を受けて、これを基準信号とし、周波数ｆ_Ｓ（ｆ_ｓ＝１／ｎ×ｆ_Ｒ：ｎは任意の数）であり、基準信号と位相が同期しているクロック信号をＡＤＣ・５に出力する。
【００３９】
したがって、本実施形態のＡ／Ｄ変換回路によれば、第１の実施形態と同様に、Ａ／Ｄ変換時のアパーチャジッタによる雑音を減少させ、等価的にＡ／Ｄ変換回路全体のＥＮｏＢを増大することができる効果が得られる。
【００４０】
次に本発明の第４の実施形態について、図面を参照して説明する。図４は、本実施形態のＡ／Ｄ変換回路の構成を示す全体構成図である。本実施形態のＡ／Ｄ変換回路は、クロック信号発生回路３１と、ＢＰＦ・４２と、分周器・４３と、ＡＤＣ・４４と、ＢＰＦ・４と、ＡＤＣ・５と、ジッタ検出部７と、不均一サンプリングＢＰＦ８とから構成される。
すなわち、本実施形態のＡ／Ｄ変換回路が、第３の実施形態と異なる点は、加算器３とＬＰＦ・６を省略し、ＢＰＦ・３２の代わりにＢＰＦ・４２を設け、分周器・３３の代わりに分周器・４３を設け、さらに、ＡＤＣ・４４を新たに設けた点である。
【００４１】
ＢＰＦ・４２が、ＢＰＦ・３２と異なる点は、ＢＰＦ・４２がＡＤＣ・４４と接続されており、ＡＤＣ・４４に参照信号Ｒ（ｔ）を出力する点である。
また、分周器・４３が分周器・３３と異なる点は、分周器・４３がＡＤＣ・５、ＡＤＣ・４４と接続されており、周波数ｆ_ＳのクロックをＡＤＣ・５だけでなく、ＡＤＣ・４４にも出力する点である。
ＡＤＣ・４４は、ＢＰＦ・４２、分周器・４３、ジッタ検出部７と接続されており、分周器・４３から出力された周波数ｆ_ｓのクロック信号の入力を受けて、これをサンプリングクロックとする。またＡＤＣ・５は、ＢＰＦ・４２から出力された参照信号Ｒ（ｔ）の入力を受けて、参照信号Ｒ（ｔ）を標本化（サンプル）し、標本化されたデジタル値を保持（ホールド）する。また、ＡＤＣ・５は、このデジタル値をデジタル信号Ｒｋとしてジッタ検出部７に出力する。
【００４２】
以下、本実施形態のＡ／Ｄ変換回路の動作について、第３の実施形態と異なる点について説明し、共通する動作は説明を省略する。
アンテナにおいて受信された受信信号が本実施形態のＡ／Ｄ変換回路に入力されると、ＢＰＦ・４を経由してＡＤＣ・５に受信信号Ｉ（ｔ）が入力される。
ＡＤＣ・５は、クロック信号発生回路３１から出力され、分周器・４３で１／ｎ倍された周波数ｆｓのクロック信号と受信信号Ｉ（ｔ）（本実施形態においては、Ｉ（ｔ）＝Ｘ（ｔ））の入力を受けて、受信信号Ｉ（ｔ）をサンプリング周波数ｆｓ標本化し、標本化されたデジタル値を保持する。
次に、ＡＤＣ・５は、このデジタル値をデジタル信号ｘｋとして不均一サンプリングフィルタ８それぞれに出力する。ここで、Ａ／Ｄ変換後のデジタル信号ｘｋは周波数ｆ_Ｓのサンプリングクロックが、もともとアパーチャジッタによる誤差を含んでいるため、雑音が発生し、等価的にＡ／Ｄ変換のＥＮｏＢを劣化させる。
【００４３】
一方、このアパーチャジッタによる雑音は、各サンプル点が時間ずれτ_Ｋを持つ不均一サンプリングだと解釈すれば、雑音成分は生じていない。そこで、τ_Ｋを用いて、不均一サンプリングＢＰＦ・８のフィルタ係数を算出し、不均一サンプリングを行う。
すなわち、まずＡＤＣ・４４は、ＢＰＦ・４２から出力される参照信号Ｒ（ｔ）の入力を受けて、分周器・４３で１／ｎ倍された周波数ｆｓのクロック信号と参照信号Ｒ（ｔ）の入力を受けて、参照信号Ｒ（ｔ）をサンプリング周波数ｆｓ標本化し、標本化されたデジタル値を保持する。
次に、ＡＤＣ・５は、このデジタル値をデジタル信号Ｒｋとしてジッタ検出部７に出力する。
ジッタ検出部７は、デジタル信号Ｒｋの入力を受けて、上述の式（２）を用いて、デジタル信号Ｒｋと参照信号Ｒ（ｔ）の周波数ｆ_Ｒ又はクロック信号の周波数ｆｓからアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）をＮ個すべて算出し、不均一サンプリングＢＰＦ・８に出力する。
【００４４】
不均一サンプリングＢＰＦ・８は、ＡＤＣ・５が出力したデジタル信号ｘｋ及びジッタ検出部７が出力したＮ個のアパーチャ時間τ_{ｋー ｐ}（ただしｐは０≦ｐ≦Ｎ−１を満たす整数）の入力を受けて、アパーチャ時間τ_{ｋー ｐ}（ｐ≠０）、τ_ｋに基づいて、フィルタ係数ｈ_０〜ｈ_ｐを算出し、このフィルタ係数をセットして、デジタル信号ｘｋに対して、不均一サンプリングを行い、参照信号Ｒ（ｔ）を含む干渉波を除去し希望波ｙｋを出力する。
なお、フィルタリング後は、希望波ｙｋのみであるため、均一サンプリングに戻しても必要なＳＮＲは十分確保することができる。
【００４５】
したがって、本実施形態のＡ／Ｄ変換回路によれば、Ａ／Ｄ変換時のアパーチャジッタによる雑音を減少させ、等価的にＡ／Ｄ変換回路全体のＥＮｏＢを増大することができる効果が得られる。
【００４６】
なお、上述のＡ／Ｄ変換回路はハードウェアによって構成される場合を示したが、本発明はこれに限られるものではなく、例えばＡ／Ｄ変換回路は内部に、コンピュータシステムを有していてもよい。この場合、上述したＡ／Ｄ変換に関する一連の処理の過程は、プログラムの形式でコンピュータ読み取り可能な記録媒体に記憶されており、このプログラムをコンピュータが読み出して実行することによって、上記処理が行われる。ここでコンピュータ読み取り可能な記録媒体とは、磁気ディスク、光磁気ディスク、ＣＤ−ＲＯＭ、ＤＶＤ−ＲＯＭ、半導体メモリ等をいう。また、このコンピュータプログラムを通信回線によってコンピュータに配信し、この配信を受けたコンピュータが当該プログラムを実行するようにしても良い。
【００４７】
【発明の効果】
以上説明したように、本発明は、クロック信号発生回路が、所定の周波数のアパーチャジッタ特性を持つ第１のクロック信号を発生し、位相同期回路が、第１のクロック信号の入力を受けて、第１のクロック信号の周波数をｎ（ｎは任意の数）倍し、第１のクロック信号と位相同期した第２のクロック信号を出力し、加算器が、受信信号及び第２のクロック信号の入力を受けて、受信信号に第２のクロック信号を加算して出力し、Ａ／Ｄ変換器が、第２のクロック信号を加算した受信信号及び第１のクロック信号の入力を受けて、第１のクロック信号をサンプリングクロックとして受信信号を標本化し、デジタル値を保持するとともに、デジタル信号を出力し、ジッタ検出部が、デジタル信号の入力を受けて、デジタル値と第１又は第２のクロック信号の周波数に基づいて、アパーチャ時間を算出し出力し、不均一サンプリングデジタルフィルタが、Ａ／Ｄ変換器が出力したデジタル信号及びアパーチャ時間の入力を受けて、アパーチャ時間に基づいてフィルタ係数を算出し、フィルタ係数をセットして、デジタル信号に対して、不均一サンプリングを行い、第２のクロック信号を含む干渉波を除去し希望波を出力するので、Ａ／Ｄ変換器のＥＮｏＢを増大させることができる効果が得られる。
【図面の簡単な説明】
【図１】第１実施形態のＡ／Ｄ変換回路の構成図である。
【図２】不均一サンプリングバンドパスフィルタ８の構成を示す構成図である。
【図３】第３実施形態のＡ／Ｄ変換回路の構成図である。
【図４】第４実施形態のＡ／Ｄ変換回路の構成図である。
【図５】入力周波数とＥＮｏＢ、ＳＮＲの関係を示す図である。
【符号の説明】
１…クロック信号発生回路
２…位相同期回路
３…加算器
４…バンドパスフィルタ
５…Ａ／Ｄ変換器
６…ローパスフィルタ
７…ジッタ検出部
８…不均一サンプリングＢＰＦ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a receiver used in mobile communication such as a digital mobile phone. In particular, the present invention provides a small-sized and inexpensive wide-band digital receiver that does not deteriorate in performance when A / D conversion is performed on a received signal at a relatively high frequency to realize channel separation and demodulation functions.
[0002]
[Prior art]
The wide band digital receiver is a receiver that performs A / D conversion of a wide band signal as it is in an RF band or an IF band, and performs processing after channel separation by a digital circuit (see Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application No. 61-504791
[0004]
[Problems to be solved by the invention]
However, in the conventional wide band digital receiver, the input frequency to A / D conversion, that is, the IF frequency cannot be set too high for the following reasons. Therefore, when the RF frequency is high, the RF front-end circuit is switched to double conversion. And the structure of the RF front-end circuit becomes complicated, which leads to an increase in the size of the receiver. In addition, there are advantages that the characteristics of the wide band receiver are that there is no variation in characteristics, there is no aging deterioration, and no adjustment is required. Is difficult to obtain.
[0005]
This is because, due to the aperture jitter characteristic of the sampling signal, error noise occurs at the time of A / D conversion and the effective number of bits (ENoB: Effective Number of Bits) of the A / D converter deteriorates. This deterioration becomes more remarkable as the input signal frequency to the A / D converter increases. FIG. 5 shows an example of the characteristics of the input frequency versus the ENoB. The standard deviation of the aperture jitter of a general crystal oscillator is about several tens ps. FIG. 5 shows the case of the 12-bit A / D converter. When σa is 10 ps and the input frequency exceeds 10 MHz, the ENoB rapidly deteriorates and becomes about 8 bits at an input frequency of 60 MHz.
Also, noise power due to aperture jitter increases in proportion to input signal power. FIG. 5 shows calculated values when a full-scale signal is input. Therefore, for example, when a high-power interference wave and a low-power desired wave are received, the SNR of the desired wave cannot be secured due to the influence of noise power generated by the influence of the high-power interference wave, and the demodulation performance deteriorates. Problems arise.
[0006]
The present invention has been made in view of such circumstances, and an object thereof is to provide an A / D conversion circuit, an A / D conversion control method, and an A / D conversion method capable of increasing the ENoB of an A / D converter. Another object of the present invention is to provide a D conversion program.
[0007]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an invention according to claim 1 is an A / D conversion circuit for performing A / D conversion of a received signal in a wide band digital receiver, wherein the A / D conversion circuit has a predetermined frequency. A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of: and receiving the input of the first clock signal, and multiplying the frequency of the first clock signal by n (n is an arbitrary number) And a phase-locked loop circuit that outputs a second clock signal that is phase-locked with the first clock signal, and receives the input of the received signal and the second clock signal, and applies the second clock signal to the received signal. An adder for adding and outputting a signal; sampling a received signal obtained by adding the second clock signal using the first clock signal as a sampling clock; and holding a digital value obtained by the sampling. Receiving the input of the digital value, calculating and outputting an aperture time based on the digital value and the frequency of the first or second clock signal. Upon receiving the jitter detector and the digital value output from the A / D converter and the input of the aperture time, a filter coefficient is calculated based on the aperture time, and the filter coefficient is set. On the other hand, a non-uniform sampling digital filter for performing non-uniform sampling, removing an interference wave including the second clock signal, and outputting a desired wave is provided.
[0008]
According to a second aspect of the present invention, there is provided an A / D conversion circuit for A / D converting a received signal in a wide band digital receiver, wherein the clock generates a first clock signal having aperture jitter characteristics of a predetermined frequency. A signal generation circuit, receiving the input of the first clock signal, multiplying the frequency of the first clock signal by n (n is an arbitrary number), and synthesizing the second clock signal in phase with the first clock signal. A phase synchronization circuit that outputs a clock signal, a filter that receives the input of the reception signal, and blocks a frequency band equal to or more than half the frequency of the first clock signal, and a reception signal that has passed through the filter. An adder that receives the second clock signal, adds the second clock signal to the received signal, and outputs the added signal; and outputs the received signal obtained by adding the second clock signal to the first clock signal. Sampling A / D converter that samples as a lock, holds the digital value obtained by the sampling, and outputs the digital value, and receives the input of the digital value, and A jitter detector that calculates and outputs an aperture time based on the frequency of the clock signal of the second clock signal, and receives a digital value output by the A / D converter and the input of the aperture time, and performs filtering based on the aperture time. Calculating a coefficient, setting the filter coefficient, performing non-uniform sampling on the digital value, removing an interference wave including the second clock signal, and outputting a desired wave. It is characterized by having.
[0009]
According to a third aspect of the present invention, there is provided an A / D conversion circuit for A / D converting a received signal in a wide band digital receiver, wherein the clock generates a first clock signal having an aperture jitter characteristic of a predetermined frequency. A signal generation circuit, receiving the input of the first clock signal, multiplying the frequency of the first clock signal by n (n is an arbitrary number), and synthesizing the second clock signal in phase with the first clock signal. A phase synchronization circuit that outputs a clock signal, an adder that receives the input of the reception signal and the second clock signal, adds the second clock signal to the reception signal, and outputs the added signal; An A / D converter that samples the received signal obtained by adding the clock signal, uses the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value; Receiving an input of the total value, a filter for blocking a frequency band of a desired wave included in the received signal, and an aperture time is calculated based on a digital value passed through the filter and a frequency of the first clock signal. Receiving a digital value output from the A / D converter and the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and setting the filter coefficient; A non-uniform sampling digital filter for performing non-uniform sampling on the value, removing an interference wave including the second clock signal, and outputting a desired wave.
[0010]
According to a fourth aspect of the present invention, there is provided an A / D conversion circuit for A / D converting a received signal in a wide band digital receiver, wherein the clock generates a first clock signal having an aperture jitter characteristic of a predetermined frequency. A signal generation circuit, an adder receiving the input of the received signal and the first clock signal, adding the first clock signal to the received signal and outputting the added signal, and an input of the first clock signal. A frequency divider that outputs a second clock signal obtained by multiplying the frequency of the first clock signal by 1 / n (n is an arbitrary number), and a reception signal obtained by adding the first clock signal to the frequency divider. An A / D converter that samples the second clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value, and receives the input of the digital value, value A jitter detector for calculating and outputting an aperture time based on the frequency of the first or second clock signal, and receiving the input of the digital value output by the A / D converter and the aperture time, Calculating a filter coefficient based on time, setting the filter coefficient, performing uneven sampling on the digital value, removing an interference wave including the second clock signal, and outputting a desired wave; And a sampling digital filter.
[0011]
A fifth aspect of the present invention is an A / D conversion circuit for A / D converting a received signal in a wide band digital receiver, wherein the clock generates a first clock signal having an aperture jitter characteristic of a predetermined frequency. A signal generating circuit, and a frequency divider receiving the input of the first clock signal and outputting a second clock signal obtained by multiplying the frequency of the first clock signal by 1 / n (n is an arbitrary number) A first A / D converter that samples the received signal using the second clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs a first digital value; , Using the second clock signal as a sampling clock, sampling the first clock signal, holding a digital value obtained by the sampling, and outputting a second digital value And an A / D converter, and a jitter detector that receives the input of the second digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal. Receiving the input of the first digital value and the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the first digital value. And a non-uniform sampling digital filter for removing an interference wave and outputting a desired wave.
[0012]
The invention according to claim 6 is an A / D conversion method for A / D converting a received signal in a wide band digital receiver, wherein the clock signal generation circuit has an aperture jitter characteristic of a predetermined frequency. A clock signal is generated, and a phase synchronization circuit receives the input of the first clock signal, multiplies the frequency of the first clock signal by n (n is an arbitrary number), and A phase-synchronized second clock signal is output, and an adder receives the received signal and the second clock signal, adds the second clock signal to the received signal, and outputs the result. A / D converter samples the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and converts the digital value into Output Receiving the digital value, calculating and outputting an aperture time based on the digital value and the frequency of the first or second clock signal. Receiving the input of the digital value output from the / D converter and the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the digital value. And removing an interference wave including the second clock signal and outputting a desired wave.
[0013]
The invention according to claim 7, wherein a clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency, and receiving the input of the first clock signal, the first clock signal Is multiplied by n (n is an arbitrary number) to output a second clock signal that is phase-locked with the first clock signal, and the input of the reception signal and the second clock signal. Receiving the received signal, adding the second clock signal to the received signal, and outputting the received signal; and sampling the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock. The digital value obtained by the sampling is retained, and the computer performs an A / D conversion process in a wide band digital receiver including an A / D converter that outputs the digital value. A / D conversion program for receiving an input of the digital value, calculating and outputting an aperture time based on the digital value and the frequency of the first or second clock signal; Receiving the input of the digital value output from the / D converter and the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the digital value. And an A / D conversion program for causing a computer to execute a process of removing an interference wave including the second clock signal and outputting a desired wave.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an overall configuration diagram showing the configuration of the A / D conversion circuit of the present embodiment. The A / D conversion circuit according to the present embodiment includes a clock signal generation circuit 1, a phase synchronization circuit (hereinafter, referred to as PLL) 2, an adder 3, and a band-pass filter (hereinafter, referred to as BPF) 4. , An A / D converter (hereinafter, referred to as ADC) 5, a low-pass filter (hereinafter, referred to as LPF) 6, a jitter detector 7, and a non-uniform sampling BPF 8.
[0015]
The clock signal generation circuit 1 is connected to the PLL 2 and the ADC 5, and has a frequency f_s, And outputs the clock signal to the phase-locked loop 2 and the ADC / 5.
The PLL 2 is an oscillation circuit that oscillates by applying feedback to the oscillator in the loop so that the phase difference between the output from the oscillator in the loop and the clock signal becomes constant. Specifically, it is connected to the clock signal generation circuit 1 and the adder 3, receives a clock signal of the frequency fs generated by the clock signal generation circuit 1, uses the clock signal as a reference signal,_R(F_R= N × f_s: N is an arbitrary number), and outputs the reference signal R (t) whose phase is synchronized with the reference signal to the adder 3.
[0016]
The adder 3 is connected to the PLL 2, the BPF 4, and the ADC 5, and receives a signal received by an antenna (not shown) provided in the wide band wireless receiver and filtered by the BPF 4. Upon receiving the input of I (t) and the reference signal R (t) output from the PLL · 2, these signals are added, and the added signal X (t) is output to the ADC · 5.
The BPF 4 is connected to the adder 3, receives input of a received signal from the above-described antenna, and has a filter characteristic of passing a signal only in a band where no alias occurs with respect to the sampling frequency of the ADC 5, that is, ADC · 5 sampling frequency (frequency f of clock signal input from clock signal generation circuit 1)_s) Is an analog filter having a filter characteristic of blocking a frequency band equal to or more than one-half of the frequency band shown in FIG.
[0017]
The ADC 5 is connected to the clock signal generating circuit 1, the adder 3, the LPF 6, and the non-uniform sampling BPF 8. The frequency f output from the clock signal generating circuit 1_sAnd receives it as a sampling clock. The ADC 5 receives the addition signal X (t) output from the adder 3, samples the addition signal X (t), and holds the sampled digital value. I do. The ADC 5 also converts this digital value into a digital signal xk (see xk in FIG. 1 where xk = Ik + Rk, where Ik is a digital signal obtained by A / D conversion of the received signal I (t), and Rk is a reference signal. R (t) is a digital signal obtained by A / D conversion) is output to the LPF 6 and the non-uniform sampling filter 8, respectively.
[0018]
The LPF 6 is connected to the ADC 5 and the jitter detection unit 7, receives the input of the digital signal xk from the ADC 5, and receives a frequency band of a desired wave included in the digital signal xk, specifically, the digital signal xk. It is a digital filter having a filter characteristic of blocking a frequency band of Ik, and outputs a digital signal Rk obtained by removing the digital signal Ik from the digital signal xk to the jitter detector 7.
The jitter detector 7 is connected to the LPF 6 and the non-uniform sampling BPF 8, and receives the input of the digital signal Rk, and receives the digital signal Rk and the frequency f of the reference signal R (t)._ROr the aperture time τ based on the frequency fs of the clock signal._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) is calculated and output to the non-uniform sampling BPF · 8.
[0019]
Here, the aperture time τk is obtained by the following equation (1).
(Equation 1)

However, in equation (1)
・ A₀Can be calculated from the amplitude of the reference signal R (t)
・ F_R/ F_s= N
・ Τk is instantaneous fluctuation (approximate to Gaussian distribution with mean 0)
Therefore, the jitter detector 7 calculates τ_kBy averaging (narrow band filter)_k→ 0, φ0 is calculated, and the calculated φ0 is substituted into Expression (1) to obtain an aperture time τ for each k._kIs calculated. Similarly, τ_{k- p}Is calculated.
[0020]
The non-uniform sampling BPF · 8 is connected to the ADC · 5 and the jitter detector 7, and outputs the digital signal xk output from the ADC · 5 and the N aperture times τ output from the jitter detector 7._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) and the aperture time τ_{k- p}(P ≠ 0), τ_kBased on the filter coefficient h₀~ H_pIs calculated, these filter coefficients are set, and non-uniform sampling is performed on the digital signal xk to remove an interference wave including the reference signal R (t) and output a desired wave yk.
Here, the filter coefficient h_pIs obtained from the following equation (2).
(Equation 2)

Here, in the equation (2), h is a known filter coefficient.
[0021]
The digital signal xk is represented by the following equation (3).
(Equation 3)

Here, in Expression (3), x is a known signal value. When the calculated filter coefficients and digital signal xk are convolved, desired wave yk is expressed by the following equation (4).
(Equation 4)

[0022]
As shown in FIG. 2, for example, the non-uniform sampling BPF 8 includes p delay elements Dt-1 to Dt-p and (p + 1) multipliers 10-0 to 10-p, It comprises an adder 11, a RAM 12, and a filter coefficient calculation unit 13.
The multiplier 10-0 is connected to the input terminal on the ADC / 5 side of the non-uniform sampling BPF / 8 and the adder 11, and the digital signal xk from the ADC / 5 and the filter coefficient h0 (the filter coefficient calculation unit 13 The filter coefficient h calculated for each sample based on the above equation and written in the RAM 12₀Is set in the multiplier 10-0 every time. ) And outputs the result to the adder 11.
[0023]
The multiplier 10-i (1 ≦ i ≦ p) is connected to the delay element Dt-i and the adder 11, and the digital signal x of the delay element Dt-i_kiAnd the filter coefficient h_iAnd outputs the result to the adder 11. Here, the filter coefficient h_iIs calculated by the filter coefficient calculation unit 13 for each sample based on the above equation, and the calculated value is written into the RAM 12 so that the filter coefficient h_iIs set in the multiplier 10-i every time.
[0024]
The delay element Dt-1 is connected to the input terminal on the ADC / 5 side of the non-uniform sampling BPF / 8, the delay element Dt-2, and the multiplier 10-1, and outputs the digital signal xk from the ADC / 5 for a predetermined time. Digital signal x delayed by_k-1To the delay element Dt-2 and the multiplier 10-1. Also. Delay element D_tj(2 ≦ j ≦ p−1) is the delay element D_t-j-1, Delay element D_{t-j + 1}, Multiplier 10-j and a delay element D_t-j-1Digital signal x from_{k-j + 1}Is a digital signal x delayed by a predetermined time_{k- j}Is the delay element D_{t-j + 1}, To the multiplier 10-j. Also. Delay element D_tpIs the delay element D_tp-1, Multiplier 10-p and a delay element D_tp-1Digital signal x from_{k- p +1}Is a digital signal x delayed by a predetermined time_k-pIs output to the multiplier 10-j.
[0025]
The adder 11 receives p + 1 added signals h₀x_k, H₁x_k-1, ..., h_px_k-pIs output as a desired signal yk.
The RAM 12 is a temporary storage unit such as a semiconductor memory, and has a filter coefficient h set in the multipliers 10-0 to 10-p calculated by the filter coefficient calculation unit 13.₀~ H_pIs stored. Note that this filter coefficient h₀~ H_pIs updated with the value updated by the filter coefficient calculation unit 13 for each sample.
The filter coefficient calculator 13 calculates the aperture time τ_k~ Τ_{k- p}, The aperture time τ is calculated by the above equation._k~ Τ_{k- p}Filter coefficient h for each sample, that is, for each k₀~ H_pIs calculated and written in the RAM 12.
[0026]
Hereinafter, the operation of the A / D conversion circuit of the present embodiment will be described.
When the received signal received by the antenna is input to the A / D conversion circuit of the present embodiment, the received signal I (t) is input to the adder 3 via the BPF 4.
The adder 3 calculates the received signal I (t) and the frequency f output from the PLL · 2._R, And adds these signals, and outputs an addition signal X (t) to the ADC · 5.
The ADC 5 receives the clock signal of the frequency fs output from the clock signal generating circuit 1 and the input of the addition signal X (t) output from the adder 3 and converts the addition signal X (t) at the sampling frequency fs. Sampling and holding the sampled digital values.
Next, the ADC 5 outputs the digital value to the LPF 6 and the non-uniform sampling filter 8 as a digital signal xk. Here, the digital signal xk after the A / D conversion has a frequency f_SOriginally includes an error due to aperture jitter, noise is generated and equivalently degrades A / D conversion ENoB.
[0027]
On the other hand, the noise due to the aperture jitter is such that each sample point has a time lag τ_KWhen interpreted as non-uniform sampling with, no noise component is generated. Then, τ_KIs used, the filter coefficient of the non-uniform sampling BPF · 8 is calculated, and non-uniform sampling is performed.
That is, in the digital signal xk, the digital signal Ik is first removed in the LPF 6, and only the digital signal Rk is input to the jitter detector 7. The jitter detector 7 receives the input of the digital signal Rk, and uses the above equation (2) to calculate the frequency f of the digital signal Rk and the reference signal R (t)._ROr from the frequency fs of the clock signal to the aperture time τ_{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) is calculated for all N and output to the non-uniform sampling BPF · 8.
[0028]
The non-uniform sampling BPF · 8 is composed of the digital signal xk output from the ADC · 5 and the N aperture times τ output from the jitter detector 7._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) and the aperture time τ_{k- p}(P ≠ 0), τ_kBased on the filter coefficient h₀~ H_pIs calculated, the filter coefficient is set, and non-uniform sampling is performed on the digital signal xk, an interference wave including the reference signal R (t) is removed, and a desired wave yk is output.
Since only the desired wave yk is obtained after the filtering, the required SNR can be sufficiently secured even if the sampling is returned to the uniform sampling.
[0029]
Therefore, according to the A / D conversion circuit of the present embodiment, it is possible to reduce the noise due to the aperture jitter at the time of A / D conversion and to equivalently increase the ENoB of the entire A / D conversion circuit. .
[0030]
Next, a second embodiment of the A / D conversion circuit of the present invention will be described. The present embodiment is different from the first embodiment in that all processes subsequent to the ADC 5 are executed by software or by an arithmetic unit such as a CPU or a DSP (not shown). That is, the A / D conversion circuit according to the present embodiment is configured by further including an arithmetic unit such as a CPU and a storage unit such as a ROM and a RAM in place of the LPF 6, the jitter detection unit 7, and the non-uniform sampling BPF 8. Is done.
An arithmetic unit such as a CPU reads a noise processing program, a jitter detection processing program, and a non-uniform sampling processing program stored in the ROM, and executes them.
[0031]
The noise processing program is for causing the CPU to execute a process of blocking a frequency band of a desired wave included in the digital signal xk, specifically, a frequency band of the digital signal Ik and removing the digital signal Ik from the digital signal xk. It is a program.
Further, the jitter detection processing program uses the above equation (1) to calculate the frequency f of the digital signal Rk and the reference signal R (t)._ROr the frequency f of the clock signal_sTo aperture time τ_{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) is a program for causing the CPU to execute processing for calculating N pieces.
The non-uniform sampling processing program is a digital signal xk processed by the noise processing program and N aperture times τ calculated by the jitter detection processing program, using the above-described equations (2) to (4)._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) and the aperture time τ_{k- p}(P ≠ 0), τ_kBased on the filter coefficient h₀~ H_pIs calculated, these filter coefficients are set, and non-uniform sampling processing is performed on the digital signal xk to remove the interference wave including the reference signal R (t) and output the desired wave yk to the CPU. This is a program to be executed.
The RAM is a temporary storage unit such as a semiconductor memory, and has the same configuration as the RAM 12 described above.
[0032]
Hereinafter, the operation of the A / D conversion circuit according to the present embodiment will be described with respect to differences from the first embodiment, and description of common points will be omitted.
The CPU reads out and executes the noise processing program, the jitter detection processing program, and the non-uniform sampling processing program stored in the ROM. That is, the CPU receives the input of the data signal xk (= digital signal xk) output from the ADC 5 and removes the data signal Ik (= digital signal Ik) from the data signal xk according to the process by the noise processing program. Then, only the data signal Rk (= digital signal Rk) is passed to the process based on the jitter detection processing program.
[0033]
In response to the data signal Rk being passed to the process of the jitter detection processing program, the CPU uses the above equation (2) to calculate the frequency f of the data signal Rk and the reference signal R (t)._ROr the aperture time data τ from the clock signal frequency fs._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) is calculated for all N and written to the RAM. And all N aperture time data τ_{k- p}To the process of the non-uniform sampling processing program.
[0034]
The CPU calculates N aperture times τ from the jitter detection processing program._{k- p}Is passed to the process of the non-uniform sampling processing program, the aperture time τ_{k- p}(P ≠ 0), τ_kBased on the filter coefficient data h₀~ H_pIs calculated and written to the RAM.
Next, the CPU receives the input of the data signal xk output from the ADC · 5, performs non-uniform sampling on the digital signal xk using the set filter coefficient, and includes the reference signal R (t). The data of the interference wave part is removed, and the data yk of the desired wave part is output to the upper application.
[0035]
Therefore, according to the A / D conversion circuit of the present embodiment, it is possible to reduce the noise due to the aperture jitter at the time of A / D conversion and to equivalently increase the ENoB of the entire A / D conversion circuit. . Further, since control by software is performed by the CPU, even when a circuit change or the like is required, the program installed in the ROM or the like can be updated to realize the change, thereby improving the efficiency of the change / improvement work. The effect is obtained.
[0036]
Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is an overall configuration diagram showing the configuration of the A / D conversion circuit of the present embodiment. The A / D conversion circuit of this embodiment includes a clock signal generation circuit 31, a BPF 32, a frequency divider 33, an adder 3, a BPF 4, an ADC 5, an LPF 6, It comprises a jitter detector 7 and a non-uniform sampling BPF 8.
That is, the difference between the A / D conversion circuit of the present embodiment and the A / D conversion circuit of the first embodiment is that the frequency f_SInstead of the clock signal generating circuit 1 for generating the clock signal_RA clock signal generating circuit 31 for generating a clock signal is provided, and a BPF 32 for outputting a reference signal R (t) is provided instead of the PLL 2. Further, a frequency of the clock signal generated by the clock signal generating circuit 31 is provided. Frequency f which is 1 / n times_sIs provided with a frequency divider 33 for generating the clock of FIG.
[0037]
The clock signal generation circuit 31 is connected to the BPF 32 and the frequency divider 33, and the frequency f_RA clock signal having an aperture jitter characteristic of (1) is output to each of the BPF 32 and the frequency divider 33.
The BPF 32 is connected to the adder 3 and has a frequency f_RFilter characteristic that allows the signal to pass only in a band in which no alias occurs with respect to the sampling frequency of the ADC 5. That is, the sampling frequency of the ADC 5 (input from the frequency divider 33) Clock signal frequency f_s) Is an analog filter having a filter characteristic of blocking a frequency band equal to or more than one-half of the frequency band, and outputs a reference signal R (t) to the adder 3.
[0038]
The frequency divider 33 is an oscillation circuit that oscillates by applying feedback to the oscillator in the loop so that the phase difference from the output from the oscillator in the loop becomes constant. Specifically, the clock signal generation circuit 31 is connected to the ADC 5 and the frequency f_RReceiving the clock signal, and using this as a reference signal, the frequency f_S(F_s= 1 / n × f_R: N is an arbitrary number), and outputs a clock signal whose phase is synchronized with the reference signal to the ADC · 5.
[0039]
Therefore, according to the A / D conversion circuit of the present embodiment, similarly to the first embodiment, noise due to aperture jitter during A / D conversion is reduced, and ENoB of the entire A / D conversion circuit is equivalently reduced. The effect that can be increased is obtained.
[0040]
Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is an overall configuration diagram showing the configuration of the A / D conversion circuit of the present embodiment. The A / D conversion circuit of the present embodiment includes a clock signal generation circuit 31, a BPF 42, a frequency divider 43, an ADC 44, a BPF 4, an ADC 5, a jitter detector 7, , Non-uniform sampling BPF 8.
That is, the difference between the A / D conversion circuit of the present embodiment and the third embodiment is that the adder 3 and the LPF 6 are omitted, the BPF 42 is provided instead of the BPF 32, and the frequency divider A point is that a frequency divider 43 is provided instead of 33, and an ADC 44 is newly provided.
[0041]
The BPF 42 differs from the BPF 32 in that the BPF 42 is connected to the ADC 44 and outputs a reference signal R (t) to the ADC 44.
The difference between the frequency divider 43 and the frequency divider 33 is that the frequency divider 43 is connected to the ADC 5 and the ADC 44, and the frequency f_SIs output not only to the ADC 5 but also to the ADC 44.
The ADC 44 is connected to the BPF 42, the frequency divider 43, and the jitter detector 7, and outputs the frequency f output from the frequency divider 43._sAnd receives it as a sampling clock. The ADC 5 receives the input of the reference signal R (t) output from the BPF 42 and samples (samples) the reference signal R (t), and holds (holds) the sampled digital value. I do. The ADC 5 outputs the digital value to the jitter detector 7 as a digital signal Rk.
[0042]
Hereinafter, the operation of the A / D conversion circuit according to the present embodiment will be described with respect to differences from the third embodiment, and description of common operations will be omitted.
When the received signal received by the antenna is input to the A / D conversion circuit of the present embodiment, the received signal I (t) is input to the ADC 5 via the BPF 4.
The ADC 5 is output from the clock signal generation circuit 31 and is a clock signal having a frequency fs multiplied by 1 / n in the frequency divider 43 and a received signal I (t) (in the present embodiment, I (t) = X (t)), the received signal I (t) is sampled at the sampling frequency fs, and the sampled digital value is held.
Next, the ADC 5 outputs the digital value to each of the non-uniform sampling filters 8 as a digital signal xk. Here, the digital signal xk after the A / D conversion has a frequency f_SOriginally includes an error due to aperture jitter, noise is generated and equivalently degrades A / D conversion ENoB.
[0043]
On the other hand, the noise due to the aperture jitter is such that each sample point has a time lag τ_KWhen interpreted as non-uniform sampling with, no noise component is generated. Then, τ_KIs used, the filter coefficient of the non-uniform sampling BPF · 8 is calculated, and non-uniform sampling is performed.
That is, first, the ADC 44 receives the input of the reference signal R (t) output from the BPF 42 and receives the clock signal of the frequency fs multiplied by 1 / n in the frequency divider 43 and the reference signal R (t). ), The reference signal R (t) is sampled at the sampling frequency fs, and the sampled digital value is held.
Next, the ADC 5 outputs this digital value to the jitter detector 7 as a digital signal Rk.
The jitter detector 7 receives the input of the digital signal Rk, and uses the above equation (2) to calculate the frequency f of the digital signal Rk and the reference signal R (t)._ROr from the frequency fs of the clock signal to the aperture time τ_{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) is calculated for all N and output to the non-uniform sampling BPF · 8.
[0044]
The non-uniform sampling BPF · 8 is composed of the digital signal xk output from the ADC · 5 and the N aperture times τ output from the jitter detector 7._{k- p}(Where p is an integer satisfying 0 ≦ p ≦ N−1) and the aperture time τ_{k- p}(P ≠ 0), τ_kBased on the filter coefficient h₀~ H_pIs calculated, the filter coefficient is set, and non-uniform sampling is performed on the digital signal xk, an interference wave including the reference signal R (t) is removed, and a desired wave yk is output.
Since only the desired wave yk is obtained after the filtering, the required SNR can be sufficiently secured even if the sampling is returned to the uniform sampling.
[0045]
Therefore, according to the A / D conversion circuit of the present embodiment, it is possible to reduce the noise due to the aperture jitter at the time of A / D conversion and to equivalently increase the ENoB of the entire A / D conversion circuit. .
[0046]
Although the above-described A / D conversion circuit has been described as being configured by hardware, the present invention is not limited to this. For example, the A / D conversion circuit has a computer system inside. Is also good. In this case, the series of processes related to the above-described A / D conversion are stored in a computer-readable recording medium in the form of a program, and the above-described process is performed by reading and executing the program by the computer. . Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to a computer via a communication line, and the computer that has received the distribution may execute the program.
[0047]
【The invention's effect】
As described above, according to the present invention, the clock signal generation circuit generates the first clock signal having the aperture jitter characteristic of a predetermined frequency, and the phase synchronization circuit receives the input of the first clock signal, The frequency of the first clock signal is multiplied by n (n is an arbitrary number), a second clock signal synchronized with the first clock signal is output, and the adder outputs the received signal and the second clock signal. Upon receiving the input, the second clock signal is added to the received signal and output. The A / D converter receives the input of the received signal obtained by adding the second clock signal and the first clock signal, and 1 is used as a sampling clock to sample a received signal, hold a digital value, and output a digital signal. The jitter detector receives the input of the digital signal, and receives the digital value and the first or second clock. An aperture time is calculated and output based on the frequency of the input signal, and a non-uniform sampling digital filter receives the input of the digital signal output from the A / D converter and the aperture time, and receives a filter coefficient based on the aperture time. Is calculated, a filter coefficient is set, non-uniform sampling is performed on the digital signal, an interference wave including the second clock signal is removed, and a desired wave is output. The effect that can be increased is obtained.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an A / D conversion circuit according to a first embodiment.
FIG. 2 is a configuration diagram showing a configuration of a non-uniform sampling bandpass filter 8;
FIG. 3 is a configuration diagram of an A / D conversion circuit according to a third embodiment.
FIG. 4 is a configuration diagram of an A / D conversion circuit according to a fourth embodiment.
FIG. 5 is a diagram illustrating a relationship between an input frequency, ENoB, and SNR.
[Explanation of symbols]
1. Clock signal generation circuit
2 ... Phase synchronization circuit
3 ... Adder
4: Bandpass filter
5 ... A / D converter
6 ... Low-pass filter
7. Jitter detector
8: Non-uniform sampling BPF

Claims (7)

An A / D conversion circuit for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
Upon receiving the input of the first clock signal, the frequency of the first clock signal is multiplied by n (n is an arbitrary number), and a second clock signal phase-synchronized with the first clock signal is output. A phase locked loop,
An adder that receives the input of the reception signal and the second clock signal, adds the second clock signal to the reception signal, and outputs the result;
A / D converter that samples the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value When,
A jitter detector that receives the input of the digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal,
Upon receiving the digital value output from the A / D converter and the input of the aperture time, a filter coefficient is calculated based on the aperture time, and the filter coefficient is set. An A / D conversion circuit comprising: a non-uniform sampling digital filter that performs sampling, removes an interference wave including the second clock signal, and outputs a desired wave. An A / D conversion circuit for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
Upon receiving the input of the first clock signal, the frequency of the first clock signal is multiplied by n (n is an arbitrary number), and a second clock signal phase-synchronized with the first clock signal is output. A phase locked loop,
A filter for receiving the input of the reception signal and blocking a frequency band equal to or more than half the frequency of the first clock signal;
An adder receiving the input of the received signal and the second clock signal that have passed through the filter, adding the second clock signal to the received signal, and outputting the added signal;
A / D converter that samples the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value When,
A jitter detector that receives the input of the digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal,
Receiving the digital value output from the A / D converter and the input of the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the digital value. And a non-uniform sampling digital filter for removing an interference wave including the second clock signal and outputting a desired wave. An A / D conversion circuit for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
Upon receiving the input of the first clock signal, the frequency of the first clock signal is multiplied by n (n is an arbitrary number), and a second clock signal phase-synchronized with the first clock signal is output. A phase locked loop,
An adder that receives the input of the reception signal and the second clock signal, adds the second clock signal to the reception signal, and outputs the result;
A / D converter that samples the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value When,
A filter that receives the input of the digital value and blocks a frequency band of a desired wave included in the received signal;
A jitter detector that calculates and outputs an aperture time based on the digital value passed through the filter and the frequency of the first clock signal;
Receiving the digital value output from the A / D converter and the input of the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the digital value. And a non-uniform sampling digital filter for removing an interference wave including the second clock signal and outputting a desired wave. An A / D conversion circuit for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
An adder that receives the input of the reception signal and the first clock signal, adds the first clock signal to the reception signal, and outputs the result;
A frequency divider that receives the input of the first clock signal and outputs a second clock signal obtained by multiplying the frequency of the first clock signal by 1 / n (n is an arbitrary number);
A / D converter that samples a received signal obtained by adding the first clock signal and uses the second clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs the digital value When,
A jitter detector that receives the input of the digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal,
Receiving the digital value output from the A / D converter and the input of the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the digital value. And a non-uniform sampling digital filter for removing an interference wave including the second clock signal and outputting a desired wave. An A / D conversion circuit for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
A frequency divider that receives the input of the first clock signal and outputs a second clock signal obtained by multiplying the frequency of the first clock signal by 1 / n (n is an arbitrary number);
A first A / D converter that samples the reception signal using the second clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs a first digital value;
A second A / D converter that samples the first clock signal using the second clock signal as a sampling clock, holds a digital value obtained by the sampling, and outputs a second digital value Container,
A jitter detector that receives the second digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal,
Receiving the first digital value and the aperture time, calculating a filter coefficient based on the aperture time, setting the filter coefficient, and performing non-uniform sampling on the first digital value And a non-uniform sampling digital filter for removing an interference wave and outputting a desired wave. An A / D conversion method for A / D converting a received signal in a wide band digital receiver,
A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency;
A phase synchronization circuit receives the input of the first clock signal, multiplies the frequency of the first clock signal by n (n is an arbitrary number), and generates a second clock synchronized with the first clock signal. Outputs a clock signal,
An adder receiving the input of the received signal and the second clock signal, adding the second clock signal to the received signal, and outputting the added signal;
An A / D converter samples the received signal obtained by adding the second clock signal using the first clock signal as a sampling clock, holds a digital value obtained by the sampling, and And output
A jitter detector that receives the input of the digital value, calculates and outputs an aperture time based on the digital value and the frequency of the first or second clock signal,
A non-uniform sampling digital filter receives the digital value output from the A / D converter and the input of the aperture time, calculates a filter coefficient based on the aperture time, sets the filter coefficient, and sets the filter coefficient. An A / D conversion method comprising performing non-uniform sampling on a value, removing an interference wave including the second clock signal, and outputting a desired wave. A clock signal generating circuit for generating a first clock signal having an aperture jitter characteristic of a predetermined frequency; and receiving the input of the first clock signal and changing the frequency of the first clock signal to n (n is an arbitrary number). A) a phase synchronization circuit that outputs a second clock signal that is phase-synchronized with the first clock signal, and receives the input of the reception signal and the second clock signal, and An adder that adds and outputs the two clock signals; a sampling circuit that uses the first clock signal as a sampling clock to sample a received signal obtained by adding the second clock signal; and outputs a digital value obtained by the sampling. A / D conversion program for causing a computer to execute A / D conversion processing in a wide band digital receiver having an A / D converter for holding and outputting the digital value There,
Receiving the input of the digital value, calculating and outputting an aperture time based on the digital value and the frequency of the first or second clock signal;
Upon receiving the digital value output from the A / D converter and the input of the aperture time, a filter coefficient is calculated based on the aperture time, and the filter coefficient is set. An A / D conversion program for causing a computer to execute a process of performing sampling, removing an interference wave including the second clock signal, and outputting a desired wave.

Images