KR100209609B1 - Digital vsb demodulator - Google Patents

Abstract

The present invention relates to a digital VSB demodulator capable of VSB demodulation at a half-symbol period. In the conventional VSB demodulator, signal processing in the analog region is increased during carrier recovery. And fine adjustment, etc., and it is input in consideration of the fact that timing error is affected by signal aliasing by aliasing. A low frequency IF signal output unit for outputting an IF signal, an LPF for LPF outputting the low frequency IF signal output unit, an A / D converter for A / D sampling the output of the LPF at twice the frequency, and the A / D At the output of the converter, each cos ( an I / Q output section for multiplying n / 4) and obtaining I and Q signals by low pass filtering; a carrier recovery section for recovering a carrier using I and Q signals of the I / Q output section; By constructing a digital VSB demodulation device with a timing recovery unit and an equalizer that recovers and equalizes timing using the I signal of the Q output unit, carrier recovery is performed in the digital domain, and VSB demodulation is performed at half-symbol periods. It has little effect, flexibility in signal processing, easy ASIC in the future, and deterioration of signal characteristics due to timing errors.

Description

Digital VB Demodulation Device

1 is a configuration diagram of a carrier recovery unit of a conventional VSB demodulator.

2 is a configuration diagram of a timing recovery unit of a conventional VSB demodulator.

3 is a configuration diagram of an equalizer of a conventional VSB demodulator.

4 is a block diagram of a digital VSB demodulation device according to the present invention.

5 (a) to 5 (c) are structural diagrams of the I / Q output unit shown in FIG.

6 is a configuration diagram of a carrier recovery unit of FIG.

7 is a configuration diagram of a timing recovery unit of FIG.

8 and 9 are schematic diagrams of the equalizer of FIG.

* Explanation of symbols for main parts of the drawings

30: low frequency IF signal output unit 31: oscillator

32, 45 Co-45 Cn, 48 Co-48 Cn, 56: Multiplier

34: A / D converter 33, 41, 42, 52, 53, 57: LPF

35: I / Q output unit 36: carrier recovery unit

37: timing recovery unit 38: equalization unit

43, 44: Even and odd code control unit 46, 49, 50, 66: Adder

46a: code control unit 51: code control and adder

47: alignment unit 54: sign extraction unit

55, D, D1: Delay 58, 63: Decimator

59 and 60: first and second timing recovery unit 61: weighted average unit

62: forward filter 64, 65: first and second filter

The present invention relates to a digital VSB demodulator, and more particularly, to a digital VSB demodulator capable of VSB demodulation at a half symbol period.

1 is a block diagram of a carrier recovery unit of a conventional VSB demodulator, and the signal received by the antenna 1 is a tuner 2, a saw filter 3, and an intermediate frequency (hereinafter, referred to as IF). ) I (t) coswt + Q (t) sinwt signals are obtained through the amplification section 4.

The output of the IF amplifier 4 is mixed with the output of the reference oscillator 5 for outputting a sin wave equal to the carrier frequency and the mixer 6 and output as a baseband Q signal, and the IF amplifier ( The output of 4) is mixed with the signal input to the mixer 8 through the 90-degree phase shifter 7 to the output of the reference oscillator 5 and output as an I signal.

The output of the mixer 8 is mixed with the Q signal which is the output of the mixer 6 and the mixer 11 through an AFC (Automatic Frequency Control) LPF 9 and an amplifying limiter 10, and then APC (Automatic). Phase Control) Input to the VCO 13 through the LPF 12, the oscillation frequency is changed in accordance with the output of the APC LPF 12 to be used for tuning the tuner (2).

Here, the AFC LPF (9), amplification limiter 10, mixer 11, APC LPF (12), VCO (13) forms a PLL loop, the AFC LPF (9), amplification limiter (10), mixer 11 corresponds to a phase detector in the PLL loop.

2 is a block diagram of a timing recovery unit of a conventional VSB demodulator, and analog-digital sampling of the I signal obtained through the mixer 8 by the A / D converter 14 is performed.

The output of the A / D converter 14 is input to the segment synchronization signal from the data segment synchronization detector 15 and the PLL 16, and the PLL 16 outputs the A / D converter 14 to the A / D converter 14. It will provide a D-sampling clock.

The AGC (Automatic Gain Control) generation unit 17 supplies the AGC signal to the tuner 2 according to the segment synchronization signal of the data segment synchronization detection unit 15.

3 is a block diagram of an equalizer of a conventional VSB demodulator, in which an output of the A / D converter 14 of the timing recovery unit is input to a subtractor 18 and subtracted from an output of a residual DC measuring unit 19. The DC component in the output of the A / D converter 14 is removed. At this time, the reason for removing the DC component is that the DC component is not equalized.

The output of the subtractor 18 is subtracted from the output of the feedback filter 22 by the subtractor 21 through the forward filter 20 to output the equalized I-channel output.

At this time, the coefficient update of the forward filter 20 and the feedback filter 22 is performed as follows.

One is selected by the multiplexer MUX1 between the output of the slicer 23 for outputting the decised data information and the output of the training sequence of the training sequence 24 in the field sink and equalized as the output of the subtractor 21. The I-channel output and subtractor 25 are subtracted to obtain an error signal.

Using the error signal and the equalized I-channel output, a coefficient value to be updated in the filter coefficient calculator 26 is calculated and loaded into the feedback filter 22 as a new coefficient value, and the error signal and the subtractor ( Using the output of 18) as an input signal, the filter coefficient calculator 26 calculates the coefficient value of the forward filter 20 and loads the coefficient value into the forward filter 20 as a new coefficient value.

However, in the conventional VSB demodulator, the carrier recovery unit performs carrier recovery with an analog signal. Therefore, signal processing in the analog region is increased, so signal characteristic deterioration occurs due to deterioration of the characteristic of the analog element, and fine adjustment is necessary.

In addition, A / D conversion is performed only for the I signal at the symbol period to recover or equalize the timing. As is widely known in the communication theory, the signal processing of the symbol period causes timing errors to affect the signal characteristics by aliasing. There was a downside.

In addition, the IF analog signal is directly lowered to the baseband. In this process, a carrier having exactly 90 degrees of phase difference is required, and two A / D converters are required when performing carrier recovery in the digital domain.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to enable carrier recovery in the digital domain, and to perform signal processing with half-symbol periods to compensate signal degradation due to analog processing and to perform VSB demodulation with half-symbol periods. The present invention provides a digital VSB demodulation device capable of compensating signal degradation due to timing error.

A feature of the present invention for achieving the above object is a low frequency IF signal output unit for outputting an IF signal of a frequency lower than the input IF signal by multiplying the input IF signal with the frequency input from the outside, and the low frequency IF signal output unit An LPF for low-pass filtering the output, an A / D converter for A / D sampling the output of the LPF at twice the frequency, and a cos () at the output of the A / D converter. n / 4) and sin ( an I / Q output section for multiplying n / 4) and obtaining I and Q signals by low pass filtering; a carrier recovery section for recovering a carrier using I and Q signals of the I / Q output section; A digital VSB demodulation scheme includes a timing recovery unit for recovering timing using an I signal of a Q output unit, and an equalization unit for compensating signal degradation on a transmission channel using an I signal of the I / Q output unit.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a digital VSB demodulator according to the present invention. The IF input signal is multiplied by the frequency output of the oscillator 31 and the multiplier 32 to output an IF signal having a frequency lower than the input IF signal. A / D sampling of the low frequency IF signal output unit 30, the LPF 33 for low pass filtering the output of the low frequency IF signal output unit 30, and the output of the LPF 33 at twice the frequency. An A / D converter 34, an I / Q output unit 35 for obtaining I and Q signals from the output of the A / D converter 34, and I and Q of the I / Q output unit 35 A carrier recovery unit 36 for recovering a carrier using a signal, a timing recovery unit 37 for recovering timing using the I signal of the I / Q output unit 35, and compensating for signal degradation on a transmission channel; It consists of an equalizing unit 38.

The I / Q output unit 35 is cos ( n / 4) and sin ( multiply n / 4) to get cos ( n / 4) multiplier (39) and sin ( n / 4) a multiplier 40 and cos ( n / 4) multiplier (39) and sin ( n / 4) LPF (41), 42 for low-pass filtering the output of the multiplier (40).

At this time, if the I / Q output unit 35 is configured as described above cos ( n / 4) = 1, 0, ..., sin ( n / 4) = 0, One, As The hardware is complicated, such as the need to multiply by.

So cos ( n / 4) and sin ( By using the relationship with n / 4), it is configured as follows so as to reduce the amount of hardware by combining with the next stage LPF (41), (42).

That is, as shown in Figs. 5A to 5B, the output r (n) of the A / D converter 34 is even (r (0), r (2), r (4)). Controls the sign of the demultiplexer (DEMUX1) and the output of the demultiplexer (DEMUX1), which are divided into ... .....) and odd (r (1), r (3), r (5), .....) The even and odd code control units 43 and 44, and the even and I / Q signals for obtaining even I and Q signals according to the output of the even code control unit 43, the output unit 45 and the odd number The odd I / Q signal output unit 46 for obtaining odd-numbered I and Q signals according to the output of the sign control unit 44, and the outputs of the even and odd I / Q signal output units 45 and 46, respectively. And an alignment unit 47 for rearranging and outputting the I signal and the Q signal, respectively.

The even I / Q signal output unit 45 alternately selects a plurality of delays D for delaying the output of the even code control unit 43 and one of the inputs and outputs of the delays D, and cos. And a plurality of multiplexers MUX for selecting even-numbered inputs to sin, coefficient multipliers 45Co to 45Cn for multiplying the outputs of the multiplexer MUX by coefficients Co to Cn, and the respective coefficient multipliers 45Co to An adder 46 that adds the output of 45Cn) to obtain even-numbered, I, Q signals, and a code control unit 46a that inverts the output of the adder 46 alternately and outputs it to the alignment unit 47. It consists of.

In addition, the odd I / Q signal output unit 46 includes a plurality of delays D1 for delaying the output of the odd code control unit 44 and a coefficient multiplier for multiplying coefficients by input / output signals of the delays D1. 48Co to 48Cn and the outputs of the respective coefficient multipliers 48Co to 48Cn have the same sign of odd-numbered inputs to cos and sin, so that only the output of the same coefficient multiplier 49 is added. An adder 50 that adds only outputs having different signs of cos and sin among odd-numbered inputs to cos and sin among the outputs of the coefficient multipliers 48Co to 48Cn, and the output of the adder 50 are alternately inverted. A code control and adder 51 which adds the output of the adder 49 to obtain odd-numbered I and Q signals and outputs them to the alignment unit 47.

On the other hand, the carrier recovery unit 36 is LPF (52), 53 for low-pass filtering the I and Q signals input from the I / Q output unit 35, as shown in FIG. A code extracting unit 54 for extracting a code among the outputs of the LPF 52, a delay 55 for delaying the output of the code extracting unit 54, and the LPF 53 and the delay 55 A multiplier 56 for multiplying the output and an LPF 57 for low-pass filtering the output of the multiplier 56, wherein the LPFs 52, 53, and 57 are external bandwidth control signals ( Bandwidth control is possible according to S1).

As shown in FIG. 7, the timing recovery unit 37 receives the I signal of the I / Q output unit 35 and uses the A / D sampling frequency of the A / D converter 34 per symbol. The decimator 58 decimates the sampling twice, and the first timing recovery unit 59 performs the timing recovery using the existing segment sink from the output of the decimator 58. And a second timing recovery unit 60 for timing recovery from the I signal input from the I / Q output unit 35 in a Gardner manner, and the first and second timing recovery units 59, ( A weight averaging section 61 for adaptively mixing the outputs of the first and second timing recovery sections 59 and 60 according to the weight control signal according to the channel state is output.

In addition, the equalizer 38 further includes a decimator 63 for decimating the output of the forward filter 62 to only one sample per symbol in the conventional equalizer of FIG. 3 as shown in FIG. The same parts as in the prior art are not shown.

The forward filter 62 and the decimator 63 filter the demultiplexer DEMUX2 for demultiplexing the input I signal into odd and even numbers as shown in FIG. 9 and the even outputs of the demultiplexer DEMUX2. The first filter 64 and the output of the first filter 64 and the odd output of the demultiplexer DEMUX2 according to the equalization control signal S3 for controlling whether the equalization of the symbol period or the equalization of the half symbol period are performed. A multiplexer MUX1 for selecting one, a second filter 65 for filtering the output of the multiplexer MUX1, and outputs of the first and second filters 64 and 65 during equalization of a half symbol period. The adder 66 adds and outputs.

The IF signal input in the present invention configured as described above is multiplied by the oscillation frequency of the oscillator 31 by the multiplier 32 to obtain an IF signal of a lower frequency.

The output of the multiplier 32 is input to the A / D converter 34 through the LPF 33, and A / D sampled and output as a digital IF signal. In this case, the sampling frequency of the A / D converter 34 is Two times the conventional A / D sampling frequency fs is used. Thus, two data are sampled per symbol period.

On the other hand, the output of the A / D converter 34 is input to the I / Q output unit 35 is output as an I and Q signal through each signal processing process, its signal processing is as follows.

First, the cos (from the IF signal of the A / D converter 34) n / 4) Multiplier (39) and sin ( n / 4) When I (n) and Q (n) signals are obtained by using the multiplier 40 and the LPFs 41 and 42, cos ( n / 4) and sin ( By multiplying n / 4), I (n) and Q (n) signals are obtained, and low pass filtering is performed to LPF 41 and 42 to improve SNR.

At this time, if simply configuring the I / Q generator 35 as described above cos ( n / 4) = 1, 0, ..., sin ( n / 4) = 0, One, As ... The hardware is complicated, such as the need to multiply by.

Therefore, in the present invention, cos ( n / 4) and sin ( It is possible to reduce the amount of hardware by combining with the LPF (41), 42 of the next stage by using the relationship with n / 4), the signal processing process for this is as follows.

First, cos ( n / 4) and sin ( The value of n / 4) is as follows.

As you can see from the above relationship, cos ( n / 4) and sin ( It can be seen that redundancy exists between n / 4).

And the low pass filtering process

Where y (n): filter processing result, h (k): impulse response of the filter, x (n-k): input signal string.

Now if you break down the above equation (1)

Becomes

And if the output is also divided into even and odd

To reduce the amount of hardware, LPF is first designed as a halfband filter. The definition of the halfband filter is as follows.

Then, the formulas (2) and (3) are as shown in the following formulas (4) and (5).

That is, only odd-numbered inputs are required to obtain even-numbered outputs, and only odd-numbered inputs are required to obtain odd-numbered outputs.

Now, the signals r (n): r _c (n) and r _s (n) of the input terminals of the LPFs 41 and 42 are divided by the even-numbered input and the odd-numbered input by the demultiplexer DEMUX2. Through the odd code control units 43 and 44, the following values are obtained.

Since the characteristics of the LPF applied to each are the same, as shown above, even-numbered inputs are alternated with each other, and odd-numbered inputs can be seen to have identical inputs except for sign inversion.

The even and odd code control units 43 and 44 output even and odd numbered I and Q signals through the even I / Q signal output unit 45 and the odd I / Q signal output unit 46. And its behavior is as follows.

First, the even-numbered output is calculated as

Values inputted to the delay D of FIG. 5 (b) are r (0), r (2), -r (4), -r (6), .....

These values are alternately inputted through r (0), -r (4), ....., r (2), -r (6), etc. through the multiplexer (MUX).

These values are alternately multiplied by Co-Cn and Co '' '-Cn' '' through coefficient multipliers 45Co through 45Cn, and the results are summed in the adder 47.

At this time, the final filter output, I, Q output is alternately output to I (0), Q (0), I (2), Q (2), .....

Meanwhile, the process of calculating the odd numbered output is as follows.

In FIG. 5C, the values input to the delay D1 are r (1), r (3), -r (5), -r (7), ..... and the like.

These values are multiplied by the coefficients Co'-Cn 'in the coefficient multipliers 48Co-48Cn, and the result of the multiplication is the same value (r (1), -r (5), .....) Are summed in summator 49, and sign-inverted values (-r (3), r (7), .....) are summed in summator 50 (sum2).

Since the sums of the adders 49 are the same for both I and Q, there is no sign inversion, and the sums of the adders 50 must alternate the signs of the sums for I and Q, which is a code control and adder 51. To be done.

That is, the code control and adder 51 alternately inverts the sum sum of the adder 49 and the sum sum2 of the adder 50 and the sign of the sum sum2 of the adder 50. The code control and the output of the adder 51 are sum1 + sum2, sum1 + (-sum2), sum1 + sum2, ..... so that the I and Q signals are alternately outputted. It is input to the alignment unit 47 and output as the respective I and Q signals.

Meanwhile, the carrier recovery unit 36 low-pass filters the I and Q signals input from the I / Q output unit 35 at the LPFs 52 and 53, and the output of the LPF 53 is extracted from a code. After inputted to the unit 54, the code is extracted, the delay 55 is input to the multiplier 56, multiplied by the Q signal output through the LPF 53, and not illustrated through the LPF 57. It is input as VCO control voltage.

That is, the LPFs 52 and 53, the code extracting unit 54, the delay 55, and the multiplier 56 correspond to phase detectors of the PLL.

In addition, the LPFs 52, 53, and 57 can control the bandwidth.

Therefore, by initially adjusting the coefficients of the LPF (52), (53), (57) to increase the bandwidth, after convergence to some extent it is possible to reduce the carrier tracking range and residual jitter by using a method of narrowing the bandwidth.

The number of taps of the LPf (52), (53), and (57) does not have to be very large, and since only the delayed code bits are stored, the capacity is not so large and the multiplier 56 actually performs only the code inversion.

In addition, the timing recovery unit 37 receives the I signal of the I / Q output unit 35 from the decimator 58 and 2 per symbol by the A / D sampling frequency of the A / D converter 34. The sampled once is decimated so as to sample once.

The output of the decimator 58 is then timing-recovered via the first timing recovery unit 59 which performs timing recovery using the existing segment sink, and I from the I / Q output unit 35. The signal input is input to the second timing recovery unit 60 to recover the time by the Gardner method.

On the other hand, since the first timing recovery unit 59 samples at a symbol period, it is difficult to detect a timing error. In the VSB method, a timing sink is inserted to detect a timing error, but the segment sink is actually a segment 832 symbol. Only once each time, the convergence rate is slow and the residual jitter becomes large.

Therefore, as the timing is restored in parallel with the second timing recovery unit 60 which processes the half symbol period, the feedback speed is increased once per symbol, thereby increasing the convergence speed.

That is, since timing is started to be recovered before detecting the segment synchronization signal, there is no instability that may occur between timing recovery and segment sync detection.

In fact, the Gardner type timing recovery circuit is very simple, so there is no heavy burden in hardware. The Gardner type algorithm is as follows.

Here, Terr: timing error, Xn: symbol period data, Xn _-1/2 , Xn _+1/2 : data on the left and right half-symbol periods.

Here, Xn may use an output of an equalizer or a signal lamp that has undergone a decision.

And this algorithm is applied to all symbol data, not just data segment sink.

On the other hand, the output of the first and second timing recovery unit 59, 60 is adaptively mixed according to the weight control signal (S2) according to the state of the channel in the weighted average unit 61 to control the voltage of the VCXO Form an input signal.

In addition, the equalizer 38 filters the I signal of the I / Q output unit 35 by the forward filter 62, and then inputs the decimator 63 to the conventional A / D converter 34. Compared to one more symbol per symbol, decimation is performed only once per symbol.

In the forward filter 62 and the decimator 63, as shown in FIG. 9, the I signals inputted by the demultiplexer DEMUX2 are divided into odd and even numbers, respectively, and the even signal is divided into the first filter 64. The odd-numbered signal is input to the multiplexer MUX2.

In this case, the input of the multiplexer MUX2 varies according to the equalization control signal S3 for determining whether the symbol period equalized or the half symbol period equalized is input to the multiplexer MUX2. The output of the first filter 64 is output through the second filter 65 through the multiplexer MUX1, and the odd-numbered output signal of the demultiplexer DEMUX2 is input to the multiplexer MUX1 when the half-symbol period is equalized. After filtering by the second filter 65, the adder 66 is added to the output of the first filter 64 and output.

In this case, the symbol period equalization and the half symbol period equalization are adaptively performed according to the user's request or channel condition. In this case, if the time difference between the pre-host and the main signal is large, the symbol period is equalized. Equalize the half-symbol cycle.

Since the other operations of the equalizer 38 are the same as in the related art, the description thereof will be omitted.

As described above, according to the present invention, carrier recovery is performed in the digital domain, and VSB demodulation is performed at a half-symbol period, which is less influenced by the characteristics of the device than the analog processing method, provides flexibility in signal processing, and facilitates ASIC. It is possible to prevent signal characteristic deterioration due to timing error.

Claims (8)

A low frequency IF signal output unit for multiplying an input IF signal by a frequency input from the outside to output an IF signal having a lower frequency than the input IF signal, an LPF for low pass filtering the output of the low frequency IF signal output unit, and the LPF An A / D converter for A / D sampling the output of twice the frequency, and cos ( n / 4) and sin ( an I / Q output section for multiplying n / 4) and then performing low pass filtering to obtain I and Q signals, a carrier recovery section for recovering a carrier using I and Q signals of the I / Q output section, and I And a timing recovery unit for recovering timing by using the I signal of the / Q output unit, and an equalizing unit for compensating signal degradation on the transmission channel using the I signal of the I / Q output unit. The output device of claim 1, wherein the I / Q output unit comprises: a demultiplexer for dividing the output of the A / D converter by an even number and an odd number; an even and odd code control unit for controlling a code of an output of the demultiplexer; An even I / Q signal output unit for obtaining even-numbered I and Q signals from an odd-numbered I / Q signal output unit for obtaining odd-numbered I and Q signals from an output of the odd-coded control unit, and the even and odd I / Q signals Digital VSB demodulation device comprising an alignment unit for rearranging the output of the output unit to the I signal and the Q signal, respectively. The signal output unit of claim 2, wherein the even I / Q signal output unit selects a plurality of delays for delaying the output of the even code control unit and one of the inputs of the delays to select even inputs for cos and sin, respectively. A plurality of multiplexers, a plurality of coefficient multipliers for multiplying the outputs of the multiplexers by a filter coefficient, an adder for adding the outputs of the respective coefficient multipliers, and a code for alternately sign-inverting the outputs of the adders and outputting them to the alignment unit. Digital VSB demodulation device comprising a control unit. The output of each coefficient multiplier of claim 2, wherein the odd I / Q signal output unit comprises a plurality of delays for delaying the output of the odd code control unit, a plurality of coefficient multipliers for multiplying coefficients by input / output signals of the delays, A first adder for adding only outputs having the same cos and sin sign in odd-numbered inputs to cos and sin, and outputs having different signs for cos and sin in odd-numbered inputs for cos and sin in the outputs of the coefficient multipliers And a code control and adder for alternately sign inverting the output of the second adder and adding the output of the first adder to the alignment unit. 2. The apparatus of claim 1, wherein the carrier recovery unit extracts first and second LPFs for low-pass filtering I and Q signals input from the I / Q output unit, and a code extraction unit for extracting a code in an output of the first LPE. And a delay for delaying the output of the code extractor, a multiplier for sign inversion by multiplying the output of the second LPF and the delay, and a third LPF for lowpass filtering the output of the multiplier. Demodulation device. The decimator of claim 1, wherein the timing recovery unit decimates the I / Q output unit's I signal once to sample the sampling twice per symbol by the A / D sampling frequency of the A / D converter. And a first timing recovery unit for timing recovery of the output of the decimator using a segment sink, a second timing recovery unit for timing recovery from an I signal input from the I / Q output unit in a Gardner method, and The output of the first and second timing recovery unit comprises a weighted average unit for adaptively mixing the output of the output of the first and second timing recovery unit according to the weight control signal according to the channel state. The digital VSB of claim 1, wherein the equalizer includes a forward filter for filtering the I signal of the I / Q output unit, and a decimator for decimating only one output of the forward filter per symbol. Demodulation device. 8. The symbol filter of claim 7, wherein the forward filter and the data generator are a demultiplexer for separating odd and even I signals input from the I / Q output unit, an equalization of a first filter and a symbol period for filtering even outputs of the demultiplexer. A multiplexer for selecting one of an output of the first filter and an odd output of the demultiplexer, a second filter for filtering an output of the multiplexer, and a half symbol period according to an equalization control signal for controlling whether the equalization of the cognitive half-symbol period is equal. And an adder configured to add and output the outputs of the first and second filters during equalization.