JP3306736B2 - Frequency offset compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset compensating circuit for automatically compensating for a frequency error between a transmitting oscillator and a receiving oscillator in digital signal transmission.

[0002]

2. Description of the Related Art When transmitting a digital signal, it is necessary to convert the frequency of the signal into a carrier band. At this time, a difference in frequency (between a local oscillator on the transmitting side and a local oscillator on the receiving side) is generated. Frequency error) is inevitable. As means for compensating for this frequency error, Costas-type carrier regeneration with a secondary loop, a method for compensating for a stationary phase error caused by a frequency offset after delay detection, and estimating the phase variation between one symbol, and To compensate for the frequency offset.

FIG. 4 shows the configuration of the Costas-type carrier reproducing circuit. In the figure, numeral code, 39 is an input terminal, 47 is an output terminal, 40 is a distributor, 41 and 42 are multipliers, 43 is a phase error extractor, 43-1 is an adder, 43
-2 is a subtractor, 44 is a π / 2 phase shifter, 46 is a loop filter, 45 is a voltage controlled oscillator (Voltage Controlled Osc).
illator: VCO).

In FIG. 1, a modulated signal in a carrier band is inputted from a terminal 39, and VC signals having phases different from each other by π / 2 are provided.
The product is detected by the O output signal and output from the terminal 47. On the other hand, the phase error extractor removes the modulation component by quadrupling the signal after the product detection, and detects the phase error between the VCO output signal and the carrier of the modulated wave.

By feeding back this phase error component to the VCO via the loop filter, it is possible to form a second-order PLL loop and simultaneously suppress the frequency error and the phase error. That is, the VCO, the phase error extraction, and the loop filter reproduce the carrier having the same phase as the carrier of the modulated wave to realize the demodulation operation.

FIG. 5 shows a configuration to which the above method is applied. In the figure, numeral 48 is an input terminal, 51 is an output terminal, 49 is a delay detection circuit, and 50 is a phase error compensator for compensating for a steady phase error after the delay detection. In the figure, the modulated signal whose frequency has been converted to the baseband is
8 and the delay detection circuit multiplies this input signal by the input signal before the symbol, and outputs the result to the phase error compensator.

In this configuration, the frequency error in the input signal appears as a stationary phase error for the demodulated signal and significantly degrades the demodulation characteristics. Therefore, the phase error compensator can compensate the frequency error equivalently by compensating the steady phase error.

FIG. 6 shows a configuration example to which the above method is applied.
In the figure, RLS (Recurisive L
east Squares) algorithm is applied to perform frequency offset estimation only in a training section.

In the figure, 51a is an input terminal, 59 is an output terminal, 52 is a complex multiplier, 53 is a training signal input terminal, 54 is a phase estimator by the RLS algorithm, 55 is a phase integrator, and 58 is a complex multiplier. It is. In this configuration, after removing the modulation component from the input signal, the phase fluctuation between one symbol is estimated by the RLS algorithm, and the phase is inverted by estimating the phase opposite to the phase fluctuation due to the frequency offset. The effect of the frequency offset is removed by multiplication.

On the other hand, as the bit rate is increased, the characteristic deterioration due to the waveform distortion of the transmission path becomes remarkable, and the application of an adaptive equalizer is being studied to compensate for this. Examples of the adaptive equalizer include a linear equalizer, a decision feedback equalizer, and a maximum likelihood sequence estimation (Mzximum Likelihood Sequence Estimation:
(MLSE) type equalizers are known. In particular, the MLSE-type equalizer has a maximum likelihood sequence estimator that minimizes the bit error rate, and therefore exhibits much higher equalization capability than the other two methods. The configurations of these equalizers are shown in FIGS.

In general, in an adaptive equalizer, fractional samples are applied in order to avoid characteristic degradation due to sampling phase errors in a received signal. When compensating for a frequency offset in a system using this adaptive equalizer,
Since the above method basically assumes symbol sampling, it cannot be applied to a fractional sampling system.

On the other hand, the method can be realized by providing a linear equalizer for fractional sampling or a decision feedback equalizer in the Costas loop. FIG. 7 shows the configuration in this case.

In the same figure, 77 is an input terminal, 84 is an identification result output terminal, 78 is a distributor, 79 and 80 are multipliers, 8
1 is an adaptive equalizer, 82 and 83 are discriminators, 85 is a complex correlator, 86 is a loop filter, 87 is a VCO, and 88 is π /
2 shows a two-phase shifter. The 85 complex correlator performs the operation shown in "Equation 1" using the equalizer output signal Ur + jUi and the identification signal Dr + jDi.

[0014]

(Equation 1)

The frequency offset can be estimated by this configuration because the linear equalizer and the decision feedback equalizer only remove the waveform distortion using the received signal or the past identification signal of the equalizer. That is, the output signal of the equalizer can be regarded as a demodulated signal by synchronous detection in a transmission line without waveform distortion.

That is, a signal from which the influence of delay distortion has been removed is output to the output 64 in FIG. 8 and to the output 70 in FIG. However, since the MLSE-type equalizer does not demodulate the signal but estimates the transmission code sequence having the highest likelihood for the received signal, the MLSE-type equalizer uses a configuration similar to a linear equalizer or a decision feedback equalizer. No demodulated signal is generated inside the equalizer.

Therefore, it is difficult to apply the MLSE equalizer in the loop. As another configuration, there is a configuration in which frequency offset detection is performed by a matched filter and frequency offset compensation is performed based on the frequency offset detection.

The matched filter can remove the influence of the noise on the delay distortion, thereby enabling accurate frequency offset compensation. The configuration is shown in FIG. In the figure, 89 is an input terminal, 98 is an output terminal, 90 is a divider, 91 and 92 are multipliers, 93 is a π / 2 phase shifter, 94 is a VCO, and 95 is 1
A next filter, 96 is a delay circuit, and 97 is a frequency offset compensator.

FIG. 12 shows the configuration of the frequency offset estimator. In the figure, 99 is an input terminal, 100 and 101 are oscillators having frequencies of -δ and + δ, 104 and 105 are matched filters, 106 is a delay circuit, 107 is a complex multiplier,
108 denotes a complex adder, 109 and 110 denote absolute value operation circuits, and 111 denotes a subtractor.

Although this frequency offset estimator utilizes the fact that the value of the correlation peak differs in principle due to the frequency offset, there is a problem that the imbalance between the frequencies of the oscillators 100 and 101 affects the estimation accuracy. is there.

Further, since this configuration is basically feedback control to the VCO, there is a trade-off relationship between the band of the loop filter and the frequency offset estimation accuracy, and the estimation accuracy is reduced to obtain a high-speed convergence characteristic. There is a problem to make it.

Therefore, when the MLSE type equalizer to which the fractional sample is applied is applied, it is difficult to estimate the frequency offset with high accuracy, and there is a problem that the transmission characteristic is deteriorated by the frequency offset.

[0023]

In digital signal transmission using the frequency of a carrier band, there is a frequency error between local oscillators of a transceiver. To demodulate an accurate signal even when phase modulation or frequency modulation is applied, it is necessary to compensate for this frequency error.

On the other hand, an adaptive equalizer is effective for compensating waveform distortion caused by delay dispersion, but an MLSE equalizer having higher equalizing ability is effective. Furthermore, in order to reduce the sampling phase error sensitivity, it is desirable to use an MLSE equalizer of fractional sampling.

However, as described above, the MLSE-type equalizer only estimates a transmission sequence having the highest likelihood for a received signal and does not correspond to a demodulation operation. Cannot be applied to the MLSE type equalizer.

In the method of establishing the frequency synchronization by feeding back the frequency error information from the matched filter to the VCO, the frequency offset can be compensated without using an adaptive equalizer in a frequency selective fading environment. In order to obtain high-speed convergence characteristics, there is a disadvantage that the frequency estimation accuracy is reduced.

Therefore, when an MLSE-type equalizer to which fractional sampling is applied is used, it is difficult to accurately and quickly estimate a frequency offset, and there is a problem that a frequency offset estimation error deteriorates characteristics.

In view of these problems, an object of the present invention is to provide a high-accuracy and high-speed frequency offset compensation method for an MLSE type equalizer to which a fractional sample is applied.

[0029]

According to the present invention, the above-mentioned object is solved by the means described in the claims.

That is, a first aspect of the present invention provides a correlation detector for detecting a correlation value between a reception signal and a transmission signal, and a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from the output signal. A frequency offset compensating circuit configured by a phase compensator that removes the frequency offset of the received signal based on the estimated frequency offset,

A known transmission signal over N time is stored, the output signal 1 is given a phase rotation by a frequency offset, multiplied by a reception signal corresponding to the output signal 1, and the output signal 2 is converted into N time. A correlation detector to be integrated over, and an output signal of the correlation detector with respect to a phase change within one time due to the frequency offset, to detect a change amount of a sum of squares,

A frequency offset estimator for estimating the phase fluctuation within one hour and updating the phase fluctuation within one hour as an output of the frequency offset estimator by updating the estimated value of the phase fluctuation so that the sum of squares becomes maximum. 2 is a frequency offset compensating circuit including a phase compensating unit for removing a frequency offset of a received signal.

According to a second aspect of the present invention, in the first aspect of the present invention, the correlation detector estimates a phase variation corresponding to a phase change amount over the K time in the known transmission signal at the time K stored in the memory. The value is multiplied by the K-th power, and this is multiplied by the received signal and output.
Over to

The output signals are integrated, and the result is used as the output of the correlation detector. The frequency offset estimator adds the known signal at the time K, which is the output of the memory provided in the correlation detector, to K- A phase change over one hour is given and output, and this is performed over N-1 hours. This output is integrated, and the output is multiplied by the output signal of the correlation detector. Estimate the phase fluctuation as the update amount of the estimated value of, and output this to the correlation detector,

Based on the updated amount of phase fluctuation, the correlation detector and the frequency offset estimator perform the above-described operation, and after repeating the above operations a plurality of times, the phase compensator passes the received signal at time L to time L. This is a frequency offset compensation circuit configured to remove a frequency offset by multiplying the amount of phase variation.

According to a third aspect of the present invention, there is provided a correlation detector for detecting a correlation value between a received signal and a transmitted signal, a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from an output signal thereof, Frequency offset compensating circuit composed of a phase compensating unit that removes the frequency offset of the received signal based on the obtained frequency offset,

The correlation detector includes a register circuit for storing a reception signal over N times, a sequence memory circuit for storing a known transmission signal pattern over N times, and an output signal from the frequency offset estimator. A vector phase compensating circuit that outputs two series of vectors of N rows, a first multiplier array that receives the first output vector and an output vector from the series memory circuit, and an output vector and an output of the register circuit. A second multiplier train having a vector as an input, and an adder for adding each element of the output vector, and the adder output signal as a correlator output signal;

The vector phase compensation circuit includes N multipliers for multiplying an input signal by an output signal from the frequency offset estimator, and each multiplier receives an output of another multiplier as an input, and outputs the output of the other multiplier. Connected to the inputs of another multiplier, the N output signals of each multiplier being a first vector output, the N input signals of the multiplier being a second vector output,

The frequency offset estimator includes a second vector output of the vector phase compensating circuit, a third series of multipliers for inputting a series memory circuit output vector of the correlation detector, and elements of the output vector. An adder for adding, a first multiplier for multiplying the output signal by the correlator output signal, a memory circuit for storing a scaling coefficient, and a second circuit for multiplying the memory circuit output signal by the first multiplier output. It is composed of two multipliers and an integrating circuit for accumulating and adding the outputs.

The output of the integrating circuit is used as the output of the frequency offset estimator. The multiplier column receives two vectors having the same dimensions as inputs and multiplies the number of dimensions by which the elements of the corresponding rows of each vector are multiplied. Output a vector having the multiplier output signal as an element,

The phase compensator multiplies the output signal of the frequency offset compensating circuit by one input and the output signal of one time earlier as the other input, and a third multiplier by the input signal. The frequency offset compensating circuit includes a fourth multiplier, and uses the output signal of the fourth multiplier as a final output signal.

[0042]

When the transmission code sequence is x _k , the fractionally sampled transmission signal S _k is given by “Equation 2”.

[0043]

(Equation 2)

In "Equation 2", the subscript k represents time, and h
_i indicates the impulse response of the transmission band limiting filter. However, in the case of a fractional sample, time k
Is represented by a rational number, not an integer. Also, x _k and S
_k is generally represented by a complex number. Here, assuming that the received signal is r _k , the output signal y _k of the correlator over the interval of time L is given by “Equation 3”.

[0045]

(Equation 3)

In the equation (3), * means complex conjugate. If, in the absence of frequency offset, the received signal r _k is equal to S _k. At that time, the output signal y _k of the correlator completely has only a real part and takes the maximum value. When there is a frequency offset ω / (2π), the output y _{k of the} correlator is as shown in “Equation 4”.

[0047]

(Equation 4)

Here, for the sake of simplicity, a case where sampling is performed at twice the symbol period is shown. In equation (4), Ts indicates a sampling period, and L / 2 (ae
ven + aodd) indicates the output of the correlator when there is no frequency offset.

Therefore, by performing phase correction on the input signal so that the output signal of the correlator is maximized, it is possible to estimate the frequency offset for an arbitrary sampling rate. Here, assuming that a phase variation term due to a frequency offset between sampling periods is w, the output signal y _k of the correlator that has been frequency offset compensated is given by “Equation 5”.

[0050]

(Equation 5)

The optimum weight coefficient W _opt is given as a solution of “ _Equation 6”. Although this equation is a nonlinear equation, a solution can be actually obtained by applying the LMS algorithm.

[0052]

(Equation 6)

In this case, as described above, the tap coefficient W is controlled by the LMS algorithm so that y _k ² is maximized. The frequency offset estimation algorithm of the present invention to which LMS is applied is shown below.

[0054]

(Equation 7)

In Expression 7, μ is a step size parameter indicating the update step size. By repeatedly performing “Equation 7”, that is, when n → ∞, w _n → w _opt
Converges to W _opt estimated by this algorithm
Can be used to realize frequency offset compensation as shown in "Equation 8".

However, it is assumed that W0 = 1 + j · 0.

[0057]

(Equation 8)

[0058]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 1 shows a configuration example of the present invention. FIG. 1 shows a configuration in a case where frequency offset estimation is performed using only a unique word pattern at the head or middle of a burst in burst signal transmission.

In the figure, numeral 1 is an input terminal, 5 is an output terminal, 6 to 8 are switches for switching between burst and data, 2 is a correlator, 3 is a frequency offset estimator, 4 is a phase compensator, 9 is A transmission signal sequence memory, 10 is a vector phase compensator, 11 and 13 are multiplier arrays, 12, 14, 21,.
25, 26, 31, and 33 are complex multipliers, and 19 and 24 are N
Input complex adder, 29 is a two-input complex adder, 17 is an N-stage shift register, 18 and 28 and 32 are delay circuits, 27
Indicates a coefficient memory circuit.

During the training period, the switch 6 is turned “ON”, and the input signal is stored in the shift register 17. On the other hand, the output of the transmission signal sequence memory in which the complex conjugate of the transmitted unique word pattern is stored is input to the multiplier array 11, and is multiplied by the output vector of the vector phase compensator.

Since the vector phase compensator performs phase compensation on each received signal based on the estimated frequency offset, the output signal of the multiplier train outputs a transmission code sequence when there is a frequency offset. . next,
The correlation operation between the output of the shift register 17 and the output of the multiplier array 11 is performed by the multiplier array 13 and the complex adder 19.

The correlator output signal is input to the frequency offset estimator. The frequency offset estimator performs a correlation operation between elements of the phase compensation vector and the transmission signal sequence vector from the vector phase compensator by using the multiplier train 20 and the complex adder 24.
Perform in. This complex adder output signal is multiplied by the correlator output signal.

Next, this output signal is weighted by a signal from the gain memory 27 and input to an integrator constituted by an adder and a delay circuit. The output signal of this integrator becomes the frequency offset estimation result, and is input to the vector phase compensator provided in the correlator. By repeating this series of calculations, an accurate frequency offset can be estimated.

Next, in the data section, the switches 7 and 8 are turned on, and data is input to the phase compensator 4. In the phase compensator 4, the output signal of the frequency offset estimator is input to a phase integrating circuit composed of a multiplier 31 and a delay circuit 32, converted into a phase change amount, and the result is multiplied by the multiplier 22 to the input signal. The frequency offset compensation is performed by matching.

FIG. 2 shows an example of the configuration of the vector phase compensator. In the figure, 33 is a complex conjugate converter, 34 is a memory circuit of coefficient “1”, 37-1 is an output vector into the correlator, 37-2 is an output vector to the frequency offset estimator 36 is a complex multiplier, 38 is a coefficient memory, and 35 is a signal input terminal from the frequency offset estimator.

Here, the frequency is converted to a phase by estimating and raising the frequency offset to the power, and this is output as a vector for each time. On the other hand, a vector corresponding to the differential term is output to 37-2. FIG. 3 shows, as an application example of the present invention, a configuration in a case where it is combined with an MLSE type equalizer.

In the figure, 113 is an input terminal, 119 is an output terminal, 114 is a divider, 115 and 116 are multipliers,
117 is the frequency offset compensator of the present invention, and 118 is M
LSE type equalizer, 120 denotes a π / 2 phase shifter, and 121 denotes a fixed oscillator. The input carrier band modulation signal is quasi-synchronously detected by the fixed oscillator 121 and input to the frequency offset estimator 117 as a signal having a beat component.

This signal has its beat component removed by a frequency offset estimator and is input to the MLSE type equalizer. The MLSE-type equalizer estimates the transmission sequence having the highest likelihood for the received signal and outputs the estimated transmission sequence to 119.

[0069]

Since the present invention utilizes a configuration using a matched filter, the effect of intersymbol interference due to the effect of delay distortion is eliminated, and frequency offset estimation can be performed with high accuracy. The accuracy can be further increased by increasing the number of repetitions of the estimation. Therefore, there is an advantage that frequency offset compensation can be performed with high accuracy from the first received burst. Furthermore, since there is no limitation on the sampling frequency of the matched filter, there is an advantage that any sampling rate can be handled.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of a vector phase compensator.

FIG. 3 is a diagram showing a configuration when the present invention is combined with an MLSE type equalizer.

FIG. 4 is a diagram illustrating an example of a configuration of a Costas-type carrier reproducing circuit.

FIG. 5 is a diagram illustrating a configuration example of frequency offset compensation by delay detection and stationary phase error compensation.

FIG. 6 is a diagram illustrating a configuration example of frequency offset compensation based on estimation of phase variation between symbols.

FIG. 7 is a diagram illustrating a configuration example of carrier regeneration when an equalizer is provided in a loop.

FIG. 8 is a diagram illustrating a configuration example of a linear equalizer.

FIG. 9 is a diagram illustrating a configuration example of a decision feedback equalizer.

FIG. 10 is a diagram illustrating a configuration example of an MLSE-type equalizer.

FIG. 11 is a diagram illustrating a configuration example of frequency offset compensation using a matched filter.

FIG. 12 is a diagram illustrating a configuration example of a frequency offset estimating unit.

[Explanation of symbols]

1,35,48,51a, 77,60,65,71,8
9, 99, 113 input terminals 5, 37-1, 37-2, 47, 51, 59, 84, 6
4, 70, 74, 98, 112, 119 Output terminal 2 Correlator 3 Frequency offset estimator 4 Phase compensator 10 Vector phase compensator 9 Transmission signal sequence memory 27, 34, 38 Coefficient memory 6, 7, 8 Switch 11, 13,20 Multiplier sequence 12,21,22,31,36,41,42,52,5
6,58,79,80,62,67,91,92,10
7, 115, 116 Multipliers 19, 24, 29, 43-1, 63, 68, 72 Adders 43-2 Subtractors 18, 28, 32, 57, 61, 66, 96, 106
Delay circuit 40, 77, 90, 114 Distributor 44, 88, 93, 120 π / 2 phase shifter 45, 87, 94 VCO 100, 103, 121 Fixed oscillator 45, 86, 95 Loop filter 43 Phase error extraction circuit 49 Delay detection circuit 50 phase error compensator 54 phase estimator 55 phase integrator 81 adaptive equalizer 69, 82, 83 discriminator 85 complex correlator 75 tapped delay line filter 76 transmission path estimator 73 maximum likelihood sequence estimator 97 Frequency offset estimator 104, 105 Matched filter 117 Frequency offset compensator 118 MLSE type equalizer

Claims (3)

(57) [Claims] 1. A correlation detector for detecting a correlation value between a received signal and a transmitted signal, a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from an output signal thereof, and a frequency offset estimator based on the estimated frequency offset. A frequency offset compensating circuit comprising a phase compensating unit for removing a frequency offset of a received signal, stores a known transmission signal over N time, and gives a phase rotation by the frequency offset to the output signal 1. , A correlation detector that multiplies the received signal corresponding to the output signal 1 and integrates the output signal 2 over N times, and an output signal of the correlation detector for a phase change within one time caused by the frequency offset. Detects the amount of change in the sum of squares, updates the estimated value of phase fluctuation so that the sum of squares is maximized, and turns off the frequency to estimate the phase fluctuation within one hour Tsu DOO estimator and frequency offset compensation circuit, characterized in that it is composed of a phase compensation unit for removing a frequency offset of the received signal based on the phase variation within one hour, which is the output of the frequency offset estimator. 2. The correlation detector multiplies a known transmission signal at time K stored in a memory by an estimated value of a phase variation corresponding to a phase change amount over K times to the Kth power, and multiplies the received signal by this. The output is multiplied and output over a memory address section N, the output signals are integrated, and the result is used as a correlation detector output. A frequency offset estimator is provided in a memory provided in the correlation detector. The known transmission signal at time K, which is the output, is given a phase change amount over K-1 hours and output, and this is performed over N-1 hours, and this output is integrated, and the output of the correlation detector is added thereto. The signals are multiplied, the phase fluctuation is estimated as an update amount of the estimated value of the phase fluctuation amount within one time, the phase fluctuation is output to the correlation detector, and the correlation detector and the correlation detector are updated based on the updated phase fluctuation amount. Frequency offset 2. The frequency compensator according to claim 1, wherein the integrator performs the above-described operation, and after repeating the operation a plurality of times, the phase compensator removes the frequency offset by multiplying the received signal at time L by the amount of phase fluctuation over time L. Frequency offset compensation circuit. 3. A correlation detector for detecting a correlation value between a reception signal and a transmission signal, a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from the output signal, and a frequency offset estimator based on the estimated frequency offset. A frequency offset compensating circuit comprising a phase compensator for removing a frequency offset of a received signal, wherein the correlation detector stores a received signal over N times, and a known transmission signal over N times. A series memory circuit for storing patterns, a vector phase compensation circuit for receiving an output signal from the frequency offset estimator as input and outputting two series of N-row vectors, and a first output vector and an output from the series memory circuit A first series of multipliers for inputting a vector, and a second series of inputting the output vector and the output vector of the register circuit. A multiplier array, and an adder for adding the elements of the output vector to each other. The adder output signal is used as a correlator output signal. The vector phase compensation circuit outputs an output from the frequency offset estimator to an input signal. N multipliers for multiplying the signals are provided, each of which is connected to receive the output of another multiplier as an input and to input the output of the other multiplier as an input to another multiplier. The output signal is a first vector output, the N input signals of the multiplier are a second vector output, the frequency offset estimator is a second vector output of the vector phase compensation circuit and the correlation detector of the A third series of multipliers which are input to the series memory circuit output vector, an adder which adds elements of the output vector, and a first which multiplies the output signal by the correlator output signal. A multiplier, a memory circuit set aside a scaling factor,
A second multiplier for multiplying the output signal of the scale circuit by the first multiplier output, and an accumulator circuit for accumulatively adding the output; the accumulator circuit output is used as the output of the frequency offset estimator; Is provided with multipliers of the number of dimensions for inputting two vectors having the same dimension and multiplying elements of the corresponding rows of each vector, and outputs a vector having the multiplier output signal as an element; The compensator is a third multiplier that uses the output of the frequency offset compensation circuit as one input and the output signal one time earlier as the other input, and a fourth multiplier that multiplies the output signal by the input signal. And a fourth multiplier output signal as a final output signal.