JP2004172587A5 - - Google Patents

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Publication number
JP2004172587A5
JP2004172587A5 JP2003356195A JP2003356195A JP2004172587A5 JP 2004172587 A5 JP2004172587 A5 JP 2004172587A5 JP 2003356195 A JP2003356195 A JP 2003356195A JP 2003356195 A JP2003356195 A JP 2003356195A JP 2004172587 A5 JP2004172587 A5 JP 2004172587A5
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Japan
Prior art keywords
wiring
forming
support substrate
manufacturing
semiconductor device
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JP2003356195A
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Japanese (ja)
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JP2004172587A (en
JP4562371B2 (en
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Priority to JP2003356195A priority Critical patent/JP4562371B2/en
Priority claimed from JP2003356195A external-priority patent/JP4562371B2/en
Publication of JP2004172587A publication Critical patent/JP2004172587A/en
Publication of JP2004172587A5 publication Critical patent/JP2004172587A5/ja
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Publication of JP4562371B2 publication Critical patent/JP4562371B2/en
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Claims (15)

第１の配線が形成された半導体ウエハの表面上に第１の支持基板を貼り合わせる工程と、
前記半導体ウエハの裏面側に第２の支持基板を貼り合わせる工程と、
前記第２の支持基板の裏面からダイシングラインに沿って、前記第１の支持基板に至るまで切削を行うことによって溝を形成し、前記第１の配線を部分的に露出させる工程と、
前記第１の配線の露出部分に接続され、前記第２の支持基板の表面に延在する第２の配線を形成する工程と、
前記第２の配線の表面に、スプレーコートにより、有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第２の配線を露出する開口部を形成する工程と、を具備することを特徴とする半導体装置の製造方法。 Bonding the first support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Bonding a second support substrate to the back side of the semiconductor wafer;
Forming a groove by cutting from the back surface of the second support substrate along the dicing line to the first support substrate, and partially exposing the first wiring;
Forming a second wiring connected to an exposed portion of the first wiring and extending to a surface of the second support substrate;
Forming a protective film made of an organic resin on the surface of the second wiring by spray coating;
And a step of forming an opening exposing the second wiring at a predetermined position of the protective film. 前記第２の支持基板上に、スプレーコートにより、緩衝部材を形成する工程を具備することを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a buffer member on the second support substrate by spray coating. 前記保護膜の表面に、スプレーコートにより、レジスト層を形成する工程を具備することを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a resist layer on the surface of the protective film by spray coating. 前記開口部に露出された第２の配線上に導電端子を形成する工程を具備することを特徴とする請求項１，２，３のいずれかに記載の半導体装置の製造方法。   4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a conductive terminal on the second wiring exposed in the opening. 第１の配線が形成された半導体ウエハの表面上に支持基板を貼り合わせる工程と、
前記半導体ウエハの裏面に溝を形成し、前記第１の配線を部分的に露出させる工程と、
前記第１の配線の露出部分に接続され、前記半導体ウエハの裏面に延在する第２の配線を形成する工程と、
前記第２の配線の表面にスプレーコートにより有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第２の配線を露出する開口部を形成する工程と、を具備す
ることを特徴とする半導体装置の製造方法。 Bonding a support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Forming a groove on a back surface of the semiconductor wafer to partially expose the first wiring;
Forming a second wiring connected to the exposed portion of the first wiring and extending to the back surface of the semiconductor wafer;
Forming a protective film made of an organic resin by spray coating on the surface of the second wiring;
And a step of forming an opening exposing the second wiring at a predetermined position of the protective film. 前記半導体ウェハの裏面に、スプレーコートにより、緩衝部材を形成する工程を具備することを特徴とする請求項５に記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a buffer member on the back surface of the semiconductor wafer by spray coating. 前記保護膜の表面に、スプレーコートにより、レジスト層を形成する工程を具備することを特徴とする請求項５または請求項６に記載の半導体装置の製造方法。   7. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming a resist layer on the surface of the protective film by spray coating. 前記開口部に露出された第２の配線上に導電端子を形成する工程を具備することを特徴とする請求項５，６，７のいずれかに記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a conductive terminal on the second wiring exposed in the opening. 前記有機系樹脂は、熱硬化性を有することを特徴とする請求項１，２，３，４，５，６，７，８のいずれかに記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 1, wherein the organic resin has thermosetting properties. 前記有機系樹脂は、エポキシ樹脂であることを特徴とする請求項１，２，３，４，５，６，７，８，９のいずれかに記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the organic resin is an epoxy resin. 第１の配線が形成された半導体ウエハの表面上に、第１の支持基板を貼り合わせる工程と、
前記半導体ウェハを、当該半導体ウェハの裏面からダイシングラインに沿ってエッチングして、複数の半導体チップに分離する工程と、
前記複数の半導体チップの裏面側に、樹脂を介して第２の支持基板を貼り合わせる工程と、
前記ダイシングラインに沿って、前記第２の支持基板の裏面から、前記第２の支持基板及び前記樹脂を切削し、さらに前記第１の支持基板の一部を切削することによって溝を形成し、前記第１の配線を部分的に露出させる工程と、
前記第１の配線の露出部分に接続され、前記第２の支持基板の表面に延在する第２の配線を形成する工程と、
前記第２の配線の表面に、スプレーコートにより、有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第２の配線を露出する開口部を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 Bonding the first support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Etching the semiconductor wafer from the back surface of the semiconductor wafer along a dicing line, and separating the semiconductor wafer into a plurality of semiconductor chips;
Bonding the second support substrate to the back side of the plurality of semiconductor chips via a resin;
Along the dicing line, from the back surface of the second support substrate, cut the second support substrate and the resin, and further form a groove by cutting a part of the first support substrate, Partially exposing the first wiring;
Forming a second wiring connected to an exposed portion of the first wiring and extending to a surface of the second support substrate;
Forming a protective film made of an organic resin on the surface of the second wiring by spray coating;
Forming an opening exposing the second wiring at a predetermined position of the protective film;
A method for manufacturing a semiconductor device, comprising: 前記第２の支持基板上に、スプレーコートにより、緩衝部材を形成する工程を具備することを特徴とする請求項１１に記載の半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a buffer member on the second support substrate by spray coating. 前記保護膜の表面に、スプレーコートにより、レジスト層を形成する工程を具備することを特徴とする請求項１１または請求項１２に記載の半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a resist layer on the surface of the protective film by spray coating. 前記開口部に露出された第２の配線上に導電端子を形成する工程を具備することを特徴とする請求項１１，１２，１３のいずれかに記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a conductive terminal on the second wiring exposed in the opening. パターニング時のマスク材としてレジスト層を使用する工程において、スプレーコートを用いることを特徴とする請求項１，５，１１のいずれかに記載の半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 1, wherein spray coating is used in the step of using a resist layer as a mask material at the time of patterning.
JP2003356195A 2002-10-30 2003-10-16 Manufacturing method of semiconductor device Expired - Fee Related JP4562371B2 (en)

Priority Applications (1)

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JP2003356195A JP4562371B2 (en) 2002-10-30 2003-10-16 Manufacturing method of semiconductor device

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Application Number Priority Date Filing Date Title
JP2002315418 2002-10-30
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JP2010021808A Division JP5258807B2 (en) 2002-10-30 2010-02-03 Manufacturing method of semiconductor device

Publications (3)

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JP2004172587A JP2004172587A (en) 2004-06-17
JP2004172587A5 true JP2004172587A5 (en) 2006-11-30
JP4562371B2 JP4562371B2 (en) 2010-10-13

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4936695B2 (en) * 2004-09-29 2012-05-23 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
JP2008166381A (en) * 2006-12-27 2008-07-17 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
JP5101157B2 (en) * 2007-05-07 2012-12-19 オンセミコンダクター・トレーディング・リミテッド Manufacturing method of semiconductor device

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* Cited by examiner, † Cited by third party
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IL123207A0 (en) * 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
JP2001053033A (en) * 1999-08-12 2001-02-23 Texas Instr Japan Ltd Dicing method of semiconductor device
JP3664432B2 (en) * 2000-05-18 2005-06-29 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP3455948B2 (en) * 2000-05-19 2003-10-14 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP3879816B2 (en) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE

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