JP2004172587A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2004172587A5 JP2004172587A5 JP2003356195A JP2003356195A JP2004172587A5 JP 2004172587 A5 JP2004172587 A5 JP 2004172587A5 JP 2003356195 A JP2003356195 A JP 2003356195A JP 2003356195 A JP2003356195 A JP 2003356195A JP 2004172587 A5 JP2004172587 A5 JP 2004172587A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- forming
- support substrate
- manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (15)
前記半導体ウエハの裏面側に第2の支持基板を貼り合わせる工程と、
前記第2の支持基板の裏面からダイシングラインに沿って、前記第1の支持基板に至るまで切削を行うことによって溝を形成し、前記第1の配線を部分的に露出させる工程と、
前記第1の配線の露出部分に接続され、前記第2の支持基板の表面に延在する第2の配線を形成する工程と、
前記第2の配線の表面に、スプレーコートにより、有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第2の配線を露出する開口部を形成する工程と、を具備することを特徴とする半導体装置の製造方法。 Bonding the first support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Bonding a second support substrate to the back side of the semiconductor wafer;
Forming a groove by cutting from the back surface of the second support substrate along the dicing line to the first support substrate, and partially exposing the first wiring;
Forming a second wiring connected to an exposed portion of the first wiring and extending to a surface of the second support substrate;
Forming a protective film made of an organic resin on the surface of the second wiring by spray coating;
And a step of forming an opening exposing the second wiring at a predetermined position of the protective film.
前記半導体ウエハの裏面に溝を形成し、前記第1の配線を部分的に露出させる工程と、
前記第1の配線の露出部分に接続され、前記半導体ウエハの裏面に延在する第2の配線を形成する工程と、
前記第2の配線の表面にスプレーコートにより有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第2の配線を露出する開口部を形成する工程と、を具備す
ることを特徴とする半導体装置の製造方法。 Bonding a support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Forming a groove on a back surface of the semiconductor wafer to partially expose the first wiring;
Forming a second wiring connected to the exposed portion of the first wiring and extending to the back surface of the semiconductor wafer;
Forming a protective film made of an organic resin by spray coating on the surface of the second wiring;
And a step of forming an opening exposing the second wiring at a predetermined position of the protective film.
前記半導体ウェハを、当該半導体ウェハの裏面からダイシングラインに沿ってエッチングして、複数の半導体チップに分離する工程と、
前記複数の半導体チップの裏面側に、樹脂を介して第2の支持基板を貼り合わせる工程と、
前記ダイシングラインに沿って、前記第2の支持基板の裏面から、前記第2の支持基板及び前記樹脂を切削し、さらに前記第1の支持基板の一部を切削することによって溝を形成し、前記第1の配線を部分的に露出させる工程と、
前記第1の配線の露出部分に接続され、前記第2の支持基板の表面に延在する第2の配線を形成する工程と、
前記第2の配線の表面に、スプレーコートにより、有機系樹脂から成る保護膜を形成する工程と、
前記保護膜の所定位置に前記第2の配線を露出する開口部を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 Bonding the first support substrate on the surface of the semiconductor wafer on which the first wiring is formed;
Etching the semiconductor wafer from the back surface of the semiconductor wafer along a dicing line, and separating the semiconductor wafer into a plurality of semiconductor chips;
Bonding the second support substrate to the back side of the plurality of semiconductor chips via a resin;
Along the dicing line, from the back surface of the second support substrate, cut the second support substrate and the resin, and further form a groove by cutting a part of the first support substrate, Partially exposing the first wiring;
Forming a second wiring connected to an exposed portion of the first wiring and extending to a surface of the second support substrate;
Forming a protective film made of an organic resin on the surface of the second wiring by spray coating;
Forming an opening exposing the second wiring at a predetermined position of the protective film;
A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003356195A JP4562371B2 (en) | 2002-10-30 | 2003-10-16 | Manufacturing method of semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002315418 | 2002-10-30 | ||
JP2003356195A JP4562371B2 (en) | 2002-10-30 | 2003-10-16 | Manufacturing method of semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010021808A Division JP5258807B2 (en) | 2002-10-30 | 2010-02-03 | Manufacturing method of semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004172587A JP2004172587A (en) | 2004-06-17 |
JP2004172587A5 true JP2004172587A5 (en) | 2006-11-30 |
JP4562371B2 JP4562371B2 (en) | 2010-10-13 |
Family
ID=32715788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003356195A Expired - Fee Related JP4562371B2 (en) | 2002-10-30 | 2003-10-16 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4562371B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4936695B2 (en) * | 2004-09-29 | 2012-05-23 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
JP2008166381A (en) * | 2006-12-27 | 2008-07-17 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
JP5101157B2 (en) * | 2007-05-07 | 2012-12-19 | オンセミコンダクター・トレーディング・リミテッド | Manufacturing method of semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IL123207A0 (en) * | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
JP2001053033A (en) * | 1999-08-12 | 2001-02-23 | Texas Instr Japan Ltd | Dicing method of semiconductor device |
JP3664432B2 (en) * | 2000-05-18 | 2005-06-29 | カシオ計算機株式会社 | Semiconductor device and manufacturing method thereof |
JP3455948B2 (en) * | 2000-05-19 | 2003-10-14 | カシオ計算機株式会社 | Semiconductor device and manufacturing method thereof |
JP3879816B2 (en) * | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE |
-
2003
- 2003-10-16 JP JP2003356195A patent/JP4562371B2/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6586836B1 (en) | Process for forming microelectronic packages and intermediate structures formed therewith | |
CN106356340B (en) | Semiconductor devices and its manufacturing method | |
JP2002118081A5 (en) | ||
JP2005072554A5 (en) | ||
US7229846B2 (en) | Semiconductor package having an optical device and a method of making the same | |
US8822325B2 (en) | Chip package and fabrication method thereof | |
JP2005051149A5 (en) | ||
US9842794B2 (en) | Semiconductor package with integrated heatsink | |
TW201535551A (en) | Chip package and method thereof | |
CN102810520A (en) | Thermally enhanced integrated circuit package | |
US20060141750A1 (en) | Semiconductor integrated device and method for manufacturing same | |
JP2005101463A (en) | Semiconductor device and its manufacturing method | |
JP2006019429A5 (en) | ||
US20060071318A1 (en) | Methods for manufacturing semiconductor device, semiconductor device and metal mold | |
CN105118819B (en) | Wafer encapsulation body | |
KR100895820B1 (en) | Circuit substrate for semiconductor package, and method of manufacturing the same and semiconductor package having the circuit substrate | |
JP2004172587A5 (en) | ||
KR100602131B1 (en) | Semiconductor device and method for fabricating the same | |
US7727812B2 (en) | Singulation method of semiconductor device | |
JP4357278B2 (en) | Integrated circuit die fabrication method | |
JP2005311215A5 (en) | ||
JP2007103595A5 (en) | ||
JP2006100666A (en) | Semiconductor device and manufacturing method thereof | |
KR101711710B1 (en) | Semiconductor package and manufacturing method thereof | |
JP2004006670A (en) | Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |