JP2004165238A - Plastic package and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plastic package having high bonding strength of a solder resist mask without overhang on a semiconductor element connection pad and without a plated coat non-adhesion part by performing plating in an electrolytic plating method dispensing with a plated lead wire, and to provide its manufacturing method. <P>SOLUTION: The plastic package 10 has the semiconductor element connection pad 14 formed to continue with a wiring pattern 13 by etching a Cu metal layer 12 of the upper face side of a resin substrate 11, an outside terminal connection pad 15 on the lower face side, and a via 17 connecting wiring patterns 13 and 13a of upper and lower faces. The semiconductor element connection pad 14, the upper surface of the lower face side wiring pattern 13a and the side of the semiconductor element connection pad 14 are covered with an Ni and Au plating coat 18 by the electrolytic plating method. Current for plating is passed to a metal layer 12a of the lower face side, the plated lead wire does not exist, and the Ni and Au plating coat 18 is not applied to the upper face side except for the semiconductor element connection pad 14. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic package for mounting a semiconductor element and a method of manufacturing the same, and more particularly, to a semiconductor element connection pad formed by etching an upper metal layer of a resin substrate and an etching processing of a lower metal layer. And a method for manufacturing the same.
[0002]
[Prior art]
With the recent increase in the performance and miniaturization of semiconductor devices, plastic packages for mounting semiconductor devices have increased the number of external terminals for connection to the outside, the mountability of semiconductor devices, lower cost, and higher heat dissipation. From the viewpoints of characteristics, low impedance, and the like, plastic packages such as a BGA (Ball Grid Array) type having external terminals formed of solder balls and the like and a flip-chip type having a size substantially the same as that of a semiconductor element are often used. This plastic package is a single-layer or multilayer high-heat-resistant resin made of a BT resin (a resin mainly composed of bismireimide triazine) having a conductor layer formed by bonding a Cu foil to the surface, or a polyimide resin. Using a copper-clad resin substrate as a substrate, there are a type in which a semiconductor element is mounted on the copper-clad resin substrate and directly molded, and a type in which the semiconductor element is directly connected. In addition, the plastic package, which forms a plating film by an electrolytic plating method and eliminates the need for wiring for lead-out plating, thereby increasing the density of wiring and improving electrical characteristics, and a plastic package as described below, A method has been proposed (for example, see Patent Document 1).
[0003]
As shown in FIG. 9, a plastic package 50 that does not require plating lead-out wiring is made of a Ni and Au plating film 53 formed on a metal layer 52 made of Cu on both surfaces of a resin substrate 51 in a desired pattern by electrolytic plating. , A wiring pattern 54, a via 55, a semiconductor element connection pad 56, an external terminal connection pad 57, and the like, which are formed by performing an etching process using the as an etching resist mask. The plastic package 50 has a solder resist mask 58 exposing an area including the semiconductor element connection pads 56 for connecting both surfaces to the semiconductor element, and external terminal connection pads 57 for connecting to the outside from the opening. It is covered with.
[0004]
With reference to FIGS. 10A to 10D, a method of manufacturing the plastic package 50 that does not require the wiring for plating lead-out will be described. As shown in FIG. 10A, a through hole 60 for making the front and back surfaces conductive is formed in the resin substrate 51 having the Cu foil 59 bonded to the front surface, and the front, back and through holes are formed. An electroless Cu plating film is provided on the wall surface of the substrate 60, and a current is applied to the electroless Cu plating film to form an electrolytic Cu plating film, thereby forming a Cu plating film 61. Thereby, on both surfaces of the resin substrate 51, the metal layers 52 on the upper surface side and the lower surface side are formed by the Cu foil 59 and the Cu plating film 61, respectively. In the through hole 60, a via 55 for making the upper and lower metal layers 52 conductive is formed. On the upper and lower metal layers 52, a dry film is spread, and a plating resist mask 62 for exposing a desired pattern from an opening is formed by a photolithography method in which a pattern mask is brought into contact with and exposed and developed. Has formed. Next, as shown in FIG. 10B, on the metal layer 52 exposed from the opening of the plating resist mask 62, the Cu plating film 61 is energized, and the wiring pattern 54 including the wall surface of the via 55 is formed. Ni and Au plating films 53 are formed on the portions to be the device connection pads 56 and the external terminal connection pads 57 by electrolytic plating.
[0005]
Next, as shown in FIG. 10C, the plating resist mask 62 made of a dry film formed on the metal layer 52 is removed by applying a peeling solution to swell the dry film and peeling it off. Next, as shown in FIG. 10D, the metal layer 52 exposed from the Ni and Au plating films 53 is dissolved and removed by performing an etching process using the Ni and Au plating films 53 as an etching resist mask. As a result, the wiring pattern 54, the semiconductor element connection pads 56, the external terminal connection pads 57, and the like are formed. Then, on the surface of the resin substrate 51, an area including the semiconductor element connection pads 56 and a solder resist mask 58 (not shown, see FIG. 9) in which the external terminal connection pads 57 are exposed from the opening are joined. The plastic package 50 is manufactured.
[0006]
[Patent Document 1]
JP-A-11-2977891 (pages 1-11, FIG. 1-3)
[0007]
[Problems to be solved by the invention]
However, the above-mentioned conventional plastic package and its manufacturing method still have the following problems to be solved.
(1) When the etching process is performed using the Ni and Au plating films as an etching resist mask, Cu is exposed without covering the side surfaces of the metal layer made of Cu with the Ni and Au plating films, and furthermore, the semiconductor element connection is performed. Since the side surfaces of the pad are not covered with the solder resist mask, for example, when evaluated by a reliability test such as a high-temperature and high-humidity current test (HHBT), the side surfaces of the metal layer are covered with a Ni and Au plating film. In some cases, the evaluation result is inferior to that of the above-described embodiment, and a difference may occur in reliability.
(2) When the etching process is performed using the Ni and Au plating films as an etching resist mask, Cu on the side surface of the metal layer is cut off, and the Ni and Au plating films overhang. Since a wire bond for connecting the semiconductor element cannot be made in this overhang part, it is necessary to design a semiconductor element connection pad with an effective area that allows for the overhang part, and the insulation interval between patterns becomes narrow. A problem occurs in wiring design. In addition, since there is a difference in the degree of overhang of each wire, it is difficult to confirm the effective area of the wire bond 、, and there may be a case where connection reliability after wire bonding is lacking.
(3) The bonding between the wiring pattern on which the Ni and Au plating films are formed and the solder resist mask does not have an oxide film formed on the Au plating film, so that the bonding strength of the bonding surface with the resin is low, and the semiconductor element bonding pad is used. When the area occupied by the area of the Au plating film surface in the resin substrate becomes large as in the surface on which the is formed, peeling is likely to occur at the joint surface with the solder resist mask, and the reliability is reduced.
The present invention has been made in view of such circumstances, and a plating film is formed by an electrolytic plating method while eliminating the need for a plating lead wire, and an overhang or a plating film non-adhesion portion is formed on a semiconductor element connection pad. It is another object of the present invention to provide a plastic package having high bonding strength of a solder resist mask and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
The plastic package according to the present invention, which meets the above object, is configured such that a metal layer on the upper surface side of a metal layer made of Cu on both surfaces of a resin substrate is etched and electrically connected to a semiconductor element formed in connection with an upper surface side wiring pattern. A semiconductor element connection pad for connection, and an external terminal connection pad for electrically connecting to the outside formed in connection with the lower surface side wiring pattern by etching the lower metal layer, In a plastic package having vias connecting an upper wiring pattern and a lower wiring pattern, the upper surface of the semiconductor element connecting pad, the upper surface of the lower wiring pattern, and the side surface of the semiconductor element connecting pad are made of Ni by electrolytic plating. And an Au plating film, and energization by the electrolytic plating method is performed on the metal layer on the lower surface side, so that plating for the electrolytic plating method is performed. With not out line forming, it is not subjected to Ni and Au plating film on the upper surface wiring patterns other than the semiconductor element connection pads. As a result, the metal layer made of Cu is not exposed on the side surface of the semiconductor element connection pad, so that the reliability test is highly evaluated. Further, since there is no overhang of the Ni and Au plating films, the effective area in the case of directly bonding a wire bond or a semiconductor element can be increased. Furthermore, since the Ni and Au plating films are not provided on the upper surface other than the semiconductor device connection pads, the adhesion with the solder resist mask can be improved.
[0009]
Here, it is preferable to have a filler formed by filling a resin paste made of a conductive material or an insulating material in the center cavity of the via. This makes it possible to reliably and accurately form a pattern such as an etching resist mask or a solder resist mask on the via, so that the etching solution at the time of etching or the plating solution at the time of electrolytic plating can be prevented from being contaminated by intrusion. Reliability can be improved.
[0010]
The plastic package according to the present invention, which meets the above object, is configured such that a metal layer on the upper surface side of a metal layer made of Cu on both surfaces of a resin substrate is etched and electrically connected to a semiconductor element formed in connection with an upper surface side wiring pattern. A semiconductor element connection pad for connection, and an external terminal connection pad for electrically connecting to the outside formed in connection with the lower surface side wiring pattern by etching the lower metal layer, In a plastic package having a via for connecting an upper wiring pattern and a lower wiring pattern, an upper surface of the semiconductor element connection pad, an upper surface of the lower wiring pattern, a wall surface of the via, and a side surface of the semiconductor element connection pad are electrolytic. It is covered with a Ni and Au plating film by a plating method, and energization by an electrolytic plating method is performed on a metal layer on a lower surface side. With plated lead is not formed, it is not subjected Ni and Au plating film on the upper surface wiring patterns other than the semiconductor element connection pads. As a result, the metal layer made of Cu is not exposed on the side surface of the semiconductor element connection pad, so that the reliability test is highly evaluated. Further, since there is no overhang of the Ni and Au plating films, the effective area in the case of directly bonding a wire bond or a semiconductor element can be increased. Further, since the upper surface side is not provided with the Ni and Au plating films other than the pads for connecting the semiconductor element, the adhesion with the solder resist mask can be improved. Furthermore, since the Ni and Au plating films are also applied to the wall surfaces of the vias, the reliability can be improved for a reliability test such as a temperature cycle test.
[0011]
According to the method for manufacturing a plastic package according to the present invention, the upper surface side metal layer and the lower surface side metal layer made of Cu on both surfaces of the resin substrate are connected to the wall surface of the through-hole by a via provided with a conductive metal. In a method of manufacturing a plastic package having a semiconductor element connection pad formed by etching a layer and an external terminal connection pad formed by etching a lower metal layer, a method for manufacturing a plastic package comprising the steps of: A first dry film is spread, and the first dry film spread on the upper surface side metal layer is subjected to a photolithography process, and an upper surface side etching resist mask having a reverse pattern of the upper surface side wiring pattern as an opening. Performing a photolithography process on the first dry film spread on the lower metal layer to cover the entire surface of the lower metal layer. A step of forming a lower surface side etching resist mask, and an upper surface side metal layer exposed from an opening of the upper surface side etching resist mask is removed by etching to form an upper surface side wiring pattern; Removing, removing, and forming a photosensitive solder resist film on the upper surface of the resin substrate on which the upper surface side wiring pattern is formed, filling the center cavity of the via with the solder resist, and forming the solder resist film and the solder resist. Forming a first solder resist mask in which an area including a semiconductor element connection pad is exposed from the opening by photolithography, and spreading a second dry film on the surface of the lower surface side metal layer, Photolithography is applied to the dry film of A step of forming a resist mask, and a step of applying an electric current from a lower surface side metal layer to a semiconductor element connection pad exposed from an opening of a first solder resist mask and a lower surface side wiring pattern exposed from an opening of a plating resist mask. Forming a Ni and Au plating film by a plating method, and removing and removing the plating resist mask, and then etching and removing the lower surface side metal layer of the opening using the Ni and Au plating film as an etching resist mask to obtain a lower surface. Forming a side wiring pattern and forming a photosensitive solder resist film on the upper surface of the resin substrate on which the lower side wiring pattern is formed, and external terminal connection pads are exposed from the opening by photolithography on the solder resist film Forming a second solder resist mask.
[0012]
Thereby, the Ni and Au plating films can be easily formed on the side surfaces of the semiconductor element connection pads. Further, it is possible to prevent the overhang of the Ni and Au plating films. Further, the Ni and Au plating films on the upper surface can be formed only in the semiconductor element connection pad portion.
[0013]
Here, before the first dry film is spread on the central cavity of the via, the method includes a step of printing a hole filling paste made of a conductive material or an insulating material to form a filler. Is good. Thereby, the via filling paste can be easily filled in the via.
[0014]
According to another method of manufacturing a plastic package according to the present invention, the upper surface-side metal layer and the lower surface-side metal layer made of Cu on both surfaces of a resin substrate are connected to a wall surface of a through-hole by a via having a conductive metal. In a method of manufacturing a plastic package having a semiconductor element connection pad formed by etching a side metal layer and an external terminal connection pad formed by etching a bottom metal layer, A first dry film is spread on the surface, a photolithography method is applied to the first dry film spread on the upper metal layer, and an upper surface etching resist having a reverse pattern of the upper wiring pattern as an opening. Photolithography is applied to the mask and the first dry film spread on the lower metal layer, and the entire surface of the lower metal layer is covered. Forming a lower-side etching resist mask to be etched, and removing the upper-side metal layer exposed from the opening of the upper-side etching resist mask by etching to form an upper-side wiring pattern; Removing the mask and removing the mask, spreading a second dry film on the upper surface of the resin substrate on which the upper surface side wiring pattern is formed, and the surface of the lower surface side metal layer, and applying a photolithography method to the second dry film To form a plating resist mask having an opening in an area including a semiconductor element connection pad in a via portion and an upper surface side wiring pattern, and a plating resist having an lower surface side wiring pattern as an opening on a lower surface side. A step of forming a mask, a semiconductor element connection pad exposed from an opening of the plating resist mask, and an inner wall surface A step of forming a Ni and Au plating film on the via portion and the lower side wiring pattern including the lower side metal layer by an electrolytic plating method in which a current flows from the lower side metal layer, and removing and removing the plating resist mask, and then including the upper side wiring pattern. Forming a cover film for an etching resist on the entire upper surface side and etching and removing the lower-side metal layer of the opening by using the Ni and Au plating films on the lower surface as an etching resist mask to form a lower-side wiring pattern. After removing and removing the etching resist cover film, a photosensitive solder resist film is formed on both surfaces of the resin substrate on which the upper side wiring pattern and the lower side wiring pattern are formed, and at the same time, the center cavity of the via is formed. Fill a photosensitive solder resist and connect the semiconductor element to the solder resist on the top side by photolithography Forming a solder resist mask on the lower surface side of the area including the pad for external terminals and the external terminal connection pad is exposed from the opening.
[0015]
Thereby, the Ni and Au plating films can be easily formed on the side surfaces of the semiconductor element connection pads. Further, it is possible to prevent the overhang of the Ni and Au plating films. Further, the Ni and Au plating films on the upper surface can be formed only in the semiconductor element connection pad portion. Further, a Ni and Au plating film can be easily formed in the via.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention.
Here, FIG. 1 is a partially enlarged sectional view of a plastic package according to one embodiment of the present invention, FIG. 2 is a partially enlarged sectional view of a modified example of the plastic package, and FIG. 3 is another modified example of the plastic package. FIGS. 4A to 4D are partially enlarged cross-sectional views each showing a part of a method of manufacturing a plastic package according to an embodiment of the present invention, and FIGS. FIGS. 6A to 6D are partially enlarged cross-sectional views each showing a part of a method of manufacturing the plastic package, and FIGS. 8A to 8C are partially enlarged cross-sectional views each showing a part of a method of manufacturing a plastic package according to another embodiment of the present invention, and FIGS. Is an enlarged partial sectional view showing a part of a manufacturing process.
[0017]
As shown in FIG. 1, a plastic package 10 according to an embodiment of the present invention has a core substrate that is excellent in high heat resistance, dielectric properties, insulation properties, workability, and the like of, for example, a BT resin or a polyimide resin. And a single-layer or multi-layer resin substrate 11 having a resin as a base material. A semiconductor element which has metal layers 12 and 12a made of Cu on both upper and lower surfaces of the resin substrate 11 and is formed by connecting the upper surface side metal layer 12 to the upper surface side wiring pattern 13 by etching. Terminal connection pads 14 for electrical connection to the semiconductor device, and external terminal connections for electrical connection to the outside formed by connecting the lower metal layer 12a to the lower wiring pattern 13a by etching the lower metal layer 12a. Pad 15. A via 17 provided with a conductive metal made of Cu is provided on the wall surface of a through hole 16 formed by drilling the resin substrate 11 for connecting the upper surface side wiring pattern 13 and the lower surface side wiring pattern 13a. Have.
[0018]
The plastic package 10 has a semiconductor element connection pad 14, an upper surface of a lower wiring pattern 13a, and a Ni and Au plating film 18 formed on the side surface of the semiconductor element connection pad 14 by electrolytic plating. . Moreover, in the plastic package 10, the energization by the electrolytic plating method is performed from the lower surface side metal layer 12a, and the plating lead wire for performing the energization by the electrolytic plating method is not formed. Further, in the plastic package 10, the Ni and Au plating films 18 are not formed on the upper surface side wiring pattern 13 other than the semiconductor element connection pads 14. In the plastic package 10, a first solder resist mask 19 exposing an area including the semiconductor element connection pads 14 from the opening on the upper surface side, and an external terminal connection pad 15 on the lower surface side from the opening. The second solder resist masks 20 are formed and formed in different processes. In addition, although the Ni and Au plating films 18 are formed on the lower surface side wiring pattern 13a, the area thereof is so small that the peeling does not occur at the bonding surface with the solder resist mask 20.
[0019]
Next, a plastic package 10a as a modified example of the plastic package 10 according to one embodiment of the present invention will be described with reference to FIG. This plastic package 10 a is basically the same as the plastic package 10, but has a filling body 21 formed by filling a cavity in the center of the via 17 with a resin paste made of a conductive material or an insulating material. I have. The plastic package 10a has a first solder resist mask 19 formed on the upper surface side and a second solder resist mask 20 formed on the lower surface side in separate processes, similarly to the case of the plastic package 10. I have.
[0020]
Next, a plastic package 10b according to another embodiment of the present invention will be described with reference to FIG. This plastic package 10b is basically the same as the plastic package 10, but has a Ni and Au plating film 18 formed on the wall surface of the via 17 by an electrolytic plating method in which a current flows through the lower surface side metal layer 12a. . In this plastic package 10b, a solder resist mask 22 exposing an area including the semiconductor element connection pads 14 on the upper surface side from the opening and exposing the external terminal connection pads 15 on the lower surface side from the opening is formed in the same step. Have formed.
[0021]
Next, a method for manufacturing the plastic package 10 according to one embodiment of the present invention will be described with reference to FIGS. 4 (A) to 4 (D) and FIGS. 5 (A) to 5 (C). As shown in FIG. 4A, a single layer made of a resin having excellent heat resistance, dielectric properties, insulation properties, workability, etc., such as BT resin or polyimide resin, for example, in which Cu foils are bonded on both sides. Alternatively, a through hole 16 is formed in a multilayer resin substrate 11 using a drill machine, a punching machine, or the like, and further subjected to electroless Cu plating and electrolytic Cu plating to form an upper metal layer 12 made of Cu, A via 17 having a conductive metal of a Cu plating film is formed on the metal layer 12 a and the wall surface of the through hole 16. Next, a first dry film mainly composed of a photosensitive acrylic resin is spread on the surfaces of the upper metal layer 12 and the lower metal layer 12 a while closing the central cavity of the via 17. The first dry film spread on the upper surface side metal layer 12 is exposed to a pattern mask and exposed and developed so that an upper surface side wiring pattern 13 is obtained. An upper surface side etching resist mask 23 having an opening formed by a reverse pattern of the pattern 13 is formed. Further, the first dry film spread on the lower metal layer 12a is exposed to light and cured by photolithography to form an entire surface of the lower metal layer 12a. 24 are formed.
[0022]
Next, as shown in FIG. 4 (B), the upper surface side metal layer 12 exposed from the opening of the upper surface side etching resist mask 23 includes, for example, a ferric chloride solution, a cupric chloride solution, an alkali etchant, Etching is performed by spraying an etchant such as a hydrogen peroxide-sulfuric acid-based etchant. Thus, the upper surface side metal layer 12 exposed from the opening of the upper surface side etching resist mask 23 is removed to form the upper surface side wiring pattern 13. Thereafter, the upper surface side etching resist mask 23 and the lower surface side etching resist mask 24 made of the first dry film are formed, for example, by using a 50 ° C., about 3% sodium hydroxide release solution when the dry film is of an alkali-soluble type. Using a stripping solution such as an aqueous solution, spraying or immersing in the stripping solution to swell the first dry film and remove it from the upper metal layer 12 and the lower metal layer 12a by removal. I do.
[0023]
Next, as shown in FIG. 4C, a solder resist film is formed on the upper surface of the resin substrate 11 on which the upper surface side wiring pattern 13 is formed by screen printing using a photosensitive solder resist paste made of resin. It is formed, or the center cavity of the via 17 is filled with a solder resist. Further, the first solder is exposed on the solder resist film by a photolithography method in which a pattern mask is brought into contact with and exposed to light and developed, and the area including the semiconductor element connection pad 14 is exposed from the opening. A resist mask 25 is formed.
[0024]
Next, as shown in FIG. 4D, a second dry film mainly composed of the same photosensitive acrylic resin as the first dry film is spread on the surface of the lower surface side metal layer 12a. . The second dry film spread on the lower surface side metal layer 12a is exposed by a pattern mask and exposed and developed so as to obtain a lower surface side wiring pattern 13a. A plating resist mask 26 having the pattern 13a as an opening is formed.
[0025]
Next, as shown in FIG. 5A, the semiconductor element connection pad 14 exposed from the opening of the first solder resist mask 25 and the lower surface side wiring pattern 13a exposed from the opening of the plating resist mask 26 are formed. For example, electrolytic Ni plating is performed by an electrolytic plating method in which a current flows from the lower metal layer 12a in a plating bath such as a Watt bath or a sulfamic acid bath. Then, subsequently, for example, electrolytic Au plating is performed by an electrolytic plating method in which a current flows from the lower metal layer 12a in a plating bath such as an Au plating bath or an Au alloy plating bath. Thus, Ni and Au plating films 18 are formed on the upper surface and side surfaces of the semiconductor element connection pads 14 on the upper surface and the upper surface of the lower wiring pattern 13a on the lower surface.
[0026]
Next, as shown in FIG. 5B, the plating resist mask 24 made of the second dry film is sprayed with a stripping solution or dipped in the stripping solution to remove the second dry film. While swelling, it is peeled off and removed from the lower surface side metal layer 12a. After that, the lower metal layer 12a exposed from the opening using the Ni and Au plating films 18 as an etching resist mask is subjected to an etching process by spraying an etching solution such as an alkali etchant. Thereby, the lower surface side wiring pattern 13a is formed on the lower surface side of the resin substrate 11.
[0027]
Next, as shown in FIG. 5C, a solder resist film is formed on the upper surface of the resin substrate 11 by screen printing or the like using a photosensitive solder resist paste made of a resin, on the lower surface side wiring pattern 13a. I do. Further, the second solder resist mask 27 in which the external terminal connection pads 15 are exposed from the openings is formed on the solder resist film by a photolithography method in which a pattern mask is brought into contact with, exposed to light, and developed. Is formed to produce the plastic package 10. The outer peripheral portion of the lower wiring pattern 13a forming the external terminal connection pad 15 is preferably covered with a second solder resist mask 27 in plan view.
[0028]
Next, a method for manufacturing a plastic package 10a as a modification of the plastic package 10 according to one embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 6 (A), a single layer made of a resin having excellent heat resistance, dielectric properties, insulation properties, workability, etc., such as BT resin or polyimide resin, having a Cu foil bonded to both sides, for example. Alternatively, through holes 16 are formed in the multilayer resin substrate 11 using a drill machine, a punching machine, or the like. Further, on the resin substrate 11, electroless Cu plating and electrolytic Cu plating are applied, and the upper metal layer 12, the lower metal layer 12 a made of Cu, and the conductive metal of the Cu plating film are coated on the wall surfaces of the through holes 16. The provided via 17 is formed.
[0029]
Next, as shown in FIG. 6B, a hole filling paste made of a conductive material of a mixture of a powder such as Ag or Cu and a resin or an insulating material such as a resin is provided in a central cavity of the via 17. Is used to screen-print, and is dried and cured to form the filler 21. Then, as shown in FIG. 6C, a first dry film mainly composed of a photosensitive acrylic resin is spread on the surfaces of the upper metal layer 12 and the lower metal layer 12a of the resin substrate 11. I do.
[0030]
Next, as shown in FIG. 6 (D), the first dry film spread on the upper surface side metal layer 12 is exposed to a pattern mask so that the upper surface side wiring pattern 13 is obtained. An upper surface side etching resist mask 23 having an opening in the reverse pattern of the upper surface side wiring pattern 13 is formed by a photolithography method formed by development. Further, the first dry film spread on the lower metal layer 12a is exposed to light and cured by photolithography to form an entire surface of the lower metal layer 12a. 24 are formed.
The subsequent steps are substantially the same as the method of manufacturing the plastic package 10 except that the cavity 21 at the center of the via 17 is filled with the filler 21 instead of the first solder resist mask 25. .
[0031]
Next, a method for manufacturing a plastic package 10b according to another embodiment of the present invention will be described with reference to FIGS. 7 (A) to 7 (C) and FIGS. 8 (A) to 8 (C). As shown in FIG. 7A, a single layer made of a resin having excellent heat resistance, dielectric properties, insulation properties, workability, etc., such as BT resin or polyimide resin, for example, in which Cu foils are bonded on both sides. Alternatively, a through hole 16 is formed in the multilayer resin substrate 11 using a drill machine, a punching machine, or the like, and further subjected to electroless Cu plating and electrolytic Cu plating to form an upper metal layer 12 made of Cu, A via 17 having a conductive metal of a Cu plating film is formed on the metal layer 12 a and the wall surface of the through hole 16. Next, a first dry film mainly composed of a photosensitive acrylic resin is spread on the surfaces of the upper metal layer 12 and the lower metal layer 12 a while closing the central cavity of the via 17. The first dry film spread on the upper surface side metal layer 12 is exposed to a pattern mask and exposed and developed so that an upper surface side wiring pattern 13 is obtained. An upper surface side etching resist mask 23 having an opening formed by a reverse pattern of the pattern 13 is formed. Further, the first dry film spread on the lower metal layer 12a is exposed to light and cured by photolithography to form an entire surface of the lower metal layer 12a. 24 are formed.
[0032]
Next, as shown in FIG. 7B, the upper surface side metal layer 12 exposed from the opening of the upper surface side etching resist mask 23 includes, for example, a ferric chloride solution, a cupric chloride solution, an alkali etchant, Etching is performed by spraying an etchant such as a hydrogen peroxide-sulfuric acid-based etchant. Thus, the upper surface side metal layer 12 exposed from the opening of the upper surface side etching resist mask 23 is removed to form the upper surface side wiring pattern 13. Thereafter, the upper surface side etching resist mask 23 and the lower surface side etching resist mask 24 made of the first dry film are formed, for example, by using a 50 ° C., about 3% sodium hydroxide release solution when the dry film is of an alkali-soluble type. Using a stripping solution such as an aqueous solution, spraying or immersing in the stripping solution to swell the first dry film and remove it from the upper metal layer 12 and the lower metal layer 12a by removal. I do.
[0033]
Next, as shown in FIG. 7 (C), the upper surface of the resin substrate 11 on which the upper surface side wiring pattern 13 is formed and the surface of the lower surface side metal layer 12a have the same photosensitivity as the first dry film. A second dry film mainly composed of an acrylic resin is spread. The second dry film formed on the upper surface side is exposed to a pattern mask, exposed, developed, and formed by a photolithography method to form the vias 17 and the semiconductor element connection pads 14 in the upper surface side wiring pattern 13. The plating resist mask 26a having the area including the opening as an opening is formed. Also, the second dry film formed on the lower surface side is exposed to a pattern mask and exposed and developed so as to obtain the lower surface side wiring pattern 13a. Is formed as a plating resist mask 26b having openings as openings.
[0034]
Next, as shown in FIG. 8A, for example, a watt bath or the like is applied to the semiconductor element connection pads 14, the via 17, and the lower surface side wiring pattern 13a exposed from the openings of the plating resist masks 26a and 26b. Then, electrolytic Ni plating is performed by an electrolytic plating method in which a current is supplied from the lower metal layer 12a in a plating bath such as a sulfamic acid bath. Then, subsequently, for example, electrolytic Au plating is performed by an electrolytic plating method in which a current flows from the lower metal layer 12a in a plating bath such as an Au plating bath or an Au alloy plating bath. Thereby, Ni and Au plating films 18 are formed on the upper surface and side surfaces of the semiconductor element connection pads 14 on the upper surface, the inner wall surface of the via 17, and the upper surface of the lower wiring pattern 13a on the lower surface. .
[0035]
Next, as shown in FIG. 8B, the plating resist masks 26a and 26b made of the second dry film are sprayed with a stripping solution or immersed in the stripping solution to form a second dry resist. The film is peeled and removed while swelling. Thereafter, an etching resist cover film 28 made of a resin film or the like is spread over the entire upper surface including the upper wiring pattern 13. Then, the etching process is performed by spraying an etching solution such as an alkali etchant on the etching resist cover film 28 and the lower metal layer 12a exposed from the opening using the Ni and Au plating films 18 as an etching resist mask. . Thereby, the lower surface side wiring pattern 13a is formed on the lower surface side of the resin substrate 11.
[0036]
Next, as shown in FIG. 8C, after removing and removing the etching resist cover film 28 spread over the entire upper surface side, the upper surface side wiring pattern 13 and the lower surface side wiring pattern 13a are formed. On the upper surface of the resin substrate 11, a solder resist film is formed by screen printing or the like using a photosensitive solder resist paste made of a resin, and at the same time, the photosensitive solder resist is also filled in the center cavity of the via 17. . On the solder resist film, an area including the semiconductor element connection pad 14 is exposed from the opening on the upper surface side by a photolithography method in which a pattern mask is brought into contact with, exposed to light, and developed, and is formed on the lower surface side. Then, a solder resist mask 22 in which the external terminal connection pads 15 are exposed from the openings is formed, and the plastic package 10b is manufactured. The outer peripheral portion of the lower surface side wiring pattern 13a forming the external terminal connection pad 15 is preferably covered with a solder resist mask 22 in plan view.
[0037]
【The invention's effect】
According to a first aspect of the present invention, there is provided a plastic package, wherein the upper surface of the semiconductor element connection pad, the upper surface of the lower surface side wiring pattern, and the side surface of the semiconductor element connection pad are plated with Ni and Au by electrolytic plating. It is covered with a coating, and the energization by the electrolytic plating method is performed on the metal layer on the lower surface side, the plating lead wire for the electrolytic plating method is not formed, and the upper surface side wiring pattern other than the semiconductor element connection pad is not formed. Since the Ni and Au plating films are not applied, there is no exposure of the metal layer made of Cu on the side surface of the semiconductor element connection pad, the evaluation in a reliability test is high, and the semiconductor element connection pad has Ni and Au. There is no overhang of the Au plating film, and the effective area in the case of directly bonding a wire bond or a semiconductor element can be increased. Furthermore, even on the upper surface side where the area ratio of the wiring pattern is high, the adhesion with the solder resist mask can be improved.
[0038]
In particular, since the plastic package according to claim 2 has a filler formed by filling a resin paste made of a conductive material or an insulating material in the center cavity of the via, it is possible to use an etching resist mask, a solder resist mask, or the like. The pattern can be reliably and accurately formed on the via, and contamination due to intrusion of an etching solution during etching or a plating solution during electrolytic plating can be prevented, and reliability can be improved.
[0039]
In the plastic package according to the third aspect, the upper surface of the semiconductor device connection pad, the upper surface of the lower surface side wiring pattern, the wall surface of the via, and the side surface of the semiconductor device connection pad are covered with a Ni and Au plating film formed by electrolytic plating. In addition, electric current for plating is applied to the metal layer on the lower surface side, no plating lead wire for electrolytic plating is formed, and Ni and Au plating films are formed on the upper surface side wiring patterns other than the pads for connecting semiconductor elements. Is not applied, there is no exposure of the metal layer made of Cu on the side surface of the semiconductor element connection pad, and the reliability test is highly evaluated. In addition, the overhang of the Ni and Au plating films on the semiconductor element connection pad An effective area in the case of directly bonding a wire bond or a semiconductor element without generation can be widened. Further, on the upper surface side, Ni and Au plating films are not provided except for the pads for connecting the semiconductor element, so that the adhesion with the solder resist mask can be improved. Furthermore, the wall surfaces of the vias are covered with a Ni and Au plating film, so that the reliability can be improved for a reliability test such as a temperature cycle test.
[0040]
According to a fourth aspect of the present invention, there is provided a method of manufacturing a plastic package, wherein a first dry film is spread on upper and lower metal layers, and an upper wiring pattern is formed on the upper dry film by photolithography. Forming an upper surface side etching resist mask having an opening of a reverse pattern of the above, forming a lower surface side etching resist mask covering the entire lower surface side metal layer on the lower surface side, and exposing from the opening of the upper surface side etching resist mask. After removing the upper-side metal layer by etching to form an upper-side wiring pattern, removing the upper and lower-side etching resist masks and removing the same; Form a solder resist film or fill the solder resist, and use photolithography method Forming a first solder resist mask exposing an opening from the opening, and spreading a second dry film on the surface of the lower surface side metal layer, and plating the lower surface side wiring pattern with the opening by photolithography. A step of forming a resist mask, a step of forming a Ni and Au plating film on the semiconductor element connection pad portion and the lower side wiring pattern by an electrolytic plating method in which a current flows from the lower side metal layer, and peeling off the plating resist mask. Forming a lower wiring pattern by etching the lower metal layer of the opening by using the Ni and Au plating films as an etching resist mask, and forming a lower wiring pattern on the resin substrate on which the lower wiring pattern is formed. A photosensitive solder resist film is formed on the upper surface, and external terminal connection pads are opened on the solder resist film by photolithography. Since a step of forming a second solder resist mask to expose the part, it is possible to easily form the Ni and Au plating film on the side surface of the pad for semiconductor element connection. Further, it is possible to prevent the overhang of the Ni and Au plating films. Further, the Ni and Au plating films on the upper surface can be formed only in the semiconductor element connection pad portion.
[0041]
In particular, in the method for manufacturing a plastic package according to the fifth aspect, a hole filling paste made of a conductive material or an insulating material is printed in the center cavity of the via before the first dry film is spread. Since the step of forming a filling body to be filled is included, the inside of the via can be easily filled with the paste for filling holes.
[0042]
7. The method for manufacturing a plastic package according to claim 6, wherein a first dry film is spread on surfaces of the upper and lower metal layers, and a photolithography process is performed on the first dry film on the upper surface. A step of forming an upper surface side etching resist mask having an opening of a reverse pattern of the wiring pattern and a lower side etching resist mask covering the entire surface of the lower side metal layer on the lower surface side; A step of removing the exposed upper-side metal layer by etching to form an upper-side wiring pattern, and removing and removing the etching resist mask on both surfaces; and a step of removing the upper-side metal of the resin substrate on which the upper-side wiring pattern is formed. A second dry film is spread on the surface of the layer and the lower metal layer, and the via portion and the upper wiring pattern are formed by photolithography. Forming a plating resist mask having an opening in an area including a semiconductor element connection pad in the pattern, and forming a plating resist mask having an undersurface side wiring pattern as an opening on a lower surface side; Forming a Ni and Au plating film by an electrolytic plating method in which a current flows from the lower metal layer to the semiconductor element connection pad exposed from the opening, and the via portion including the inner wall surface and the lower wiring pattern; After removing and removing the resist mask, a cover film for etching resist is spread on the entire upper surface side, and the lower surface side metal layer of the opening is etched and removed using the Ni and Au plating films on the lower surface as an etching resist mask. After forming the lower side wiring pattern by peeling and removing the etching resist cover film, A photosensitive solder resist film is formed on both sides of the resin substrate on which the surface wiring pattern is formed, and at the same time, a photosensitive solder resist is filled in the center cavity of the via, and a photolithography method is used to connect a semiconductor element to the upper surface side. Since the method includes the step of forming a solder resist mask in which an area including the pad and the external terminal connection pad portion is exposed from the opening on the lower surface side, a Ni and Au plating film can be easily formed on the side surface of the semiconductor element connection pad. , Ni, and Au plating films can be prevented from overhanging. Further, the formation of the Ni and Au plating films on the upper surface side can be performed only with the semiconductor element connection pads. Further, a Ni and Au plating film can be easily formed in the via.
[Brief description of the drawings]
FIG. 1 is a partially enlarged cross-sectional view of a plastic package according to an embodiment of the present invention.
FIG. 2 is a partially enlarged sectional view of a modified example of the plastic package.
FIG. 3 is a partially enlarged sectional view of another modified example of the plastic package.
FIGS. 4A to 4D are partially enlarged cross-sectional views each showing a part of a method of manufacturing a plastic package according to an embodiment of the present invention.
FIGS. 5A to 5C are partially enlarged cross-sectional views each showing a part of a method of manufacturing the plastic package.
6A to 6D are partially enlarged cross-sectional views each showing a part of a method of manufacturing a modification of the plastic package.
7A to 7C are partially enlarged cross-sectional views each showing a part of a method of manufacturing a plastic package according to another embodiment of the present invention.
FIGS. 8A to 8C are partially enlarged cross-sectional views each showing a part of a method of manufacturing the plastic package.
FIG. 9 is a partially enlarged sectional view of a conventional plastic package.
FIGS. 10A to 10D are partially enlarged cross-sectional views illustrating a conventional method of manufacturing a plastic package.
[Explanation of symbols]
10, 10a, 10b: plastic package, 11: resin substrate, 12: upper metal layer, 12a: lower metal layer, 13: upper wiring pattern, 13a: lower wiring pattern, 14: semiconductor element connection pad, 15: Pad for connecting external terminals, 16: Through hole, 17: Via, 18: Ni and Au plating film, 19: First solder resist mask, 20: Second solder resist mask, 21: Filler, 22: Solder resist mask, 23: Upper side etching resist mask, 24: Lower side etching resist mask, 25: First solder resist mask, 26, 26a, 26b: Plating resist mask, 27: Second solder resist mask, 28: Cover film for etching resist

Claims (6)

A semiconductor element connection pad for electrically connecting the semiconductor layer formed in connection with the upper surface side wiring pattern by etching the metal layer on the upper surface side of the metal layer made of Cu on both surfaces of the resin substrate, An external terminal connecting pad formed in connection with the lower surface side wiring pattern and electrically connected to the outside formed by etching the metal layer on the lower surface side and connecting the upper surface side wiring pattern and the lower surface side wiring In a plastic package having vias connecting patterns,
The upper surface of the semiconductor element connection pad, the upper surface of the lower surface side wiring pattern, and the side surface of the semiconductor element connection pad are covered with a Ni and Au plating film by an electrolytic plating method. The energization is performed on the metal layer on the lower surface side, the plating lead wire for the electrolytic plating method is not formed, and the Ni and Au plating films are formed on the upper surface side wiring pattern other than the semiconductor element connection pads. A plastic package characterized by not being applied. 2. The plastic package according to claim 1, further comprising a filler formed by filling a resin paste made of a conductive material or an insulating material in a central cavity of the via. A semiconductor element connection pad for electrically connecting the semiconductor layer formed in connection with the upper surface side wiring pattern by etching the metal layer on the upper surface side of the metal layer made of Cu on both surfaces of the resin substrate, An external terminal connecting pad formed in connection with the lower surface side wiring pattern and electrically connected to the outside formed by etching the metal layer on the lower surface side and connecting the upper surface side wiring pattern and the lower surface side wiring In a plastic package having vias connecting patterns,
The upper surface of the semiconductor element connection pad, the upper surface of the lower surface side wiring pattern, the wall surface of the via, and the side surface of the semiconductor element connection pad are covered with a Ni and Au plating film by an electrolytic plating method. The energization in the electrolytic plating method is performed on the metal layer on the lower surface side, the plating lead wire for the electrolytic plating method is not formed, and the Ni on the upper surface side wiring pattern other than the semiconductor element connection pad is formed. And a plastic package not provided with an Au plating film. A semiconductor element connection pad formed by connecting the upper surface side metal layer and the lower side metal layer made of Cu on both surfaces of the resin substrate to the wall surface of the through hole with a via having a conductive metal and etching the upper surface side metal layer; In a method of manufacturing a plastic package provided with external terminal connection pads formed by etching the lower surface side metal layer,
A first dry film is spread on the surfaces of the upper and lower metal layers, and a photolithography process is performed on the first dry film spread on the upper metal layer to form an upper wiring pattern. A photolithography method is applied to the upper surface side etching resist mask having the reverse pattern as an opening and the first dry film spread on the lower side metal layer, and the lower surface covering the entire surface of the lower side metal layer Forming a side etching resist mask;
Removing the upper surface side metal layer exposed from the opening of the upper surface side etching resist mask by etching to form the upper surface side wiring pattern, and then removing and removing the upper surface side and lower surface side etching resist masks; When,
Forming a photosensitive solder resist film on the upper surface of the resin substrate on which the upper surface side wiring pattern is formed, filling the center cavity of the via with a solder resist, and applying a photolithography method to the solder resist film and the solder resist. Forming a first solder resist mask in which an area including the semiconductor element connection pad is exposed from an opening;
Spreading a second dry film on the surface of the lower surface side metal layer, performing a photolithography process on the second dry film, and forming a plating resist mask having the lower surface side wiring pattern as an opening; ,
The semiconductor element connection pad exposed from the opening of the first solder resist mask and the lower surface side wiring pattern exposed from the opening of the plating resist mask are subjected to an electrolytic plating method in which current flows from the lower surface side metal layer. Forming a Ni and Au plating film;
Removing and removing the plating resist mask, forming the lower-side wiring pattern by etching and removing the lower-side metal layer of the opening using the Ni and Au plating films as an etching resist mask;
A second solder in which a photosensitive solder resist film is formed on the upper surface of the resin substrate on which the lower surface side wiring pattern is formed, and the external terminal connection pads are exposed from the opening in the solder resist film by photolithography. A method for manufacturing a plastic package, comprising a step of forming a resist mask. 5. The method of manufacturing a plastic package according to claim 4, wherein a paste for filling a hole made of a conductive material or an insulating material is printed in the central cavity of the via before the first dry film is spread. A method for producing a plastic package, comprising a step of forming a filling body to be filled. A semiconductor element connection pad formed by connecting the upper surface side metal layer and the lower side metal layer made of Cu on both surfaces of the resin substrate to the wall surface of the through hole with a via having a conductive metal and etching the upper surface side metal layer; In a method of manufacturing a plastic package provided with external terminal connection pads formed by etching the lower surface side metal layer,
A first dry film is spread on the surfaces of the upper and lower metal layers, and a photolithography process is performed on the first dry film spread on the upper metal layer to form an upper wiring pattern. A photolithography method is applied to the upper surface side etching resist mask having the reverse pattern as an opening and the first dry film spread on the lower side metal layer, and the lower surface covering the entire surface of the lower side metal layer Forming a side etching resist mask;
Removing the upper surface side metal layer exposed from the opening of the upper surface side etching resist mask by etching to form the upper surface side wiring pattern, and then removing and removing the upper surface side and lower surface side etching resist masks; When,
Spreading a second dry film on the upper surface of the resin substrate on which the upper surface side wiring pattern is formed, and the surface of the lower surface side metal layer, performing a photolithography process on the second dry film, A plating resist mask having an opening in the area including the semiconductor element connection pad in the via portion and the upper surface side wiring pattern is formed, and the plating resist mask having the lower surface side wiring pattern as an opening is formed on the lower surface side. Forming,
Ni and Au plating by an electrolytic plating method in which the semiconductor element connection pad exposed from the opening of the plating resist mask, the via portion including the inner wall surface, and the lower wiring pattern are energized from the lower metal layer. Forming a coating;
After peeling and removing the plating resist mask, a cover film for an etching resist is spread on the entire upper surface including the upper wiring pattern, and the opening is formed using the Ni and Au plating films on the lower surface as an etching resist mask. Forming the lower surface side wiring pattern by etching and removing the lower surface side metal layer,
After removing and removing the etching resist cover film, a photosensitive solder resist film is formed on both surfaces of the resin substrate on which the upper surface side wiring pattern and the lower surface side wiring pattern are formed. A cavity in which a photosensitive solder resist is filled into a cavity, and an area including the semiconductor element connection pad on the upper surface side and the external terminal connection pad is exposed from the opening on the lower surface side by photolithography in the solder resist; A method for manufacturing a plastic package, comprising a step of forming a resist mask.

Images