JP2004159467A - Inverter and its method of operation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter wherein increase in the delay time of switching elements for output can be suppressed as much as possible, and further high-frequency noise which is produced when the switching elements for output are turned off can be reduced. <P>SOLUTION: The inverter (1) comprises output MISFETs connected with a load (2), and gate drivers (6) which apply gate voltage to the gate terminals of the output MISFETs (5). When the gate voltage of the output MISFETs (5) is varied from supply voltage V<SB>cc</SB>to 0, the gate drivers (6) carry out step (a) in which gate current is drawn from the gate terminals of the output MISFETs (5) with first drive capability, and step (b) in which following step (a) above, gate current is drawn from the gate terminals with second drive capability lower than the first drive capability. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inverter. The present invention relates to a technique for reducing high-frequency noise of current and voltage output from an inverter.
[0002]
[Prior art]
Inverters are widely used as power sources for driving motors and other AC-operated electric devices. The inverter generates AC power by switching an output switching element connected to a DC power supply. Generally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used as output switching elements.
[0003]
Since the output switching element included in the inverter is switched at a high speed, the output of the inverter includes high-frequency noise. The high frequency noise is particularly large when the output switching element is turned off. High-frequency noise causes electromagnetic interference as exemplified by radio and television reception interference. Therefore, it is desirable that high-frequency noise be suppressed as much as possible.
[0004]
2. Description of the Related Art In order to reduce high-frequency noise, a technique is known in which a noise filter exemplified by a ferrite core is provided in an output wiring of an inverter. However, the use of a noise filter is not preferable because it increases the space required for installing the wiring and further increases the cost.
[0005]
Further, there is known a technique for reducing the switching speed of the output switching element (that is, the time required for the output switching element to transition between the ON state and the OFF state) in order to reduce high-frequency noise. Reducing the switching speed is performed by increasing the gate resistance of a MOSFET or IGBT used as an output switching element. However, reducing the switching speed is not preferable because the delay time of the output switching element of the inverter is increased and the efficiency of the inverter is reduced.
[0006]
Still another technique for reducing high-frequency noise is disclosed in Non-Patent Document 1. The technique disclosed in Non-Patent Document 1 reduces high-frequency noise by suppressing the time change dv / dt of the output voltage of the inverter. In the known technique, the gate current of the output IGBT is actively controlled by a gate current control circuit to be large, small, large. The period during which the gate current is small coincides with the period during which the collector voltage rises, thereby reducing dv / dt.
[0007]
It is desired to reduce high-frequency noise generated at the output of the inverter when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible.
[0008]
[Non-patent document 1]
Masahiro Nagasu et al., "Soft Gate Driver with High-Speed Short-Circuit Protection Function", Proceedings of Railway Sipane Symposium, 2000, vol. 37th, p. 158-161.
[0009]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an inverter capable of reducing high-frequency noise generated at the output when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible. It is in.
[0010]
[Means for Solving the Problems]
Hereinafter, means for solving the problem will be described using numbers and symbols used in [Embodiments of the invention]. These numbers and symbols are added to clarify the correspondence between the description in [Claims] and the description in [Embodiment of the Invention]. However, the added numbers and symbols shall not be used for interpreting the technical scope of the invention described in [Claims].
[0011]
The inverter (1) according to the present invention includes an output MISFET (5) connected to a load (2), and a gate driver (6) for applying a gate voltage to a gate terminal of the output MISFET (5). When the gate driver (6) changes the gate voltage of the output MISFET (5) from the power supply voltage _VCC to 0,
(A) extracting a gate current from the gate terminal of the output MISFET (5) with the first drive capability;
(B) after the step (a), the step of extracting a gate current from the gate terminal with the second drive capability smaller than the first drive capability. The time when the gate driver (6) starts executing the step (b) is substantially the same as the time when the gate voltage of the output MISFET (5) becomes the threshold voltage of the output MISFET (5). Thus, the gate voltage of the output MISFET (5) is quickly pulled down, and the rate of change of the drain-source voltage of the output MISFET (5) is suppressed. Accordingly, it is possible to reduce high-frequency noise generated at the output when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible.
[0012]
An inverter (1) according to the present invention includes an output MISFET connected to a load (2), and a gate driver (6) for applying a gate voltage to a gate terminal of the output MISFET (5). When the gate driver (6) changes the gate voltage of the output MISFET (5) from the power supply voltage _VCC to 0,
(A) extracting a gate current from the gate terminal of the output MISFET (5) with the first drive capability;
(B) after the step (a), the step of extracting a gate current from the gate terminal with the second drive capability smaller than the first drive capability. At the time when the gate driver (6) starts executing the step (b), the rate of change of the drain-source voltage of the output MISFET (5) is higher than the first rate of change by the second rate of change. Is set to be substantially the same as the switching time. Thus, the gate voltage of the output MISFET (5) is quickly pulled down, and the rate of change of the drain-source voltage of the output MISFET (5) is suppressed. Accordingly, it is possible to reduce high-frequency noise generated at the output when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible.
[0013]
The gate driver (6) further includes
After the steps (c) and (b), it is preferable to execute a step of extracting the gate current from the gate terminal of the output MISFET (5) with the third drive capability larger than the second drive capability.
[0014]
In this case, the time when the gate driver (6) starts executing the step (c) is preferably substantially the same as the time when the gate voltage of the output MISFET (5) starts to transition from the threshold voltage to 0. It is.
[0015]
Further, at the time when the gate driver (6) starts executing the step (c), the change rate of the drain-source voltage of the output MISFET (5) is smaller than the second change rate by the third change rate. It is preferable that the time is substantially the same as the time of switching to the change rate.
[0016]
It should be noted that the first drive capability and the third drive capability may be different and may even be the same.
[0017]
An inverter according to the present invention comprises an output MISFET (5) connected to a load (2), a ground terminal (11b), a power terminal (11a) having a power supply voltage _VCC with respect to the ground terminal (11b), and an output terminal. A power supply side switching element (12) interposed between the gate terminal of the MISFET (5) and the power supply terminal (11a), and an interposition between the gate terminal of the output MISFET (5) and the ground terminal (11b). A first ground-side switching element (14), a second ground-side switching element (16) interposed between the gate terminal of the output MISFET (5) and the ground terminal (11b), and a power-source-side switching element. (12), a control circuit (19) for controlling the first ground-side switching element (14) and the second ground-side switching element (16). When the control circuit (19) turns off the output MISFET (5),
(D) turning off the power supply side switching element (12);
(E) after the step (d), turning on the first ground-side switching element (14) and the second ground-side switching element (16);
(F) after step (e), turning off the second ground-side switching element (16). The time when the control circuit (19) turns off the second ground-side switching element (16) is substantially the same as the time when the gate voltage of the output MISFET (5) becomes the threshold voltage of the output MISFET (5). Thus, the gate voltage of the output MISFET (5) is quickly pulled down, and the rate of change of the drain-source voltage of the output MISFET (5) is suppressed. Accordingly, it is possible to reduce high-frequency noise generated at the output when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible.
[0018]
An inverter according to the present invention comprises an output MISFET (5) connected to a load (2), a ground terminal (11b), a power terminal (11a) having a power supply voltage _VCC with respect to the ground terminal (11b), and an output terminal. A power supply side switching element (12) interposed between the gate terminal of the MISFET (5) and the power supply terminal (11a), and an interposition between the gate terminal of the output MISFET (5) and the ground terminal (11b). A first ground-side switching element (14), a second ground-side switching element (16) interposed between the gate terminal of the output MISFET (5) and the ground terminal (11b), and a power-source-side switching element. (12), a control circuit (19) for controlling the first ground-side switching element (14) and the second ground-side switching element (16). When the control circuit (19) turns off the output MISFET (5),
(D) turning off the power supply side switching element (12);
(E) after the step (d), turning on the first ground-side switching element (14) and the second ground-side switching element (16);
(F) after step (e), turning off the second ground-side switching element (16). At the time when the control circuit (19) turns off the second ground-side switching element (16), the second rate of change of the drain-source voltage of the output MISFET (5) is larger than the first rate of change from the first rate of change. The time is substantially the same as the time when the change rate is changed. Thus, the gate voltage of the output MISFET (5) is quickly pulled down, and the rate of change of the drain-source voltage of the output MISFET (5) is suppressed. Accordingly, it is possible to reduce high-frequency noise generated at the output when the output switching element is turned off, while suppressing an increase in the delay time of the output switching element as much as possible.
[0019]
The control circuit (19) further comprises:
After the steps (g) and (f), it is preferable to execute a step of turning on the second ground-side switching element (16).
[0020]
In this case, the time when the control circuit (19) turns on the second ground-side switching element (16) in step (g) is substantially the time when the gate voltage of the output MISFET (5) starts to shift from the threshold voltage to 0. It is preferred that they be simultaneously simultaneous.
[0021]
When the control circuit (19) turns on the second ground-side switching element (16) in the step (g), the rate of change of the drain-source voltage of the output MISFET (5) is the second rate from the second rate of change. It is preferable that the time is substantially the same as the time of switching to the third change rate smaller than the change rate.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
In one embodiment of the inverter according to the present invention, as shown in FIG. 1, an inverter 1 is provided together with a three-phase motor 2. Inverter 1 supplies three-phase power to armature windings of three-phase motor 2 via power lines 3a to 3c.
[0023]
The inverter 1 includes a DC power supply 4, power MOS transistors 5a to 5f, gate drivers 6a to 6f, and a controller 7. DC power supply 4 generates a DC voltage between power supply line 4a and ground line 4b. The DC power supply 4, the power supply line 4a is kept at the power supply voltage _{V CC} with respect to ground line 4b.
[0024]
The power MOS transistors 5a to 5f are output switching elements for pulling up or pulling down the power lines 3a to 3c connected to the output of the inverter 1. The power MOS transistors 5a to 5f have a large drive capability (that is, have high driving capability). , W / L are large). Power MOS transistors 5a, 5b, 5c drain terminal of is connected to a power supply line 4a having a power supply voltage _{V CC,} the power MOS transistors 5a, 5b, the source terminal of 5c, are connected power lines 3a, 3b, and 3c . Power MOS transistors 5a, 5b, 5c are used to pull up power lines 3a, 3b, 3c to power supply voltage V _CC (High voltage), respectively. The drain terminals of the power MOS transistors 5d, 5e, 5f are connected to power lines 3a, 3b, 3c, respectively, and the source terminals of the power MOS transistors 5d, 5e, 5f are connected to the ground line 4b. The power MOS transistors 5d, 5e, 5f are used to pull down the power lines 3a, 3b, 3c to the ground potential (the potential of the ground line 4b).
[0025]
The gate terminals of the power MOS transistors 5a to 5f are connected to gate drivers 6a to 6f, respectively, and the power MOS transistors 5a to 5f are turned on and off by the gate drivers 6a to 6f, respectively. The gate drivers 6a to 6f are connected to the controller 7. The controller 7 outputs PWM signals 8a to 8f to the gate drivers 6a to 6 to turn on and off the power MOS transistors 5a to 5f, respectively. When the voltage of the PWM signals 8a to 8f is the power supply voltage _Vdd , the power MOS transistors 5a to 5f are turned on. When the voltage of the PWM signals 8a to 8f is 0, the power MOS transistors 5a to 5f are turned on. , Each turn off.
[0026]
The power MOS transistors 5a to 5f have the same structure, and are described as the power MOS transistor 5 unless otherwise specified. Further, the gate drivers 6a to 6f have the same configuration, and unless otherwise specified, these are described as gate drivers 6. Further, the PWM signals 8a to 8f are described as PWM signals 8 unless otherwise specified.
[0027]
FIG. 2 shows the configuration of the gate driver 6. The gate driver 6 includes a DC power supply 11, a P-channel MOS transistor 12, an adjustment resistor 13, an N-channel MOS transistor 14, an adjustment resistor 15, an N-channel MOS transistor 16, an adjustment resistor 17, a gate resistor 18, , Control circuit 19. In Figure 2, the armature winding of the three-phase motor 2, it is noted that it is represented as an impedance Z _L. Also note that the power supply is equivalently shown as power supply 30. The adjusting resistors 13, 15, and 17 have the same role as the gate resistor 18, and the gate current amount can be appropriately adjusted by adjusting the resistance values of the adjusting resistors 13, 15, and 17.
[0028]
The DC power supply 11 generates a DC voltage _Vdd between the power supply line 11a and the ground line 11b. The DC power supply 11 maintains the power supply line 11a at the power supply voltage _Vdd with respect to the ground line 11b.
[0029]
P-channel MOS transistor 12 and adjustment resistor 13 are connected in series between power supply line 11a and node 20. P channel MOS transistor 12 has a role of pulling up the gate terminal of power MOS transistor 5. The adjustment resistor 13 is provided for protecting the P-channel MOS transistor 12.
[0030]
An N-channel MOS transistor 14 and an adjustment resistor 15 connected in series and an N-channel MOS transistor 16 and an adjustment resistor 17 connected in series are connected in parallel between the node 20 and the ground line 11b. . The N-channel MOS transistors 14 and 16 have a role of pulling down the gate terminal of the power MOS transistor 5. The adjustment resistors 15 and 17 are provided for protecting the N-channel MOS transistors 14 and 16, respectively.
[0031]
A gate resistor 18 is interposed between the node 20 and the gate terminal of the power MOS transistor 5. The gate resistor 18 has a role of appropriately adjusting a gate current.
[0032]
Gate terminals of the P-channel MOS transistor 12, the N-channel MOS transistor 14, and the N-channel MOS transistor 16 are connected to a control circuit 19. The control circuit 19 controls on / off of the P-channel MOS transistor 12, the N-channel MOS transistor 14, and the N-channel MOS transistor 16.
[0033]
FIG. 3 is a timing chart showing the operation of the gate driver 6 when the power MOS transistor 5 is turned off from on. In the initial state (time t ₀ ), at time t ₀ , the PWM signal 8 is at the High voltage, and the gate voltages of the P-channel MOS transistor 12, the N-channel MOS transistor 14, and the N-channel MOS transistor gate 16 (as viewed from the gate 11b) Vg _Q1 , Vg _Q2 , Vg _Q3 are all Low voltages. In this state (t ₀ ), the gate-source voltage of the P-channel MOS transistor 12 is negative. In this state, P-channel MOS transistor 12 is on, and N-channel MOS transistors 14 and 16 are off. The gate voltage Vg of the power MOS transistor 5 is the power supply voltage _Vdd , and the power MOS transistor 5 is on.
[0034]
The operation of turning off the power MOS transistor 5 is started by the operation of turning off the P-channel MOS transistor 12 (time t ₁ ). When the PWM signal 8 becomes 0 voltage, the control circuit 19 pulls up the gate voltage (the voltage as viewed from 11b) of the P-channel MOS transistor 12 to the power supply voltage _Vdd and turns off the P-channel MOS transistor 12. When the P-channel MOS transistor 12 is turned off, the supply of the power supply voltage _Vdd to the gate terminal of the power MOS transistor 5 is stopped. However, the gate voltage Vg of the power MOS transistor 5 is substantially maintained at the power supply voltage _Vdd because there is substantially no path through which the charge flows out from the gate terminal.
[0035]
Subsequently, the control circuit 19 turns on both the N-channel MOS transistor 14 and the N-channel MOS transistor 16 (time t ₂ ). When the N-channel MOS transistors 14 and 16 are turned on, a gate current Ig is drawn from the gate terminal of the power MOS transistor 5. The drawing of the gate current Ig is illustrated in FIG. 3 by the flow of the negative gate current Ig. As the gate current Ig is drawn, the gate voltage Vg of the power MOS transistor 5 starts to decrease. Since the gate voltage Vg is reduced by the driving capabilities of both the N-channel MOS transistor 14 and the N-channel MOS transistor 16, the gate current Ig (the absolute value) is increased, and the gate voltage Vg is rapidly reduced. Thus, the delay time of the power MOS transistor 5 is reduced.
[0036]
While the gate voltage Vg is decreased, the drain / source voltage V _DS of the power MOS transistor 5 rises only a minute change rate. Therefore, even if the gate voltage Vg is rapidly reduced, noise is hardly generated in the output of the inverter 1. Change in the drain / source voltage V _DS between the gate voltage Vg is decreased, it can be approximated to be substantially linear with respect to time t.
[0037]
When the gate voltage Vg reaches the threshold voltage Vth of the power MOS transistor 5, the drain / source voltage _VDS starts to rise sharply. Change in the drain / source voltage V _DS can be approximated to be substantially linear with respect to time t. On the other hand, since the gate capacitance of the power MOS transistor 5 decreases, the gate voltage Vg is maintained at the threshold voltage Vth even if the gate current Ig flows. The gate voltage Vg, drain / source voltage _{V DS} of the power MOS transistor 5 is maintained at the threshold voltage Vth to approach the power supply voltage _{V dd.}
[0038]
Rate of change of the drain / source voltage V _DS at this time is dependent on the gate current Ig. When the gate current Ig between the gate voltage Vg is maintained at the threshold voltage Vth is large, the rate of change of the drain / source voltage V _DS increases, the high frequency noise is likely to occur in the output of the inverter 1.
[0039]
Therefore, the control circuit 19 turns off the N-channel MOS transistor 16 at substantially the same time when the gate voltage Vg reaches the threshold voltage Vth of the power MOS transistor 5. (Time t ₃ ). The N-channel MOS transistor 14 is kept on. The gate current Ig is drawn from the gate terminal of the power MOS transistor 5 by the drive capability of the N-channel MOS transistor 14 alone. As a result, while the drain / source voltage _VDS is increasing at a rapid change rate (that is, while the gate voltage Vg is maintained at the threshold voltage Vth), the gate current Ig is suppressed to a small value, and the drain / source voltage is reduced. The rate of change of the source-to-source voltage _VDS is kept small. Since the rate of change of the drain-source voltage _VDS is suppressed, noise is less likely to be generated in the output of the inverter 1.
[0040]
Drain / source voltage _{V DS} approaches the power supply voltage _{V dd,} the gate voltage Vg begins to transition to a Low voltage from the threshold voltage Vth (time _t 4). At substantially the same time that the gate voltage Vg starts to shift from the threshold voltage Vth to 0, the control circuit 19 turns on the N-channel MOS transistor 16 again. The gate voltage Vg is reduced by the drive capability of both the N-channel MOS transistor 14 and the N-channel MOS transistor 16, and the gate voltage Vg is quickly pulled down to zero. In the meantime, since the power rate of change of the drain / source voltage V _DS of the MOS transistor 5 is small, the output of the inverter 1 is noise is less likely to occur. Change in the meantime in the drain / source voltage V _DS can be approximated to be substantially linear with respect to time t.
[0041]
By turning off the power MOS transistor 5 by the above operation, it is possible to reduce the high-frequency noise generated at the output of the inverter 1 at the time of turning off, while suppressing the increase in the delay time of the power MOS transistor 5 as much as possible. It is.
[0042]
In the present embodiment, even when the transition from the threshold voltage Vth to 0 starts, the N-channel MOS transistor 16 can be kept off. Such an operation is preferable in that the operation of the control circuit 19 is simplified. On the other hand, from the viewpoint of further reducing the delay time of the power MOS transistor 5, it is preferable that the N-channel MOS transistor 16 be turned on when starting to shift from the threshold voltage Vth to 0.
[0043]
Further, in the present embodiment, the driving of the gate terminal of the power MOS transistor 5 can be performed by a bipolar transistor instead of the P-channel MOS transistor 12 and the N-channel MOS transistors 14 and 16.
The drive unit of the IGBT has the same gate structure as the MOSFET. Therefore, the present invention is also applicable to IGBTs. Further, the above MOSFET may be read as IGBT.
[0044]
【The invention's effect】
According to the present invention, there is provided an inverter capable of reducing high-frequency noise generated at an output when the output switching element is turned off, while suppressing an increase in delay time of the output switching element as much as possible.
[Brief description of the drawings]
FIG. 1 shows an embodiment of an inverter according to the present invention.
FIG. 2 shows a configuration of a gate driver 6.
FIG. 3 is a timing chart showing the operation of the gate driver 6.
[Explanation of symbols]
1: Inverter 2: Three-phase motors 3a to 3c: Power line 4: DC power supply 4a: Power supply line 4b: Ground line 5 (5a to 5f): Power MOS transistor 6 (6a to 6f): Gate driver 7: Controller 8 (8a) 8f): PWM signal 11: DC power supply 11a: power supply line 11b: ground line 12: P-channel MOS transistor 13: adjustment resistor 14: N-channel MOS transistor 15: adjustment resistor 16: N-channel MOS transistor 17: adjustment resistor 18: Gate resistance 19: Control circuit 20: Node

Claims (15)

An output MISFET connected to the load,
A gate driver for applying a gate voltage to a gate terminal of the output MISFET;
When the gate driver changes the gate voltage from the power supply voltage _VCC to 0,
(A) extracting a gate current from the gate terminal with a first drive capability;
(B) after the step (a), extracting the gate current from the gate terminal with a second drive ability smaller than the first drive ability;
An inverter in which the time when the gate driver starts executing the step (b) is substantially the same as the time when the gate voltage of the output MISFET becomes the threshold voltage of the output MISFET. An output MISFET connected to the load,
A gate driver for applying a gate voltage to a gate terminal of the output MISFET;
When the gate driver changes the gate voltage from the power supply voltage _VCC to 0,
(A) extracting a gate current from the gate terminal with a first drive capability;
(B) after the step (a), extracting the gate current from the gate terminal with a second drive ability smaller than the first drive ability;
The time when the gate driver starts executing the step (b) is the time when the change rate of the drain-source voltage of the output MISFET switches from the first change rate to the second change rate larger than the first change rate. And an inverter that is substantially the same. 3. The gate driver according to claim 1, wherein the gate driver further executes a step of (c) extracting a gate current from the gate terminal with a third drive capability greater than the second drive capability after the step (b). 4. Inverter as described. 4. The inverter according to claim 3, wherein the time when the gate driver starts executing the step (c) is substantially the same as the time when the gate voltage of the output MISFET starts to transition from the threshold voltage to 0. . At the time when the gate driver starts executing the step (c), the change rate of the drain-source voltage of the output MISFET is changed from the second change rate to a third change rate smaller than the second change rate. 4. The inverter according to claim 3, wherein the switching time is substantially the same as the switching time. The inverter according to claim 3, wherein the first drive capability and the third drive capability are the same. An output MISFET connected to the load,
A ground terminal,
A power terminal having a power voltage V _CC with respect to the ground terminal;
A power supply side switching element interposed between the gate terminal of the output MISFET and the power supply terminal;
A first ground-side switching element interposed between the gate terminal and the ground terminal;
A second ground-side switching element interposed between the gate terminal and the ground terminal;
A control circuit for controlling the power supply side switching element, the first ground side switching element, and the second ground side switching element;
When the control circuit turns off the output MISFET,
(D) turning off the power supply side switching element;
(E) turning on the first ground-side switching element and the second ground-side switching element after the step (d);
(F) after the step (e), turning off the second ground-side switching element.
An inverter in which a time at which the control circuit turns off the second ground-side switching element is substantially the same as a time at which the gate voltage of the output MISFET becomes a threshold voltage of the output MISFET. An output MISFET connected to the load,
A ground terminal,
A power terminal having a power voltage V _CC with respect to the ground terminal;
A power supply side switching element interposed between the gate terminal of the output MISFET and the power supply terminal;
A first ground-side switching element interposed between the gate terminal and the ground terminal;
A second ground-side switching element interposed between the gate terminal and the ground terminal;
A control circuit for controlling the power supply side switching element, the first ground side switching element, and the second ground side switching element;
When the control circuit turns off the output MISFET,
(D) turning off the power supply side switching element;
(E) turning on the first ground-side switching element and the second ground-side switching element after the step (d);
(F) after the step (e), turning off the second ground-side switching element.
The time when the control circuit turns off the second ground-side switching element is the time when the rate of change of the drain-source voltage of the output MISFET switches from the first rate of change to a second rate of change that is greater than the first rate of change. An inverter that substantially matches. The control circuit further comprises:
9. The inverter according to claim 7, wherein after the step (f), the step of turning on the second switching element is performed. The time when the control circuit turns on the second ground-side switching element in the step (g) substantially coincides with the time when the gate voltage of the output MISFET starts to shift from the threshold voltage to zero. An inverter according to claim 9. When the control circuit turns on the second ground-side switching element in the step (g), the change rate of the drain-source voltage of the output MISFET is smaller than the second change rate from the second change rate. The inverter according to claim 9, wherein the time is substantially the same as the time when the switching to the third rate of change is performed. (H) changing the gate voltage of the output MISFET connected to the load from the power supply voltage _VCC to 0,
The step (h) includes:
(H1) drawing a gate current from the gate terminal of the output MISFET with the first drive capability and stepping the gate voltage of the output MISFET;
(H2) after the step (h1), extracting the gate current from the gate terminal with a second drive capability smaller than the first drive capability.
The method of operating an inverter, wherein the time when the execution of the step (h2) is started is substantially the same as the time when the gate voltage of the output MISFET becomes the threshold voltage of the output MISFET. (H) changing the gate voltage of the output MISFET connected to the load from the power supply voltage _VCC to 0,
The step (h) includes:
(H1) drawing a gate current from the gate terminal of the output MISFET with the first drive capability and stepping the gate voltage of the output MISFET;
(H2) after the step (h1), extracting the gate current from the gate terminal with a second drive capability smaller than the first drive capability.
The time when the execution of the step (h2) is started is substantially the same as the time when the change rate of the drain-source voltage of the output MISFET switches from the first change rate to the second change rate larger than the first change rate. Inverter operation method that is the same as An output MISFET connected to the load,
A ground terminal,
A power terminal having a power voltage V _CC with respect to the ground terminal;
A power supply side switching element interposed between the gate terminal of the output MISFET and the power supply terminal;
A first ground-side switching element interposed between the gate terminal and the ground terminal;
A second ground-side switching element interposed between the gate terminal and the ground terminal;
An operation method of an inverter having:
(I) turning off the power supply side switching element;
(J) turning on the first ground-side switching element and the second ground-side switching element after the step (i);
(K) after the step (j), turning off the second ground-side switching element;
The method of operating an inverter, wherein a time at which the second ground-side switching element is turned off is substantially the same as a time at which the gate voltage of the output MISFET becomes a threshold voltage of the output MISFET. An output MISFET connected to the load,
A ground terminal,
A power terminal having a power voltage V _CC with respect to the ground terminal;
A power supply side switching element interposed between the gate terminal of the output MISFET and the power supply terminal;
A first ground-side switching element interposed between the gate terminal and the ground terminal;
A second ground-side switching element interposed between the gate terminal and the ground terminal;
An operation method of an inverter having:
(I) turning off the power supply side switching element;
(J) turning on the first ground-side switching element and the second ground-side switching element after the step (i);
(K) after the step (j), turning off the second ground-side switching element;
The time at which the second ground-side switching element is turned off is substantially the time at which the rate of change of the drain-source voltage of the output MISFET switches from the first rate of change to a second rate of change greater than the first rate of change. Inverter operation method that matches.

Images