JP2004145435A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power source noises from digital circuits, relating to a semiconductor integrated circuit which effectively controls clock generation. <P>SOLUTION: A clock generation circuit 100 receives the input of a reference clock with a period T and outputs a plurality of partial clocks 11-11n each with a phase difference which is an integer multiple of the reference clock. A clock control circuit 106 controls the period and phase difference of the partial clocks 11-1n. With the circuit blocks 1031-103n operated by the partial clocks each with the phase difference which is an integer multiple of the reference block, peak currents are reduced to reduce the power source noise. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit that effectively controls generation of a clock.
[0002]
2. Description of the Related Art Generally, in a semiconductor integrated circuit, a plurality of circuit blocks operate in synchronization with a clock. Therefore, a peak current is generated at a change point of the clock, which causes noise in the power supply. This power supply noise has become a major problem in designing equipment on which a semiconductor integrated circuit is mounted.
[0003]
FIG. 6 shows a timing chart of a semiconductor integrated circuit in which no countermeasures are taken for peak current. In FIG. 6, clocks 61 to 6n have the same phase, a peak current is generated at a change point of the clock, and noise is generated in the power supply. Therefore, as a method of reducing the peak current at the transition point of the clock, a method of shifting the phases of the respective clocks so that the phases of the clocks are different has been conventionally performed (for example, see Patent Document 1).
[0004]
FIG. 4 shows a circuit configuration in which a conventional peak current reduction circuit has taken measures against power supply noise. Conventionally, the clock is delayed by the delay gate 401 to generate the clocks 41 to 4n. FIG. 5 shows a timing chart in the conventional clock generation. As shown in FIG. 5, the clocks 41 to 4n are shifted in phase according to the delay set by the delay gate 401, and the peak current is reduced.
[0005]
[Patent Document 1]
JP-A-2002-158286 (pages 3 to 6, FIG. 5)
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional method, there is a problem that the delay varies due to process variations because the phase of the clock is shifted by the delay gate. Further, when the clock frequency is high, there is a problem that fine adjustment is difficult.
[0007]
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit that can easily and easily shift the phase of a clock.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a solution taken specifically by the invention of claim 1 is a clock which generates a plurality of clocks having a phase difference of time nT (n is an integer) by inputting a reference clock having a period T. It is characterized by comprising a generating means, and a clock control means for controlling a cycle and a phase difference of the plurality of clocks.
[0009]
In order to achieve the above object, a solution specifically taken by the invention of claim 2 is to input a reference clock having a period T and generate a plurality of clocks having a phase difference of time nT (n is an integer). Clock generating means for controlling the cycle and phase difference of the plurality of clocks, and circuit block state monitoring means for estimating current consumption of each circuit block and outputting the estimated current to the clock control means. I do.
[0010]
In order to achieve the above object, specifically, the solution taken by the invention of claim 3 is a clock generation means according to claim 1 or 2, wherein the clock generation means counts at the reference clock cycle; It is characterized by comprising partial clock generating means for generating the plurality of clocks having different phases and periods from the output of the counter means.
[0011]
In order to achieve the above-mentioned object, the present invention according to a fourth aspect of the present invention resides in that the partial clock generating means according to the third aspect is configured such that the partial clock generating means generates a plurality of control signals generated from a plurality of control signals from the clock control means. A plurality of coincidence detecting means for comparing the numerical value of the counter with the counter output; a logical sum generating means for generating a logical sum of all of the plural coincidence detecting means; A latch means for latching at a clock timing is provided.
[0012]
In order to achieve the above-mentioned object, the present invention according to claim 5, wherein the partial clock generating means according to claim 3, wherein the partial clock generating means stores waveform information using the counter output as an address input. It is characterized by having.
[0013]
In order to achieve the above object, according to a sixth aspect of the present invention, each circuit block includes a circuit operation information generating unit. It is characterized by comprising a plurality of partial block state monitoring means for receiving current consumption estimation information from blocks and estimating current consumption of each circuit block.
[0014]
In order to achieve the above object, specifically, according to an embodiment of the present invention, a circuit operation information generating unit outputs a toggle signal indicating that a signal of an arbitrary node of each circuit block has changed. The partial block state monitoring means according to claim 6, further comprising averaging means for receiving a toggle signal as input and obtaining an average value.
[0015]
In order to achieve the above object, specifically, according to an embodiment of the present invention, the circuit operation information generating unit includes a current measuring unit that measures and outputs a current of each of the circuit blocks. The partial block state monitoring means described in Item 6 is characterized by comprising an averaging means for receiving an output of the current measuring means as an input and obtaining an average value.
[0016]
In order to achieve the above object, a solution means specifically taken by the invention of claim 9 is that the circuit operation information generation means includes a temperature measurement means for measuring and outputting the temperature of an arbitrary place of each circuit block, According to a sixth aspect of the present invention, the partial block state monitoring means is provided with an averaging means for receiving an output of the temperature measuring means and obtaining an average value.
[0017]
Further, in order to achieve the above object, a solution taken specifically by the invention of claim 10 is to increase the clock phase difference between circuit blocks having large current consumption estimated by the clock control means according to claim 2. It is characterized by the following.
[0018]
Further, in order to achieve the above object, a solution specifically taken by the invention of claim 11 is characterized in that a period and a phase difference can be directly set by inputting a control signal from the outside.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
FIG. 1 shows a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 100 receives a reference clock as input and outputs a plurality of partial clocks 11 to 1n each having a phase difference of an integral multiple of the reference clock. The semiconductor integrated circuit 100 includes a counter 101 that counts with a reference clock, and partial clock generation circuits 1021 to 102n that generate partial clocks 11 to 1n based on a count value output from the counter 101 and a clock control signal output from a clock control circuit 106. Is provided. The circuit blocks 1031 to 103n are a group of circuit blocks that operate with the partial clocks 11 to 1n and input and output signals to and from each other. The circuit block state monitoring circuit 104 monitors a plurality of circuit block states based on circuit operation information from each circuit block group. Output a signal. The circuit block state monitoring circuit 104 includes partial block state monitoring circuits 1051 to 105n that generate circuit block state monitoring signals from partial circuit operation information output from the circuit operation information generation circuits 1071 to 107n included in the circuit blocks 1031 to 103n. The clock control circuit 106 generates a clock control signal for controlling the phases and periods of the partial clocks 11 to 1n from the circuit block state monitoring signals output from the partial block state monitoring circuits 1051 to 105n.
[0021]
The detailed operation of the semiconductor integrated circuit configured as described above will be described with reference to the timing chart of FIG. 2 and FIG. 2A, a reference clock having a period T for operating the counter 101, an output of the counter 101 in FIG. 2B, an output of the OR circuit 303 in FIG. 2C, and a part in FIGS. 2D, 2F, and 2G. It shows the partial clocks generated by the clock generation circuits 1021 to 102n, and (i) shows the operating current. FIG. 3 shows a configuration example of the partial clock generation circuit 1021. In FIG. 3, the coincidence circuits 301a to 301d are set in the registers 302a to 302d by the output of the counter 101 and the clock control signal output from the clock control circuit 106. The logical sum circuit 303 performs a logical sum of the outputs of the match circuits 301a to 301d, and the latch circuit 304 latches the output of the logical sum circuit 303 with a reference clock to generate a partial clock. Is output. Based on the output of the counter 101 and the numerical values a to d, the coincidence circuits 301a to 301b detect a match, and the OR circuit 303 performs a logical sum of the respective match detection results. In the case of the partial clock 11 shown in FIG. 2, the numerical values a to d are set to 0, 1 by the clock control signal so that the logical value is 1 when the numerical value count value is 0 to 3 and the logical value is 0 when 4 to 7 , 2, and 3 to generate a partial clock as shown in FIG. It is sufficient that 0, 1, 2, and 3 are all set in any of the registers 302a to 302d, and it does not matter which register is set. Each of the partial clock generation circuits 1022 to 102n has the same configuration as that of FIG. 3, so that the partial clocks 12 to 1n are also controlled by the count value and the clock control signal, and the logic shown in FIGS. A sum is generated to generate a partial clock as shown in (f) and (h).
As a result, since the rising edges of the respective partial clocks do not overlap, an operating current with a reduced peak current as shown in (i) is obtained.
[0022]
With this configuration, it is possible to generate a clock having an arbitrary cycle having a phase difference of cycle T. Here, by shifting the rising edge of each partial clock, it is possible to reduce the peak current and thus the power supply noise. When the cycle required for the clock is limited by each circuit block, the value of the register may be set so that the cycle of the corresponding clock is fixed.
[0023]
Further, the circuit block state monitoring circuit 104 estimates the current consumption of each block and outputs the estimated current consumption to the clock control circuit 106. For estimating the current consumption, it is possible to use toggle information indicating that a signal at an arbitrary node of each circuit block has changed. The toggle information output can be output by an easy circuit that outputs a signal of logical value 1 every time the signal of each node toggles. The partial block state monitoring circuits 1051 to 105n are circuits for estimating the current consumption of each of the circuit blocks 1031 to 103n. The current consumption is estimated from the average value of the toggle information signal. The clock control circuit 106 outputs a clock control signal based on the output of the circuit block state monitoring circuit 104. At this time, the peak current can be further reduced by controlling so as to increase the phase difference between the clocks supplied to the blocks consuming a large amount of current.
[0024]
Note that, in the present embodiment, the configuration in which the numerical value is controlled by the clock control signal has been described. However, in the case where the distribution of the current consumption is known in advance, even when the numerical value output as the clock control signal is a fixed value, The same effect can be obtained, and the circuit scale can be reduced.
[0025]
In this embodiment, the clock control signal is controlled by the circuit block state monitoring circuit and the clock control circuit. However, the clock control signal may be directly controlled from outside the semiconductor integrated circuit. In this case, the circuit scale can be reduced and more flexible control is possible.
[0026]
Further, in the present embodiment, the toggle information is used for estimating the current consumption, but information on only the rise or fall of a signal at an arbitrary node may be used.
[0027]
Further, the output of the current measuring means for measuring the current supplied to each circuit block may be used as the estimation of the current consumption. In this case, more accurate estimation is possible.
[0028]
Further, the current consumption may be estimated from a temperature measurement result at an arbitrary location in each circuit block.
[0029]
Furthermore, the partial clock generation circuit may be configured by a memory in which the output of the counter 101 is used as an address input and waveform information is stored.
[0030]
Further, the clock control signal may be controlled so that the partial clock generated by the partial clock generation circuit is a gated clock. In this case, the average current can be reduced.
[0031]
Further, the clock phase control signal is generated by the configuration of the circuit block state monitoring circuit and the clock control circuit, but may be generated inside the circuit blocks 1031 to 103n. In this case, more detailed clock phase control becomes possible.
[0032]
【The invention's effect】
As described above, according to the present invention, it is possible to logically generate clocks having different phases and periods in the period T of the reference clock, and it is possible to easily and easily adjust the phase of the clock. Further, by shifting the phase of the clock, the peak current is reduced and the power supply noise can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a timing chart of the semiconductor integrated circuit according to an embodiment of the present invention. FIG. 3 is a partial clock generation circuit according to an embodiment of the present invention. FIG. 4 is a configuration diagram showing a conventional semiconductor integrated circuit. FIG. 5 is a timing chart of a semiconductor integrated circuit when the conventional peak current is reduced. FIG. 6 is a semiconductor integration when the conventional peak current is not reduced. Circuit timing chart [Explanation of symbols]
REFERENCE SIGNS LIST 100 clock generation circuit 101 counters 1021 to 102 n partial clock generation circuits 1031 to 103 n circuit block 104 circuit block state monitoring circuits 1051 to 105 n partial block state monitoring circuit 106 clock control circuits 1071 to 107 n circuit operation information generation circuit

Claims (11)

Clock generating means for receiving a reference clock having a period T as input and generating a plurality of clocks having a phase difference of time nT (n is an integer), and clock controlling means for controlling a period and a phase difference of the plurality of clocks A semiconductor integrated circuit characterized by the above-mentioned. A clock generation unit that receives a reference clock having a period T as input and generates a plurality of clocks having a phase difference of time nT (n is an integer); a clock control unit that controls a period and a phase difference of the plurality of clocks; A semiconductor integrated circuit comprising: a circuit block state monitoring unit that estimates current consumption of a circuit block and outputs the estimated current to the clock control unit. 3. The clock generating means according to claim 1, further comprising: counter means for counting at the reference clock cycle; and partial clock generating means for generating the plurality of clocks having different phases and periods from the output of the counter means. A semiconductor integrated circuit characterized by the above-mentioned. 4. The plurality of coincidence detecting means for comparing a plurality of numerical values generated from a plurality of control signals from the clock control means with the counter output, and the plurality of coincidence detecting means, wherein the partial clock generating means according to claim 3 is provided. A semiconductor integrated circuit, comprising: a logical sum generating means for generating all logical sums of the above; 4. A semiconductor integrated circuit according to claim 3, wherein said partial clock generating means includes memory means for storing waveform information having said counter output as an address input. 3. The semiconductor integrated circuit according to claim 2, wherein each circuit block includes circuit operation information generation means, and said circuit block state monitoring means outputs current consumption estimation information from each circuit block output from said circuit operation information generation means. And a plurality of partial block state monitoring means for estimating a current consumption of each circuit block. 7. The semiconductor integrated circuit according to claim 6, wherein said circuit operation information generating means outputs a toggle signal indicating that a signal of an arbitrary node of each of said circuit blocks has changed, and said partial block state monitoring means has said current consumption. A semiconductor integrated circuit comprising averaging means for receiving the toggle signal as estimation information and calculating an average value. 7. The semiconductor integrated circuit according to claim 6, wherein said circuit operation information generating means includes a current measuring means for measuring and outputting a current of each of said circuit blocks, and said partial block state monitoring means is configured to output said current as said consumed current estimation information. A semiconductor integrated circuit comprising an averaging means for receiving an output of a measuring means as an input and obtaining an average value. 7. The semiconductor integrated circuit according to claim 6, wherein said circuit operation information generating means includes a temperature measuring means for measuring and outputting a temperature at an arbitrary place of each circuit block, and said partial block state monitoring means comprises: And an averaging means for receiving an output of the temperature measuring means as an input and obtaining an average value. 3. A semiconductor integrated circuit, wherein a clock phase difference between circuit blocks having large current consumption estimated by the clock control means according to claim 2 is increased. 2. The semiconductor integrated circuit according to claim 1, wherein a period and a phase difference can be directly set by inputting a control signal from outside.

Images