JPH11143572A - Clock generation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the peak level of harmonic noise generated from a clock needed for the operation of a microcomputer. SOLUTION: A clock signal is generated by an oscillator 1 is inputted to a clock shaping circuit 2 in a microcomputer package and is reshaped as a rectangular wave. A frequency adjusting circuit 3 changes the frequency of a clock by randomly or cyclically delaying it within the range that defines a rise edge, a fall edge or both of them. The clock signal whose reshaping and frequency are adjusted is divided by a clock frequency dividing circuit 4 and is supplied to function blocks that constitute the microcomputer such as a port control 5, an interrupt control 6, an A/D D/A control 7 and a bus interface 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation method for a microcomputer, and more particularly, to a clock generation method for a microcomputer involving transmission and reception of radio waves.

[0002]

2. Description of the Related Art Generally, a microcomputer (hereinafter, referred to as a microcomputer)
In a device using a microcomputer, an oscillator supplies a clock necessary for the operation of the microcomputer, and the oscillator oscillates at a frequency unique to the oscillator.

In a device using a microcomputer, an unnecessary signal such as a harmonic component of a clock generated from a mechanism which operates in response to the clock interferes with a signal which the device originally intends to handle, and transmits / receives a signal. And so on.

[0004] There are various effects caused by harmonics actually generated based on the operation clock. In the case of wireless communication equipment, particularly in the case of a mobile phone, connection and connection which are basic functions of the mobile phone are performed. In communication, radio waves of a plurality of frequencies are used for control and communication. If radio waves of a plurality of frequencies are used, the probability of occurrence of a frequency that is subject to interference by harmonics generated from the operation clock of the microcomputer increases.

If radio waves used for control and communication interfere with harmonics generated from the operation clock, the control information exchanged between the mobile phone terminal and the base station, for example, phase-modulated data may be The mixing of waves may change the level of the received wave and cause a phase shift, and important information such as terminal authentication and call channel assignment may not be transmitted correctly. May be mixed.

A conventional measure for reducing noise of a microcomputer is to adjust the operating clock frequency of the microcomputer to set it to a frequency that does not interfere with the signals used by the device, or to set the oscillation clock of the microcomputer and the In order to prevent interference with the signals used by the devices, hardware measures such as shielding and isolation were taken. In some cases, a clock signal is analyzed and a noise canceller signal is generated and superimposed to eliminate harmonic noise components.

Here, as a conventional example, harmonics included in the operation clock of the microcomputer are analyzed by analyzing the operation clock signal.
A signal that generates a signal having a component that cancels the harmonic component by the inverse Fourier transform and cancels the harmonic component by superimposing the signal on a clock signal is introduced.

Conventionally, this type of noise suppression oscillator for a system LSI has been designed to reduce noise caused by harmonics generated with clock oscillation in a clock oscillator as disclosed in, for example, JP-A-6-315259. It is used as

FIG. 7 is a block diagram showing a noise reduction device described in the above publication. This noise reduction device includes a PWM signal generator PS, a drive circuit D, a load L, and a DC power supply B, as well as a current sensor 10 and a frequency analysis unit 2 as components generally seen from a clock oscillator to a load.
0, a signal processing unit 30, an inverse Fourier transform unit 40, a PLL unit 50, and a mixing unit 60.

The current sensor 10 detects the load current, and the frequency analysis unit 20 measures the spectrum of the load current.
The signal processing unit 30 calculates an erasure spectrum based on the spectrum, and the inverse Fourier transform unit 40 generates a noise canceller signal based on the erasure spectrum calculation result. The PLL unit 50 synchronizes the noise canceller signal with the load current, and the mixing unit 60 combines the noise canceller signal and the signal from the PWM signal generator PS.

As described above, the amplitude and the phase are obtained for each frequency with respect to the harmonic which becomes noise, the waveform having the amplitude and the phase which attenuates the harmonic most is obtained, the noise canceller signal is generated, and the PWM signal generator PS The harmonic noise is suppressed by superimposing the signal on the signal from the controller and inputting the signal to the drive circuit D.

[0012]

A first problem of a device using a microcomputer is generation of harmonic noise. Noise generated by the clock of the microcomputer can be generated by all circuits operated by the operation clock, but a main source of the noise is a signal line extending from a port of the microcomputer to a peripheral circuit over a wide range. When the levels of these signal lines are turned on / off, harmonic noise is generated from the pulses.

Of course, the oscillation clock itself does not ride on these ports, but the on / off control of the ports is performed in synchronization with a clock obtained by dividing the oscillation clock. As long as the signal is controlled in synchronization with the clock, the output signal is composed of pulses having a width that is an integral multiple of the original oscillation clock.

A signal generated by turning on / off a port has various widths of a high level and a low level.
If both are regarded as pulses having both rising and falling edges, the interval between the peak frequencies of the harmonics by the pulse is inversely proportional to the pulse period, and the envelope representing the relationship between the frequency of occurrence of the harmonics and the peak level is: It is inversely proportional to the pulse width.

In any case, even if the shape of the pulse on the signal line is seemingly random, as long as the pulse is an integral multiple of the clock, the harmonics generated therewith have some relation to the clock. Further, when a pulse having a certain shape such as a clock signal between the microcomputer and the memory is continuously generated, the generated harmonic also has a certain shape.

For example, PHS used in Japan
In the case of, digital signals of 0 and 1 used in control and communication are superimposed on a carrier by a phase modulation method called π / 4 shift QPSK modulation.

Not only when information is superimposed by such phase modulation, but also in other cases, when a harmonic is generated at a frequency very close to the carrier, the carrier is affected by level fluctuation and phase shift, In some cases, normal demodulation may not be performed, and communication using the carrier may not be performed.

The abnormal operation of the system due to harmonic noise has been treated as a problem to be solved before, and various attempts have been made to solve the problem.

As described above, even if the operating clock frequency of the microcomputer is adjusted to a frequency that does not interfere with the signal used by the device, the frequency band that interferes between the two signals is merely shifted. However, if the signal bandwidth required by the device is wide, no matter how the clock frequency of the microcomputer is adjusted, interference will occur in some frequency band, and this will not be a fundamental solution. Changing the frequency of the operation clock may adversely affect a mechanism such as a clock of the system that requires time accuracy, and is not practical.

On the other hand, if hardware measures such as shielding and isolation are performed so that the oscillation clock of the microcomputer does not interfere with the signals used by the device, fundamentally harmful oscillation signals can be suppressed. Even if the band of the signal to be handled is wide as described above, no problem occurs. However, in order to deal with shielding and isolation in a hardware manner, if noise sources such as buses around the microcomputer are widespread, all of them must be shielded and isolated, and that much space is required. And all the equipment goes against the trend toward lightness and small size, which is not very realistic.

As shown in FIG. 7, a device for adding a negative-phase signal of the harmonic component of the original oscillation signal to the operation clock of the microcomputer to cancel the harmonic component is used to reduce the harmonic component. A complicated additional circuit such as a clock signal analysis mechanism and an inverse Fourier transform unit for generating a harmonic component is required, and it cannot be said to be superior in cost.

The second problem of the device using the microcomputer is as follows.
This is the effect of the clock error. The frequency of the clock according to the present invention is adjusted within a specified range by a frequency adjustment circuit built in a system control unit or the like of the microcomputer.

When the frequency of the clock serving as the operation reference changes, noise generated due to the operation of each functional block of the microcomputer is dispersed in frequency. On the other hand, in the case where a microcomputer is provided with a function for obtaining the accuracy of a clock, such as a clock, there is a concern that if the operation reference clock is unstable in frequency, a problem may occur in the reliability of the operation.

An object of the present invention is to provide a clock generation method for reducing the influence of harmonic noise generated from a clock required for operation of a microcomputer on a circuit controlled by the microcomputer.

Another object of the present invention is to provide a clock generation apparatus which solves the problems of measures conventionally taken as countermeasures for harmonic noise, such as requiring a complicated circuit and affecting operation performance. It is to provide a method.

[0026]

The present invention comprises an oscillator,
In a clock generation method of a semiconductor integrated circuit having a waveform shaping means for shaping an output signal of the oscillator and outputting a clock signal, a frequency is adjusted by delaying a rising edge, a falling edge, or both edges of the clock signal. Having means. In order to control the delay time, there is provided a means for randomly selecting a delay element for generating a delay signal, or a means for storing a delay pattern in a storage element and reading it in synchronization with a clock.

According to the present invention, since a harmonic component itself generated from a mechanism that operates in response to a clock is suppressed, a complicated mechanism such as shielding or isolating a noise source or generating and superimposing a noise canceller signal is not required. It is not necessary to take measures to limit the operation of the system, such as operating at a shifted frequency.

Further, in the present invention, the frequency of the clock signal to be generated is changed randomly or periodically within a designated range, so that the time information obtained by dividing the clock can be accurately maintained while maintaining the basic frequency. The noise component generated as a harmonic of the above can be dispersed in frequency, and the peak level of the noise can be suppressed low.

[0029]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a microcomputer provided with a noise reduction mechanism according to the clock generation method of the present invention. The microcomputer shown in FIG. 1 is a general microcomputer configuration including a clock oscillator 1, a clock shaping circuit 2, a clock frequency dividing circuit 4, a port control 5, an interrupt control 6, an A / D, a D / A control 7, The frequency adjustment circuit 3 is connected to the bus interface 8.
Is added.

The configuration of the microcomputer may include addition or deletion of functional blocks as long as there are an oscillator 1, a clock shaping circuit 2, a frequency adjusting circuit 3, and a clock dividing circuit 4 related to clock generation.

The clock signal generated by the oscillator 1 enters a clock shaping circuit 2 in the microcomputer package and is shaped as a rectangular wave. The frequency adjustment circuit 3 randomly or periodically delays the rising edge, the falling edge, or both within a prescribed range to change the clock frequency.

The shaped and frequency-adjusted clock signal is frequency-divided by the clock frequency dividing circuit 4, and the port control 5, interrupt control 6, A / D, D /
The signals are supplied to functional blocks constituting the microcomputer, such as the A control 7 and the bus interface 8. A control signal is transmitted from each control block that operates in response to the clock to peripheral devices such as a key matrix and a memory connected outside the microcomputer.

FIG. 2 is a configuration diagram of a microcomputer having no noise reduction mechanism. Clock shaping circuit 12
1 and the clock divider 14, only the frequency adjustment circuit is not provided, and the configuration and the operation of each unit are the same as those in FIG.

FIG. 3 is a detailed configuration diagram of the frequency adjustment circuit 3 of FIG. This extends the H level period of the clock and delays the falling edge.

The frequency adjusting circuit 3 randomly takes a 4-bit value for delaying the signal from the oscillator 1 to the H level.
Bit random counter 24 and random counter 4
4 to output H level from only one of 16 output ports using bit information (0 to 15) as selection information
H, which has 16 decoders 25, 15 delay elements 26 to 40 each having a different delay time, and an OR element 57 for synthesizing the output signals of the delay elements,
It comprises a set / reset F / F element 58 that generates a new signal from the falling edge of the signal and the rising edge of the original L signal. The clock supplied from the clock shaping circuit 2 in FIG. 1 is a 4-bit random counter 24, a 4to16 decoder 25 in FIG.
ND element 41, inverter 23, and delay elements 26-4
It reaches 0.

The 4-bit random counter 24 and 4to
The 16 decoder 25 operates with the supplied clock. The 4-bit output of the 4-bit random counter 24 is
The signal is transmitted to the 4to16 decoder 25, and the output port of the 4to16 decoder 25 is controlled so that only one of the 16 ports is at the active level.

The 16 outputs of the 4to16 decoder 25 are transmitted to 16 AND elements 41 to 56, and select a clock signal delayed by the delay elements 26 to 40 and a clock signal which is not delayed. The clocks selected by the AND elements 41 to 56 of which only one of the 16 gates is open pass through the OR element 57 and enter the set terminal of the set / reset F / F 58.

An undelayed clock is supplied from the inverter 23 to the reset terminal of the set / reset F / F 58. As a result, the output of the set / reset F / F 58 becomes a signal in which only the in-phase or the rising edge is delayed as compared with the signal before being supplied to the frequency adjustment circuit 3.

FIG. 4 shows a case where the L level period is extended and the rising edge is delayed. Although not shown, if the circuit example of FIG. 3 and the circuit example of FIG. 4 are combined,
Both rising and falling edges can be delayed.

If the microcomputer receiving this clock operates at the falling edge of the clock, the mechanism for delaying the falling edge is used as described above. If the microcomputer operates at the rising edge, , L level and a rising edge are delayed. If necessary, both edges can be delayed.

Of course, the number of bits of the random counter,
As long as the number of input / output bits of the decoder and the number of delay elements are not theoretically wrong, this oscillator is established as long as there is no theoretical error.

The frequency adjustment circuit is not limited to being built in a microcomputer or the like, but can be realized by changing the circuit configuration, such as by integrating it with an oscillator.

The operation of the delay element will be described with reference to FIG. The 15 delay elements 26 to 40 have different delay times, respectively, and only one signal selected by the output of the 4to16 decoder 25 outputs the set / reset F / F5.
8, the delay time is in the range in which the frequency of the original oscillation signal is adjusted. Therefore, the maximum delay time is within the frequency range of the original oscillation and the frequency range required by the device to which the oscillation signal is supplied. Set to fit.

For example, when an oscillation signal is supplied to a device whose original oscillation is 10 MHz and a frequency error is specified to be within 5%, the delay time by the delay element is 5% of the longest one clock period 100 ns. 4.8 ns
And At this time, the frequency of the original oscillation changes in the following range.

Original oscillation frequency = 10000 kHz Original oscillation cycle = 100.0 ns + 5% on the side = 10500 kHz
z + side 5% = 95.2 ns Difference from the period of original oscillation = 4.8 ns-side 5% =
9500 kHz-5% on the negative side = 105.2 ns Difference from the period of the original oscillation = 5.2 ns The output frequency range when the maximum delay time is 4.8 ns is 9.54 MHz to 10.50 MHz.

FIG. 5 is a configuration diagram of a 4-bit random counter. The 4-bit random counter is composed of 4-bit set / reset F / Fs 101, 102, 104, and 105. Each F / F is basically connected in series, but the input of the first bit 101 is The EXOR operation result of the output level of the third bit 105 and the fourth bit 106 is supplied, and the EXOR operation result of the output level of the second bit 102 and the fourth hit 106 is supplied to the third bit 105. Thereby, a pseudo random value according to a certain rule is output from the 4-bit output of the random counter.

FIG. 6 shows that, instead of the 4-bit random counter, an arbitrary delay pattern is created by previously storing a 4-bit selection pattern that changes every clock in the storage element and sequentially reading out the synchronization pattern in synchronization with the clock. This employs a 4-bit pattern reading mechanism.

(Amount of Improvement of Adverse Effects by Harmonic Noise) With the above-described configuration, a frequency component is diffused in a harmonic including a fundamental wave between an oscillator and a device using a clock signal from the oscillator. At a particular frequency, the level drops. As a result, interference with the originally required frequency band can be reduced.

The reason is as follows. The spectrum of the harmonic generated from the pulse wave is represented by the following equation by Fourier transform.

[0051]

(Equation 1)

From this equation, the spectrum when T / τ = 2 is shown in the graph as follows.

[0053]

[Table 1]

When the above equation τ (= H level width of the pulse) is fixed and T (period of the pulse) is changed, the spectrum changes as follows.

A spectrum when T / τ is slightly larger than 2 is shown.

[0056]

[Table 2]

As described above, by changing the period while keeping the H width of the pulse constant, the appearing spectrum changes in frequency.

Further, the peak of the harmonics changes in frequency, has a frequency width, and its amplitude decreases.

From the above equation, the spectrum frequency Cn is such that the n (order) is larger with respect to the change of T, that is, the higher the spurious the frequency is, the wider the frequency changes (distribution bandwidth: F
c) is increased. As the distribution bandwidth Fc increases, the amplitude of the peak of the harmonic component proportional to 1 / Fc decreases.

[0060]

[Table 3]

By changing the operating clock in terms of frequency, the accompanying harmonics also change in terms of frequency. The level of the signal obtained by integrating these is
The level is lowered by the frequency spread.

[0062]

As described above, between the oscillator and the device using the clock signal from the oscillator, the frequency components are spread in the harmonics including the fundamental wave.
The level decreases at a specific frequency. As a result, the present invention can reduce interference with the originally required frequency band.

Further, the present invention increases the space and weight for shielding noise, and changes the clock frequency itself, which are problems with the noise reduction mechanism that has been conventionally implemented. The effects of harmonic noise can be reduced without compromising the operation accuracy of the device that operates upon receiving, without requiring a complicated circuit such as a clock signal analysis and an inverse Fourier transform unit.

The clock source oscillating mechanism of the present invention continues to oscillate accurately in frequency similarly to the conventional oscillating mechanism having no clock adjusting function.
This is performed by delaying the rising edge and the falling edge in the waveform shaping stage.

For this reason, there is a frequency error only for a short time, but the error is not of a nature of being integrated. In other words, the delay time that occurs during 500 ms or 1 second, which is the clock counting interval, is not different from the maximum delay time per pulse.

By controlling the delay time to change periodically and devising a change pattern of the delay time, the operation executed at an interval of less than one second can fluctuate in terms of time. It is also possible to make the operation performed once every time fluctuate in time (operate in synchronization with a clock pulse having the same delay time every time).

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microcomputer including a noise reduction mechanism according to a clock generation method of the present invention.

FIG. 2 is a configuration diagram of a microcomputer having no noise reduction mechanism.

FIG. 3 is a configuration diagram of a frequency adjustment circuit that extends an H level period of a clock and delays a falling edge.

FIG. 4 is a configuration diagram of a frequency adjustment circuit that extends an L level period of a clock and delays a rising edge.

FIG. 5 is a configuration diagram of a 4-bit random counter.

FIG. 6 is a configuration diagram of a frequency adjustment circuit using a 4-bit pattern reading mechanism.

FIG. 7 is a configuration diagram showing a conventional noise reduction device.

[Explanation of symbols]

1,11 Oscillator 2,12 Clock shaping circuit 3 Frequency adjustment circuit 4,14 Clock divider circuit 5,15 Port control 6,16 Interrupt control 7,17 A / D, D / A control 8,18 Bus interface 23,59 , 99, 113, 149 Inverter 24, 64 4-bit random counter 25, 65, 115 4 to 16 decoder 26 to 40, 66 to 80, 116 to 130 Delay element 41 to 56, 81 to 96, 131 to 146 AND element 57, 97 , 147 OR element 58, 98, 148 Set reset F / F 101, 104 EXOR element 102, 103, 105, 106 Set reset F / F
F 114 4-bit pattern reading mechanism

Claims (8)

[Claims] 1. A clock generation method for a semiconductor integrated circuit comprising: an original oscillation generating means; and a waveform shaping means for shaping an output signal of the original oscillation generating means and outputting a clock signal. A clock generation method, characterized by having: 2. The clock generation system according to claim 1, wherein said frequency varying means comprises a plurality of delay elements and a selection means for selecting one of output signals of each of the delay elements. A clock generation method for selecting a delay amount for delaying an edge. 3. The clock generation method according to claim 2, wherein a rising edge of an output signal of said source oscillation generation means is delayed. 4. The clock generation method according to claim 2, wherein a falling edge of an output signal of said source oscillation generation means is delayed. 5. The clock generation method according to claim 2, wherein both a rising edge and a falling edge of an output signal of said source oscillation generating means are delayed. 6. The clock generation method according to claim 3, further comprising frequency variable means for changing selection of an output signal of said delay element at a predetermined cycle. 7. The clock generation method according to claim 6, wherein said frequency variable means randomly selects a delay element. 8. The clock generation system according to claim 7, wherein said frequency variable means includes a random counter,
A clock generation method wherein a delay element is selected based on an output signal of the random counter or a decoded signal of the output signal.