JP2004139111A - Driving circuit and driving method of electro-optical device, and electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit of a liquid crystal device etc., which can horizontally or vertically invert the directions of horizontal scanning and vertical scanning. <P>SOLUTION: The driving circuit of the electro-optical device has a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching means which is connected to the respective data lines and respective scanning lines, and a pixel electrode which is connected to the switching means. Then the driving circuit is equipped with a sampling circuit for sampling and supplying the image signal to the data lines, a shift register which supplies a 1st transfer signal according to a 1st clock signal, and a plurality of waveform selecting circuits which supply a sampling circuit drive signal to the sampling circuit according to input of one of 1st and 2nd waveform select signals. Further, an adjacent waveform selecting circuit is supplied with the mutually different waveform select signals of the 1st and 2nd waveform select signals and pulses of the 1st waveform select signal do not overlap with pulses of the 2nd waveform select signal. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a liquid crystal device of an active matrix driving method by driving a thin film transistor (hereinafter, appropriately referred to as a TFT), a driving circuit of an electro-optical device such as electroluminescence, an electro-optical device provided with the driving circuit, and a driving of the electro-optical device. The invention belongs to the technical field of methods and electronic equipment using the electro-optical device, and particularly to the technical field of peripheral circuits such as a scanning line driving circuit and a data line driving circuit of a liquid crystal device suitably used as a light valve of a liquid crystal projector. Belong.

Conventionally, when a liquid crystal device is used as a light valve of this type of liquid crystal projector, a single-panel system using only one colored liquid crystal device (that is, a color filter formed on a counter substrate) and a colorless ( That is, there is a double-panel system using three liquid crystal devices for each of R, G, and B (no color filter is formed). The single-plate system is simple in configuration, but the double-plate system is superior in that the display screen is bright and high quality image quality can be obtained. According to this double-plate system, three-color lights separately modulated by three liquid crystal devices are combined into one projection light by a prism or a dichroic mirror, and then projected on a screen.

In this way, when combined by a prism or the like, for example, as shown in FIG. 16, three light valves 500R, 500G for RGB, and R light and B light reflected by the prism 502 after modulation by the 500B, The G light is not reflected by the prism 502. That is, the number of times of light inversion is reduced for G light. This phenomenon is, of course, the same even when an optical system is configured so that R light or B light is not reflected by the prism 502 instead of G light. Further, even when three-color light is synthesized using a dichroic mirror or the like, Happens as well. Therefore, in such a case, it is necessary to invert the display image of the G light in some form left and right.

On the other hand, depending on the product strategy, there may be cases where a single-panel or double-panel LCD projector needs to be configured so that it can be used as a floor-standing type, which is normally installed on the floor, or as a ceiling-mounted type, which is installed upside down on the ceiling. is there. In this case, even in the single-panel system, there is a need to invert the display image supplied to the liquid crystal device left, right, up, and down in accordance with the manner of installation. Further, there is a case where it is desired that a liquid crystal monitor, which is a single-panel type liquid crystal device, such as a liquid crystal monitor of a portable video camera, can be inverted and viewed, for example, with a flexible joint as a fulcrum, according to the shooting posture of the user. In this case, it is necessary to invert the display image of the liquid crystal device up, down, left, and right in any way.

Therefore, conventionally, an image signal processing IC that supplies an image signal to a data line driving circuit of a liquid crystal device in a predetermined format, for example, for only an image signal for G, or an image signal for all colors, Thus, an image signal corresponding to an image whose top, bottom, left and right are inverted is generated and supplied for each field. This is convenient because it is not necessary to make any changes to the liquid crystal device and peripheral circuits.

Or, conventionally, for example, in the case of the above-described double-panel type liquid crystal projector application, the scanning direction was reversed left and right compared to the liquid crystal device for R and the liquid crystal device for B in order to synthesize three color lights. A liquid crystal device is used as a liquid crystal device for G.

However, the above-described method of inverting the display image vertically and horizontally using the conventional image signal processing IC requires too much load on the image signal processing IC to cope with recent high-definition images. It is not practical.

(4) The method using a liquid crystal device whose scanning direction is inverted vertically and horizontally has the following problems. That is, generally, a scanning line driving circuit or a data line driving circuit has a unidirectional shift register in which a transfer direction is fixed to one side, and based on a transfer signal generated from the unidirectional shift register, line sequential or A scanning signal or an image signal is supplied in a dot-sequential manner or the like, and scanning is performed on a display screen vertically and horizontally. Therefore, in the case of a double-panel type liquid crystal projector application, in order to use a liquid crystal device in which the scanning direction is inverted, the shift register is configured such that the data line driving circuit scans the display image from left to right. There is a need to manufacture two types of shift type liquid crystal devices: an L shift type liquid crystal device in which a shift register is configured so that a data line driving circuit scans a display image from right to left. It is clearly disadvantageous to manufacture two types of liquid crystal devices in, for example, a TFT manufacturing process using a semiconductor manufacturing device or the like from the viewpoint of a manufacturer. Further, from a user's point of view, there is a practical problem that similar liquid crystal devices are not compatible with each other, and that each individual device can be used only as one type. Further, in the liquid crystal device having such a fixed scanning direction, a liquid crystal projector which can be used as the floor-standing type or the ceiling-hanging type, or a liquid crystal monitor of a portable video camera whose screen is inverted cannot be realized.

In addition, when a scan signal or an image signal is supplied to a data line or a group of data lines based on a transfer signal from a shift register, image signals supplied to adjacent data lines or a group of data lines may be overlapped with each other, for example, due to overlap of image signals. Then, the preceding image signal component is written, and ghosts and image unevenness occur. Such a problem becomes remarkable in a high frequency driving environment.

The present invention solves the above-described problems, and a driving circuit for an electro-optical device such as a liquid crystal device capable of easily reversing the direction of horizontal scanning or vertical scanning horizontally or vertically using a relatively simple configuration. It is an object to provide an electro-optical device including a driving circuit and an electronic apparatus including the electro-optical device.

In order to solve the above problem, a driving circuit of the electro-optical device according to the present invention includes a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, the data lines and the respective A driving circuit of an electro-optical device having switching means connected to a scanning line and a pixel electrode connected to the switching means, and a sampling circuit for sampling the image signal and supplying the image signal to the data line, A shift register for supplying a first transfer signal based on a first clock signal, a sampling circuit drive signal based on input of the first transfer signal from the shift register, and one of a first and a second waveform selection signal And a plurality of waveform selection circuits for supplying the first and second waveform selection signals to the sampling circuit. That the waveform selection signal is supplied, a pulse of the first waveform selection signal, characterized in that it does not overlap with the pulse of the second waveform selection signal.

According to the drive circuit of the electro-optical device, the first and second waveform selection signals supplied to the adjacent waveform selection circuits are spaced at appropriate time intervals, and thus the image signal components due to the overlap of the image signals are generated. Ghosts and image unevenness due to writing can be prevented beforehand. In particular, it is effective in a high frequency driving environment.

The present invention is also characterized in that the waveform selection circuit includes a first logic circuit that takes a logical product or an exclusive logical product of the first transfer signal and the first waveform selection signal.

According to this configuration, the pulse width can be limited to a predetermined pulse width because the first logic circuit that takes the logical product or the exclusive logical product of the first transfer signal and the first waveform selection signal is included.

Further, the driving circuit of the electro-optical device of the present invention is connected to a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, and the data lines and the scanning lines. A driving circuit for an electro-optical device having switching means and a pixel electrode connected to the switching means, wherein a sampling circuit for sampling the image signal and supplying the image signal to the data line is provided, based on the first clock signal. A shift register that supplies a first transfer signal; and a plurality of waveform selection circuits that supply a sampling circuit drive signal to the sampling circuit based on input of the first transfer signal from the shift register and one of the waveform selection signals. Wherein the pulse width of the waveform selection signal is smaller than the pulse width of the first clock signal.

According to the driving circuit of the electro-optical device, since an appropriate time interval is provided between image signals supplied to adjacent data lines or a group of data lines in succession, an image due to overlapping of image signals is generated. Ghosts and image unevenness due to writing of signal components can be prevented beforehand. In particular, it is particularly effective in a high frequency driving environment.

Further, the driving circuit of the electro-optical device of the present invention is connected to a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, and the data lines and the scanning lines. A driving circuit of an electro-optical device having a switching unit and a pixel electrode connected to the switching unit, wherein the sampling circuit is configured to sample the image signal and supply the sampled image signal to the data line. A shift register that supplies a first transfer signal based on the first transfer signal, and a plurality of waveform selection circuits that supply the sampling circuit drive signal to the sampling circuit based on the input of the first transfer signal and the waveform selection signal. And smoothing the transition of the pulse waveform of the waveform selection signal.

According to the driving circuit of the electro-optical device, the pulse waveform is blunted, so that the ringing of the waveform selection signal itself can be suppressed, and the signal component of the waveform selection signal is prevented from being written as noise on the image signal line. You can do it.

Further, the driving circuit of the electro-optical device according to the present invention is a driving circuit of the electro-optical device that sequentially drives a plurality of switching elements that supply a plurality of image signals to a plurality of pixel electrodes. A register, and a selection circuit that outputs a drive signal obtained from the output signal supplied from the shift register according to an enable signal, and switches the image signal corresponding to the switching based on the drive signal output from the selection circuit. A sampling circuit that supplies the sampling signal to the element, wherein the enable signal is a non-rectangular pulse that defines a timing at which the selection circuit should supply the drive signal to the sampling circuit.

{Rise or fall transition of the non-rectangular pulse of the enable signal is in the range of 20 to 50 ns.

According to this configuration, it is possible to reliably prevent the signal component of the waveform selection signal from being written as noise in the image signal. A driving method for an electro-optical device, comprising: lines, a plurality of scanning lines to which a scanning signal is supplied, switching means connected to the data lines and the scanning lines, and pixel electrodes connected to the switching means. A step of sampling the image signal by a sampling control signal having a pulse width smaller than the pulse width of the first clock signal and supplying the image signal to the data line; and selecting the scanning line while selecting the scanning line. Supplying the sampled image signal to the switching means connected to a scanning line via the data line. I do.

According to this method of driving an electro-optical device, a sampling control signal having a pulse width smaller than the pulse width of the first clock signal is applied between image signals supplied to adjacent data lines or data line groups one after another. Since an appropriate time interval is provided, it is possible to prevent ghost and image unevenness due to writing of image signal components due to overlapping of image signals. In particular, it is particularly effective in a high frequency driving environment.

In the method for driving an electro-optical device according to the present invention, the plurality of data lines to which an image signal is supplied, the plurality of scanning lines to which a scanning signal is supplied, and the data lines and the scanning lines are connected. A method for driving an electro-optical device having a switching unit and a pixel electrode connected to the switching unit, wherein the sampling is performed based on a first transfer signal from a shift register and one of first and second waveform selection signals. A step of sampling the image signal by a circuit drive signal and supplying the sampled image signal to the data line; and, while selecting the scanning line, switching means connected to the selected scanning line. Supplying the data via a data line, wherein the first and second waveform selection signals are output alternately without overlapping each other.

According to the method of driving the electro-optical device, the first and second waveform selection signals output to the adjacent data lines or data line groups alternately from the first and second waveform selection signal lines so as not to overlap with each other. Since the image signal is sampled by the sampling circuit drive signal based on the signal and supplied to the data line, it is possible to prevent ghost and image unevenness due to writing of the image signal component due to overlapping of the image signal on the data line. . In particular, it is particularly effective in a high frequency driving environment.

In the method for driving an electro-optical device according to the present invention, the plurality of data lines to which an image signal is supplied, the plurality of scanning lines to which a scanning signal is supplied, and the data lines and the scanning lines are connected. A method of driving an electro-optical device having a switching unit and a pixel electrode connected to the switching unit, wherein the method supplies a sampling circuit driving signal to a sampling circuit based on inputs of the first clock signal and a waveform selection signal, The image signal is sampled by the sampling control signal and supplied to the data line, and while selecting the scanning line, switching means connected to the selected scanning line transmits the sampled image signal to the data line. The waveform selection signal is supplied through a line, and the transition of the pulse waveform of the waveform selection signal is smoothed.

According to the driving circuit of the electro-optical device, by smoothing the transition of the pulse waveform, it is possible to suppress the ringing of the waveform selection signal itself and to prevent the signal component of the waveform selection signal from being written as noise to the image signal. You can do it.

The driving method of the electro-optical device according to the present invention is a driving method of the electro-optical device that sequentially drives a plurality of switching elements that supply a plurality of image signals to a plurality of pixel electrodes, and sequentially outputs output signals from a shift register. Supplying, outputting a drive signal obtained from the output signal supplied from the shift register according to an enable signal, and supplying an image signal to the corresponding switching element based on the output drive signal. Wherein the enable signal is a non-rectangular pulse that defines a timing at which an image signal is to be supplied to the corresponding switching element based on the drive signal.

(4) The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Overall configuration of liquid crystal device)
First, an overall configuration of a liquid crystal device as an example of an electro-optical device will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of various wirings, peripheral circuits, and the like provided on a TFT array substrate 1 in an embodiment of a liquid crystal device. In this embodiment mode, the present invention is applied to a liquid crystal device of an active matrix driving system using TFT driving.

In FIG. 1, the TFT array substrate 1 is made of, for example, a quartz substrate, a hard glass, a silicon substrate, or the like. On the TFT array substrate 1, a plurality of pixel electrodes 11 provided in a matrix, a plurality of data lines 35 arranged in the X direction, each extending in the Y direction, and a plurality of data lines 35 arranged in the Y direction. The scanning lines 31 each extending along the X direction are formed. Further, a scanning line 31 is electrically connected to the gate of the TFT 30, and the scanning signals Y1, Y2,..., Ym are applied to the scanning line 31 at predetermined timing in a pulsed manner. The pixel electrode 11 is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signal VID supplied from the image signal line 304 is changed to D1, D2,. , Dn. The image signal VID of a predetermined level written to the liquid crystal via the pixel electrode 11 is held for a certain period between the counter electrode (described later) formed on the counter substrate (described later). On the TFT array substrate 1, a capacitance line 31 ′ (storage capacitance electrode), which is a wiring for the storage capacitance 70, is formed substantially in parallel along the scanning line 31, and the storage capacitance 70 is connected to the pixel electrode 11. Is added. As a result, it is possible to prevent display quality degradation such as flicker caused by the parasitic capacitance. Note that the scanning line 31 in the preceding stage may be used as an electrode for forming a storage capacitor to form the storage capacitor 70. With such a configuration, the capacitance line 31 'need not be provided.

The image signal VID written to the data line 35 may be supplied line-sequentially for each data line 35 or may be supplied to a plurality of adjacent data lines 35 for each group. If a plurality of adjacent data lines 35 are to be simultaneously driven, the driving frequency of the data line driving circuit can be reduced by shifting the phase of the image signal VID, thereby reducing circuit reliability and power consumption. Can be realized.

(4) On the TFT array substrate 1, there are further formed a sampling circuit 301 for sampling the image signal VID and supplying it to the data line 35, a data line driving circuit 101, and a scanning line driving circuit 104.

The scanning line driving circuit 104 has a bidirectional shift register described later, and performs the bidirectional shift register based on a reference clock signal CLY supplied from an external control circuit, its inverted clock signal CLINV, a start signal SPY, and the like. A scanning signal having a predetermined waveform and a predetermined timing is generated from the transfer signal output from the shift register, and is applied to the scanning line 31 in a pulse-like manner. In particular, the scanning line driving circuit 104 fixes the transfer direction of the bidirectional shift register to the forward direction or the reverse direction in accordance with a transfer direction control signal input from the outside, as described later in detail. On the other hand, it is possible to sequentially supply the scanning signals in the order of T to B in FIG. 1 or to sequentially supply the scanning signals in the order of B to T.

The data line driving circuit 101 has a bidirectional shift register described later, and includes a reference clock CLX supplied from an external control circuit, an inverted signal of the clock signal (hereinafter referred to as an inverted clock signal) CLX INV, and a start signal. The sampling circuit driving signals S1, S2,... Sn of a predetermined waveform and a predetermined timing are generated from the transfer signal output from the bidirectional shift register based on the signal SPX and the like.

The sampling circuit 301 includes a TFT 302 for each data line 35, an image signal line 304 is connected to a source electrode of the TFT 302, and a sampling circuit drive signal line 306 is connected to a gate electrode of the TFT 302. When the sampling circuit drive signals S1, S2,..., Sn are input to the sampling circuit 301 via the sampling circuit drive signal line 306, the image signals VID supplied from the image signal line 304 are converted into data lines DL, D2,. 35. The data line driving circuit 101 is connected to the data line 35 by fixing the transfer direction of the bidirectional shift register in the forward or reverse direction in accordance with a transfer direction control signal input from the outside, as will be described in detail later. On the other hand, the image signal VID can be sequentially supplied in the order of L to R or the image signal VID can be sequentially supplied in the order of R to L. As described above, in the present embodiment, the configuration is such that the data lines 35 are selected one by one. However, the configuration may be such that the data lines 35 are collectively selected for a plurality of lines at the same time. For example, the image signal VID expanded into a plurality of phases (for example, three phases, six phases, twelve phases...) Is converted to an image signal line 304 in accordance with the writing characteristics of the TFT 302 constituting the sampling circuit 301 and the frequency of the image signal VID. , And these may be simultaneously sampled for each group. At this time, it is needless to say that the image signal lines 304 are required at least for the number of phase developments.

(First Embodiment of Drive Circuit)
Next, a first embodiment of the drive circuit will be described with reference to FIGS. FIG. 2 shows the data line driving circuit 101 according to the first embodiment. In FIG. 2, an image signal output as a serial signal is phase-expanded into six parallel image signals, and image signals VID1 to VID6 are input to data lines 35 via six image signal lines 304, respectively. This will be described using a configuration example. FIGS. 3A and 3B are timing charts of various signals in the data line driving circuit 101. FIG. FIGS. 4A and 4B are circuit diagrams of a clocked inverter constituting the bidirectional shift register 111 of the data line driving circuit 101. FIG. FIG. 5 is a diagram showing a modification of the sampling circuit drive signal lines 306 output from the data line drive circuit 101 in FIG.

{First, the data line driving circuit will be described.

In FIG. 2, a data line driving circuit 101 includes a bidirectional shift register 111, a plurality of waveform selection circuits 112a provided corresponding to the outputs of odd-numbered stages of the bidirectional shift register 111, and the bidirectional shift register 111, respectively. And a plurality of waveform selection circuits 112b respectively provided corresponding to the outputs of the even-numbered stages of the sex shift register 111.

In the present embodiment, in particular, the data line driving circuit 101 as an example of the data line driving means includes a bidirectional shift register 111 having an odd number of output stages. For example, each of the data line driving circuits 101 includes six adjacent data lines 35. Sampling circuit drive signals S1 and S2 sequentially output from each stage of the bidirectional shift register 111 in the transfer direction corresponding to the direction from L to R or the direction from R to L for the odd number of data line groups. Based on S2, S3,..., Sn, the image signals VID1 to VID6 can be sequentially supplied in cooperation with the sampling circuit 302. The start signal SP (L) for starting the transfer of the transfer signal from L to R is input to the bidirectional shift register 111 from the L side in the figure, or the start signal SP (L) of the transfer signal from R to L A start signal SP (R) for starting transfer is input from the R side in the figure. Then, the data line driving circuit 101 generates the start signal SP (L), the clock signal CL, the inverted clock signal CL INV, and the first and second waveform selection signals ENB1 and ENB2 at the timing shown in the timing chart of FIG. Are sequentially delayed by a half cycle of the clock signal CL, and the sampling circuit driving signals S1, S2, S3,..., Sn (where n is (Odd number) is supplied to the sampling circuit 301.

Next, the bidirectional shift register 111 will be described in detail.

As shown in FIG. 2, each stage of the bidirectional shift register 111 includes a binary transfer direction control signal D as an example of a first direction control signal and an inverted signal of the transfer direction control signal (hereinafter referred to as an inverted transfer direction). The transfer direction is fixed according to D INV, and is fed back to the transfer signal every time the binary level of the reference clock signal CL and the inverted clock signal CL INV as an example of the first clock signal of a predetermined cycle changes. And four clocked inverters 114, 115, 116 and 117 which constitute an example of a first gate means for transferring and outputting to the next stage.

The clocked inverter 114 as an example of the first clocked inverter is configured such that the transfer can be performed when the transfer direction control signal D is at a high level, and the transfer direction is fixed in a direction from L to R as an example of the forward direction. It is connected.

The clocked inverter 115 as an example of the second clocked inverter can transfer data when the inverted transfer direction control signal D INV is at a high level, and fixes the transfer direction in a direction from R to L as an example in the reverse direction. Structured and connected.

When the transfer direction is fixed in a direction from L to R, the clocked inverter 116 as an example of the third clocked inverter outputs the transfer signal transferred via the clocked inverter 114 to the high level of the clock signal CL. And when the transfer direction is fixed in the direction from R to L, the transfer signal transferred via the clocked inverter 115 is fed back when the clock signal CL is at a high level. It is connected.

In addition, the clocked inverter 117 as an example of the fourth clocked inverter, when the transfer direction is fixed in the direction from R to L, transfers the transfer signal transferred via the clocked inverter 115 to the inverted clock signal CL. When the transfer is performed at the INV high level and the transfer direction is fixed in the direction from L to R, the transfer signal transferred via the clocked inverter 114 is fed back when the inverted clock signal CL INV is at the high level. Are connected and connected.

FIG. 4B is a circuit diagram showing a specific circuit configuration of the clocked inverter 116 extracted from FIG. 4A. For the other clocked inverters 114, 115, and 117, the clock signal CL and the inverted clock signal CL INV input to the clock input terminal are respectively the transfer direction control signal D, the inverted transfer direction control signal D INV, and the inverted transfer direction. Only the control signal D INV and the transfer direction control signal D, and the inverted clock signal CL INV and the clock signal CL are the same, but all have the same circuit configuration.

As shown in FIG. 4B, the clocked inverter 116 includes an N-channel TFT to which a clock signal CL is input to a gate, a P-channel TFT to which an inverted clock signal CL INV is input, and a transfer signal to a gate. P-channel TFTs and N-channel TFTs connected in parallel so as to be input, and power supplies VSS (ground potential power supply) and VDD (high potential power supply) are connected as shown in the figure. As described above, since each clocked inverter needs the power supplies VSS and VDD, it is necessary to route the power supply wiring to each clocked inverter also in the entire bidirectional shift register 111 shown in FIG. Further, in each clocked inverter, since the input terminal and the output terminal are insulated by the gate insulating film of each TFT, even if the frequency of the transfer signal is high, no current leaks in the transfer direction. There are advantages. Therefore, the bidirectional shift register 111 as a whole has an advantage that a stable transfer signal can be output with respect to a high frequency.

Next, the waveform selection circuits 112a and 112b will be described.

In FIG. 2, the waveform selection circuit 112a is configured to limit the pulse width of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111 to the pulse width of the first waveform selection signal ENB1. For example, as shown in FIG. 2, the waveform selection circuit 112a forms an example of a first logic circuit, which is a NAND circuit that performs an exclusive logical product of the transfer signal and the waveform selection signal ENB1, and an inverter circuit that inverts the result. The logic operation limits the pulse width of the transfer signal to the pulse width of the signal ENB1, as shown in FIGS. 3A and 3B.

{Circle around (2)} The waveform selection circuit 112b is configured to limit the pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 to the pulse width of the second waveform selection signal ENB2. For example, as shown in FIG. 2, the waveform selection circuit 112b includes, as an example of a second logic circuit, a NAND circuit that takes an exclusive logical product of the transfer signal and the waveform selection signal ENB2, and an inverter circuit that inverts the result. The logic operation limits the pulse width of the transfer signal to the pulse width of the signal ENB2, as shown in FIGS. 3A and 3B.

Next, the operation of the data line driving circuit 101 configured as described above will be described.

First, as a first case in FIG. 2, when the transfer direction control signal D is fixed at a high level and the inverted transfer direction control signal D INV is fixed at a low level, and is input to the bidirectional shift register 111, The transfer direction from L to R is provided by a clocked inverter 114 provided at each stage of the bidirectional shift register 111 and enabled to transfer under this condition and a clocked inverter 115 disabled to transfer under this condition. It is fixed in the direction to go. In this state, as shown in FIG. 3A, when the signal SP (L) for starting the transfer is input, every time the binary level of the clock signal CL and the inverted clock signal CL INV changes, Clocked inverters 116 and 117 to which the clock signal CL and the inverted clock signal CL INV are input perform transfer and feedback, respectively. Then, the transfer signal to which the feedback is applied is transferred to the next stage (stage on the R side) of the bidirectional shift register 111 and output to the corresponding waveform selection circuit 112a or 112b. In this way, since the feedback is performed in each stage, the transfer signal is not rounded and is sequentially transferred to the next stage.

On the other hand, as a second case in FIG. 2, when the transfer direction control signal D is fixed at a low level and the inverted transfer direction control signal D INV is fixed at a high level, and is input to the bidirectional shift register 111. In each stage of the bidirectional shift register 111, the transfer direction is from R to L by the clocked inverter 114 disabled to transfer under this condition and the clocked inverter 115 enabled to transfer under this condition. Fixed. In this state, as shown in FIG. 3B, when a start signal SP (R) for starting the transfer is input, every time the binary level of the clock signal CL and its inverted clock signal CLINV changes. Then, the clocked inverters 116 and 117 to which the clock signal CL and its inverted clock signal CL INV are input perform feedback and transfer, respectively. Then, the transfer signal subjected to the feedback is transferred to the next stage (stage on the L side) of the bidirectional shift register 111 and output to the corresponding waveform selection circuit 112a or 112b.

Here, assuming that the bidirectional shift register 111 is an even-numbered bidirectional shift register, if the transfer direction is from L to R and from R to L, The transfer signal output from the first stage (for example, the stage at the L end or the R end) of the bidirectional shift register 111 is a signal whose phase is shifted by a half cycle of the clock signal CL. Therefore, in order to actually reverse the transfer direction and perform image display by the liquid crystal device 10 without any trouble, it is not enough to simply change the binary levels of the transfer direction control signal D and the inverted transfer direction control signal D INV. , The clock signal CL and the inverted clock signal CL INV need to be respectively inverted. That is, in this case, the wiring of the clock signal CL and the inverted clock signal CL INV must be switched somewhere, but in this embodiment, the bidirectional shift register 111 has an odd number of output stages. Therefore, as shown in FIGS. 3A and 3B, the transfer direction of the bidirectional shift register 111 is either the direction from L to R or the direction from R to L. The transfer signal output from the first stage (left end or right end stage) is the same signal. That is, in order to invert the transfer direction, it is only necessary to change the binary level of the transfer direction control signal D and the inverted transfer direction control signal D INV, and it is not necessary to invert the clock signal CL and the inverted clock CL INV. This is very advantageous in terms of the configuration and control of the device.

Similarly, when the bidirectional shift register has an even number of output stages, the waveform selection circuit also includes a waveform selection signal input to a waveform selection circuit 112a controlled by an output signal from an odd number stage of the bidirectional shift register. It is necessary to exchange the waveform selection signals ENB1 and ENB2 with the waveform selection signal ENB2 input to the waveform selection circuit 112b controlled by ENB1 and the output signal from the even-numbered stage of the bidirectional shift register every time the transfer direction is reversed. In the present embodiment, since the bidirectional shift register 111 is configured to have an odd number of output stages, the transfer direction is from L to R as shown in FIGS. Output signal from the first stage (left end or right end stage) of the bidirectional shift register 111, whether in the direction from R to L. To become. That is, in order to invert the transfer direction, it is only necessary to change the level of the transfer direction control signal D and the inverted transfer direction control signal D INV2, and it is not necessary to invert the waveform selection signals ENB1 and ENB2. It is also very advantageous in terms of control.

Therefore, in the image signal processing IC or the like, a mechanism or control for switching the clock signal by providing a memory or the like is not required, which is very advantageous not only in the configuration and control of the liquid crystal device 10 but also in cost. In particular, such switching becomes generally difficult as the driving frequency increases, and thus is very effective in the case of the data line driving circuit 101 having a high driving frequency.

As described above, when the transfer signal is sequentially output from each of the bidirectional shift registers 111 in the direction from L to R or in the direction from R to L, the waveform selecting circuits 112a and 112b perform the following operations. .

That is, as shown in FIG. 3A or 3B, the pulse width of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111 is changed by the waveform selection circuit 112a. Limited by pulse width. The pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 is, as shown in FIG. 3A or 3B, the pulse width of the second waveform selection signal ENB2 by the waveform selection circuit 112b. Is limited to Thereafter, as shown in FIG. 3A, the transfer signals whose pulse widths are limited are directed to the sampling circuit drive signals S1, S2,..., Sn (provided that the transfer direction is from R to L). , N are odd numbers) are sequentially output to the sampling circuit 301. Alternatively, if the transfer direction is from L to R, as shown in FIG. 3B, the data is sequentially output to the sampling circuit 301 as the sampling circuit drive signals Sn, Sn-1, Sn-2,. Is done.

Therefore, according to the signals S1, S2,..., Sn which have an appropriate time interval due to the limitation of the pulse width, there is an appropriate time between the image signals supplied to the adjacent data line groups one after another. Spaced. If an appropriate time interval is provided between the image signals as described above, these image signals are overlapped particularly in a high-frequency driving environment, and a ghost or a ghost caused by writing any preceding image signal component at all is considered. This is very advantageous because it is possible to prevent the occurrence of image unevenness beforehand.

As described above, the sampling circuit drive signals S1, S2,..., Sn generated by limiting the pulse width of the transfer signal by the waveform selection circuits 112a and 112b, or Sn, Sn-1,. Here, N is an odd number) is, for example, the gate of six TFTs 302 constituting the sampling circuit 301 in a data line group consisting of six adjacent data lines corresponding to the respective image signals VID1 to VID6 developed in six phases. Input at the same time. As a result, the data lines 35 are simultaneously driven six by two, and this operation is repeated, and the image signal is sequentially supplied to each data line group including the six data lines.

Since the image signal is supplied to one data line group based on the same transfer signal, the number of the data lines 35 constituting the data line group depends on the number of the image signal processing IC to the data line driving circuit. It is preferable to make the number of phases equal to the number of phase expansions of the image signal input to the image signal 101. Therefore, when the phase expansion is not performed depending on the format of the image signal, or when the writing capability of each TFT 302 of the sampling circuit 301 is high or when a sufficient writing time is given to the sampling circuit 302, for example, as shown in FIG. As described above, the data line group may be formed by one data line.

FIG. 5 shows a modification of the sampling circuit drive signal lines 306 respectively output from the data line drive circuit 101 of FIG. 5, the configuration of the data line driving circuit 101 is the same as that of FIG. 2, but each TFT 302 of the sampling circuit 301 is connected to one waveform selection circuit 112a or 112b. As a result, the data lines 35 are sequentially driven one by one by the data line driving circuit 101.

Next, the scanning line driving circuit will be described.

The scanning line driving circuit 104 as an example of the scanning line driving means has the bidirectional shift register 111 having the odd-numbered output stages shown in FIG. Of the bidirectional shift register 111 in the transfer direction corresponding to the direction from T to B or the direction from B to T with respect to the scan line 31. Are sequentially supplied as scanning signals as they are, or as scanning signals via the waveform selection circuits 112a and 112b shown in FIG. 2 as in the case of the data line driving circuit 101. ing.

In this case, the configuration of the bidirectional shift register 111 is the same, but the same transfer direction control signal D and inverted transfer direction control signal D INV as the data line drive circuit 101 may be used as the transfer direction control signals. Alternatively, a transfer direction control signal dedicated to the scanning line driving circuit 104 may be prepared. If the same transfer direction control signal D and inverted transfer direction control signal D INV are used, the transfer directions of the data line drive circuit 101 and the scan line drive circuit 104 can be switched completely in conjunction with each other. If a signal is used, the transfer directions of the data line driving circuit 101 and the scanning line driving circuit 104 can be switched independently.

The clock signal for the scanning line driving circuit 104 depends on the total number of the scanning lines 31 and the length of the vertical scanning period. However, unless a special high-speed driving such as multi-sync driving is performed, the clock signal of the data line driving circuit 101 is used. A clock signal having a lower frequency than the signals CL and CL INV is used. In addition, if the scan signal supplied to the adjacent scan lines 31 can be prevented from substantially overlapping by setting the clock frequency in the scan line drive circuit 104 to be low, the scan line drive circuit 104 requires an external signal. The waveform selection circuits 112a and B controlled by the waveform selection signal can be omitted.

(Second embodiment of drive circuit)
Next, a second embodiment of the drive circuit will be described with reference to FIGS. FIG. 6 shows a data line driving circuit 101 according to the second embodiment. FIG. 7 is a circuit diagram of a transmission gate constituting a bidirectional shift register of the data line driving circuit 101. Note that the same components as those of the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 6, the data line drive circuit 101 includes a bidirectional shift register 121 having an odd number of output stages, and each stage of the bidirectional shift register 121 forms another example of the first gate unit. It is configured to include two transmission gates 124 and 125 and two clocked inverters 126 and 127.

The transmission gate 124 as an example of the first transmission gate is configured and connected so that the transfer is enabled when the transfer direction control signal D is at a high level, and the transfer direction is fixed in a direction from L to R.

The transmission gate 125 as an example of the second transmission gate is configured and connected so that transfer is enabled when the inverted transfer direction control signal D INV is at a high level, and the transfer direction is fixed in a direction from R to L.

When the transfer direction is fixed in a direction from L to R, the clocked inverter 126 as another example of the first clocked inverter outputs the transfer signal transferred via the transmission gate 124 and the clock signal CL becomes high. When the clock signal CL is at a high level, the transfer signal is transferred when the clock signal CL is at a high level. Have been.

When the transfer direction is fixed in a direction from R to L, a clocked inverter 127 as another example of the second clocked inverter outputs a transfer signal transferred through the transmission gate 125 to the transfer signal of the inverter 128. Before and after, when the inverted clock signal CL INV is at a high level, feedback is performed, and when the transfer direction is fixed in the direction from L to R, the transfer signal transferred via the transmission gate 124 is added to the signal before and after the inverter 128. Are configured and connected so as to provide feedback when the inverted clock signal CLINV is at a high level.

FIG. 7B is a circuit diagram showing a specific circuit configuration of the transmission gate 126 extracted from FIG. 7A. The circuit configuration of the other transmission gates 127 is the same except that the clock signal CL and the inverted clock signal CL INV input to the clock input terminal become the inverted transfer direction control signal D INV and the transfer direction control signal D, respectively. It is.

The transmission gate 126 is configured so that the N-channel TFT to which the clock signal CL is input to the gate and the P-channel TFT to which the inverted clock signal CL INV is input transfer the transfer signal between the source and the drain as shown in the figure. It is connected to the. As described above, since each transmission gate does not require a power supply, there is an advantage that the power supply wiring does not need to be routed to each transmission gate even for the bidirectional shift register 121 as a whole. Thus, the layout area of the data line driving circuit 101 and the scanning line driving circuit 104 can be reduced, so that a small liquid crystal device can be realized.

With the above configuration, the bidirectional shift register 121 determines whether the transfer direction is from L to R or R in accordance with the binary level of the transfer direction control signal D and the inverted transfer direction control signal D INV. Function as a unidirectional shift register in the direction from.

Note that the waveform selection circuits 112a and 112b are the same as in the first embodiment.

In the second embodiment, the scanning line driving circuit may be configured in the same manner as the scanning line driving circuit 104 in the first embodiment using the bidirectional shift register 111 or 121. Description is omitted.

(Third Embodiment of Drive Circuit)
Next, a third embodiment of the drive circuit will be described with reference to FIG. FIG. 8 shows a data line driving circuit according to the third embodiment. Note that the same components as those of the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

8, the data line driving circuit 101 includes a bidirectional shift register 131 having an odd number of output stages, and each stage of the bidirectional shift register 131 forms another example of the first gate unit. It is configured to include four transmission gates 134 to 137.

The transmission gate 134 as another example of the first transmission gate is configured to be able to transfer when the transfer direction control signal D is at a high level, and to fix the transfer direction from L to R.

The transmission gate 135 as another example of the second transmission gate is configured to be able to transfer when the inverted transfer direction control signal D INV is at a high level, and to fix the transfer direction from R to L.

The transmission gate 136 as an example of the third transmission gate transfers a transfer signal transferred via the transmission gate 134 when the transfer direction is fixed from L to R when the clock signal CL is at a high level. When the transfer direction is fixed in the direction from R to L, the transfer signal transferred through the transmission gate 135 is transferred and transferred when the clock signal CL is at a high level. I have.

Further, the transmission gate 137 as an example of the fourth transmission gate, when the transfer direction is fixed in the direction from R to L, the inverted clock signal CL INV becomes high in the transfer signal transferred through the transmission gate 135. When the level is at the level, feedback is performed before and after the inverters 138 and 139, and when the transfer direction is fixed in the direction from L to R, the inverted clock signal CLINV is added to the transfer signal transferred through the transmission gate 134. At the time of the high level, feedback is applied before and after the inverters 138 and 139.

With the above-described configuration, the bidirectional shift register 131 determines whether the transfer direction is from L to R or R, depending on the binary level of the transfer direction control signal D and the inverted transfer direction control signal D INV. Function as a unidirectional shift register in the direction from.

Further, in the present embodiment, since all the circuits constituting the bidirectional shift register 131 are constituted by transmission gates, there is no need to route power to the bidirectional shift register 131, and the data line driving circuit 101 and the scanning line Since the layout area of the driver circuit 104 can be reduced, a small liquid crystal device can be realized.

The waveform selection circuits 112a and 112b are the same as those in the first embodiment.

In the third embodiment, the scanning line driving circuit may be configured in the same manner as the scanning line driving circuit 104 in the first embodiment using the bidirectional registers 111, 121, or 131. The description is omitted.

(Modification of drive circuit)
Next, a modification of the driving circuit will be described with reference to FIGS. Since each modification relates to a modification of the bidirectional shift register, only this point will be described.

First, a first modified embodiment is different from the first embodiment (see FIG. 2) in that the transmission direction fixing clocked inverters 114 and 115 are replaced with “transmission gates” as shown in FIG. + Inverter "114 'and" transmission gate + inverter "115'. If the transfer direction control signal D and the inverted transfer direction control signal D INV are input to the “transmission gate + inverter” 114 ′ and 115 ′, the transfer direction goes from L to R according to their binary levels. It may be a unidirectional shift register that is a direction or a direction from R to L. In this case, as compared with the first embodiment, a power supply is not required for the transmission gate as shown in FIG. 7B, so that the layout area of the peripheral circuit can be reduced, and Liquid crystal device can be realized.

Next, in a second modified embodiment, P is replaced by at least one of the transmission gates 124, 125, and 134 to 137 in the second and third embodiments (see FIGS. 6 and 8). Either a channel TFT or an N-channel TFT is used. FIG. 10 shows an example using one of such a P-channel TFT and an N-channel TFT. In this case, as compared with the first embodiment, the structure using one of the P-channel TFT and the N-channel TFT is simpler than the transmission gate shown in FIG. 7 and does not require a power supply. . Since the number of elements is only half that of the transmission gate, the layout area of the data line driving circuit 101 and the scanning line driving circuit 104 can be further reduced, and a very small liquid crystal device can be realized.

In addition, a bidirectional shift register having an odd-numbered output stage according to the present invention can be configured using various semiconductor elements, basic circuits, and the like. By changing the binary level of the transfer direction control signal without having to invert the signal, a convenient bidirectional register can be constructed that can reverse the transfer direction by simply changing the binary level of the transfer direction control signal. The device can be realized.

In the above-described embodiment, in the bidirectional shift register, the waveform selection signals ENB1 and ENB2 are spaced at appropriate time intervals, that is, the waveform selection signals ENB1 and ENB2 output from the adjacent waveform selection circuits do not overlap. It is configured as follows. However, even in the case of a shift register having no bidirectional shift register, the pulse width of the clock signal is adjusted using the waveform selection circuit of this embodiment so that adjacent waveform selection signals do not overlap. This configuration is effective for preventing ghosts and image unevenness.

{Modification of the waveform selection signal in the above embodiment will be described with reference to FIG. FIG. 17 shows the waveforms of the start signal SP, the clock signal CL, the inverted clock signal CL INV, and the waveform selection signals ENB1 and ENB2. Only the differences from the above embodiment will be described, and the common configuration will be described. Is omitted.

In FIG. 17, the transition of the pulse waveform of the waveform selection signal is smoothed by several + ns, preferably in the range of 20 ns to 50 ns. Specifically, at the rising and falling edges of the waveform selection signals ENB1 and ENB2, the waveform selection signals are configured to be smoothed within the above range. By blunting the pulse waveform in this manner, ringing of the waveform selection signal itself can be suppressed, and the signal component of the waveform selection signal can be prevented from being written to the image signal line as noise.

{Further description will be given with reference to a plan view of the layout of the waveform selection signal lines and the image signal lines in FIG. In FIG. 18, 185 and 186 are waveform selection signal lines for waveform selection signals ENB1 and ENB2, respectively, and 187 to 192 are image signal lines for image signals VIDL to VID6.

Waveform selection signals ENB1 and ENB2 and image signals VID1 and VID2 are input from external circuits (not shown) to waveform selection signal lines 185 and 186 and image signal lines 187 and 188 via mounting terminals 181, 182, 183 and 184, respectively. Is done. The mounting terminals of the image signal wirings 189 to 192 are omitted in the drawing.

For example, as shown in FIG. 18, when the waveform selection signal lines 185 and 186 of the waveform selection signals ENB1 and ENB2 and the image signal lines 187 to 192 of the image signals VIDL to VID6 are arranged adjacent to each other, the waveform selection signal The waveform selection signals ENB1 and ENB2 of the lines 185 and 186 may be superimposed as noise on the image signals VID1 to VID6 of the image signal wirings 187 to 182. However, even if they are arranged adjacent to each other, such a problem can be prevented if the transition of the waveform selection signal is smoothed as described above.

In the above-described embodiment, an example of a pixel driving unit that actively drives a liquid crystal portion corresponding to a pixel from the pixel electrode 11 and the TFT 30 is configured. However, the pixel driving means is not limited to this example. For example, one of the data line 35 and the scanning line 31 is provided on a counter substrate as a counter electrode, and the other of the data line 35 and the scanning line 31 formed on the TFT array substrate 1 and the pixel electrode 11 are provided. By interposing two terminal type non-linear elements such as MIM driving elements each having bidirectional diode characteristics, another example of the pixel driving means is constituted by the counter electrode, the pixel electrode 11 and the two terminal type non-linear element. Is also good. In addition, this embodiment can be applied to various switching elements, various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal arrangements, driving methods, and the like.

(Electronics)
Next, an embodiment of an electronic apparatus including the liquid crystal device 10 described in detail above will be described with reference to FIGS.

First, FIG. 11 shows a schematic configuration of an electronic apparatus including the liquid crystal device 10 as described above.

In FIG. 11, an electronic device includes a display information output source 1000, a display information processing circuit 1002, a driving circuit 1004 including the above-described scanning line driving circuit 104 and data line driving circuit 101, a liquid crystal device 10, a clock generation circuit 1008, and a power supply circuit. 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Read Access Memory), a memory such as an optical disk device, a tuning circuit, and the like, and based on a clock signal from the clock generation circuit 1008, an image signal of a predetermined format. Is output to the display information processing circuit 1002. The display information processing circuit 1002 includes well-known various processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. A digital signal is sequentially generated from the information and output to the driving circuit 1004 together with the clock signal CLK. The driving circuit 1004 drives the liquid crystal device 10 by the above-described driving method. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 10, and in addition, the display information processing circuit 1002 may be mounted.

Next, FIGS. 12 to 15 show specific examples of the electronic device configured as described above.

12, a liquid crystal projector 1100, which is an example of an electronic apparatus, prepares three liquid crystal display modules including the liquid crystal device 10 in which the above-described driving circuit 1004 is mounted on a TFT array substrate, and respectively includes RGB light valves 10R, It is configured as a projection type projector used as 10G and 10B. In the liquid crystal projector 1100, when the projection light is emitted from the lamp unit 1102 of the white light source, the light corresponding to the three primary colors of RGB is generated by the two dichroic mirrors 1108 via the plurality of mirrors 1106 inside the light guide 1104. The components are divided into R, G, and B, and are led to light valves 10R, 10G, and 10B corresponding to the respective colors. The light components corresponding to the three primary colors modulated by the light valves 10R, 10G, and 10B are combined again by the dichroic prism 1112, and then projected as a color image on a screen or the like via the projection lens 1114.

In FIG. 13, a laptop personal computer 1200 as another example of the electronic apparatus includes the above-described liquid crystal device 10 in a top cover case, further houses a CPU, a memory, a modem, and the like, and has a keyboard 1202. An integrated main body 1204 is provided.

In FIG. 14, a pager 1300, which is another example of an electronic device, includes a liquid crystal device 10 in which a driving circuit 1004 is mounted on a TFT array substrate in a metal frame 1302 to form a liquid crystal display module, and a light including a backlight 1306a. It is housed together with a guide 1306, a circuit board 1308, first and second shield plates 1310 and 1312, two elastic conductors 1314 and 1316, and a film carrier tape 1318. In this case, the above-described display information processing circuit 1002 (see FIG. 11) may be mounted on a circuit board 1308 or on a TFT array substrate of the liquid crystal device 10. Further, the above-described drive circuit 1004 can be mounted on a circuit board 1308.

Since the example shown in FIG. 14 is a pager, a circuit board 1308 and the like are provided. However, in the case of the liquid crystal device 10 that forms the liquid crystal display module by mounting the driving circuit 1004 and the display information processing circuit 1002, a device in which the liquid crystal device 10 is fixed in the metal frame 1302 is used as the liquid crystal device or in addition to this. It can also be manufactured, sold, used, etc. as a backlight type liquid crystal device incorporating a light guide 1306.

As shown in FIG. 15, in the case of the liquid crystal device 10 in which the driving circuit 1004 and the display information processing circuit 1002 are not mounted, the TCP 1324 including the driving circuit 1004 and the display information processing circuit 1002 is mounted on a polyimide tape 1322. (Tape Carrier Package) 1320 can be physically and electrically connected to the TFT array substrate 1 through an anisotropic conductive film provided on the periphery of the TFT array substrate 1 to produce, sell, use, etc. as a liquid crystal device. It is possible.

In addition to the electronic devices described with reference to FIGS. 12 to 15, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, a workstation, a mobile phone , A video phone, a POS terminal, a device having a touch panel, and the like are examples of the electronic apparatus shown in FIG.

The electro-optical device according to the present invention can be used as an electro-optical device such as a liquid crystal, a light emitting polymer, and an LED. Further, the pixel driving circuit according to the present invention can be used for various active matrix driving type devices. is there. Further, the electronic apparatus according to the present invention is configured using such an electro-optical device and its driving circuit, and can be used as an electronic apparatus capable of displaying high-quality images.

FIG. 3 is a block diagram of various wirings, peripheral circuits, and the like formed on the TFT array substrate in the embodiment of the liquid crystal device. FIG. 2 is a circuit diagram of a first embodiment of a drive circuit provided in the liquid crystal device of FIG. 1. (A) and (b) are timing charts of various signals in the drive circuit of FIG. FIG. 3 is a circuit diagram of a clocked inverter included in the drive circuit of FIG. FIG. 13 is a circuit diagram showing a modification in which the output wiring to the sampling circuit of the drive circuit of FIG. 2 is changed. FIG. 4 is a circuit diagram of a drive circuit provided in the liquid crystal device of FIG. 1 according to a second embodiment. FIG. 7 is a circuit diagram of a transmission gate included in the drive circuit of FIG. FIG. 9 is a circuit diagram of a third embodiment of a drive circuit provided in the liquid crystal device of FIG. 1. FIG. 3 is a circuit diagram illustrating a first modification of the drive circuit of FIG. 2. FIG. 9 is a circuit diagram illustrating a second modification of the drive circuit of FIG. 2. 1 is a block diagram illustrating a schematic configuration of an electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus. FIG. 18 is a front view illustrating a personal computer as an example of an electronic apparatus. FIG. 2 is an exploded perspective view illustrating a pager as an example of the electronic apparatus. FIG. 3 is a perspective view illustrating a liquid crystal device using TCP as an example of an electronic apparatus. It is a conceptual diagram which shows the prism optical system which synthesize | combines RGB three color light of a liquid crystal projector. 7 is a modified example of the waveform selection signal of the timing chart in FIG. FIG. 4 is a plan view illustrating a layout example of a waveform selection signal line and an image signal line.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... TFT array substrate 10 ... Liquid crystal device 11 ... Pixel electrode 31 ... Scan line 35 ... Data line 101 ... Data line drive circuit 104 ... Scan line drive circuits 111, 121, 131 ... Bidirectional shift registers 112a, 112b ... Waveform selection Circuit 301: sampling circuit

Claims (15)

A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. A drive circuit of an electro-optical device having
A sampling circuit for sampling the image signal and supplying the image signal to the data line;
A shift register that supplies a first transfer signal based on a first clock signal;
The first transfer signal from the shift register, and a plurality of waveform selection circuits for supplying a sampling circuit drive signal to the sampling circuit based on the input of one of the first and second waveform selection signals,
Different waveform selection signals of the first and second waveform selection signals are supplied to adjacent waveform selection circuits,
The driving circuit for an electro-optical device, wherein the pulse of the first waveform selection signal does not overlap with the pulse of the second waveform selection signal. 2. The electro-optical device according to claim 1, wherein the waveform selection circuit includes a first logic circuit that performs an AND operation or an exclusive AND operation of the first transfer signal and the first waveform selection signal. 3. Drive circuit. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. There is a driving circuit of the electro-optical device having
A sampling circuit for sampling the image signal and supplying the image signal to the data line;
A shift register that supplies a first transfer signal based on the first clock signal;
The first transfer signal from the shift register, and a plurality of waveform selection circuit that supplies a sampling circuit drive signal to the sampling circuit based on input of one of the waveform selection signals,
The pulse width of the waveform selection signal is narrower than the pulse width of the first clock signal. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. A drive circuit of an electro-optical device having
A sampling circuit for sampling the image signal and supplying the image signal to the data line;
A shift register that supplies a first transfer signal based on the first clock signal;
The first transfer signal from the shift register, and a plurality of waveform selection image paths for supplying the sampling circuit drive signal to the sampling circuit based on the input of the waveform selection signal,
A drive circuit for an electro-optical device, wherein a transition of a pulse waveform of the waveform selection signal is smoothed. A drive circuit of an electro-optical device that sequentially drives a plurality of switching elements that supply a plurality of image signals to a plurality of pixel electrodes,
A shift register for sequentially supplying an output signal;
A selection circuit that outputs a drive signal obtained from an output signal supplied by the shift register according to an enable signal,
A sampling circuit that supplies an image signal to the corresponding switching element based on the drive signal output from the selection circuit,
The drive circuit for an electro-optical device, wherein the enable signal is a non-rectangular pulse that defines a timing at which the selection circuit supplies the drive signal to the sampling circuit. 6. The driving circuit according to claim 5, wherein the rising transition of the non-rectangular pulse of the enable signal is in a range of 20 to 50 ns. 7. The driving circuit for an electro-optical device according to claim 5, wherein the transition of the falling edge of the non-rectangular pulse of the enable signal is in a range of 20 to 50 ns. An electro-optical device comprising the electro-optical device drive circuit according to any one of claims 1 to 7. An electronic apparatus having the electro-optical device according to claim 8. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. A method for driving an electro-optical device having
A step of sampling the image signal by a sampling control signal having a pulse width smaller than the pulse width of the first clock signal and supplying the sampled signal to the data line;
Supplying the sampled image signal to the switching means connected to the selected scanning line via the data line while selecting the scanning line. Drive method. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. A method for driving an electro-optical device having
Sampling the image signal by a first transfer signal from a shift register and a sampling circuit drive signal based on one of the first and second waveform selection signals and supplying the image signal to the data line;
Supplying the sampled image signal to the switching means connected to the selected scanning line via the data line while selecting the scanning line, wherein the first and second waveforms are selected. A method for driving an electro-optical device, wherein selection signals are alternately output without overlapping each other. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, a switching unit connected to each of the data lines and each of the scanning lines, and a pixel electrode connected to the switching unit. A method for driving an electro-optical device having
Supplying a sampling circuit drive signal to the sampling circuit based on the input of the first clock signal and the waveform selection signal;
The image signal is sampled by the sampling control signal and supplied to the data line,
While selecting the scanning line, supplying the sampled image signal to the switching means connected to the selected scanning line via the data line,
A method of driving an electro-optical device, wherein a transition of a pulse waveform of the waveform selection signal is smoothed. A driving method of an electro-optical device that sequentially drives a plurality of switching elements that supply a plurality of image signals to a plurality of pixel electrodes,
Sequentially supplying an output signal from the shift register;
Outputting a drive signal obtained from the output signal supplied by the shift register according to an enable signal;
Supplying an image signal to the corresponding switching element based on the output drive signal,
The method of driving an electro-optical device according to claim 1, wherein the enable signal is a non-rectangular pulse that defines a timing at which an image signal is to be supplied to the corresponding switching element based on the drive signal. 14. The method according to claim 13, wherein the rising transition of the non-rectangular pulse of the enable signal is in a range of 20 to 50 ns. 15. The method according to claim 13, wherein the transition of the falling edge of the non-rectangular pulse of the enable signal is in a range of 20 to 50 ns.

Images