JP2004138480A - Semiconductor device and ac specification inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and an AC specification inspection method capable of performing high-speed AC specification inspection accurately and stably without being influenced by an LSI tester and a wiring impedance of a performance board. <P>SOLUTION: This semiconductor device 31 is equipped with a data input terminal 40, a clock input terminal 38, a timing generation circuit 41 for generating a timing signal at prescribed timing corresponding to a clock signal inputted from the clock input terminal 38, a clock selection circuit 42 for selecting and outputting the timing signal at the AC specification inspection time, a first stage register 44 which is a first stage as a view from the data input terminal 40, for changing the output from the clock selection circuit 42 into a clock signal, and a selector 45 for supplying a data signal to the first stage register 44 by using the clock signal inputted from the clock input terminal 38 as a trigger. Only the clock signal is supplied to the semiconductor device 31, and the output value from the first stage register 44 is compared with an expected value prepared beforehand. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and an AC spec inspection method, and more particularly to a semiconductor device capable of accurately and stably performing a high-speed AC spec inspection.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the operating frequency of semiconductor devices has increased, and in the inspection of semiconductor devices, AC spec inspection using an expensive LSI tester has been performed.
The AC specification of a semiconductor device refers to the AC (alternating current) characteristics of the semiconductor device, and the AC specification test is to check whether or not the timing relationship between a plurality of signals is as specified.
FIG. 13 is a diagram showing a conventional semiconductor device, LSI tester, and performance board.
As shown in FIG. 13, the semiconductor device 1 on which the AC specification test is performed has an internal function which is a first stage when viewed from the clock input terminal 11, the data input terminal 14, the internal function circuit 16, and the data input terminal 14. It comprises a first stage register 17 in the circuit 16 and an output terminal 18 from which the output value of the first stage register 17 can be observed.
[0003]
An LSI tester 2 for performing an AC specification test of the semiconductor device 1 is connected to a clock driver 4, a clock output terminal 5, a data driver 7, a data output terminal 8, a data input terminal 20, and a data input terminal 20. And a voltage level judging circuit 21 for judging a voltage level that has arrived inside the LSI tester 2.
[0004]
The performance board 3 connecting the semiconductor device 1 and the LSI tester 2 includes a clock input terminal 10, a data input terminal 13, and an output terminal 19 from which an output value from the output terminal 18 of the semiconductor device 1 can be observed. Have.
A wiring 6 having a wiring impedance Z3 is provided between the clock driver 4 and the clock output terminal 5 of the LSI tester 2, and a wiring impedance Z1 is provided between the data driver 7 and the data output terminal 8 of the LSI tester 2. The wiring 9 has a wiring 12 having a wiring impedance Z4 between the clock input terminal 10 of the performance board 3 and the clock input terminal 11 of the semiconductor device 1, and has a data input terminal 13 of the performance board 3 and a data input terminal of the semiconductor device 1. Wirings 15 having a wiring impedance Z2 exist between the terminals 14 and 14, respectively.
[0005]
The operation of the conventional semiconductor device, LSI tester, and performance board configured as described above will be described.
[0006]
First, the operation for checking the setup time of the input AC timing will be described.
FIG. 14A is a timing chart showing signal waveforms in a conventional setup time test. In the figure, S40 is a data output waveform of the data driver 7, and S41 is a clock output waveform of the clock driver 4. S42 is a data input waveform of the first-stage register 17, and S43 is a clock input waveform of the first-stage register 17.
[0007]
The data signal S 40 output from the data driver 7 of the LSI tester 2 passes through the wiring 9, the data output terminal 8 of the LSI tester 2, the data input terminal 13 on the performance board 3, and the wiring 15 in order, and the data input to the semiconductor device 1 is performed. The data is input to the terminal 14 and reaches the data input terminal D of the first stage register 17 in the internal function circuit 16.
[0008]
On the other hand, the clock signal S41 output from the clock driver 4 at a predetermined delay time from the output of the data signal from the data driver 7 is sequentially supplied to the wiring 6, the clock output terminal 5 of the LSI tester 2, and the performance board 3. Through the clock input terminal 10 and the wiring 12 to the clock input terminal 11 of the semiconductor device 1 and reaches the clock input terminal CLK of the first-stage register 17 in the internal function circuit 16.
[0009]
The first-stage register 17 latches the data signal S42 at the timing of the reached clock signal S43.
The output signal of the first-stage register 17 reaches the voltage level determination circuit 21 of the LSI tester 2 through the output terminal 18 of the semiconductor device 1, the output terminal 19 on the performance board 3, and the data input terminal 20 of the LSI tester 2 in order. .
[0010]
The voltage level determination circuit 21 compares the data signal output from the data driver 7 of the LSI tester 2 with the clock signal of the LSI tester 2 by comparing the prepared expected value with the reached output signal of the first stage register 17. Then, a setup time check of the output delay time difference from the clock signal output from No. 4 is performed. If the data Dd shown in S42 of FIG. 14A is observed by the voltage level determination circuit 21, it is determined that a predetermined AC specification is satisfied.
[0011]
Next, the operation when checking the hold time of the input AC timing will be described.
FIG. 14B is a timing chart showing signal waveforms in a conventional hold time test. In the drawing, S44 is a data output waveform of the data driver 7, and S45 is a clock output waveform of the clock driver 4. S46 is a data input waveform of the first-stage register 17, and S47 is a clock input waveform of the first-stage register 17.
[0012]
The clock signal S45 output from the clock driver 4 of the LSI tester 2 passes through the wiring 6, the clock output terminal 5 of the LSI tester 2, the clock input terminal 10 on the performance board 3, and the wiring 12 in this order. The signal is input to the terminal 11 and reaches the clock input terminal CLK of the first stage register 17 in the internal function circuit 16.
[0013]
On the other hand, the data signal S44 output from the data driver 7 at a predetermined delay time from the output of the clock signal from the clock driver 4 is sequentially transmitted to the wiring 9, the data output terminal 8 of the LSI tester 2, and the performance board 3. Of the semiconductor device 1 through the data input terminal 13 and the wiring 15 of the semiconductor device 1, and reaches the data input terminal D of the first stage register 17 in the internal function circuit 16.
[0014]
The first-stage register 17 latches the data signal S46 at the timing of the reached clock signal S47.
The output signal of the first-stage register 17 reaches the voltage level determination circuit 21 of the LSI tester 2 through the output terminal 18 of the semiconductor device 1, the output terminal 19 on the performance board 3, and the data input terminal 20 of the LSI tester 2 in order. .
[0015]
The voltage level determination circuit 21 compares the clock signal output from the clock driver 4 of the LSI tester 2 with the data driver of the LSI tester 2 by comparing the expected signal prepared in advance with the output signal of the first-stage register 17 which has reached. 7 is performed to check the hold time of the output delay time difference from the data signal output from.
[0016]
That is, the data De (see S46 in FIG. 14B) immediately before the data output from the data driver 7 after a predetermined delay time from the output of the clock signal from the clock driver 4, is sent to the voltage level determination circuit 21. If it is observed, it is determined that a predetermined AC specification is satisfied.
In the inspection of such a semiconductor device, a probe attached to a probe card is attached to an electrode of a semiconductor integrated circuit (a performance board on which the semiconductor integrated circuit is mounted) as described in, for example, the related art section of Patent Document 1. The test is performed by pressing a semiconductor integrated circuit and supplying a test clock signal and a data signal by a tester connected to a probe card by a cable.
[0017]
[Patent Document 1]
JP 2000-164650 A (page 1, FIG. 7)
[0018]
[Problems to be solved by the invention]
However, in the conventional AC spec inspection method using the semiconductor device, the LSI tester, and the performance board, the impedance Z3 of the wiring 6 of the LSI tester 2, the impedance Z1 of the wiring 9, the impedance Z4 of the wiring 12 on the performance board 3, and the wiring The delay time difference between the clock signal and the data signal input to the semiconductor device 1 is different from the delay time difference set by the clock driver 4 and the data driver 7 of the LSI tester 2 because of the influence of the impedance Z2 of the semiconductor device 1. Further, even if the clock driver 4 and the data driver 7 drive accurate square waves, the waveforms of the clock signal and the data signal input to the semiconductor device 1 are the impedance Z3 of the wiring 6, the impedance Z1 of the wiring 9, 12 and the impedance Z2 of the wiring 15, the clock signal input to the clock input terminal 11 on the performance board 3 and the data on the performance board 3 must be adjusted unless the wiring impedance is precisely adjusted. The shape of the data signal input to the input terminal 14 is greatly distorted from the shape of the square wave, and a phase difference occurs between the clock signal and the data signal. Therefore, the conventional semiconductor device, LSI tester, and performance board have a problem that it is difficult to accurately and stably perform a high-speed AC specification inspection.
[0019]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems, and can accurately and stably perform a high-speed AC specification inspection without being affected by the wiring impedance of an LSI tester and a performance board. It is an object to provide a semiconductor device and an AC specification inspection method.
[0020]
[Means for Solving the Problems]
A semiconductor device according to claim 1 of the present invention has a data input terminal for inputting a data signal from outside the device, a clock input terminal for inputting a clock signal from outside the device, and a clock signal input from the clock input terminal. A timing generating means for generating a timing signal at a predetermined timing, a clock signal input from the clock input terminal, and a clock selecting means for selecting and outputting any of the timing signals; and an output of the clock selecting means. A first-stage register that is a clock signal and is a first stage as viewed from the data input terminal; and a signal selection unit that supplies a signal based on the clock signal input from the clock input terminal to the first-stage register as a data signal, The clock selection means selects the above timing signal at the time of the AC specification inspection. And, said signal selecting means, the AC specifications when the inspection is obtained shall select the supply of a signal based on the clock signal.
[0021]
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the timing generation means outputs a timing signal after a predetermined delay time has elapsed according to a clock signal input from the clock input terminal. Is generated by delay means for generating
[0022]
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the timing generation means synchronizes with a clock signal input from the clock input terminal and has a predetermined phase difference. It comprises a DLL circuit for generating a timing signal and selecting an arbitrary timing signal from the plurality of timing signals.
[0023]
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein the timing generating means includes a PLL circuit that generates a frequency according to a clock signal input from the clock input terminal. It is something that was taken.
[0024]
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the clock signal is input instead of the data input terminal and the signal selection means. A bidirectional IO terminal including an IO buffer and an input IO buffer to which the data signal is input is provided at a connection node between an output of the output IO buffer and an input thereof.
[0025]
A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fifth aspect, wherein a clock signal input from the clock input terminal is used as a reference signal immediately before input of the bidirectional IO terminal to the output-side IO buffer. And a test pattern generating means for generating a test pattern and outputting the test pattern in place of the clock signal.
[0026]
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the sixth aspect, wherein the test pattern generating means is constituted by a rewritable storage means.
[0027]
A semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the seventh aspect, further comprising storage means for temporarily holding an output value of the first-stage register immediately after the output of the first-stage register. It is what it was.
[0028]
According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect, immediately after the output of the first-stage register, an output value of the first-stage register is compared with an output value of the test pattern generating means. A comparison means is provided.
[0029]
An AC specification inspection method according to claim 10 of the present invention is the AC specification inspection method for inspecting an AC specification of a semiconductor device according to any one of claims 1 to 7, wherein only the clock signal is supplied to the semiconductor device. The AC specification is inspected by comparing the output value of the first-stage register with an expected value prepared in advance.
[0030]
An AC specification inspection method according to claim 11 of the present invention is the AC specification inspection method for inspecting the AC specification of a semiconductor device according to claim 8, wherein only the clock signal is supplied to the semiconductor device and the storage device temporarily stores the clock signal. The AC specification is inspected by comparing the output value of the first-stage register, which is temporarily stored, with an expected value prepared in advance.
[0031]
An AC specification inspection method according to a twelfth aspect of the present invention is the AC specification inspection method for inspecting an AC specification of a semiconductor device according to the ninth aspect, wherein only the clock signal is supplied to the semiconductor device and the output of the comparison means is provided. It is determined whether or not a predetermined AC specification is satisfied based on the value.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to the first embodiment of the present invention.
As shown in FIG. 1, a semiconductor device 31 on which an AC specification test is performed includes a clock input terminal 38, a data input terminal 40 with a 3-state buffer, and a predetermined delay time after a clock signal is input. A timing generating circuit (timing generating means) 41 for outputting AC signals, which outputs a plurality of timing signals, for inspecting AC specifications using a delay element; a clock signal input from a clock input terminal 38 and a timing signal input from the timing generating circuit 41 A clock selection circuit (clock selection means) 42, an internal function circuit 43, a first stage register 44 in the internal function circuit 43, which is a first stage when viewed from the data input terminal 40, and a clock input terminal at the time of AC specification inspection. The signal on the basis of the clock signal input from 38 is stored in the first-stage register 44. A selector (signal selecting means) 45 for supplying a data signal, and is configured to output values of the first-stage register 44 from observable output terminal 46.
[0033]
An LSI tester 32 that performs an AC specification test of the semiconductor device 31 is connected to a clock driver 34, a clock output terminal 35, a data input terminal 48, and a data input terminal 48, and receives a voltage level input to the LSI tester 32. And a voltage level judgment circuit 49 for judging.
The performance board 33 that connects the semiconductor device 31 and the LSI tester 32 has a clock input terminal 37 and an output terminal 47 that can observe the output value of the output terminal 46 of the semiconductor device 31.
A wiring 36 having a wiring impedance Z3 is provided between the clock driver 34 of the LSI tester 32 and the clock output terminal 35, and is provided between the clock input terminal 37 of the performance board 33 and the clock input terminal 38 of the semiconductor device 31. Each of the wirings 39 having the wiring impedance Z4 exists.
[0034]
Here, the semiconductor device 31 has a delay time in a path from the data input terminal 40 to the data signal input terminal D of the first stage register 44, and a clock signal input from the first stage register 44 which does not pass through the timing generation circuit 41 from the clock signal input terminal 38. The difference between the delay time on the path from the clock signal input terminal 38 to the data signal input terminal D of the first-stage register 44; the difference between the delay time on the path from the clock signal input terminal 38 to the data signal input terminal D of the first-stage register 44; It is designed in advance so that the difference between the delay time in the path to the clock signal input terminal CLK of 44 and the delay time excluding the delay time in the timing generation circuit 41 is equal.
[0035]
FIG. 2 is a timing chart showing signal waveforms according to the first embodiment of the present invention.
In FIG. 2, S1 is a clock signal waveform input to the clock input terminal 38 of the semiconductor device 31, S2 is a data signal input waveform of the first-stage register 44 in the internal function circuit 43, and S3 is a timing generator. A clock input signal waveform that reaches the first-stage register 44 in the internal function circuit 43 through the circuit 41, and S4 is an output signal waveform of the first-stage register 44.
[0036]
The operation of the semiconductor device, the LSI tester, and the performance board configured as described above when inspecting the AC specifications of the semiconductor device will be described.
At the time of the AC specification inspection, the clock selection circuit 42 selects the output of the timing generation circuit 41, and the selector 45 selects the through output of the clock signal from the clock input terminal 38.
[0037]
The clock signal output from the clock driver 34 of the LSI tester 32 passes through the wiring 36, the clock output terminal 35 of the LSI tester 32, the clock input terminal 37 on the performance board 33, and the wiring 39, and then the clock input terminal of the semiconductor device 31. 38. The clock signal input to the clock input terminal 38 is input to the timing generation circuit 41 and the selector 45, respectively. The clock signal input to the timing generation circuit 41 is input as a clock signal to a first-stage register 44 in the internal function circuit 43 via a clock selection circuit 42.
That is, the clock input waveform S3 that reaches the first-stage register 44 in the internal function circuit 43 through the timing generation circuit 41 is obtained by adding the delay time in the timing generation circuit 41 to the clock signal waveform S1 input to the clock input terminal 38, and The clock signal is input to the register 44.
[0038]
On the other hand, the selector 45 to which the clock signal is input inputs a signal based on the input clock signal to the data input terminal D of the first-stage register 44 of the internal function circuit 43 as the data signal. At this time, by setting the output value of the data input terminal 40 with the 3-state buffer of the semiconductor device 31 to the Hi-Z (high-impedance) state, a data signal is unexpectedly applied to the data input terminal 40 despite the AC spec measurement. When input, this prevents the output value of the selector 45 in the semiconductor device 31 from colliding.
That is, the data signal input waveform S2 input to the first register 44 of the semiconductor device 31 is input as a data signal to the first register 44 after a delay time based on a design value with respect to the clock signal waveform S1 input to the clock input terminal 38. Is done.
[0039]
The first-stage register 44 latches the data signal input from the selector 45 with the clock signal input from the clock selection circuit 42.
The output data signal waveform S4 of the first-stage register 44 latched by the clock input waveform S3 reaching the first-stage register 44 is sequentially output from the output terminal 46 of the semiconductor device 31, the output terminal 47 on the performance board 33, and the data input terminal 48 of the LSI tester 32. Is input to the voltage level determination circuit 49 of the LSI tester 32.
[0040]
The voltage level determination circuit 49 performs an AC specification test by comparing whether or not desired data has been latched in the first stage register 44 with an expected value test pattern of the LSI tester 32 prepared in advance.
At this time, the phase of the timing signal generated by the timing generation circuit 41 can be arbitrarily set so that a predetermined delay time can be obtained from among a plurality of delay times that can be set. The delay time of the input waveform S3 in the timing generation circuit 41 can be set to various values.
[0041]
Hereinafter, a timing inspection method for AC specifications according to the first embodiment will be described.
In the timing test of the AC specification according to the first embodiment, the LSI tester 32 outputs only the clock signal to the semiconductor device 31 during the timing test of the AC specification.
The semiconductor device 31 receives the clock signal waveform S1 and uses the clock signal waveform S1 as a data signal of the internal function circuit 43. The semiconductor device 31 also outputs the timing signal generated by the timing generation circuit 41 based on the clock signal waveform S1 to the internal function circuit 43. The internal function circuit 43 is configured to execute a predetermined process by using it as a clock signal.
Then, the output data signal waveform S4 output from the internal function circuit 43 after executing the predetermined processing is output to the voltage level determination circuit 49 of the LSI tester 32, where the semiconductor device 31 has a predetermined AC specification. Is determined.
[0042]
This makes it possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to perform the AC spec inspection accurately without being affected by the wiring impedance of the LSI tester and the performance board. It can be performed stably.
[0043]
Note that the timing generation circuit 41 appropriately adjusts the delay of the timing signal with respect to the data signal, and observes the determination result of the voltage level determination circuit 49 at each delay time to determine the AC specification when the delay time is appropriately changed. It is also possible to get results.
[0044]
As described above, according to the semiconductor device of the first embodiment, the timing generation circuit for the AC specification inspection, the clock selection circuit for selecting and outputting any of the clock signal and the timing signal input from the clock input terminal, A selector that supplies a signal based on a clock signal input from the outside to the first stage register as a data signal is provided, so that a clock signal introduced from the outside can be used as a test data signal inside the semiconductor device. By setting so that the clock signal and the data signal can be supplied by the same wiring at the time of the AC specification inspection, it is possible to eliminate the influence due to the difference in wiring impedance when the clock signal and the data signal are supplied by separate wirings. Semiconductor device having an inspection support mechanism suitable for AC specification inspection It is possible to obtain.
[0045]
Further, according to the AC spec inspection method according to the first embodiment, at the time of the AC spec inspection, the semiconductor device configured as described above is used for the inspection, only the clock signal is supplied from the LSI tester, and the clock introduced from the outside is used. By setting a signal to be used internally as a data signal, it is possible to obtain an AC spec inspection method capable of accurately and stably performing an AC spec inspection without being affected by wiring impedance of an LSI tester and a performance board. it can.
[0046]
In the first embodiment, the timing generation circuit 41 is realized by a delay element having a predetermined delay time. However, instead of the delay element, a plurality of inverters are connected in a ring, and a plurality of inverter output terminals are provided. (Delay Locked Loop) circuit which can select the inverter output signal of the above. When the DLL circuit is used, it is possible to continuously change the delay time of the timing signal with respect to the external input clock signal by changing the frequency of the external input clock signal, so that a more detailed AC spec inspection can be performed. it can.
[0047]
In the first embodiment, the timing generation circuit 41 is realized by a delay element having a predetermined delay time. However, a PLL (Phase Locked Loop) circuit capable of generating a predetermined frequency is used instead of the delay element. You may.
When a PLL circuit is used, the frequency of the clock input signal input to the first-stage register 44 can be set higher than the frequency of the clock signal input to the clock input terminal 38. Since latching is possible, more detailed AC specification inspection can be performed.
[0048]
Embodiment 2 FIG.
FIG. 3 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to the second embodiment of the present invention.
As shown in FIG. 3, a semiconductor device 61 on which an AC specification test is performed includes a clock input terminal 68, a bidirectional IO terminal 70 including an output three-state IO buffer 70a and an input IO buffer 70b, and a clock signal. A timing generation circuit (timing generation means) 71 using a delay element for outputting a plurality of timing signals after a predetermined delay time has elapsed after being input, and a clock signal and timing input from a clock input terminal 68 A clock selection circuit (clock selection means) 72 for selecting any of the timing signals input from the generation circuit 71, an internal function circuit 73, and a first-stage register in the internal function circuit 73 which is the first stage when viewed from the bidirectional IO terminal 70 74 and an output terminal 75 from which the output value of the first stage register 74 can be observed. To have.
[0049]
An LSI tester 62 that performs an AC specification test of the semiconductor device 61 is connected to a clock driver 64, a clock output terminal 65, a data input terminal 77, and a data input terminal 77, and receives a voltage level input to the LSI tester 62. And a voltage level judging circuit 78 for judging.
[0050]
The performance board 63 that connects the semiconductor device 61 and the LSI tester 62 has a clock input terminal 67 and an output terminal 76 from which the output value of the output terminal 75 of the semiconductor device 61 can be observed.
A wiring 66 having a wiring impedance Z3 is provided between the clock driver 64 of the LSI tester 62 and the clock output terminal 65, and is provided between the clock input terminal 67 of the performance board 63 and the clock input terminal 68 of the semiconductor device 61. Each of the wirings 69 has the wiring impedance Z4.
[0051]
Here, the semiconductor device 61 has a delay time in a path from the bidirectional IO terminal 70 to the data signal input terminal D of the first stage register 74, and a clock signal of the first stage register 74 that does not pass through the timing generation circuit 71 from the clock signal input terminal 68. The difference between the delay time on the path to the input terminal CLK, the delay time on the path from the clock signal input terminal 68 to the data signal input terminal D of the first stage register 74 via the bidirectional IO terminal 70, and the difference from the clock signal input terminal 68 It is designed in advance so that the difference between the delay time in the path to the clock signal input terminal CLK of the first stage register 74 passing through the timing generation circuit 71 and the delay time excluding the delay time in the timing generation circuit 71 is equal.
[0052]
FIG. 4 is a timing chart showing signal waveforms according to the second embodiment of the present invention.
In FIG. 4, S5 is an input clock signal waveform input to the clock input terminal 68 of the semiconductor device 61, S6 is a data input waveform of the first-stage register 74 in the internal function circuit 73, and S7 is a timing generator. A clock input waveform that reaches the first-stage register 74 in the internal function circuit 73 through the circuit 71, and S8 is an output waveform of the first-stage register 74.
[0053]
The operation of the semiconductor device, the LSI tester, and the performance board configured as described above when inspecting the AC specifications of the semiconductor device will be described.
At the time of the AC specification inspection, the clock selection circuit 72 selects the output of the timing generation circuit 71, and the output 3-state IO buffer 70a of the bidirectional IO terminal 70 selects to output the clock signal from the clock input terminal 68 through. It shall be.
[0054]
The clock signal output from the clock driver 64 of the LSI tester 62 passes through the wiring 66, the clock output terminal 65 of the LSI tester 62, the clock input terminal 67 on the performance board 63, and the wiring 69, and then the clock input terminal of the semiconductor device 61. 68. The clock signal input to the clock input terminal 68 is input to the timing generation circuit 71 and the bidirectional IO terminal 70, respectively. The clock signal input to the timing generation circuit 71 is input as a clock signal to the first stage register 74 of the internal function circuit 73 via the clock selection circuit 72.
That is, the clock input waveform S7 of the first stage register 74 that reaches the first stage register 74 in the internal function circuit 73 through the timing generation circuit 71 is delayed by the timing generation circuit 71 with respect to the clock signal waveform S5 input to the clock input terminal 68. The time is added and the clock is input to the first stage register 74 as a clock signal.
[0055]
On the other hand, the clock signal input to the bidirectional IO terminal 70 passes through the three-state IO buffer 70 a on the output side of the bidirectional IO terminal 70 and the input-side IO buffer 70 b as a data signal to the first-stage register 74 in the internal function circuit 73. Is entered.
That is, the data input signal waveform S6 input to the first register 74 is input as a data signal to the first register 74 after a delay time based on a design value with respect to the clock signal waveform S5 input to the clock input terminal 68.
[0056]
The first-stage register 74 latches a data signal input from the bidirectional IO terminal 70 with a clock signal input from the clock selection circuit 72.
The output data signal waveform S8 of the first-stage register 74 latched by the clock input waveform S7 reaching the first-stage register 74 is sequentially output from the output terminal 75 of the semiconductor device 61, the output terminal 76 on the performance board 63, and the data input terminal 77 of the LSI tester 62. Is input to the voltage level determination circuit 78 of the LSI tester 62.
The voltage level determination circuit 78 performs an AC specification test by comparing whether or not the desired data has been latched in the first stage register 74 with an expected value test pattern of the LSI tester 62 prepared in advance.
[0057]
At this time, the phase of the timing signal generated by the timing generation circuit 71 can be arbitrarily set so that a predetermined delay time can be obtained from among a plurality of delay times that can be set. The delay time of the input waveform S7 in the timing generation circuit 71 can be set to various values.
[0058]
Hereinafter, a timing inspection method for AC specifications according to the second embodiment will be described.
In the timing test of the AC specification according to the second embodiment, the LSI tester 62 outputs only the clock signal to the semiconductor device 61 during the timing test of the AC specification.
The semiconductor device 61 receives the clock signal waveform S5 and uses it as a data signal for the internal function circuit 73. The semiconductor device 61 also uses the timing signal generated by the timing generation circuit 71 based on the clock signal waveform S5 for the internal function circuit 73. By using it as a clock signal, the internal function circuit 73 is configured to execute a predetermined process.
[0059]
Then, the output data signal waveform S8 output from the internal function circuit 73 after executing the predetermined processing is output to the voltage level determination circuit 78 of the LSI tester 62, where the semiconductor device 61 has a predetermined AC specification. Is determined.
This makes it possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to perform the AC spec inspection accurately without being affected by the wiring impedance of the LSI tester and the performance board. It can be performed stably.
Note that the timing generation circuit 71 appropriately adjusts the delay of the timing signal with respect to the data signal, and observes the determination result of the voltage level determination circuit 78 in each delay time to determine the AC specification when the delay time is appropriately changed. It is also possible to get results.
[0060]
As described above, according to the semiconductor device of the second embodiment, the timing generation circuit for AC specification inspection and the bidirectional IO terminal are provided, and the clock signal can be used internally as a test data signal. Therefore, it is possible to set so that the clock signal and the data signal can be supplied by the same wiring. In this case, the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied by the separate wiring is excluded. A semiconductor device having an inspection support mechanism suitable for AC specification inspection can be obtained.
In addition, by supplying a data signal from the IO pad of the bidirectional IO terminal to the first-stage register, the data signal and the clock signal are input through different signal paths during the AC specification inspection, and the same data signal as in normal use is input. Since the path is used, more accurate AC specification inspection can be performed, and the design of the semiconductor device is facilitated by using the output-side IO buffer of the bidirectional IO terminal.
[0061]
Further, according to the AC spec inspection method according to the second embodiment, the semiconductor device configured as described above is used for the inspection at the time of the AC spec inspection, and only the clock signal is supplied from the LSI tester. Can be used as a data signal, and it is possible to accurately and stably perform an AC specification test without being affected by the wiring impedance of the LSI tester and the performance board. By supplying the data to the register, the same data signal path as in normal use is used, and more accurate AC specification inspection can be performed. Further, by using the output-side IO buffer of the bidirectional IO terminal, In addition, it is possible to obtain an AC specification inspection method that facilitates designing of a semiconductor device.
[0062]
Embodiment 3 FIG.
FIG. 5 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to the third embodiment of the present invention.
As shown in FIG. 5, a semiconductor device 91 on which an AC specification test is performed includes a clock input terminal 98, a bidirectional IO terminal 100 including an output three-state IO buffer 100a and an input IO buffer 100b, and a clock signal. A timing generation circuit (timing generation means) 101 using a delay element for outputting a plurality of timing signals after a predetermined delay time has elapsed after being input, and a clock signal and timing input from a clock input terminal 98 A clock selection circuit (clock selection means) 102 for selecting any of the timing signals input from the generation circuit 101; an internal function circuit 103; and a test pattern generation circuit (test pattern generation circuit) for generating a test pattern using the clock signal as a reference signal. Means) 104, bidirectional IO A first stage register 105 of the internal function circuit 103 as a first stage when viewed from the child 100 is configured to output values of the first-stage register 105 from observable output terminal 106..
[0063]
An LSI tester 92 that performs an AC specification test of the semiconductor device 91 is connected to a clock driver 94, a clock output terminal 95, a data input terminal 108, and a data input terminal 108, and outputs a voltage level input to the LSI tester 92. And a voltage level judgment circuit 109 for judging.
[0064]
Further, the performance board 93 connecting the semiconductor device 91 and the LSI tester 92 has a clock input terminal 97 and an output terminal 107 capable of observing the output value of the output terminal 106 of the semiconductor device 91.
A wiring 96 having a wiring impedance Z3 is provided between the clock driver 94 of the LSI tester 92 and the clock output terminal 95, and is provided between the clock input terminal 97 of the performance board 93 and the clock input terminal 98 of the semiconductor device 91. Each of the wires 99 having the wire impedance Z4 exists.
[0065]
Here, the semiconductor device 91 includes a delay time in a path from the bidirectional IO terminal 100 to the data signal input terminal D of the first stage register 105, and a clock signal of the first stage register 105 that does not pass through the timing generation circuit 101 from the clock signal input terminal 98. The difference between the delay time on the path to the input terminal CLK and the path from the clock signal input terminal 98 to the test signal generating circuit 104 for generating a test pattern, to the data signal input terminal D of the first stage register 105 via the bidirectional IO terminal 100 Is different from the delay time in the path from the clock signal input terminal 98 to the clock signal input terminal CLK of the first stage register 105 passing through the timing generation circuit 101, excluding the delay time in the timing generation circuit 101. Pre-designed to be equal There.
[0066]
FIG. 6 is a timing chart showing signal waveforms according to the third embodiment of the present invention.
In FIG. 6, S9 is an input clock signal waveform input to the clock input terminal 98 of the semiconductor device 91, S10 is a clock signal input to the test pattern generation circuit 104, and S11 is a test pattern generation circuit The dynamic test pattern output from the register 104 is S12, the data input waveform of the first-stage register 105 in the internal function circuit 103, and the S13 reaches the first-stage register 105 in the internal function circuit 103 through the timing generation circuit 101. It is a clock input waveform.
[0067]
The operation of the semiconductor device, the LSI tester, and the performance board configured as described above when inspecting the AC specifications of the semiconductor device will be described.
At the time of the AC specification inspection, the clock selection circuit 102 selects the output of the timing generation circuit 101, and the output 3-state IO buffer 100a of the bidirectional IO terminal 100 outputs the test pattern signal from the test pattern generation circuit 104 through. Shall be selected.
The clock signal output from the clock driver 94 of the LSI tester 92 passes through the wiring 96, the clock output terminal 95 of the LSI tester 92, the clock input terminal 97 on the performance board 93, and the wiring 99, and then the clock input terminal of the semiconductor device 91. 98. The clock signal input to the clock input terminal 98 is input to the timing generation circuit 101 and the test pattern generation circuit 104, respectively. The clock signal input to the timing generation circuit 101 is input as a clock signal to the first stage register 105 of the internal function circuit 103 via the clock selection circuit 102.
That is, the clock input waveform S13 that reaches the first stage register 105 in the internal function circuit 103 through the timing generation circuit 101 is obtained by adding the delay time in the timing generation circuit 101 to the clock signal waveform S9 input to the clock input terminal 98, and The clock signal is input to the register 105.
[0068]
On the other hand, the clock signal input to the test pattern generation circuit 104 serves as a trigger for the test pattern generation circuit 104, and the test pattern generation circuit 104 outputs a preset AC specification test pattern. The test pattern for AC specification inspection output from the test pattern generation circuit 104 passes through the 3-state IO buffer 100a on the output side of the bidirectional IO terminal 100 and the input-side IO buffer 100b, and is stored in the first-stage register 105 in the internal function circuit 103. Input as a data signal.
That is, the clock signal S10 is input to the test pattern generation circuit 104 after a delay time based on the design value with respect to the clock signal waveform S9 input to the clock input terminal 98, and the test pattern generation circuit 104 receives the clock signal S10. The pattern S11 is output.
[0069]
The data input waveform S12 of the first-stage register 105 is input as a data signal to the first-stage register 105 after a delay time based on a design value with respect to the dynamic test pattern S11 output from the test pattern generation circuit 104.
The first-stage register 105 latches a data signal input from the bidirectional IO terminal 100 with a clock signal input from the clock selection circuit 102.
The output data of the first-stage register 105 latched by the clock input waveform S13 reaching the first-stage register 105 sequentially passes through the output terminal 106 of the semiconductor device 91, the output terminal 107 on the performance board 93, the data input terminal 108 of the LSI tester 92, and the LSI. It is input to the voltage level determination circuit 109 of the tester 92.
[0070]
The voltage level determination circuit 109 performs an AC specification test by comparing whether or not the desired data has been latched in the first stage register 105 with an expected value test pattern of the LSI tester 92 prepared in advance.
At this time, the phase of the timing signal generated by the timing generation circuit 101 can be arbitrarily set so that a predetermined delay time can be obtained from among a plurality of delay times that can be set. The delay time of the input waveform S13 in the timing generation circuit 101 can be set to various values.
[0071]
Hereinafter, a timing inspection method for AC specifications according to the third embodiment will be described.
In the timing test of the AC specification according to the third embodiment, the LSI tester 92 outputs only the clock signal to the semiconductor device 91 during the timing test of the AC specification.
[0072]
The semiconductor device 91 receives the clock signal waveform S9, uses the clock as the trigger, uses the test pattern S11 generated by the test pattern generation circuit 104 as the data signal S12 of the internal function circuit 103, and generates a timing based on the clock signal waveform S9. The internal function circuit 103 is configured to execute a predetermined process by using a timing signal generated by the generation circuit 101 as a clock signal of the internal function circuit 103.
[0073]
Then, the output data signal waveform output from the internal function circuit 103 after executing the predetermined processing is output to the voltage level determination circuit 109 of the LSI tester 92, where the semiconductor device 91 has a predetermined AC specification. Is determined.
[0074]
This makes it possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to perform the AC spec inspection accurately without being affected by the wiring impedance of the LSI tester and the performance board. It can be performed stably.
Further, it is possible to perform an AC specification test with a plurality of preset dynamic test patterns without being affected by the wiring impedance of the LSI tester and the performance board. As a result, the power supply voltage fluctuation of the bidirectional IO terminal can be performed. Also, it is possible to accurately and stably inspect AC specifications (AC characteristics) due to fluctuations in rising and falling output delays at the bidirectional IO terminals.
Note that the timing generation circuit 101 appropriately adjusts the delay of the timing signal with respect to the data signal, and observes the determination result of the voltage level determination circuit 109 at each delay time to determine the AC specification when the delay time is appropriately changed. It is also possible to get results.
[0075]
As described above, according to the semiconductor device of the third embodiment, an AC spec test timing generator, a bidirectional IO terminal, and a plurality of preset AC spec test patterns are generated by using a clock signal as a trigger. And a test pattern generator circuit that can use the internally generated test pattern signal as a test data signal based on a clock signal introduced from the outside, so that the clock signal and the data signal are supplied by the same wiring. In this case, it is possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wirings, and to set a plurality of predetermined dynamic signals. Test patterns and LSI tester and performance board wiring impedance The AC spec inspection can be performed without being affected by the dance. As a result, the AC spec (AC characteristic) due to the power supply voltage fluctuation of the bidirectional IO terminal and the fluctuation of the rising and falling output delays at the bidirectional IO terminal can be obtained. Can be obtained accurately and stably, and a semiconductor device having an inspection support mechanism suitable for the inspection of AC specifications can be obtained.
[0076]
Further, according to the AC spec inspection method according to the third embodiment, the semiconductor device configured as described above is used for the inspection at the time of the AC spec inspection, and only the clock signal is supplied from the LSI tester, thereby introducing the semiconductor device from the outside. A test pattern signal generated internally based on a clock signal can be used as a data signal, so that accurate and stable AC spec inspection can be performed without being affected by wiring impedance of an LSI tester and a performance board. With a plurality of set dynamic test patterns, an AC spec inspection can be performed without being affected by the wiring impedance of the LSI tester and the performance board. As a result, the power supply voltage fluctuation of the bidirectional IO terminal and the Rising and falling output delay at IO terminal AC specifications inspection method capable of inspecting an AC specs (AC characteristics) accurately and stably by the dynamic can be obtained.
[0077]
In the third embodiment, the test pattern generation circuit 104 is a circuit that generates a plurality of test patterns for AC specification inspection using a clock signal as a trigger. However, a rewritable storage is used instead of this circuit. You may implement | achieve using an element. When a rewritable storage element is used, an AC specification (AC characteristic) in an arbitrary test pattern can be accurately and stably inspected by providing a test pattern to the storage element in advance from the outside. AC specification evaluation becomes possible.
[0078]
Embodiment 4 FIG.
FIG. 7 is a diagram illustrating a semiconductor device, an LSI tester, and a performance board according to the fourth embodiment of the present invention.
As shown in FIG. 7, a semiconductor device 121 on which an AC spec inspection is performed has a clock input terminal 128, a bidirectional IO terminal 130 including an output three-state IO buffer 130a and an input IO buffer 130b, and a clock signal. A timing generation circuit (timing generation means) 131 for AC spec inspection using a delay element, which outputs a plurality of timing signals after a predetermined delay time has elapsed after being input, and a clock signal input from a clock input terminal 128; A clock selection circuit (clock selection means) 132 for selecting one of the timing signals input from the timing generation circuit 131, an internal function circuit 133, and a test pattern generation circuit (test pattern generation circuit for generating a test pattern using the clock signal as a reference signal) Generating means) 134, A first-stage register 135 in the internal function circuit 133 which is a first-stage as viewed from the IO terminal 130, a storage element (storage means) 136 for temporarily storing an output value of the first-stage register 135, and an output value of the storage element 136 And an output terminal 137 capable of observing.
[0079]
An LSI tester 122 that performs an AC specification test of the semiconductor device 121 is connected to a clock driver 124, a clock output terminal 125, a data input terminal 139, and a data input terminal 139, and outputs a voltage level input to the LSI tester 122. And a voltage level judging circuit 140 for judging.
[0080]
Further, the performance board 123 that connects the semiconductor device 121 and the LSI tester 122 has a clock input terminal 127 and an output terminal 138 capable of observing the output value of the output terminal 137 of the semiconductor device 121.
A wiring 126 having a wiring impedance Z3 is provided between the clock driver 124 of the LSI tester 122 and the clock output terminal 125, and is provided between the clock input terminal 127 of the performance board 123 and the clock input terminal 128 of the semiconductor device 121. Each of the wirings 129 having the wiring impedance Z4 exists.
[0081]
Here, the semiconductor device 121 has a delay time in a path from the bidirectional IO terminal 130 to the data signal input terminal D of the first stage register 135, and a clock signal of the first stage register 135 that does not pass through the timing generation circuit 131 from the clock signal input terminal 128. The difference between the delay time on the path to the input terminal CLK and the path from the clock signal input terminal 128 to the data signal input terminal D of the first stage register 135 via the test pattern generating circuit 134 for generating a test pattern and the bidirectional IO terminal 130 Is different from the delay time in the path from the clock signal input terminal 128 to the clock signal input terminal CLK of the first stage register 135 passing through the timing generation circuit 131 from the delay time excluding the delay time in the timing generation circuit 131. So that they are equal It is total.
[0082]
FIG. 8 is a timing chart showing signal waveforms according to Embodiment 4 of the present invention.
8, S14 is a waveform of an input clock signal at the clock input terminal 128, S15 is a clock signal input to the test pattern generation circuit 134, and S16 is a dynamic test signal output from the test pattern generation circuit 134. S17 is a data input waveform of the first-stage register 135, S18 is a clock input waveform of the first-stage register 135 that reaches the first-stage register 135 via the timing generation circuit 131, and S19 is an input to the storage element 136. Signal.
[0083]
The operation of the semiconductor device, the LSI tester, and the performance board configured as described above when inspecting the AC specifications of the semiconductor device will be described.
At the time of the AC specification inspection, the clock selection circuit 132 selects the output of the timing generation circuit 131, and the output 3-state IO buffer 130a of the bidirectional IO terminal 130 outputs the test pattern signal from the test pattern generation circuit 134 through. Shall be selected.
The clock signal output from the clock driver 124 of the LSI tester 122 passes through the wiring 126, the clock output terminal 125 of the LSI tester 122, the clock input terminal 127 on the performance board 123, and the wiring 129 in this order, and the clock input terminal of the semiconductor device 121. 128. The clock signal input to the clock input terminal 128 is input to the timing generation circuit 131 and the test pattern generation circuit 134, respectively. The clock signal input to the timing generation circuit 131 is input as a clock signal to the first-stage register 135 of the internal function circuit 133 via the clock selection circuit 132.
That is, the clock input waveform S18 that reaches the first-stage register 135 in the internal function circuit 133 through the timing generation circuit 131 is obtained by adding the delay time in the timing generation circuit 131 to the clock signal waveform S14 input to the clock input terminal 128, and The signal is input to the register 135 as a clock signal.
[0084]
On the other hand, the clock signal input to the test pattern generation circuit 134 serves as a trigger for the test pattern generation circuit 134, and the test pattern generation circuit 134 outputs a test pattern for AC spec inspection set in advance. The test pattern for AC specification inspection output from the test pattern generating circuit 134 passes through the three-state IO buffer 130a on the output side of the bidirectional IO terminal 130 and the input-side IO buffer 130b, and is stored in the first-stage register 135 in the internal function circuit 133. Input as a data signal.
That is, the clock signal S15 is input to the test pattern generation circuit 134 after a delay time based on the design value with respect to the clock signal waveform S14 input to the clock input terminal 128, and the test pattern generation circuit 134 receives the clock signal S15. The pattern S16 is output.
[0085]
The data input waveform S17 of the first-stage register 135 is input as a data signal to the first-stage register 135 after a delay time based on a design value with respect to the dynamic test pattern S16 output from the test pattern generation circuit 134.
[0086]
The first-stage register 135 latches a data signal input from the bidirectional IO terminal 130 with a clock signal input from the clock selection circuit 132.
[0087]
The output data of the first-stage register 135 latched by the clock input waveform S18 reaching the first-stage register 135 is input to the storage element 136. The input signal S19 of the storage element 136 is sequentially input to the voltage level determination circuit 140 of the LSI tester 122 via the output terminal 137 of the semiconductor device 121, the output terminal 138 of the performance board 123, and the data input terminal 139 of the LSI tester 122. . When the frequency of the clock input waveform S18 reaching the first-stage register 135 is very high, the frequency read from the storage element 136 is made low.
[0088]
The voltage level determination circuit 140 compares the input signal S19 of the storage element 136 with the expected value test pattern of the LSI tester 122 prepared in advance to determine whether or not the desired data has been latched in the first stage register 135. Performs an AC specification inspection.
[0089]
At this time, the phase of the timing signal generated by the timing generation circuit 131 can be arbitrarily set so that a predetermined delay time can be obtained from among a plurality of delay times that can be set. The delay time of the input waveform S18 in the timing generation circuit 131 can be set to various values.
[0090]
Hereinafter, a timing inspection method for AC specifications according to the fourth embodiment will be described.
In the timing test of the AC specification according to the fourth embodiment, the LSI tester 122 outputs only the clock signal to the semiconductor device 121 during the timing test of the AC specification.
The semiconductor device 121 receives the clock signal waveform S14, uses the clock signal waveform S14 as a trigger, uses the test pattern S16 generated by the test pattern generation circuit 134 as the data signal S17 of the internal function circuit 133, and generates a timing based on the clock signal waveform S14. The internal function circuit 133 is configured to execute predetermined processing by using the timing signal generated by the generation circuit 131 as a clock signal of the internal function circuit 133.
Then, the output data signal output from the internal function circuit 133 after executing the predetermined processing is temporarily stored by the storage element 136 and then output to the voltage level determination circuit 140 of the LSI tester 122, where the semiconductor device 121 It is determined whether the specified AC specification is provided.
[0091]
This makes it possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to perform the AC spec inspection accurately without being affected by the wiring impedance of the LSI tester and the performance board. It can be performed stably.
Further, it is possible to perform an AC specification test with a plurality of preset dynamic test patterns without being affected by the wiring impedance of the LSI tester and the performance board. As a result, the power supply voltage fluctuation of the bidirectional IO terminal can be performed. Also, it is possible to accurately and stably inspect AC specifications (AC characteristics) due to fluctuations in rising and falling output delays at the bidirectional IO terminals.
[0092]
Further, since the output signal of the internal function circuit 133 can be temporarily stored in the storage element 136 and then read out, it is possible to reliably obtain the inspection result even if the testable speed of the LSI tester 122 is low. Become.
The timing generation circuit 131 appropriately adjusts the delay of the timing signal with respect to the data signal, and observes the determination result of the voltage level determination circuit 140 at each delay time to determine the AC specification when the delay time is appropriately changed. It is also possible to get results.
[0093]
As described above, according to the semiconductor device of the fourth embodiment, the AC specification test timing generation circuit, the bidirectional IO terminal, the AC specification test pattern generation circuit triggered by the clock signal, and the output of the first stage register It has a storage element that temporarily holds data, and a test pattern signal generated internally based on a clock signal introduced from the outside can be used as a data signal for testing, so that the clock signal and the data signal are the same. In this case, it is possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to set the clock signal and the data signal in advance. LSI tester and performance board distribution using multiple dynamic test patterns An AC specification test can be performed without being affected by impedance. As a result, AC specifications (AC characteristics (AC characteristics) due to fluctuations in the power supply voltage of the bidirectional IO terminal and fluctuations in the rising and falling output delays at the bidirectional IO terminal) can be obtained. ) Can be inspected accurately and stably. Furthermore, the output data of the first-stage register is temporarily held, and after the test pattern generation is completed, the held data in the storage element is read at a low frequency, so that the input to the first-stage register can be performed. Even when the clock frequency is very high, a high-speed AC spec test can be performed accurately and stably, and a semiconductor device having a test support mechanism suitable for the AC spec test can be obtained.
[0094]
In addition, according to the AC spec inspection method according to the fourth embodiment, the semiconductor device configured as described above is used for the inspection at the time of the AC spec inspection, and only the clock signal is supplied from the LSI tester, thereby introducing the semiconductor device from the outside. A test pattern signal generated internally based on a clock signal can be used as a data signal, and an AC spec inspection can be performed accurately and stably without being affected by the wiring impedance of an LSI tester and a performance board. It is possible to eliminate the influence of the difference in the wiring impedance when the data signal and the data signal are supplied through separate wirings, and to perform the influence of the wiring impedance of the LSI tester and the performance board with a plurality of preset dynamic test patterns. AC without receiving Peck inspection can be performed, and as a result, AC specifications (AC characteristics) due to fluctuations in the power supply voltage of the bidirectional IO terminal and fluctuations in the rising and falling output delays at the bidirectional IO terminal can be accurately and stably inspected. When the clock frequency input to the first stage register is very high by temporarily holding the output data of the first stage register and reading out the held data in the storage element at a low frequency after the completion of the test pattern generation In addition, it is possible to obtain an AC spec inspection method capable of accurately and stably performing a high-speed AC spec inspection.
[0095]
Modification of the fourth embodiment.
In the fourth embodiment, as the timing generation circuit, one constituted by delay elements for outputting a plurality of timing signals is provided. However, as shown in FIG. 9, a PLL circuit 191 is provided instead of the timing generation circuit. A timing chart in this case may be as shown in FIG.
When the PLL circuit is provided as shown in FIG. 10, by setting the frequency of the clock signal input to the first-stage register 195 to be a multiple of the clock signal input to the clock input terminal 188, the data input signal of the first-stage register 195 Can be latched a plurality of times, not only can a more detailed AC specification test be performed, but also the output data signal of the first-stage register 195 can be temporarily stored in the storage element 196, and the low-speed operation can be performed after the completion of the test pattern generation. Even when the maximum testable frequency of the LSI tester 182 is lower than the test frequency of the semiconductor device 181, a high-speed AC spec test can be accurately and stably performed using an inexpensive LSI tester. can do.
[0096]
Embodiment 5 FIG.
FIG. 11 shows a semiconductor device, an LSI tester, and a performance board according to the fifth embodiment of the present invention.
As shown in FIG. 11, a semiconductor device 151 on which an AC specification test is performed has a clock input terminal 158, a bidirectional IO terminal 160 including an output three-state IO buffer 160a and an input IO buffer 160b, and a clock signal. A timing generation circuit (timing generation means) 161 for AC spec inspection using a delay element, which outputs a plurality of timing signals after a predetermined delay time has elapsed after being input, and a clock signal input from a clock input terminal 158; A clock selection circuit (clock selection means) 162 for selecting any of the timing signals input from the timing generation circuit 161; an internal function circuit 163; and a test pattern generation circuit (test pattern generation circuit) for generating a test pattern using the clock signal as a reference signal. Generating means) 164, A first stage register 165 in the internal function circuit 163 which is a first stage as viewed from the IO terminal 160, a register 171 to which an output of the first stage register 165 is input and outputs a signal to be measured, and an output of the test pattern generation circuit 164 to which a reference signal is input. 172, and an Ex-OR gate 173 to which the outputs of the registers 171 and 172 are input, and a comparison circuit (compares an output value of the first stage register 165 and an output value of the test pattern generation circuit 164) (Comparing means) 166 and an output terminal 167 of the semiconductor device 151 from which the output value of the comparing circuit 166 can be observed.
[0097]
An LSI tester 152 that performs an AC specification test of the semiconductor device 151 determines a voltage level inside the LSI tester 152 connected to the clock driver 154, the clock output terminal 155, the data input terminal 169, and the data input terminal 169. And a voltage level determination circuit 170 that performs the operation.
[0098]
Further, the performance board 153 that connects the semiconductor device 151 and the LSI tester 152 has a clock input terminal 157 and an output terminal 168 capable of observing the output value of the output terminal 167 of the semiconductor device 151.
A wiring 156 having a wiring impedance Z3 is provided between the clock driver 154 of the LSI tester 152 and the clock output terminal 155, and is provided between the clock input terminal 157 of the performance board 153 and the clock input terminal 158 of the semiconductor device 151. Each of the wirings 159 having the wiring impedance Z4 exists.
[0099]
Here, the semiconductor device 151 includes a delay time in a path from the bidirectional IO terminal 160 to the data signal input terminal D of the first stage register 165, and a clock signal of the first stage register 165 that does not pass through the timing generation circuit 161 from the clock signal input terminal 158. The difference between the delay time on the path to the input terminal CLK and the path from the clock signal input terminal 158 to the data signal input terminal D of the first stage register 165 via the test pattern generation circuit 164 for generating a test pattern and the bidirectional IO terminal 160 Is different from the delay time in the path from the clock signal input terminal 158 to the clock signal input terminal CLK of the first stage register 165 passing through the timing generation circuit 161 from the delay time obtained by excluding the delay time in the timing generation circuit 161. So that they are equal It is total.
[0100]
FIG. 12 is a timing chart showing signal waveforms according to the fifth embodiment of the present invention.
In FIG. 12, S26 is the input clock signal waveform of the clock input terminal 158, S27 is the clock signal input to the test pattern generation circuit 164, S28 is the data input waveform of the first stage register 165, and S29 Is a data output waveform of the first-stage register 165, S30 is a measurement target signal output by the register 171, S31 is a data input waveform of the register 172, and S32 is a reference signal output by the register 172. .
[0101]
The operation of the semiconductor device, the LSI tester, and the performance board configured as described above when inspecting the AC specifications of the semiconductor device will be described.
At the time of the AC specification inspection, the clock selection circuit 162 selects the output of the timing generation circuit 161, and the output 3-state IO buffer 160 a of the bidirectional IO terminal 160 outputs the test pattern signal from the test pattern generation circuit 164 through. Shall be selected.
The clock signal output from the clock driver 154 of the LSI tester 152 passes through the wiring impedance 156, the clock output terminal 155 of the LSI tester 152, the clock input terminal 157 on the performance board 153, and the wiring 159 in that order. Input to terminal 158. The clock signal input to clock input terminal 158 is input to timing generation circuit 161 and test pattern generation circuit 164, respectively. The clock signal input to the timing generation circuit 161 is input as a clock signal to the first stage register 165 of the internal function circuit 163 via the clock selection circuit 162.
That is, the clock input that reaches the first-stage register 165 in the internal function circuit 163 through the timing generation circuit 161 is obtained by adding the delay time in the timing generation circuit 161 to the clock signal waveform S26 input to the clock input terminal 158. 165 is input as a clock signal.
[0102]
On the other hand, the clock signal input to the test pattern generation circuit 164 serves as a trigger for the test pattern generation circuit 164, and the test pattern generation circuit 164 outputs a preset AC specification test pattern. The test pattern for AC specification inspection output from the test pattern generation circuit 164 passes through the three-state IO buffer 160a on the output side of the bidirectional IO terminal 160 and the input-side IO buffer 160b to the first-stage register 165 in the internal function circuit 163. Input as a data signal.
[0103]
The first-stage register 165 latches a data signal input from the bidirectional IO terminal 160 with a clock signal input from the clock selection circuit 162. Thereafter, the output value of the first-stage register 165 is input to the comparison circuit 166. In the comparison circuit 166, the output data signal of the first-stage register 165 that has reached the register 171 connected to the first-stage register 165 is latched by the clock signal input to the clock input terminal 158 in order to temporarily hold it as a measurement target signal. Is done.
[0104]
On the other hand, the output data signal of the test pattern generation circuit 164 is also input to the comparison circuit 166. In the comparison circuit 166, the output data signal of the test pattern generation circuit 164 that has reached the register 172 connected to the test pattern generation circuit 164 is a clock input to the clock input terminal 158 for temporarily holding as a reference signal. Latched by signal.
[0105]
That is, the clock signal S27 is input to the test pattern generation circuit 164, the register 171, and the register 172 after a delay time based on the design value with respect to the clock signal waveform S26 input to the clock input terminal 158.
The data input waveform S28 of the first-stage register 165 is input as a data signal to the first-stage register 165 after a delay time based on a design value with respect to the dynamic test pattern output from the test pattern generation circuit 164. The data input waveform S31 of the register 172 is input as a data signal to the register 172 after a delay time based on a design value with respect to the dynamic test pattern output from the test pattern generation circuit 164.
[0106]
The Ex-OR gate 173 receives the measurement target signal S30 output from the register 171 latched by the clock signal S27 and the reference signal S32 output from the register 172 latched by the clock signal S27. The Ex-OR gate 173 compares the measurement target signal S30 with a reference signal S32 as an expected value. The output of the Ex-OR gate 173 is input to the voltage level determination circuit 170 of the LSI tester 152 via the output terminal 167 of the semiconductor device 151, the output terminal 168 of the performance board 153, and the data input terminal 169 of the LSI tester 152 in order. .
[0107]
The voltage level determination circuit 170 can determine whether or not the semiconductor device 151 satisfies a predetermined AC specification simply by determining the level of the output of the Ex-OR gate 173.
This is compared with the comparison between the output of the first-stage register and the expected value test pattern, which is performed in the LSI tester in the first to fourth embodiments. In the fifth embodiment, the comparison circuit in the semiconductor device 151 is used. This is because the measurement has already been performed according to 166. If the High voltage level is observed by the voltage level determination circuit 170, a determination result that the predetermined AC specification is not satisfied is obtained, and conversely, the High voltage level must be observed. For example, a determination result that a predetermined AC specification is satisfied is obtained.
[0108]
Further, the phase of the timing signal generated by the timing generation circuit 161 can be arbitrarily set so that a predetermined delay time can be obtained from among a plurality of delay times that can be set. The delay time in the timing generation circuit 161 can be set to various values.
[0109]
Hereinafter, a method for checking the timing of AC specifications according to the fifth embodiment will be described.
In the timing test of the AC specification according to the fifth embodiment, the LSI tester 152 outputs only the clock signal to the semiconductor device 61 during the timing test of the AC specification.
The semiconductor device 151 receives the clock signal waveform S26, uses the clock signal waveform S26 as a trigger to generate a test pattern generated by the test pattern generation circuit 164 as the data signal S28 of the internal function circuit 153, and generates the test pattern based on the clock signal waveform S26. The internal function circuit 163 is configured to execute a predetermined process by using the timing signal as a clock signal of the internal function circuit 163.
Then, the comparison circuit 166 compares the output data signal output from the internal function circuit 163 after executing the predetermined processing with the output data signal of the test pattern generation circuit 164 as a reference signal. This comparison result is output to the voltage level determination circuit 170 of the LSI tester 152. In the voltage level determination circuit 170, since the comparison has already been performed using the reference signal as the expected value by the comparison circuit 166, it is determined whether the semiconductor device 151 has a predetermined AC specification simply by determining the level of the comparison result. Is determined.
[0110]
This makes it possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wiring, and to perform the AC spec inspection accurately without being affected by the wiring impedance of the LSI tester and the performance board. It can be performed stably.
Further, it is possible to perform an AC specification test with a plurality of preset dynamic test patterns without being affected by the wiring impedance of the LSI tester and the performance board. As a result, the power supply voltage fluctuation of the bidirectional IO terminal can be performed. Also, it is possible to accurately and stably inspect AC specifications (AC characteristics) due to fluctuations in rising and falling output delays at the bidirectional IO terminals.
Further, by comparing the test pattern signal with the output data of the first-stage register as a reference signal, the pattern of the expected value which had to be prepared in advance in the LSI tester becomes unnecessary, and a high-speed AC spec inspection can be performed. Accurate, stable and easy.
Note that the timing generation circuit 161 appropriately adjusts the delay of the timing signal with respect to the data signal, and observes the determination result of the voltage level determination circuit 170 at each delay time to determine the AC specification when the delay time is appropriately changed. It is also possible to get results.
[0111]
As described above, according to the semiconductor device of the fifth embodiment, the AC specification test timing generation circuit, the bidirectional IO terminal, the AC specification test pattern generation circuit triggered by the clock signal, and the comparison circuit are provided. Since the test pattern signal generated internally based on the clock signal introduced from the outside can be used as the data signal for testing, it can be set so that the clock signal and the data signal can be supplied by the same wiring, With this setting, it is possible to eliminate the influence of the difference in the wiring impedance when the clock signal and the data signal are supplied through separate wirings, and to make the clock frequency input to the first-stage register extremely high. In some cases, temporarily hold the output data of the first stage register and wait for the completion of test pattern generation. By reading the data held in the storage element at a low frequency, a high-speed AC specification test can be accurately and stably performed. In addition, an LSI tester and a performance test can be performed using a plurality of preset dynamic test patterns. The AC spec inspection can be performed without being affected by the wiring impedance of the board. As a result, the AC spec due to the power supply voltage fluctuation of the bidirectional IO terminal and the fluctuation of the rising / falling output delay at the bidirectional IO terminal can be obtained. (AC characteristics) can be inspected accurately and stably, and the test pattern signal is used as a reference signal to compare with the output data of the first-stage register, so that it is necessary to prepare in advance in the LSI tester. The pattern of the expected value is not required, and the high-speed AC spec inspection is accurate, stable and Can be done easily, it is possible to obtain a semiconductor device having a test support mechanisms suitable for inspection of AC specifications.
[0112]
Further, according to the AC spec inspection method according to the fifth embodiment, the semiconductor device configured as described above is used for the inspection at the time of the AC spec inspection, and only the clock signal is supplied from the LSI tester, so that the semiconductor device is externally introduced. A test pattern signal generated internally based on a clock signal can be used as a data signal, and an AC spec inspection can be performed accurately and stably without being affected by the wiring impedance of an LSI tester and a performance board. It is possible to eliminate the influence of the difference in wiring impedance when the data signal and the separate signal are supplied, and if the clock frequency input to the first register is very high, the output data of the first register Is temporarily stored and stored after the completion of test pattern generation. By reading stored data in a chip at a low frequency, high-speed AC spec inspection can be performed accurately and stably. In addition, an LSI tester and a performance board can be tested with a plurality of preset dynamic test patterns. The AC spec inspection can be performed without being affected by the wiring impedance of the bidirectional IO terminal, and as a result, the AC spec ( AC characteristics) can be accurately and stably inspected, and the test pattern signal is compared with the output data of the first-stage register as a reference signal, so that the LSI tester needs to prepare in advance. Accurate, stable, and easy high-speed AC spec inspection without the need for value patterns Can Nau, it is possible to obtain the AC spec inspection method.
[0113]
【The invention's effect】
As described above, according to the semiconductor device of claim 1 of the present invention, a data input terminal for inputting a data signal from outside the device, a clock input terminal for inputting a clock signal from outside the device, and a clock input terminal A clock generation unit that generates a timing signal at a predetermined timing according to the input clock signal, a clock signal input from the clock input terminal, and a clock selection unit that selects and outputs any of the timing signals; A first stage register which is an initial stage when viewed from the data input terminal, and a signal which supplies a signal based on the clock signal input from the clock input terminal to the first stage register as a data signal, wherein the output of the clock selecting means is a clock signal; Selection means, wherein the clock selection means is set to an upper Since the timing signal is selected, and the signal selecting means selects the supply of the signal based on the clock signal at the time of the AC specification inspection, and only the clock signal is supplied from the LSI tester at the time of the AC specification inspection, There is an effect that a semiconductor device capable of accurately and stably performing the AC specification inspection without being affected by the wiring impedance of the LSI tester and the performance board is obtained.
[0114]
According to the semiconductor device according to claim 2 of the present invention, in the semiconductor device according to claim 1, the timing generation means is provided after a predetermined delay time elapses according to a clock signal input from the clock input terminal. Since it is configured by the delay means for generating the timing signal, there is an effect that a semiconductor device in which the timing generation means can be easily configured is obtained.
[0115]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the timing generation means has a predetermined phase difference while synchronizing with a clock signal input from the clock input terminal. Since the DLL circuit is configured to generate a plurality of timing signals and select an arbitrary timing signal from the plurality of timing signals, the frequency of the external input clock signal is changed to change the frequency of the external input clock signal. Since the delay time of the timing signal can be continuously changed, there is an effect that a semiconductor device capable of performing more detailed AC spec inspection can be obtained.
[0116]
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the timing generation means includes a PLL circuit that generates a frequency corresponding to a clock signal input from the clock input terminal. By setting the frequency of the clock input signal input to the first-stage register to be a multiple of the clock signal input to the clock input terminal, the data input signal of the first-stage register can be latched multiple times. This makes it possible to obtain a semiconductor device capable of performing a more detailed AC specification inspection.
[0117]
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the clock signal is input instead of the data input terminal and the signal selection unit. Since a bidirectional IO terminal including an output-side IO buffer and an input-side IO buffer to which the data signal is input is provided at a connection node between an output of the output-side IO buffer and its input, an AC spec inspection is performed. Since only the clock signal is supplied from the LSI tester, it is not affected by the wiring impedance of the LSI tester and the performance board, and the data signal is supplied to the first-stage register from the IO pad of the bidirectional IO terminal. Uses the same data signal path as the above, and allows for more accurate AC spec inspection. The semiconductor device has an effect obtained that.
[0118]
According to the semiconductor device of the sixth aspect of the present invention, in the semiconductor device of the fifth aspect, the clock signal input from the clock input terminal is input immediately before the input of the bidirectional IO terminal to the output-side IO buffer. Test pattern generating means for generating a test pattern as a reference signal and outputting the test pattern in place of the clock signal is provided. At the time of AC specification inspection, only the clock signal is supplied from the LSI tester. In addition, it is possible to perform an AC specification test using a plurality of preset dynamic test patterns without being affected by the wiring impedance of the performance board. As a result, the AC specification (AC Semiconductor device that can accurately and stably inspect characteristics) There is an effect.
[0119]
According to the semiconductor device of claim 7 of the present invention, in the semiconductor device of claim 6, the test pattern generating means is constituted by a rewritable storage means. Is given to the storage element, an AC specification (AC characteristic) for an arbitrary test pattern can be accurately and stably inspected, and a semiconductor device capable of performing more detailed AC specification evaluation is obtained. .
[0120]
According to the semiconductor device of claim 8 of the present invention, in the semiconductor device of claim 7, the storage means for temporarily holding the output value of the first-stage register immediately after the output of the first-stage register is provided. Since only the clock signal is supplied from the LSI tester at the time of the AC specification inspection, the dynamic AC specification inspection can be performed without being affected by the wiring impedance of the LSI tester and the performance board. When the clock frequency input to the register is very high, the output data of the first-stage register is temporarily held, and the data stored in the storage element is read out at a low frequency after the completion of the test pattern generation, so that the high-speed operation is performed. Of obtaining a semiconductor device capable of accurately and stably performing a simple AC specification test A.
[0121]
According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect, immediately after the output of the first-stage register, the output value of the first-stage register and the output value of the test pattern generating unit are changed. A comparison means is provided for comparison, and only the clock signal is supplied from the LSI tester at the time of the AC specification test. Therefore, the dynamic AC specification test can be performed without being affected by the wiring impedance of the LSI tester and the performance board. In addition to the above, the pattern of the expected value which has to be prepared in advance in the LSI tester is not required, and a semiconductor device capable of accurately, stably and easily performing a high-speed AC spec inspection can be obtained.
[0122]
According to an AC specification inspection method according to claim 10 of the present invention, in the AC specification inspection method for inspecting an AC specification of a semiconductor device according to any one of claims 1 to 7, only a clock signal is supplied to the semiconductor device. In addition, since the AC specification is checked by comparing the output value of the first-stage register with an expected value prepared in advance, accurate and stable without being affected by the wiring impedance of the LSI tester and the performance board. Thus, there is an effect that an AC specification inspection method capable of performing an AC specification inspection can be obtained.
[0123]
According to an AC specification inspection method according to claim 11 of the present invention, in the AC specification inspection method for inspecting the AC specification of a semiconductor device according to claim 8, only the clock signal is supplied to the semiconductor device, and The AC specification is inspected by comparing the output value of the first-stage register temporarily held with the expected value prepared in advance, so that it is affected by the wiring impedance of the LSI tester and the performance board. In addition to the above, a dynamic AC spec inspection can be performed, and when the clock frequency input to the first-stage register is extremely high, the output data of the first-stage register is temporarily held, and after the test pattern generation is completed, Accurate high-speed AC spec inspection by reading stored data in the storage element at low frequency One AC specifications inspection method capable of stably inspected the effect obtained.
[0124]
According to the AC specification inspection method according to claim 12 of the present invention, in the AC specification inspection method for inspecting the AC specification of a semiconductor device according to claim 9, only the clock signal is supplied to the semiconductor device, Is determined on the basis of the output values of the above, so that a dynamic AC specification test can be performed without being affected by the wiring impedance of the LSI tester and the performance board. This eliminates the need for the pattern of the expected value that had to be prepared in advance in the LSI tester, and has the effect of providing an AC spec inspection method capable of performing accurate, stable and easy high-speed AC spec inspection.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a timing chart of each signal waveform according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to a second embodiment of the present invention.
FIG. 4 is a diagram showing a timing chart of each signal waveform according to the second embodiment of the present invention.
FIG. 5 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a timing chart of each signal waveform according to the third embodiment of the present invention.
FIG. 7 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to a fourth embodiment of the present invention.
FIG. 8 is a diagram showing a timing chart of each signal waveform according to the fourth embodiment of the present invention.
FIG. 9 is a diagram showing a modification in which a PLL circuit is used instead of the delay element of the timing generation circuit according to the fourth embodiment of the present invention.
FIG. 10 is a diagram showing a timing chart of each signal waveform when a PLL circuit is used instead of a delay element of the timing generation circuit of the semiconductor device according to the fourth embodiment of the present invention;
FIG. 11 is a diagram showing a semiconductor device, an LSI tester, and a performance board according to a fifth embodiment of the present invention.
FIG. 12 is a diagram showing a timing chart of each signal waveform according to the fifth embodiment of the present invention.
FIG. 13 is a diagram showing a conventional semiconductor device, LSI tester, and performance board.
14A and 14B are diagrams showing timing charts of respective signal waveforms in a conventional example, FIG. 14A is a diagram showing a timing chart of each signal waveform in a conventional setup time inspection, and FIG. It is a figure showing a timing chart of each signal waveform in a time inspection.
[Explanation of symbols]
1,31,61,91,121,151,181 Semiconductor device
2,32,62,92,122,152,182 LSI tester
3,33,63,93,123,153,183 Performance board
4,34,64,94,124,154,184 clock driver
5,35,65,95,125,155,185 Clock output terminal
6, 9, 12, 15, 36, 39, 66, 69, 96, 99, 126, 129, 156, 159, 186, 189 Wiring impedance
7 Data driver
8 Data output terminal
10, 11, 37, 38, 67, 68, 97, 98, 127, 128, 157, 158, 187, 188 Clock input terminal
13, 14, 20, 40, 48, 77, 108, 139, 169, 199 Data input terminal
16, 43, 73, 103, 133, 163, 193 Internal function circuit
17,44,74,105,135,165,195 First stage register
18, 19, 46, 47, 75, 76, 106, 107, 137, 138, 167, 168, 197, 198 Output terminal
21,49,78,109,140,170,200 Voltage level determination circuit
41, 71, 101, 131, 161, 191 Timing generation circuit
42, 72, 102, 132, 162, 192 clock selection circuit
45 Selector
70,100,130,160,190 Bidirectional IO terminal
70a, 100a, 130a, 160a, 190a Output 3-state IO buffer
70b, 100b, 130b, 160b, 190b Input side IO buffer
104, 134, 164, 194 test pattern generation circuit
136,196 storage element
166 Comparison circuit
171,172 register
173 Ex-OR gate
D Data input terminal
CLK Clock input terminal

Claims (12)

A data input terminal for inputting a data signal from outside the device,
A clock input terminal for inputting a clock signal from outside the device,
Timing generating means for generating a timing signal at a predetermined timing according to a clock signal input from the clock input terminal;
A clock signal input from the clock input terminal, and a clock selection unit for selecting and outputting any of the timing signals;
An output of the clock selection means as a clock signal, an initial stage register which is an initial stage as viewed from the data input terminal,
Signal selection means for selecting whether to supply a signal based on a clock signal input from the clock input terminal to the first-stage register as a data signal,
The clock selecting means selects the timing signal at the time of the AC specification inspection,
The signal selection means selects the supply of a signal based on the clock signal at the time of an AC specification test.
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The timing generating means includes delay means for generating a timing signal after a predetermined delay time has elapsed according to a clock signal input from the clock input terminal.
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The timing generating means generates a plurality of timing signals having a predetermined phase difference while synchronizing with a clock signal input from the clock input terminal, and selects a DLL from the plurality of timing signals. (Delay Locked Loop) circuit,
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The timing generating means includes a PLL (Phase Locked Loop) circuit that generates a frequency corresponding to a clock signal input from the clock input terminal.
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1, wherein
Instead of the data input terminal and the signal selection means,
A bidirectional IO terminal including an output-side IO buffer to which the clock signal is input, and an input-side IO buffer to which the data signal is input to a connection node between the output of the output-side IO buffer and its input;
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 5,
Immediately before input to the output-side IO buffer of the bidirectional IO terminal, a test pattern is generated by using a clock signal input from the clock input terminal as a reference signal and outputting the test pattern instead of the clock signal. Comprising means,
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 6,
The test pattern generating means is constituted by a rewritable storage means,
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 7,
Immediately after the output of the first-stage register, storage means for temporarily holding the output value of the first-stage register,
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 7,
Immediately after the output of the first-stage register, a comparison unit that compares an output value of the first-stage register with an output value of the test pattern generation unit is provided.
A semiconductor device characterized by the above-mentioned. An AC specification inspection method for inspecting an AC specification of a semiconductor device according to claim 1,
Supplying only a clock signal to the semiconductor device,
Check the AC specification by comparing the output value of the first-stage register with an expected value prepared in advance.
An AC specification inspection method, characterized in that: An AC specification inspection method for inspecting an AC specification of a semiconductor device according to claim 8,
Supplying only a clock signal to the semiconductor device,
Comparing the output value of the first-stage register temporarily held in the storage means with an expected value prepared in advance to check AC specifications;
An AC specification inspection method, characterized in that: An AC specification inspection method for inspecting an AC specification of a semiconductor device according to claim 9,
Supplying only a clock signal to the semiconductor device,
Determining whether or not a predetermined AC specification is satisfied based on an output value of the comparing means;
An AC specification inspection method, characterized in that:

Images