JP2008305450A - Test system and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test system and a test method which are simple and by which a test in high frequency is achieved. <P>SOLUTION: The system is provided with a clock generating unit which has a test circuit corresponding to a device to be tested having a test circuit responding to a test signal and which supplies first clocks corresponding to operational frequencies of a test device being normal and the device to be tested to the test device and the device to be tested. A test unit inputs a test signal group to the device to be tested and the test device. The test device is operated corresponding to the input test signal group, and supplies a test pattern signal to the device to be tested corresponding to the first clock, the device to be tested is operated by the test pattern signal input corresponding to the first clock, while generates a test result. The test unit inputs the test result of the device to be tested. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test system and a test method, and more particularly, to a technique effective for use in a test system and a test method for a semiconductor device that operates with a clock having a frequency higher than the operation clock frequency of the test device.

As a test method using a test chip called BOST (Built Out Self Test) and a BIST (Built In Self Test) which is a circuit for testing a device under test, there is JP-A-2003-016799. Japanese Patent Laid-Open No. 2003-028928 discloses a method (loop) for performing an operation test of an I / O interface at an actual operation speed by connecting an output terminal and an input terminal of an LSI as a device under test externally.
JP 2003-016799 A JP 2003-028928 A

  The applicant of the present application has developed a high-speed memory that performs a high-speed operation such as 1.0 Gbps by performing a DDR operation using a clock signal such as 500 MHz. For such high-speed memory AC testing, a test apparatus having a test frequency corresponding to 1.0 Gbps is required, and the development of such a high-speed memory faced the problem of enormous cost and time. Patent Document 1 relates to a chip test in a wafer state, and presupposes electrical connection by a probe. Such electrical connection with the probe is not suitable for the actual operation test as described above because the high-frequency signal transmission as described above is impossible. Patent Document 2 is not concerned with testing the entire device exclusively for the actual operation test of the I / O interface. Accordingly, the inventors of the present application have developed a test system and a test method capable of performing a test at a higher frequency by using an existing test apparatus having a test frequency lower than the test frequency.

  An object of the present invention is to provide a test system and a test method that realize a test at a high frequency with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The test apparatus outputs a first test signal group and inputs a test result in response to the first test signal group. A test circuit corresponding to the device under test having a test circuit that operates in response to the first test signal group, a test device in which the circuit operation is normal, and a first clock corresponding to the operating frequency of the device under test A clock generator for generating a signal and supplying the signal to the test device and the device under test is provided. The test apparatus performs a first operation of inputting the first test signal group to the device under test and the test device. The test device operates in response to the input first test signal group, supplies a test pattern signal to the device under test in response to the first clock signal, and the device under test has the first clock. A second operation for generating a test result is performed while operating with the test pattern signal input corresponding to the signal. The test apparatus performs a third operation for capturing the test result of the device under test.

  The clock generator generates a clock signal corresponding to the operating frequency of the device under test, operates the device under test and the test device, and the test device handles the test signal and the result as the test preparation operation. For the exchange of signals between the device under test and the test device, it is possible to use a clock signal having its own low frequency that is asynchronous with the clock signal.

  FIG. 1 is a block diagram showing an embodiment of a test system according to the present invention. The test system of this embodiment is composed of a test apparatus (hereinafter sometimes referred to as ATE) 1 and a test substrate 2 indicated by a one-dot chain line in FIG. On the test board 2, a clock generation device (hereinafter also referred to as CLKG) 3, a test device (also referred to as RAM 1) 4 and a device under test (also referred to as RAM 2) 5 are mounted. The test board 2 is provided with sockets corresponding to the clock generator 3, the test device 4, and the device under test 5. Wiring L1, L2, and L3 which connect the electrodes corresponding to these sockets are provided. The test substrate 2 has wirings for connecting to the test apparatus 1 and electrodes L4 to L6. The test apparatus 1 and the test device 4 mounted on the test board 2 are connected by the wiring and the electrode L4, and the test apparatus 1 and the device under test 5 mounted on the test board 2 are connected with the wiring. The test apparatus 1 and the clock generator 3 mounted on the test board 2 are connected by the wiring and the electrode L6.

  The device under test 5 is a high-speed memory that performs a high-speed operation such as 1.0 Gbps by performing a DDR operation using a clock signal such as 500 MHz as described above, and is not particularly limited, but conforms to the JTAG standard. It has an interface circuit such as a test (BIST) circuit and a TAP (Test Access Port) for the test circuit. The test device 4 has the same functions and performance as the device under test 5 and includes the same test circuit and interface circuit as described above. Specifically, it is formed using the same semiconductor chip as the device under test 5 and it has been confirmed that the circuit operates normally.

  The test device 4 is, for example, one connected to an external terminal so as to make use of only a circuit portion necessary for generating and supplying a test pattern signal toward the device under test 5 among the same semiconductor chip as the device under test 5 It is. In addition, the test device 4 has the same package and terminal configuration as the device under test 5, and generates and supplies a test pattern toward the device under test 5 by the wiring L 2 provided on the test substrate 2. A necessary circuit portion may be made effective. With such a configuration, it is not necessary for the test device 4 to develop a dedicated semiconductor device toward the device under test 5. Of course, the test device 4 may be one that is uniquely designed and developed and manufactured only for the circuit portion necessary for generating and supplying the test pattern signal as described above of the device under test 5.

  It is confirmed that the test device 4 operates normally by, for example, a development test apparatus. The development test apparatus has high performance, but is limited to a small number of connection terminals. The test device 4 has only a small number of terminals to be measured because only a part of the circuit under test 5 needs to operate, or has only the limited terminals by repeating the same test several times. Otherwise, an operation test is possible. On the other hand, the device under test 5 has a large number of terminals and is mass-produced, and requires a large number of test devices, and is mass-produced for the development test device. In order to make a modification to increase the number of terminals so that an operation test of a high-speed LSI can be performed in a limited time, an enormous cost is required.

  The test device 4 is mounted on a system in which the device under test 5 is mounted in addition to the operation test by the development high-performance test apparatus as described above, and is normally operated on the system. It may be determined that the device operates normally by verifying that it operates normally.

  In the relationship with the test apparatus 1, the device under test 5 has an operating frequency higher than the clock frequency of the clock signal of the test apparatus 1. That is, the test apparatus 1 is in a relationship in which it cannot perform an AC test at the operating frequency in the actual operation of the device under test 5 with its test performance.

  The device under test 5 includes a test (BIST) circuit compliant with the JTAG standard, and has a TAP interface corresponding to the test (BIST) circuit. In this TAP interface, the test data input signal TDI, the test data output TDO, and the test reset signal TRST as a control signal are synchronized with the test clock signal TCK, for example, irrespective of the clock signal in the actual operation in the device under test. Then, a signal such as a test mode selection signal TMS is input and output. Therefore, the test apparatus 1 may have only a clock signal lower than a high operating frequency corresponding to the actual operation of the device under test 5.

  In this embodiment, the test board 2 is mounted with a clock generator 3 for generating a clock signal corresponding to the actual operation of the device under test. The clock generator 3 generates a high-frequency clock signal necessary for the actual operation of the device under test 5. That is, the clock signal generated by the clock generation device 3 is not subject to the clock signal of the test device 1, in other words, it does not require synchronization with the clock signal of the test device 1, and is exclusively covered. A clock signal adapted to the operating frequency of the test device 5 is formed. The clock generation device 3 is attached to, for example, a socket provided on the test board 2 or is fixedly connected to the test board.

  A rough test operation only for the AC test in the test system of this embodiment is as follows: (1) an input circuit unit such as an address of the device under test 5 using the test device 4; (2) test of the device under test (BIST 3) Three test operations, such as the internal circuit section of the circuit, (3) the test (BIST) circuit of the device under test, and the data output circuit section and data input circuit section using the loop wiring provided on the test board It is divided into.

  The test of the input circuit section such as the address of the device under test 5 in (1) is performed in the following procedure. The test apparatus 1 inputs a test signal to the test device 4 through the TAP interface. At the same time, an expected value corresponding to the test signal is input to the device under test 5 through the TAP interface. The test device 4 decodes the test signal to generate a test pattern, receives the clock signals C and Cb supplied from the clock generation device 3, and outputs the test pattern from the data output circuit unit accordingly. . This test pattern signal is supplied to the address input terminal and the control input terminal of the device under test 5 through the wiring L2 formed on the test substrate 1, and is taken into the input circuit of the device under test 5. The test circuit of the device under test 5 compares the input signal input through the input circuit with the expected value input from the test apparatus 1 to obtain a good / bad test result. Then, the test apparatus 1 accesses the test circuit of the device under test 5 and acquires the test result through the TAP interface.

  In the device under test 5 of this embodiment, a clock signal and an address signal and a write data signal are input in synchronization with the signal input operation for high-speed operation. In addition, a clock signal and an output signal synchronized with the clock signal are output for a signal output operation for high-speed operation. The device under test 5 of this embodiment is not particularly limited, but an address signal such as a signal SA, a control signal such as a signal Control, and complementary clock signals K and Kb for capturing the same are input in synchronization. Is done. The complementary clock K is a normal phase clock signal, and Kb is a reverse phase clock signal. The test device 4 outputs an output signal Q and data strobe clocks CQ and CQb synchronized with the output signal Q corresponding to the input circuit section of the device under test 5.

  Therefore, when viewed from the input circuit section of the device under test 5, the test device 4 performs an operation equivalent to a host system or the like that performs memory access. The test device 4 and the device under test 5 use the clock signal generated by the same clock generator 3, and the input circuit section of the device under test 5 synchronizes with the data strobe clock from the test device 4. Then, an operation of fetching the input address signal and control signal is performed. Since this operation is performed by a clock having a frequency corresponding to the actual operation of the device under test, the test device 4 is guaranteed to operate normally. An operation test can be performed as to whether or not the input circuit unit of the device 5 operates normally. That is, the device under test 5 can determine whether or not the input operation is correctly performed by comparing the input signal with the expected value.

  The test result of the input circuit section in the device under test 5 is taken into the test apparatus 1 according to the clock signal of the test apparatus 1 that is irrelevant to the actual operating frequency formed by the clock generation apparatus 3 using the TAP interface. Is.

  The test of the internal circuit section of the device under test 5 in (2) is performed in the following procedure. The test apparatus 1 inputs a test signal to the device under test 5 through the TAP interface. The test circuit decodes the test signal and generates a test pattern to select an internal circuit of the memory, that is, a memory cell, and write and read data. The read signal is compared with an expected value to form a good / bad test result as described above. The test circuit also performs a boundary scan test (BST) and tests the internal logic unit. Then, the test apparatus 1 accesses the test circuit of the device under test 5 and acquires the test result of the internal circuit unit through the TAP interface.

  The test of the data input / output path of the device under test 5 in (3) is performed in the following procedure. The test apparatus 1 inputs a test signal to the device under test 5 through the TAP interface. The test circuit decodes the test signal to generate a test pattern and outputs an output signal from the output circuit. Since this output signal is connected to the input terminal of the input circuit by the wiring L3 of the test board 2 (loop connection), it is taken into the input circuit. The output circuit shown in FIG. 2 outputs the signal Q and the complementary clock signals CQ and CQb in synchronization. Also in the input circuit of the figure, the signal D and the complementary clock signals K and Kb are input in synchronization.

  The output circuit Q outputs the output signal Q and the clock signals CQ and CQb as described above, and these are taken as the input signal D into the input circuit through the wiring L3 of the test board 2. The test circuit compares both data Q and D to make a pass / fail judgment and obtains a test result. The test apparatus 1 accesses the test circuit of the device under test 5 and acquires the test result of the input / output circuit unit through the TAP interface.

  As described above, the device under test 5 is a high-speed memory that performs a high-speed operation such as 1.0 Gbps by performing a DDR operation using a clock signal such as 500 MHz. In order to perform such a high-speed memory AC test in real time, the test apparatus 1 needs to operate with a clock signal such as 1.0 GHz. However, a test apparatus that performs such a high-speed test operation and has a large number of terminals as described above becomes very expensive if developed.

  In the present invention, the clock generator 3 generates a clock signal having a frequency such as 500 MHz and supplies the clock signal to the test device 4 and the device under test 5 through the wiring L1 of the test board 2. The test device 4 receives a clock signal C, Cb such as 500 MHz supplied from the clock generator 3 and outputs an output signal Q and data strobe clocks CQ, CQb synchronized therewith. The test device 4 performs a DDR operation in the same manner as the device under test 5 which is the high-speed memory, and is 1.0 Gbps in synchronization with the leading and trailing edges (both edges) of the data strobe clocks CQ and CQb. A test pattern (output signal Q) is formed, and the test operation (1) can be executed.

  In the test operation (2), the device under test 5 receives the clock signals C and Cb such as 500 MHz supplied from the clock generation device 3 and the test circuit (BIST) responds to the internal operation corresponding to the actual operation. A write operation and a read operation to the memory cell in the circuit can be performed. The test operation (3) is also performed in synchronization with the leading and trailing edges (both edges) of the data strobe clocks CQ and CQb in the device under test 5 in the same manner as the test operation (1). A test pattern (output signal Q) of 0 Gbps is formed and received by its own input circuit, and a test operation with a test pattern of 1.0 Gbps can be executed in the same manner as (1).

  FIG. 2 shows a block diagram of an embodiment of the clock generator 3 of FIG. The power supply circuit REG1 (1.8V) receives the power supply voltage VDD such as + 5V from the test apparatus 1 and forms a first internal voltage such as 1.8V. The power supply circuit REG2 (3.3V) receives the power supply voltage VDD such as + 5V from the test apparatus 1 and forms a second internal voltage such as 3.3V. A direct digital synthesizer (hereinafter referred to as DDS) multiplies a reference clock signal such as 38 MHz formed by an oscillation circuit using a crystal oscillator Xtal by, for example, 11 by an internal PLL circuit to form 418 MHz. The DDS converts waveform data calculated by a digital circuit based on frequency data from the outside (test apparatus 1) into an analog signal by a digital / analog conversion circuit. In addition to making the frequency variable, the output voltage may be variable within the scope of digital claims. As such DDS, those used for digital control measuring instruments, clock generators and the like are used.

  In the output signal of the DDS, output noise peculiar to the DDS is reduced by a low pass filter (hereinafter referred to as LPF). The LPF output signal is supplied to a frequency multiplier (hereinafter referred to as FMUT). For example, the FMUT multiplies the clock signal formed by the DSS by four. A level detection circuit (hereinafter referred to as LDET) is provided for receiving the output signal of the FMUT and confirming whether the clock signal is normally output by detecting the level. The output level changing circuit (hereinafter referred to as OVC) is configured by a multiplier, and the clock signal amplitude based on the analog voltage formed by the digital-to-analog converter circuit (hereinafter referred to as DAC) to the MULT output signal. Is changed.

  The switch circuits SW1 and SW2 selectively transmit the output signal of the OVC to two band pass filters (hereinafter referred to as BPF1 and BPF2) for output. BPF1 is set to a pass band of 475.0 MHz to 512.5 MHz, for example. BPF2 is set to a pass band of 512.5 MHz to 550.0 MHz, for example. The output circuits (hereinafter referred to as RF1 and RF2) are transformer circuits that convert single-ended output signals into differential outputs. RF1 forms complementary clock signals C and Cb (1) to be supplied to the test device 4, for example. RF2 forms complementary clock signals C and Cb (2) to be supplied to the device under test 5, for example.

  The control circuit (hereinafter referred to as FPGA) has an interface circuit with the outside (test apparatus 1) and a digital control circuit. This is a digital control circuit for forming the clock signal based on the digital control signal CDT from the outside (test apparatus 1), and is composed of a field rewritable FPGA (Field Programmable Gate Array). This clock generation device 3 does not generate a single clock signal, but does not perform a dedicated clock generation operation toward the device under test 5, for example, in the range from 475.0 MHz to 550.0 MHz. In this case, a clock signal having an arbitrary voltage level can be formed at an arbitrary frequency. Therefore, the device under test that can be tested by the test board 2 is assumed to operate in the frequency range as described above.

  3 and 4 show waveform diagrams of an embodiment of the test method according to the present invention. FIG. 3 mainly shows the test signal input operation from the test apparatus 1 to the test circuit (BIST) from the test device 1 to the test device 4 and the device under test 5. FIG. 4 mainly shows the operation by the test circuit based on the test signal and the operation for obtaining the test result by the test apparatus.

  In FIG. 3, the power supply voltage VDD / VDDQ (reference voltage as necessary) is supplied from the test apparatus 1, and the clock generation apparatus 3 mounted on the test substrate 2 supplies the test device 4 and the device under test 5 to the test device 4. The clock signals C and Cb such as 500 MHz are supplied. The test apparatus 1 performs a power-on sequence and an internal sequence operation on the test device 4 and the device under test 5 by a control signal to perform a preparatory operation in the memory test mode. The test apparatus 1 synchronizes with the rising edge of the low-frequency clock signal TCK such as about 10 MHz that is asynchronous with the high-frequency clock signals C and Cb such as 500 MHz, and the test device 4 and the device under test 5. Input test signal to.

  For example, in 1 to 6 cycles of TCK, TMS is set to the high level to reset the internal register, and the test signal is taken into each register after 7 cycles of TCK. In 12 to 15 cycles of TCK, a pattern of TDI 0101 is input, and the BIST mode is set in the register IR. After 20 cycles of TCK, the test pattern is set from the TDI. Such 1 to N cycles of TCK are an ALPG pattern set period.

  After N cycles of the TCK, the BIST-CTRL is set to the high level and the test circuit (BIST) is executed. This BIST operation (BIST running) is performed by a memory circuit operation synchronized with the high-speed clock signals C and Cb.

  In FIG. 4, the end of BIST running is detected by BIST-STATUS, and a test result serial output preparation operation is performed. From six cycles of TCK, test result TDO is directed to test apparatus 1 in synchronization with the rising edge of TCK. Is output. This is a pass / fail scanning period.

  As described above, the test apparatus 1 according to the present invention inputs a test signal and takes in a test result between the test device 4 and the device under test 5 by using the clock signal having a low frequency such as about 10 MHz. Therefore, an existing IC tester or the like can be used as it is.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the installed BIST, JTAG, and TPA interface circuits can take various embodiments. In addition to the above JTAG and TPA, the interface circuit for inputting a test signal group and capturing the test result can take various embodiments. The clock generation device may be any device installed near the device under test. The present invention can be widely used as a test system and a test method for a semiconductor device in which a test operation at an actual operation frequency cannot be performed at a clock frequency of the test device.

It is a block diagram which shows one Example of the test system which concerns on this invention. It is a block diagram which shows one Example of the clock generation apparatus 3 of FIG. It is a wave form diagram which shows one Example of the test method which concerns on this invention. It is a wave form diagram which shows one Example of the test method which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Test apparatus, 2 ... Test board, 3 ... Clock generation apparatus, 4 ... Test device, 5 ... Device under test, L1-L3 ... Wiring, L4-L6 ... Electrode and wiring,
REG1, 2 ... Power supply circuit, DDS ... Direct digital synthesizer, LPF ... Low pass filter, FMUT ... Frequency multiplier, LDET ... Level detection circuit, OVC ... Output voltage change circuit, DAC ... Digital / analog converter, SW12... Switch circuit, BPF1, 2. Bandpass filter, RF1, 2. Output circuit, FPGA. Control circuit.

Claims (11)

A test apparatus for outputting a first test signal group and inputting a test result in response to the first test signal group;
A clock generator for generating a first clock signal corresponding to the operation cycle of the device under test in a cycle faster than the first test signal group;
A second test circuit corresponding to the device under test having a first test circuit responsive to the test signal group, and a test device whose circuit operation is normal,
The clock generator supplies the first clock signal to the device under test and the test device,
A first operation in which the test apparatus inputs the first test signal group to the device under test and the test device;
The second test circuit of the test device operates in response to the input first test signal group, supplies a test pattern signal to the device under test corresponding to the first clock signal, and A second operation in which the test device operates with a test pattern signal input corresponding to the first clock signal and generates a test result in the first test circuit;
And a third operation in which the test apparatus inputs the test result of the device under test corresponding to the first test signal group. In claim 1,
The test device and the clock generator are mounted on a test substrate of the device under test or installed in the vicinity of the device under test. In claim 1,
The first test signal group includes a second clock signal output from the test apparatus in synchronization with part or all of the other test signals,
The device under test and the first and second test circuits of the test device have a circuit corresponding to JTAG and a TAP interface,
The test system, wherein the second clock signal is a clock signal used for the TAP interface. In claim 3,
A fourth operation in which the test apparatus inputs a second test signal corresponding to the second clock signal to the device under test;
In the device under test, the first test circuit generates a test pattern signal corresponding to the first clock signal based on the second test signal inputted to the first test circuit, operates an internal circuit, and generates a test result. 5 actions,
A test system further comprising: a sixth operation in which the test apparatus inputs a test result by the test circuit of the device under test in response to the second clock signal. In claim 4,
The test substrate further includes a signal path for connecting the output terminal and the input terminal of the device under test,
A seventh operation in which the test apparatus inputs a third test signal corresponding to the second clock signal to the device under test;
In the device under test, the first test circuit outputs an output signal through the output circuit and the output terminal in response to the first clock signal based on the third test signal input thereto, and passes through the input terminal and the input circuit. An eighth operation for taking the output signal and generating a test result;
A test system further comprising a ninth operation in which the test apparatus inputs a test result signal corresponding to the eighth operation of the device under test in response to the second clock signal. In claim 5,
The test system, wherein the device under test and the test device are synchronous semiconductor integrated circuit devices in which input / output operations are performed in synchronization with both edges of a timing signal corresponding to the first clock signal. A test apparatus for outputting a first test signal group and inputting a test result in response to the first test signal group;
A clock generator for generating a first clock signal corresponding to the operation cycle of the device under test in a cycle faster than the first test signal group;
A test device having a second test circuit corresponding to the device under test having a first test circuit responding to the test signal and having a normal circuit operation;
The clock generation device supplies the first clock signal to the device under test and the test device,
The test apparatus performs a first operation of inputting the first test signal group to the device under test and the test device,
In the test device, a second operation in which the second test circuit operates in response to the input first test signal and supplies a test pattern signal to the device under test corresponding to the first clock signal. And
The device under test operates with a test pattern signal input corresponding to the first clock signal, and performs a third operation for generating a test result in the first test circuit,
A test method in which the test apparatus performs a fourth operation of inputting a test result corresponding to the third operation of the device under test corresponding to the first test signal group. In claim 7,
A test method in which the test device and the clock generation device are mounted on a test substrate of the device under test or installed in the vicinity of the device under test. 8. The first test signal group according to claim 7, wherein the first test signal group includes a second clock signal output from the test apparatus in synchronization with part or all of the other test signals.
The device under test and the first and second test circuits of the test device have a circuit corresponding to JTAG and a TAP interface,
The test method, wherein the second clock signal is a clock signal used for the TAP interface. In claim 9,
The test apparatus performs a fifth operation of inputting a second test signal corresponding to the second clock signal to the device under test,
The device under test generates a test pattern signal corresponding to the first clock signal based on the second test signal input in the first test circuit, operates an internal circuit, and generates a test result. 6 actions,
The test apparatus performs a seventh operation of inputting a test result by the test circuit of the device under test corresponding to the first clock signal. In claim 10,
The test substrate further includes a signal path for connecting the output terminal and the input terminal of the device under test,
The test apparatus performs an eighth operation of inputting a third test signal corresponding to the second clock signal to the device under test,
In the device under test, the first test circuit outputs an output signal through the output circuit and the output terminal in response to the first clock signal based on the third test signal input thereto, and passes through the input terminal and the input circuit. The ninth operation of taking the output signal and generating a test result is performed,
A test method in which the test apparatus performs a tenth operation of inputting a test result signal corresponding to the eighth operation of the device under test corresponding to the first clock signal.

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