JP2004129405A - Method for controlling voltage-type inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for controlling a surge voltage generated from the load end of a voltage-type inverter in the inverter for performing a pulse width modulation calculation of a command value to set an output voltage to a predetermined value. <P>SOLUTION: When a pulse width of a collapsed pulse of the output voltage is narrowed near the peak value of a phase voltage by a carrier oscillator 16a of the voltage-type inverter 2, voltage pattern generating means 21-23, a U-phase PWM control block 24, a V-phase PWM control block 25 and a W-phase PWM control block 26, this pulse width is limited so as to become wider; and further in order to set a change of the output voltage, even in the limited pulse width to the same as a prior art, an operation for turning on during one period of the PWM calculation at an upper arm or a lower arm of the corresponding phase is used in combination. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention basically turns on or off each of the semiconductor switch circuits forming the upper and lower arms of each phase based on a drive signal obtained by performing a PWM operation on each phase voltage command value of each phase. The present invention relates to a method of controlling a voltage-source inverter that converts an input DC voltage into a desired AC voltage and outputs the converted voltage, and more particularly, relates to a surge voltage induced at a load terminal of the voltage-type inverter due to switching of each of the semiconductor switch circuits. The present invention relates to a method of controlling a voltage-source inverter to be reduced.
[0002]
[Prior art]
Semiconductor switch circuits that form the upper and lower arms of each phase of a voltage-source inverter, which use valve devices capable of high-speed switching, such as IGBTs, have become widespread. It is known that a surge voltage is applied to an AC motor or the like as a load of this voltage-source inverter due to a higher carrier frequency in the calculation, and insulation deterioration of windings of the AC motor due to the surge voltage is known. In order to prevent this, it is necessary to reduce the surge voltage (for example, see Non-Patent Document 1).
[0003]
The related art including Non-Patent Document 1 described above and its problems will be described below with reference to FIGS.
[0004]
FIG. 8 is a circuit diagram (principal partial view) showing a voltage source inverter of this type. Reference numeral 1 denotes a voltage source inverter, and reference numeral 5 denotes an AC motor driven by the voltage source inverter 1 at a variable speed. In this voltage source inverter 1, a DC power supply 11 such as a rectified power supply, and an anti-parallel circuit of an IGBT and a diode as a semiconductor switch circuit are formed as upper and lower arms of a U-phase, a V-phase, and a W-phase, respectively. An inverter main circuit 12 having upper and lower arms bridge-connected, a PWM calculator 13 for performing a PWM calculation based on a _U- phase voltage command value v _U ^* and a carrier signal from a carrier oscillator 16; PWM calculator 14 for performing a PWM operation based on phase voltage command value v _V ^* and a carrier signal from carrier oscillator 16, and PWM based on W-phase phase voltage command value v _W ^* and a carrier signal from carrier oscillator 16 a PWM calculator 15 for calculating, PWM calculator 13 to 15 respectively output ^{(PWMu *, PWMv *, PWMw} *) the corresponding upper and lower arms And a gate drive circuit 17 for converting the drive signal to GBT.
[0005]
FIG. 9 is a circuit diagram and a waveform diagram illustrating a surge voltage applied to AC motor 5 as a load of voltage source inverter 1 shown in FIG. In this figure, when the line voltage between the output terminals UV of the voltage source inverter 1 the voltage is Ed of the DC power supply 11 and v _UV, become solid line waveform thick at the output terminal of the voltage source inverter 1, the load end It is known that the waveform of the thin solid line waveform greatly depends on the cable impedance between the voltage source inverter 1 and the AC motor 5 and the rise time of the IGBT. A surge voltage twice as large as the DC voltage Ed is generated.
[0006]
[Non-patent document 1]
The Institute of Electrical Engineers of Japan, Special Committee on Investigation of Semiconductor Power Conversion Systems, “Power Electronics Circuit,” Ohmsha, November 30, 2000, p. 208-210
[0007]
[Problems to be solved by the invention]
FIG. 10 shows the phase relationship between the U-phase phase voltage command value v _U ^* and the V-phase phase voltage command value v _V ^* and the phase voltage command value v _U ^* in the circuit configuration of the voltage source inverter 1 shown in FIG. FIG. 4 is a waveform diagram showing a phase relationship between a line voltage command value v _UV ^* derived from a phase voltage command value v _V ^* and a peak value vicinity and a line voltage of a phase voltage command value hatched in the figure. The PWM calculation near the zero crossing of the command value and the surge voltage generated at the load end based on the calculation result will be described below with reference to FIGS.
[0008]
FIG. 11 shows a U-phase voltage command value v _U ^* (thick solid line) near the peak value, a V-phase phase voltage command value v _V ^* (dashed line), and a triangular carrier signal from the carrier oscillator 16. fc (thin solid line) and the operation result by the PWM calculator 13 based on PWMu ^*, PWMv ^* and the line shows the voltage _{V UV,} wave height of the phase voltage instruction value _v ^{U *} positive U-phase in this view The PWMu ^* obtained by the PWM operation in the vicinity indicates that the pulse width of the drive signal for turning off the semiconductor switch circuit of the upper arm of the U phase is reduced. As a result, as shown in FIG. 12, a pulse-like voltage collapse occurs in the line voltage v _UV, as this was caused by voltage depression, surge voltage across the load based on the fall of the pulse voltage (the above , Twice the DC voltage Ed), the surge voltage at the load end based on the rise of the pulsed voltage (two times the DC voltage Ed as described above) is phase-added, and the voltage collapse of the pulse width is reduced. At times, a surge voltage four times the DC voltage Ed may be generated at the load terminal.
[0009]
FIG. 13 shows a U-phase phase voltage command value v _U ^* (thick solid line) and a V-phase phase voltage command value v _V ^* (dashed line) in which the line voltage command value v _UV ^* is near the zero crossing. PWM calculator 13 according to the operation result PWMu by a triangular carrier signal Fc from the carrier oscillator 16 (thin solid line) ^*, PWMv ^* and line-to-line shows a voltage _{V UV,} in this figure by the PWMu ^* and PWMv ^* the pulse width of the line voltage v _UV at line voltage command value v _UV ^* zero crossing point near indicate that becomes narrower. As a result, a pulse-like voltage is generated in the line voltage v _UV as shown in FIG. 14, due to this voltage, as a surge voltage across the load based on the rise of the pulse voltage (above, DC voltage When the surge voltage at the load end based on the falling edge of the pulsed voltage (as described above, twice as large as the DC voltage Ed) is a pulse voltage having a pulse width that is added in phase, There is a possibility that a surge voltage four times the DC voltage Ed is generated at the load end.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and reduce the surge voltage induced at the load terminal of a voltage type inverter by switching of a semiconductor switch circuit forming the upper and lower arms of each phase to twice or less. It is an object of the present invention to provide a control method of a voltage type inverter which can be performed.
[0011]
[Means for Solving the Problems]
In the control method of the voltage source inverter according to the first invention, the semiconductor switch circuits forming the upper and lower arms of each phase are turned on based on the drive signal obtained by performing the PWM operation on the phase voltage command value of each phase. Or by turning off, a voltage-type inverter that converts an input DC voltage to a desired AC voltage and outputs the AC voltage.
The pulse width of the drive signal for turning off the semiconductor switch circuit of the upper arm or the lower arm obtained by the PWM operation in the vicinity of the positive or negative peak value of the phase voltage command value of each phase is smaller than a predetermined value tw. And a driving signal having a predetermined pulse width T _LIM (tw <T _LIM ) for turning off the semiconductor switch circuit of the upper arm or the lower arm as a new driving signal replacing the driving signal. And a drive signal for turning on the semiconductor switch circuit of the lower arm, and a semiconductor switch circuit for forming the upper and lower arms of each phase based on these new drive signals. By turning on or off, an AC voltage that is substantially equivalent to the AC voltage based on the phase voltage command value on the average value is previously set. The voltage is output from each of the corresponding phases of the voltage type inverter.
[0012]
Further, in the voltage type inverter control method according to a second aspect of the present invention, in the voltage type inverter, in the voltage type inverter, the voltage of each phase near the zero cross point of the line voltage command value of each phase derived from the phase voltage command value of each phase. When the pulse width of the line voltage of each phase generated from the drive signal based on the phase voltage command value of each phase becomes narrower than a predetermined value tw, the line drive signal is replaced with the line drive signal as a new drive signal. A drive signal whose voltage pulse width is a predetermined pulse width T _LIM (tw <T _LIM ) and a drive signal that makes the line voltage zero are generated, and a driving signal for each phase is generated based on these new driving signals. By turning on or off each of the semiconductor switch circuits forming the upper and lower arms, an AC voltage, which is substantially equivalent to the AC voltage based on the phase voltage command value on average, is converted to the voltage type inverter. Are output from the respective phases.
[0013]
According to the present invention, for switching to a pulse width tw or less at which an excessive surge voltage occurs at the load end of the voltage type inverter, the pulse width is changed to the predetermined value T _LIM (tw <T _LIM ), the surge voltage generated at the output terminal of the voltage-type inverter is reduced and the AC voltage based on the phase voltage command value at this time is substantially equivalent to the AC voltage as described later. An AC voltage can be output.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit configuration diagram (main part diagram) showing a first embodiment of a voltage source inverter control method according to the present invention. Components having the same functions as those of the conventional configuration shown in FIG. Is attached.
[0015]
That is, the voltage source inverter 2 shown in FIG. 1 has a function of outputting a synchronization signal of a carrier signal to the conventional carrier oscillator 16 shown in FIG. 8 in addition to the DC power supply 11, the inverter main circuit 12, and the gate drive circuit 17. Includes an added carrier oscillator 16a, voltage pattern generation means 21 to 23, a U-phase PWM control block 24 including a PWM calculator 13, a V-phase PWM control block 25 including a PWM calculator 14, and a PWM calculator 15. And a W-phase PWM control block 26.
[0016]
The voltage source inverter 2, U-phase described with reference to FIG. 11, V-phase, the phase voltage command value of the W-phase ^{_{v U *, v V *,}} v W * respective positive or negative PWM at peak value near If the pulse width tw of the drive signal for turning off the semiconductor switch circuit of the upper arm or the lower arm of the relevant phase obtained by the calculation becomes narrow, a pulse-like voltage depression occurs in any of the line voltages v _UV , v _VW , and v _WU. And a function of preventing a surge voltage four times the DC voltage Ed from being generated at the load terminal due to the voltage depression. Hereinafter, the operation of the voltage source inverter 2 will be described with reference to FIGS.
[0017]
FIG. 2 is a characteristic diagram for explaining the operation of the voltage pattern generating means 21 (22, 23) and the U-phase PWM control block 24 (the V-phase PWM control block 25, the W-phase PWM control block 26). Is divided into voltage patterns 1 to 5 in the order of increasing value near the positive peak value, and similarly, the phase voltage command value is set in the order of decreasing the absolute value near the negative peak value in the order of decreasing absolute value. pattern 6-10 stepwise divided, for example, as a phase voltage command value of a new U-phase v _U ^** when the phase voltage command value v _U ^* is positive peak value near the U-phase, inverter main circuit 12 The pulse width for turning off the U-phase upper arm is such that a value T _LIM (tw <T _LIM ) at which the aforementioned surge voltage does not become excessive is output.
[0018]
The waveform diagram shown in FIG. 3 shows the operation in the voltage pattern 3 shown in FIG. 2. In the drawing, first, in the first PWM calculation cycle, the voltage pattern is selected from the voltage pattern generation means 21 (22, 23). In the U-phase PWM control block 24 (V-phase PWM control block 25, W-phase PWM control block 26), the third register issues a command to select in1 by the signal and the synchronization signal from the carrier oscillator 16a. An arm-on pulse generation signal is output from the selector, and as a result, generation of an excessive surge voltage in this section is prevented.
[0019]
Next, in the second PWM calculation cycle, the U-phase PWM control block 24 (the V-phase PWM control block 25, the W-phase PWM control block 25) uses the selection signal from the voltage pattern generation means 21 (22, 23) and the synchronization signal from the carrier oscillator 16a. In the PWM control block 26), the third register issues a command to select in3, and according to this command, a phase voltage command value that sets the pulse width for turning off the U-phase upper arm to T _LIM is output from the selector via the first register. As a result, generation of an excessive surge voltage in this section is prevented.
[0020]
Next, in the third PWM operation cycle, the U-phase PWM control block 24 (V-phase PWM control block 25, W-phase PWM control block 25) uses the selection signal from the voltage pattern generation means 21 (22, 23) and the synchronization signal from the carrier oscillator 16a. In the PWM control block 26), the third register issues a command to select in1, and this command outputs an upper arm on-pulse generation signal from the selector. As a result, generation of an excessive surge voltage in this section is prevented. You.
[0021]
Next, in the fourth PWM operation cycle, the U-phase PWM control block 24 (the V-phase PWM control block 25, the W-phase PWM control block 25 and the W-phase PWM control block 25) use the selection signal from the voltage pattern generation unit 21 (22, 23) and the synchronization signal from the carrier oscillator 16a. In the PWM control block 26), the third register issues a command to select in3, and according to this command, a phase voltage command value that sets the pulse width for turning off the U-phase upper arm to T _LIM is output from the selector via the first register. As a result, generation of an excessive surge voltage in this section is prevented.
[0022]
Thus, U-phase, V-phase, the phase voltage command value of the W-phase ^{_{v U *, v V *,}} v W * is in each positive or negative peak value near according to the value at that time, for example, FIG. 2 Is determined, and the surge voltage generated at the load 5 end of the voltage source inverter 2 is reduced from four times to less than twice the DC voltage Ed by selecting a voltage pattern every four periods of the PWM operation. While reducing, it is possible to output an AC voltage that is substantially equivalent in average to the AC voltage based on the phase voltage command value at this time.
[0023]
In the region other than the peak value near the above, for example, by outputting a _v ^{U *} as the voltage pattern generating means 21 in _v ^{U **,} the third register in the U-phase PWM control block 24 selects in3, A PWM operation similar to the conventional one is performed.
[0024]
FIG. 4 is a circuit configuration diagram (main part diagram) showing a second embodiment of the control method of the voltage source inverter according to the present invention, and those having the same functions as those of the conventional configuration shown in FIG. Is attached.
[0025]
That is, the voltage source inverter 3 shown in FIG. 4 has a function of outputting a synchronization signal of a carrier signal to the conventional carrier oscillator 16 shown in FIG. 8 in addition to the DC power supply 11, the inverter main circuit 12, and the gate drive circuit 17. Includes an added carrier oscillator 16a, voltage pattern generating means 31 to 33, a U-phase PWM control block 34 including a PWM calculator 13, a V-phase PWM control block 35 including a PWM calculator 14, and a PWM calculator 15. And a W-phase PWM control block 36.
[0026]
The voltage-source inverter 4, U-phase described with reference to FIG. 13, V-phase, the phase voltage command value of the W-phase ^{_{v U *, v V *,}} v W * line voltage command value _{v UV} derived from each ^* , V _VW ^* , v _WU ^{* The} DC voltage is applied to the load terminal due to the narrowing of the pulse width tw of the pulse-shaped line voltage obtained by the PWM calculation of the phase voltage command value near the zero cross point. It has a function of preventing a surge voltage four times the voltage Ed from being generated. The operation of the voltage source inverter 3 will be described below with reference to FIGS.
[0027]
FIG. 5 is a characteristic diagram for explaining the operation of the voltage pattern generating means 31 (32, 33) and the U-phase PWM control block 34 (the V-phase PWM control block 35, the W-phase PWM control block 36). When the command value is near the zero crossing point, it is divided stepwise into voltage patterns 1 to 9 in descending order of the value. For example, when the line voltage command value v _UV ^* is near the positive zero crossing point, a new U-phase as the phase voltage instruction value v _U ^**, value the pulse width for turning on the U-phase upper arm of the inverter main circuit 12 does not become excessive surge voltage described above (i.e., the pulse width of PWMv from the pulse width of the PWMu ^{* *} _v ^{U **)} so as to output, as well, a new U-phase when the line voltage command value _{v UV} ^* negative near zero cross points subtracted value is corresponding to a new PWMu ^* to be _{2T LIM} of As phase voltage command value v _U ^**, pulse width for turning on the U-phase lower arm of the inverter main circuit 12 does not become excessive surge voltage foregoing values (i.e., reduce the pulse width of the PWMu ^* from the pulse width of PWMv ^* value is to output a _v ^{U **)} corresponding to the new PWMu ^* to be _{2T LIM.}
[0028]
The waveform diagram shown in FIG. 6 shows the operation in the voltage pattern 3 shown in FIG. 5. In the diagram, first, in the first PWM operation cycle, the operation is selected from the voltage pattern generation means 31 (32, 33). In the U-phase PWM control block 34 (the V-phase PWM control block 35 and the W-phase PWM control block 36), the fourth register issues a command to select in1 based on the signal and the synchronization signal from the carrier oscillator 16a. For example, the above-mentioned v _U ^** is output from the selector via one register, and as a result, generation of an excessive surge voltage in this section is prevented.
[0029]
Next, in the second PWM operation cycle, the U-phase PWM control block 34 (the V-phase PWM control block 35 and the W-phase PWM control block 35) use the selection signal from the voltage pattern generation means 31 (32, 33) and the synchronization signal from the carrier oscillator 16a. issues a command PWM control block 36) in the fourth register selects in2, via a second register by this command, for example, v _V ^* is outputted from the selector, as a result, the line voltage in this interval is It becomes zero (that is, PWMu ^* and PWMv ^* have the same pulse width at the same timing), and generation of an excessive surge voltage is prevented.
[0030]
Next, in the third PWM operation cycle, the U-phase PWM control block 34 (the V-phase PWM control block 35, the W-phase PWM control block 35) receives a selection signal from the voltage pattern generating means 31 (32, 33) and a synchronization signal from the carrier oscillator 16a. issues a command PWM control block 36) in the fourth register selects the in1, this command via the first register, for example, is output from the above v _U ^** is selector, so that in this section The generation of an excessive surge voltage is prevented.
[0031]
Next, in the fourth PWM calculation cycle, the U-phase PWM control block 34 (the V-phase PWM control block 35, the W-phase PWM control block 35) uses the selection signal from the voltage pattern generation means 31 (32, 33) and the synchronization signal from the carrier oscillator 16a. issues a command PWM control block 36) in the fourth register selects in2, via a second register by this command, for example, v _V ^* is outputted from the selector, as a result, the line voltage in this interval is It becomes zero (that is, PWMu ^* and PWMv ^* have the same pulse width at the same timing), and generation of an excessive surge voltage is prevented.
[0032]
Thus, U-phase, V-phase, the phase voltage command value of the W-phase ^{_{v U *, v V *,}} v W * is in the zero cross point near the line voltage command value derived from each according to the value at that time For example, by determining one of the voltage patterns in FIG. 5 and selecting a voltage pattern every four periods of the PWM operation, the surge voltage generated at the load 5 end of the voltage-source inverter 2 can be reduced by the DC voltage Ed. It is possible to output an AC voltage that is approximately equivalent to the AC voltage based on the phase voltage command value at this time and that is substantially equivalent to the average value, while reducing the frequency from twice to twice or less.
[0033]
In the region other than the vicinity of zero cross point of the above, for example, and outputs the _v ^{U *} as the voltage pattern generating means 31 in _v ^{U **,} by the fourth register in the U-phase PWM control block 34 selects the in1 , A PWM operation similar to the conventional one is performed.
[0034]
FIG. 7 is a circuit configuration diagram (main part diagram) showing a third embodiment of the control method of the voltage source inverter according to the present invention. Components having the same functions as those of the conventional configuration shown in FIG. Is attached.
[0035]
That is, the voltage source inverter 4 shown in FIG. 7 has a function of outputting a synchronization signal of a carrier signal to the conventional carrier oscillator 16 shown in FIG. 8 in addition to the DC power supply 11, the inverter main circuit 12, and the gate drive circuit 17. Includes an added carrier oscillator 16a, voltage pattern generation means 41 to 43, a U-phase PWM control block 44 including a PWM calculator 13, a V-phase PWM control block 45 including a PWM calculator 14, and a PWM calculator 15. And a W-phase PWM control block 46.
[0036]
In this voltage source inverter 4, the voltage pattern generation means 41 (42, 43) has the functions of the above-described voltage pattern generation means 21 (22, 23) and the voltage pattern generation means 31 (32, 33), The PWM control control block 44 has the functions of the above-described U-phase PWM control block 24 and U-phase PWM control block 34, and similarly, the V-phase PWM control control block 45 includes the V-phase PWM control block 25 and the V-phase PWM control. The function of the block 35 is also provided, and the W-phase PWM control block 46 also has the function of the W-phase PWM control block 26 and the function of the W-phase PWM control block 36. Therefore, the description of the operation is omitted.
[0037]
【The invention's effect】
According to the present invention, for the switching that becomes equal to or less than the pulse width at which an excessive surge voltage occurs at the load end of the voltage type inverter, the pulse width is set to a value at which the surge voltage does not become excessive, and switching is performed. Since the surge voltage generated at the output terminal of the voltage-source inverter can be reduced by a factor of two or less, it is possible to make the same handling as the conventional surge voltage.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a characteristic diagram for explaining the operation of FIG. 1. FIG. 3 is a waveform diagram for explaining the operation of FIG. FIG. 5 is a characteristic diagram for explaining the operation of FIG. 4; FIG. 6 is a waveform diagram for explaining the operation of FIG. 4; FIG. 7 is a diagram showing a third embodiment of the present invention. FIG. 8 is a circuit diagram showing a conventional voltage source inverter. FIG. 9 is a circuit diagram and a waveform diagram for explaining a surge voltage applied to a load of the inverter shown in FIG. FIG. 11 is a waveform diagram showing a relationship between a phase voltage command value and a line voltage command value. FIG. 11 is a PWM calculation waveform diagram for explaining the operation of the inverter of FIG. 8; FIG. 12 is a diagram for explaining the operation of the inverter of FIG. 13 is a circuit diagram and a waveform diagram of FIG. 13. FIG. 13 is a PWM calculation for explaining the operation of the inverter of FIG. Shape Figure 14 is a waveform diagram for explaining the operation of the inverter of FIG. 8 EXPLANATION OF REFERENCE NUMERALS
1 to 4: voltage-type inverter, 5: AC motor, 11: DC power supply, 12: inverter main circuit, 13 to 15: PWM calculator, 16, 16a: carrier oscillator, 17: gate drive circuit, 21 to 23, 31 ... 33, 41-43 ... voltage pattern generation means, 24, 34, 44 ... U-phase PWM control block, 25, 35, 45 ... V-phase PWM control block, 26, 36, 46 ... W-phase PWM control block.

Claims (2)

By turning on or off each of the semiconductor switch circuits forming the upper and lower arms of each phase based on a drive signal obtained by performing a PWM operation on each phase voltage command value of each phase, the input DC voltage can be changed to a desired value. In a voltage-type inverter that converts to AC voltage and outputs it,
The pulse width of the drive signal for turning off the semiconductor switch circuit of the upper arm or the lower arm obtained by the PWM operation in the vicinity of the positive or negative peak value of the phase voltage command value of each phase is smaller than a predetermined value tw. And a driving signal having a predetermined pulse width T _LIM (tw <T _LIM ) for turning off the semiconductor switch circuit of the upper arm or the lower arm as a new driving signal replacing the driving signal. And a drive signal for turning on the semiconductor switch circuit of the lower arm, and a semiconductor switch circuit for forming the upper and lower arms of each phase based on these new drive signals. By turning on or off, an AC voltage that is substantially equivalent to the AC voltage based on the phase voltage command value on the average value is previously set. A method of controlling a voltage-source inverter, characterized in that the voltage-source inverter outputs an output from each corresponding phase. By turning on or off each of the semiconductor switch circuits forming the upper and lower arms of each phase based on a drive signal obtained by performing a PWM operation on each phase voltage command value of each phase, the input DC voltage can be changed to a desired value. In a voltage-type inverter that converts to AC voltage and outputs it,
Lines of each phase generated from the drive signals based on the respective two-phase phase voltage command values in the vicinity of the zero crossing point of the line voltage command value of each phase derived from the phase voltage command value of each phase When the pulse width of the line voltage becomes narrower than the predetermined value tw, the pulse width of the line voltage becomes a predetermined pulse width T _LIM (tw <T _LIM ) as a new driving signal instead of the driving signal. By generating a drive signal and a drive signal for reducing the line voltage to zero, and turning on or off each of the semiconductor switch circuits forming the upper and lower arms of each phase based on these new drive signals, A method for controlling a voltage-source inverter, comprising outputting an AC voltage, which is substantially equivalent to the average value of the AC voltage based on a phase voltage command value, from each corresponding phase of the voltage-type inverter.

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