JP2004128280A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor in which high reliability is provided by preventing a dielectric film from being electrostatically destroyed by a plasma when forming a contact hole, and to provide a manufacturing method thereof. <P>SOLUTION: Until forming upper electrode wiring and a lower electrode wiring, a first conductive film 5 which becomes an upper electrode and a lower electrode 3 are electrically short-circuited. As a result, even when a contact hole 6a reaches the first conductive film 5 faster than a contact hole 6b, since the first conductive film 5 which becomes the upper electrode and the lower electrode 3 are electrically short-circuited, they are kept in the same potential. Therefore, since a current which flows from the first conductive film 5 which becomes the upper electrode to the lower electrode 3 via a dielectric film 4 is reduced, the electrostatic destruction of the dielectric film 4 is prevented and the semiconductor device having the reliable capacitor is manufactured. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a capacitor and a method for manufacturing the same.
[0002]
[Prior art]
In an analog circuit such as a bipolar integrated circuit or a BiCMOS integrated circuit, a capacitance element is indispensable. As one of the capacitance elements, there is an MIS (Metal Insulator Semiconductor) type capacitance element (for example, see Patent Document 1).
[0003]
As a conventional method for manufacturing a capacitor, for example, a method for manufacturing an MIS-type capacitor will be described with reference to the drawings.
[0004]
First, as shown in FIG. 11A, an element isolation insulating film 102 for element isolation is formed on a p-type semiconductor substrate 101 by, for example, selective oxidation (LOCOS: Local Oxidation of Silicon). The whole is thermally oxidized to form a buffer film 109 made of silicon oxide.
[0005]
Next, as shown in FIG. 11B, an n-type impurity is introduced into the semiconductor substrate 101 by photolithography and ion implantation to form a lower electrode 103 made of a high-concentration n-type semiconductor layer.
[0006]
Next, as shown in FIG. 12C, after removing the buffer film 109, silicon nitride is deposited on the entire surface of the semiconductor substrate 101 by, for example, a CVD (Chemical Vapor Deposition) method, and silicon nitride is formed by photolithography and dry etching. Is patterned so as to remain in the capacitor formation region, and a dielectric film 104 is formed.
[0007]
Next, as shown in FIG. 12D, for example, polycrystalline silicon doped with phosphorus at a high concentration is deposited on the entire surface of the semiconductor substrate 101, and the polycrystalline silicon is patterned by, for example, photolithography and dry etching. Then, the upper electrode 105 of the capacitor is formed.
[0008]
Next, as shown in FIG. 13E, an interlayer insulating film 106 is formed by depositing silicon oxide on the entire surface of the semiconductor substrate 101 by, for example, a CVD method and smoothing the deposited silicon oxide by CMP (Chemical Mechanical Polishing). Subsequently, a part of the interlayer insulating film 106 is removed by photolithography and dry etching to form contact holes 106a and 106b for the upper electrode and the lower electrode.
[0009]
Next, as shown in FIG. 13F, a conductive film is buried in each of the contact holes 106a and 106b to form an upper electrode connection plug 107a in the contact hole 106a, and a lower electrode connection plug 107b is formed in the contact hole 106b. .
Subsequently, an upper electrode wiring 108a connected to the upper electrode connecting plug 107a and a lower electrode wiring 108b connected to the lower electrode connecting plug 107b are formed. In the subsequent steps, an upper wiring and a passivation film are further formed, but are not shown.
[0010]
[Patent Document 1]
JP-A-6-338588
[Problems to be solved by the invention]
Conventionally, in the step shown in FIG. 13E, since the interlayer insulating film 106 is smoothed, the lower electrode is compared with the film thickness of the interlayer insulating film 106 on the upper electrode 105 by the thickness of the upper electrode 105. The film thickness of the interlayer insulating film 106 on 103 is larger.
[0012]
Due to the difference in the thickness of the interlayer insulating film 106, when forming the contact holes 106a and 106b, the contact hole 106a reaches the upper electrode 105 before the contact hole 106b reaches the lower electrode 103.
[0013]
Therefore, when the contact holes 106a and 106b are formed by dry etching, a potential difference occurs between the upper electrode 105 and the lower electrode 103 due to plasma charge during the etching. As a result, a large current flows through the dielectric film 104 between the upper electrode 105 and the lower electrode 103, and the so-called plasma induced damage (PID) lowers the reliability of the capacitor and reduces the leakage current. This has led to an increase and a decrease in yield.
[0014]
On the other hand, it is necessary to reduce the thickness of the dielectric film 104 in order to respond to an increase in the capacitance of the capacitor. However, there is a limit to the reduction in the thickness of the dielectric film 104 due to the influence of plasma irradiation damage. In particular, in a high-density plasma etching apparatus used in the Sub-half-μm generation or later, plasma irradiation damage at the time of forming a contact hole is large, and the reliability of a capacitive element is a problem.
[0015]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a highly reliable capacitive element that prevents electrostatic breakdown of a dielectric film due to plasma when forming a contact hole. An object of the present invention is to provide an apparatus and a method of manufacturing the same.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first electrode on a substrate, and a step of forming a dielectric film on the first electrode, the dielectric film exposing a part of the first electrode. Forming, forming a first conductive film on the dielectric film and the exposed first electrode so as to be connected to the first electrode, and forming an interlayer insulating film on the first conductive film Forming a plurality of contact holes exposing the first conductive film in the interlayer insulating film by dry etching using plasma; embedding a second conductive film in the contact holes; Removing a film and part of the first conductive film, and electrically insulating the first conductive film on the dielectric film from the first electrode to form a second electrode.
[0017]
In the above-described method for manufacturing a semiconductor device according to the present invention, the first conductive film and the first electrode on the dielectric film serving as the second electrode are electrically connected until the step of embedding the second conductive film. As a result, when a plurality of contact holes exposing the first conductive film are formed in the interlayer insulating film by dry etching using plasma, even if the first conductive film is charged by the plasma, the first conductive film and the first conductive film may be charged. One electrode is kept at the same potential. Therefore, the current flowing from the first conductive film to the first electrode via the dielectric film is reduced.
[0018]
Further, in order to achieve the above object, a semiconductor device according to the present invention includes a first electrode, a dielectric film formed on the first electrode by exposing a part of the first electrode, and a dielectric film formed on the first electrode. A body film and a conductive film formed on the exposed first electrode, and the dielectric film on the dielectric film electrically insulated from the first electrode due to a partial defect of the conductive film. A second electrode is formed from the conductive film, and the capacitor has a capacitor element utilizing electric capacitance between the first electrode and the second electrode.
[0019]
In the above-described semiconductor device of the present invention, the conductive film is formed on the dielectric film and the exposed first electrode. Then, due to partial loss of the conductive film, a second electrode is formed by the conductive film on the dielectric film that is electrically insulated from the first electrode, and an electric capacitance between the first electrode and the second electrode is formed. Are formed.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same of the present invention will be described with reference to the drawings. The semiconductor device according to the present embodiment is a semiconductor device having a capacitor.
[0021]
First Embodiment FIG. 1 is a sectional view of a semiconductor device according to the present embodiment. Although not shown, active elements such as transistors are formed in other regions. FIG. 2 is a plan view showing the arrangement of the lower electrode 3, the dielectric film 4, and the first conductive films 5a and 5b. FIG. 1 corresponds to a cross-sectional view taken along line AA ′ of FIG.
[0022]
As shown in FIG. 1, an element isolation insulating film 2 made of silicon oxide for element isolation is formed on a semiconductor substrate 1 made of p-type silicon. On the semiconductor substrate 1 in the active region defined by the element isolation insulating film 2, a lower electrode (first electrode) 3 of a capacitor composed of a high-concentration n-type semiconductor layer is formed.
[0023]
On the lower electrode 3, a dielectric film 4 of a capacitive element made of, for example, silicon nitride is formed so as to expose a part of the lower electrode 3. The thickness of the dielectric film 4 is, for example, about 30 nm.
[0024]
On the dielectric film 4 and the exposed lower electrode 3, for example, first conductive films 5a and 5b made of polycrystalline silicon into which an n-type impurity is introduced at a high concentration are formed. The first conductive film 5a on the dielectric film 4 constitutes an upper electrode (second electrode) of the capacitor, and is insulated from the first conductive film 5b.
[0025]
An interlayer insulating film 6 made of silicon oxide or the like is formed on the entire surface covering the first conductive films 5a and 5b. The thickness of the interlayer insulating film 6 is, for example, about 1.2 μm. An insulating hole C for separating and electrically insulating the first conductive films 5a and 5b is formed in the interlayer insulating film 6. The insulating hole C is provided in a region where the dielectric film 4 is formed.
[0026]
The second conductive films 7a and 7b are formed by burying the interlayer insulating film 6. The second conductive film 7a is connected to the conductive film 5a serving as an upper electrode, and serves as an upper electrode connection plug. A plurality of upper electrode connection plugs made of the second conductive film 7a are provided to reduce resistance. The second conductive film 7b is connected to the lower electrode 3 via the first conductive film 5b and serves as a lower electrode connection plug. The second conductive films 7a and 7b are formed, for example, by forming tungsten on a stacked film of Ti and TiN.
[0027]
On the interlayer insulating film 6, an upper electrode wiring 8a connected to the second conductive film 7a and a lower electrode wiring 8b connected to the second conductive film 7b are formed. Each of the electrode wirings 8a and 8b is formed of a laminated film of, for example, a barrier metal containing titanium and aluminum or an aluminum alloy.
[0028]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
[0029]
First, as shown in FIG. 3A, an element isolation insulating film 2 for element isolation is formed on a semiconductor substrate 1 made of p-type silicon, for example, by selective oxidation (LOCOS: Local Oxidation of Silicon). . Subsequently, for example, the entire substrate is thermally oxidized to form a buffer film 9 made of silicon oxide. The p-type semiconductor substrate 1 contains, for example, about 1 × 10 ¹⁵ / cm ^{3 of} boron as a p-type impurity. The element isolation insulating film 2 is formed with a thickness of, for example, about 400 nm.
[0030]
Next, as shown in FIG. 3 (b), an n-type impurity is introduced into the semiconductor substrate 1 in the active region defined by the element isolation insulating film 2 by photolithography and ion implantation, and a high-concentration n-type A lower electrode 3 made of a semiconductor layer is formed. For example, phosphorus is ion-implanted as an n-type impurity at an implantation energy of 70 keV and a dose of 5 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ . Preferably, the dose is 5 × 10 ^{15 to} 7 × 10 ¹⁵ / cm ³ .
[0031]
Next, as shown in FIG. 4C, for example, the entire substrate is immersed in a hydrofluoric acid solution to remove the buffer film 9. Subsequently, for example, silicon nitride is deposited on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method, and patterning is performed by photolithography and dry etching so that the silicon nitride is left in the capacity formation region, thereby forming the dielectric film 4. I do. At this time, the silicon nitride is patterned so that the surface of the lower electrode 3 in the extraction region is exposed. The thickness of the dielectric film 4 is, for example, about 30 nm.
[0032]
Next, as shown in FIG. 4D, for example, polycrystalline silicon doped with phosphorus of an n-type impurity at a high concentration is deposited on the entire surface of the semiconductor substrate 1 and, for example, polycrystalline by photolithography and dry etching. The silicon is patterned to form a first conductive film 5 serving as an upper electrode of the capacitor. Polycrystalline silicon is deposited, for example, to a thickness of about 200 nm. As shown in the plan view of FIG. 7, the first conductive film 5 is formed by patterning so as to cover the dielectric film 4 and the exposed lower electrode 3, thereby forming the first conductive film 5 serving as an upper electrode. And the lower electrode 3 are electrically short-circuited.
[0033]
Next, as shown in FIG. 5E, silicon oxide is deposited on the entire surface of the semiconductor substrate 1 to a thickness of about 1.2 μm by, for example, a CVD method, and is smoothed by CMP (Chemical Mechanical Polishing) to form an interlayer insulating film 6. Form.
[0034]
Next, as shown in FIG. 5F, a part of the interlayer insulating film 6 is removed by photolithography and dry etching to form contact holes 6a and 6b for the upper electrode and the lower electrode. The contact hole 6b is formed so as to expose the first conductive film 5 formed in a region where the lower electrode 3 is exposed. The diameter of the contact holes 6a and 6b is set to 1.2 μm or less, preferably about 0.4 μm, in consideration of the burying property of the conductive film later.
[0035]
Here, dry etching refers to the chemical effect of chemically active molecules (called radicals) decomposed and generated by plasma, and the active molecules and ions due to the electric field generated by the space charge formed by ions having a large mass and slow movement. Is a method of etching due to the physical effect of accelerating in the vertical direction of the substrate. That is, dry etching is a general term for etching using plasma including RIE (Reactive Ion Etching) and the like.
[0036]
Next, as shown in FIG. 6G, the second conductive films 7a and 7b are buried in the contact holes 6a and 6b. For example, about 30 nm of titanium and about 70 nm of titanium nitride are sequentially deposited by sputtering, and then, for example, about 600 nm of tungsten is deposited by, for example, a CVD method. Etch back in order. As a result, the unnecessary second conductive film deposited on portions other than the contact holes 6a and 6b of the interlayer insulating film 6 is removed, and the second conductive films 7a and 7b remain only in the contact holes 6a and 6b. The second conductive film 7a embedded in the contact hole 6a becomes an upper electrode connection plug, and the second conductive film 7b embedded in the contact hole 6b becomes a lower electrode connection plug.
[0037]
Next, as shown in FIG. 6H, the upper electrode wiring 8a connected to the second conductive film 7a serving as the upper electrode connecting plug, and the lower electrode wiring connected to the second conductive film 7b serving as the lower electrode connecting plug. 8b is formed. For example, a barrier metal containing titanium is deposited to a thickness of about 100 nm and aluminum or an aluminum alloy is deposited to a thickness of about 500 nm on the entire surface of the interlayer insulating film 6 and the second conductive films 7a and 7b by a sputtering method. It is formed by patterning by dry etching.
[0038]
Next, for example, by photolithography and dry etching, the interlayer insulating film 6 and a part of the first conductive film 5 are sequentially removed to form an insulating hole C (see FIG. 1). The electrically insulated first conductive film 5a is used as an upper electrode. For example, as shown in FIG. 7, it is preferable to form an insulating opening C on the dielectric film 4 near the boundary between the lower electrode 3 and the dielectric film 4.
[0039]
In the subsequent steps, an upper layer wiring and a passivation film are further formed, but are not shown. As described above, the semiconductor device having the capacitor according to the present embodiment is manufactured.
[0040]
In the method for manufacturing a semiconductor device according to the present embodiment, the first conductive film 5 serving as the upper electrode and the lower electrode 3 are electrically short-circuited until the upper electrode wiring 8a and the lower electrode wiring 8b are formed. As a result, in the step shown in FIG. 5F, even if the contact hole 6a reaches the first conductive film 5 before the contact hole 6b, the first conductive film 5 serving as an upper electrode and the lower electrode 3 Are electrically short-circuited and kept at the same potential.
Accordingly, the current flowing from the first conductive film 5 serving as the upper electrode to the lower electrode 3 via the dielectric film 4 is reduced, so that the electrostatic breakdown of the dielectric film 4 can be prevented, and the reliability can be improved. A semiconductor device having a certain capacitance element can be manufactured.
[0041]
As described above, since the plasma irradiation damage of the dielectric film 4 due to the formation of the contact holes 6a and 6b by dry etching using plasma can be prevented, the thickness of the dielectric film 4 can be reduced. Thus, a semiconductor device having a high-capacitance capacitive element can be manufactured.
[0042]
Further, in the present embodiment, a region for forming an insulating hole C for separating and insulating the first conductive films 5a and 5b is provided on the dielectric film 4, so that the semiconductor substrate 1 is damaged by plasma irradiation. Not even. Further, the first conductive film 5 can be removed with a high etching selectivity with respect to the dielectric film 4.
[0043]
In the present embodiment, the lower electrode connection plug formed by the second conductive film 7b is provided immediately above the region of the lower electrode 3 exposed from the dielectric film 4, so that the lower electrode connection plug and the lower electrode 3 It is possible to reduce an increase in resistance due to the first conductive film 5b remaining between them.
[0044]
Second embodiment FIG. 8 is a sectional view of a semiconductor device according to the second embodiment . Although not shown, active elements such as transistors are formed in other regions. FIG. 9 is a plan view showing the arrangement of the lower electrode 3, the dielectric film 4, and the first conductive films 5a and 5b. FIG. 8 corresponds to a cross-sectional view taken along line AA ′ of FIG.
[0045]
The cross section of the semiconductor device having the capacitive element according to the present embodiment is similar to that of the first embodiment, but the planar shapes of the first conductive films 5a and 5b are different. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0046]
As shown in FIG. 9, in the present embodiment, the first conductive films 5a and 5b extending from the dielectric film 4 to the lower electrode 3 near the region where the insulating hole C is formed in the interlayer insulating film 6 are formed. The line width is formed so as to be smaller than other regions.
[0047]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG.
[0048]
First, as in the first embodiment, as shown in FIGS. 3A to 4C, the lower electrode 3 and the dielectric film 4 are formed.
[0049]
Then, in the step of forming the first conductive film 5 serving as the upper electrode shown in FIG. 4D, as shown in FIG. 10, the line width of the portion 5c which is to be lost due to the formation of the insulating hole C later becomes smaller. A small first conductive film 5 is formed. It is preferable that the portion 5 c having the small line width is formed on the dielectric film 4.
[0050]
Thereafter, in the same manner as in the first embodiment, through the steps shown in FIGS. 5E to 6H, the second conductive film serving as the interlayer insulating film 6, the contact holes 6a and 6b, and the electrode connection plug 7a and 7b and electrode wirings 8a and 8b are formed.
[0051]
Next, for example, by photolithography and dry etching, the portion 5c of the interlayer insulating film 6 and the first conductive film 5 where the line width is small is sequentially removed to form an insulating hole C (see FIG. 8). Thus, an upper electrode made of the first conductive film 5a electrically insulated from the lower electrode 3 is formed. In this step, as shown in FIG. 10, an insulating opening C is formed so as to remove the conductive film 5 in the portion 5c having a small line width.
[0052]
In the subsequent steps, an upper layer wiring and a passivation film are further formed, but are not shown. As described above, the semiconductor device having the capacitor according to the present embodiment is manufactured.
[0053]
In the method for manufacturing a semiconductor device according to the present embodiment, the first conductive film 5 serving as the upper electrode and the lower electrode 3 are electrically short-circuited until the upper electrode wiring 8a and the lower electrode wiring 8b are formed. As a result, in the step shown in FIG. 5F, even if the contact hole 6a reaches the first conductive film 5 before the contact hole 6b, the first conductive film 5 serving as an upper electrode and the lower electrode 3 Are electrically short-circuited and kept at the same potential.
Accordingly, the current flowing from the first conductive film 5 serving as the upper electrode to the lower electrode 3 via the dielectric film 4 is reduced, so that the electrostatic breakdown of the dielectric film 4 can be prevented, and the reliability can be improved. A semiconductor device having a certain capacitance element can be manufactured.
Further, a portion 5c having a small line width is provided in the first conductive film 5, and the first conductive film 5a, 5b is insulated by removing the portion 5c of the first conductive film. Therefore, the area of a region removed by dry etching when insulating the first conductive films 5a and 5b is reduced. As a result, it is considered that plasma irradiation damage due to dry etching when insulating the first conductive films 5a and 5b can be suppressed as compared with the first embodiment.
[0054]
As described above, since the plasma irradiation damage of the dielectric film 4 due to the formation of the contact holes 6a and 6b by dry etching using plasma can be prevented, the thickness of the dielectric film 4 can be reduced. Thus, a semiconductor device having a high-capacitance capacitive element can be manufactured.
[0055]
Further, by providing the portion 5c to be removed for insulatingly separating the first conductive films 5a and 5b on the dielectric film 4, the semiconductor substrate 1 is not damaged by plasma irradiation. Further, the portion 5c of the first conductive film 5 can be removed at a high etching selectivity with respect to the dielectric film 4.
[0056]
Further, as in the first embodiment, the region for forming the lower electrode connection plug formed by the second conductive film 7b is provided immediately above the region of the lower electrode 3 exposed from the dielectric film 4, so that the lower electrode An increase in resistance due to the first conductive film 5b remaining between the connection plug and the lower electrode 3 can be reduced.
[0057]
The present invention is not limited to the description of the above embodiment.
In the present embodiment, the MIS type capacitance element has been described. However, the present invention is not limited to this, and the present invention is also applicable to a MOS (Metal Oxide Semiconductor) type capacitance element, a MIM (Metal Insulator Metal), or the like. That is, another dielectric film such as a silicon oxide film may be used as the dielectric film 4. Further, an example in which polycrystalline silicon is used as the first conductive film 5 serving as the upper electrode has been described. However, the present invention is not limited to this, and a silicide film or a metal film can be used.
[0058]
Similarly, in the present embodiment, an example in which a lower electrode made of a semiconductor layer is formed on a substrate has been described. However, a lower electrode is formed by forming a polycrystalline silicon or metal film on an interlayer insulating film, and The present invention is also applicable to a capacitor having a dielectric film and an upper electrode formed thereon.
[0059]
Also, an example in which the interlayer insulating film 6 is smoothed by CMP has been described. However, the present invention is not limited to this example. It may be.
[0060]
The second conductive films 7a and 7b serving as electrode connection plugs are not limited to a stacked film of Ti, TiN, and W, and may be formed by, for example, various combinations of W, WSi, TiN, and Ti. Similarly, the material of the electrode wires 8a and 8b is not particularly limited.
In addition, various changes can be made without departing from the spirit of the present invention.
[0061]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the manufacturing method of the semiconductor device of this invention, the dielectric breakdown of the dielectric film by the plasma at the time of forming a contact hole can be prevented, and the semiconductor device having a highly reliable capacitive element can be manufactured. Can be.
Further, according to the semiconductor device of the present invention, electrostatic breakdown of a dielectric film forming a capacitor is prevented, and a semiconductor device having a highly reliable capacitor can be realized. In addition, the thickness of the dielectric film of the capacitor can be reduced, and high capacitance can be realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device having a capacitance element according to a first embodiment.
FIG. 2 is a plan view showing an arrangement of a lower electrode, a dielectric film, and a first conductive film shown in FIG.
FIG. 3 is a process cross-sectional view until a lower electrode is formed in the manufacture of the semiconductor device according to the first embodiment.
FIG. 4 is a process cross-sectional view up to the formation of a first conductive film serving as an upper electrode in the manufacture of the semiconductor device according to the first embodiment.
FIG. 5 is a process cross-sectional view until a contact hole is formed in an interlayer insulating film in the manufacture of the semiconductor device according to the first embodiment.
FIG. 6 is a process cross-sectional view up to formation of an electrode wiring in the manufacture of the semiconductor device according to the first embodiment.
FIG. 7 is a plan view for explaining a step of forming an insulating hole in an interlayer insulating film in the manufacture of the semiconductor device according to the first embodiment.
FIG. 8 is a sectional view of a semiconductor device having a capacitive element according to a second embodiment.
FIG. 9 is a plan view showing an arrangement of a lower electrode, a dielectric film, and a first conductive film shown in FIG.
FIG. 10 is a plan view for explaining a step of forming an insulating hole in an interlayer insulating film in the manufacture of the semiconductor device according to the second embodiment.
FIG. 11 is a process cross-sectional view until a lower electrode is formed in the manufacture of a conventional capacitive element.
FIG. 12 is a process cross-sectional view up to formation of an upper electrode in the manufacture of a conventional capacitive element.
FIG. 13 is a process cross-sectional view up to formation of an electrode wiring in the manufacture of a conventional capacitive element.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Lower electrode, 4 ... Dielectric film, 5, 5a, 5b ... 1st conductive film, 6 ... Interlayer insulating film, 6a, 6b ... Contact hole, 7a, 7b ... second conductive film, 8a ... upper electrode wiring, 8b ... lower electrode wiring, 9 ... buffer film, 101 ... semiconductor substrate, 102 ... element isolation insulating film, 103 ... lower electrode, 104 ... dielectric film, 105 ... upper electrode , 106a, 106b contact hole, 107a upper electrode connection plug, 107b lower electrode connection plug, 108a upper electrode wiring, 108b lower electrode wiring, 109 buffer film, C insulating hole.

Claims (8)

Forming a first electrode on the substrate;
Forming a dielectric film exposing a part of the first electrode on the first electrode;
Forming a first conductive film on the dielectric film and the exposed first electrode so as to be connected to the first electrode;
Forming an interlayer insulating film on the first conductive film;
Forming a plurality of contact holes exposing the first conductive film in the interlayer insulating film by dry etching using plasma;
Embedding a second conductive film in the contact hole;
Removing a part of the interlayer insulating film and the first conductive film, and electrically insulating the first conductive film on the dielectric film from the first electrode to form a second electrode; A method of manufacturing a semiconductor device having: The method of manufacturing a semiconductor device according to claim 1, further comprising: after the step of forming the interlayer insulating film, and before the step of forming the contact hole, smoothing the interlayer insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the first conductive film, a portion where the first conductive film is to be removed later has a smaller width than other portions. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of removing a part of the interlayer insulating film and the first conductive film, a part of the interlayer insulating film and the first conductive film on the dielectric film are removed. 3. Method. Forming a plurality of contact holes exposing the first conductive film, the plurality of contacts exposing the first conductive film in a region where the dielectric film is formed and a region where the first electrode is exposed; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the holes are formed. A first electrode;
A dielectric film formed on the first electrode by exposing a part of the first electrode;
A conductive film formed on the dielectric film and the exposed first electrode,
Due to the partial defect of the conductive film, a second electrode is formed by the conductive film on the dielectric film that is electrically insulated from the first electrode,
A semiconductor device having a capacitance element utilizing electric capacitance between the first electrode and the second electrode. The semiconductor device according to claim 6, wherein the conductive film is formed to have a smaller width in the vicinity of the defective portion than in other regions. An interlayer insulating film formed on the dielectric film and the conductive film,
7. The semiconductor device according to claim 6, further comprising: a connection electrode formed to be embedded in said interlayer insulating film and electrically connected to said second electrode and said first electrode.

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