JP2000323482A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce break and deterioration of control electrode parts by reducing the quantity of charges remaining on a metal film to prevent break and deterioration of an insulation layer due to the charges flowing to the control electrodes. SOLUTION: The thickness of hard mask film 18 is pref. 150 to 300 nm for adequately etching a metal film. If the thickness of the hard mask film 18 is less than 150 nm, its function is not displayed as a mask material in etching the metal film 16, i.e., it is too thin as a mask material with taking account of the film loss by etching. If the hard mask 18 is thicker than 300 nm, break and deterioration become remarkable due to the increase of the quantity of charges during etching. Thus, this range of the film is preferable and a film thickness range of 180 to 230 nm is more preferable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a metal wiring is formed on a metal-insulator-semiconductor (MIS) semiconductor device having a control electrode. .

[0002]

2. Description of the Related Art When forming metal wiring and the like of a semiconductor integrated circuit, plasma etching is widely and generally employed. For example, when plasma etching an aluminum film (Al film) or an aluminum alloy film (Al alloy film),
In general, a gas containing Cl atoms, such as Cl ₂ , BCl ₃ , or CCl ₄ , is used as an etching gas. In plasma etching of a metal film, a photoresist is used as a mask material, and a Ti-based film such as a TiN film may be formed as an antireflection film between the metal film and the photoresist film.

[0003]

However, when manufacturing a semiconductor integrated circuit having a metal-insulator-semiconductor type semiconductor device having a control electrode on a surface layer of a semiconductor substrate, the control electrode portion of the semiconductor device is not etched. A phenomenon such as destruction or deterioration such as a decrease in withstand voltage may be observed.

In order to avoid such a phenomenon, countermeasures have been taken by changing an etching condition or an etching apparatus. For this reason,
The etching shape and the process margin could not always be improved to a satisfactory state. Therefore, further improvement is required for further miniaturization in the future.

An object of the present invention has been made in view of such circumstances, and when forming a metal wiring on a semiconductor device having a control electrode, the destruction and deterioration of the control electrode portion can be reduced. Another object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006]

Means for Solving the Problems The inventor made various studies to achieve the above object. M by etching
The breakdown of the OS semiconductor device is caused by the breakdown and deterioration of the silicon oxide film sandwiched between the control electrode and the semiconductor substrate by the discharge. The inventor paid attention to charging (charge-up) of the control electrode when forming the metal film. This is because a high electric field may be applied to the silicon oxide film (gate insulating film) by charging the control electrode during etching.

In order to reduce the charging of the control electrode during etching, there are a method of reconsidering the etching conditions, a method of modifying the etching apparatus, and the like. However, many of these methods have been discussed. Therefore, the inventors have further studied whether there is a method for reducing the charge amount itself. As a result, the present invention has the following configuration.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device for forming a metal wiring of a predetermined pattern connected to a control electrode on an insulating layer formed on a substrate so as to have conductivity. (1) a first step of forming a metal film, and (2) a film thickness of 150 nm to 300 nm,
A second step of forming a hard mask made of a silicon-based inorganic insulating film on the metal film having a predetermined pattern, and (3) etching the metal film using the hard mask with an etching gas to form a metal having a predetermined pattern. A third step of forming a wiring.

Thus, during the third step, the amount of charge remaining on the metal film is reduced, thereby preventing the breakdown and deterioration of the insulating layer caused by the charge flowing into the control electrode. I have.

As described above, a hard mask is used instead of a photoresist as a mask material used when forming a wiring layer having a conductive wire path between the control electrode and the control electrode. When a hard mask is employed, the initial thickness of the mask material required for etching the metal film can be reduced. For this reason, the volume of the mask material can be reduced, and the portion that captures electric charge during etching is reduced. Therefore, the amount of charge on the mask material can be reduced, and the voltage applied between the control electrode and the substrate can be reduced.

The inventor has found that a preferable range of the thickness of the hard mask is in a range of 150 nm to 300 nm in order to reliably perform the etching of the metal wiring while utilizing the above effects. . Further, the preferable range of the thickness of the hard mask in which the above-mentioned effects are more remarkably obtained is
It was found to be in the range from 180 nm to 230 nm.

As a result of further detailed studies, the inventor has found that
It has been found that the present invention can be applied as follows.

In the method of manufacturing a semiconductor device according to the present invention, when a silicon-based inorganic film such as silicon oxide is used as the material of the hard mask, the insulating material for insulating the wiring even after the mask material forms the metal wiring. Since it becomes a part of the film, there is no need to remove the hard mask. For example, as a silicon-based inorganic film, SiO ₂ , SiN, SiOF and Si
ON may be included.

In the method of manufacturing a semiconductor device according to the present invention, an Al film and an Al alloy film can be applied as the metal film, and further, a tungsten film and a copper film can be applied.

In the method of manufacturing a semiconductor device according to the present invention, Cl
It is preferable to etch the metal film with an etching gas containing

The method for manufacturing a semiconductor device according to the present invention may include a step of providing a barrier metal film in contact with the metal film. A step of etching the barrier metal film using a hard mask can be provided. In addition, a step of providing an antireflection film on the metal film before forming the hard mask can be provided. A step of etching the antireflection film using a hard mask can be provided.

As described above, since at least one of the antireflection film and the barrier metal layer can be etched using the same mask as the metal film, the manufacturing process is simplified.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. Where possible, the same parts are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1A is a process sectional view of a semiconductor device manufactured on a substrate by applying the method of manufacturing a semiconductor device according to the embodiment of the present invention, and FIG. (A)
FIG. 14 is a plan view corresponding to the process cross-sectional view shown in FIG. FIG.
(A) corresponds to the II section of FIG. 1 (b). Less than,
A P-type silicon substrate 2 is used as a substrate, and a metal-oxide-semiconductor type (hereinafter referred to as “M”) is used as a MIS type semiconductor device.
The case where a transistor is described) will be described.

Referring to FIGS. 1 (a) and 1 (b),
An element isolation film 4 is formed on a surface layer of the silicon substrate 2. The element isolation film 4 is an insulating region for isolating the element regions 6 where the MOS transistors are formed.
The element isolation film 4 is formed by, for example, LOCOS, LOPOS,
It is formed by forming a silicon oxide film on the insulating region by employing a method or the like.

Subsequently, a polysilicon layer 8 is formed on the substrate 2. The polysilicon layer 8 is formed by forming a gate insulating film 10 by a thermal oxidation method, forming a polysilicon film by a CVD method, and etching the polysilicon film into a predetermined shape. Polysilicon layer 8
Is composed of a control electrode 8 a provided on the element region 6 and a wiring layer 8 b provided on the element isolation film 4.

In the element region 6, N-type semiconductor regions 6a and 6a are self-aligned with the control electrode 8a and the element isolation film 4.
b is formed. This N-type impurity can be introduced by, for example, an ion implantation method. One of the N-type semiconductor regions 6a and 6b forms a source region of the MOS transistor, and the other forms a drain region of the MOS transistor. The N-type semiconductor regions 6a and 6b are separated by a control electrode 8a. A channel region 6c is formed between the separated N-type semiconductor regions 6a and 6b. The channel region 6c and the control electrode 8a sandwich the gate oxide film 10 from both sides. The conductivity of the channel region 6c is modulated by the voltage applied to the control electrode 8a. As a result, the control electrode 8a becomes a control electrode for controlling a current flowing between the source region and the drain region.

On the substrate 2, an N-type semiconductor region 6 of a source region and a drain region of the MOS transistor
a, 6b, and a control electrode 8a, and an interlayer insulating film 14 for electrically separating the control electrode 8a from a wiring layer formed thereover are formed. This insulating film 14 is, for example,
After a BPSG film having a predetermined thickness is deposited by using the CVD method, the BPSG film can be planarized by heat treatment. In the interlayer insulating film 14, the N-type semiconductor regions 6a and 6b of the source region and the drain region, the control electrode 8
a and a conductive portion for electrically connecting the wiring layer 8b to the metal wiring formed thereon is formed. Therefore, the contact holes 12a, 12a are formed in the interlayer insulating film 14.
b, 12c and 12d are formed. Contact hole 12a,
12b, 12c, and 12d are formed by, for example, forming a photoresist mask having an opening in a predetermined portion by using a photolithography method, and then removing the interlayer insulating film 14 in the opening by a plasma etching method. The contact hole 12a is provided on the N-type semiconductor region 6a, and a conductive portion for connecting the N-type semiconductor region 6a and a wiring layer thereover is formed. The contact hole 12b is provided on the N-type semiconductor region 6b.
And a conductive portion for connecting the wiring layer thereabove. The contact hole 12c is provided on the wiring layer 8b, and a conductive portion for connecting the wiring layer 8b and a wiring layer thereabove is formed. The contact hole 12d is provided on the control electrode 8a, and a conductive portion for connecting the control electrode 8a and an upper wiring layer is formed.

FIG. 2A is a process sectional view after a photoresist for forming a mask pattern is formed on the hard mask film. Referring to FIG. 2A, on the substrate 2,
A metal film 16 is deposited. The metal film 16 includes a conductive film made of at least one of aluminum (Al), an Al alloy, tungsten, and copper. A barrier metal film made of Ti or Ti / TiN can be provided between the metal film 16 and the interlayer insulating film 14. Further, an antireflection film may be further formed on the conductive film in contact with the conductive film. P-SiON, T
iN, Ti / TiN, Si, Si / TiN, p-SiO
A single-layer film and a laminated film having N / TiN, SiC, an organic coating film, or the like can be used. Barrier metal film,
Each of the conductive film and the antireflection film can be formed by, for example, a sputtering method or a CVD method.
Since the metal film 16 is also formed in the contact holes 12a, 12b, 12c and 12d (not shown) formed in the interlayer insulating film 14, the N-type semiconductor regions 6a and 6b, the control electrode 8a and the wiring layer 8b And conductive portions 16a, 16b, 16c for electrically connecting the metal film formed thereover to
16d is also formed at the same time.

As an example of the thickness of the metal film 16, in order to ensure the characteristics and reliability of the manufactured semiconductor device,
It is preferably from 100 nm to 1000 nm. One embodiment is described in detail: Ti-based barrier metal film: 50 nm or more and 100 nm or less Conductive film made of Al film: 100 nm or more and 1000 nm
Or less Antireflection film: 50 nm or more and 100 nm or less.

Next, a hard mask film 18 serving as a hard mask is formed on the metal film 16. Hard mask film 18
As a material of the first material, a silicon-based insulating film can be used. As an example of a silicon-based insulating film, as a silicon-based inorganic film,
SiO ₂ may be included. These inorganic films are deposited by using, for example, a CVD method.

The thickness of the hard mask film 18 is
In order to properly perform the etching, the thickness is preferably 150 nm or more and 300 nm or less. The thickness of the hard mask film 18 (hard mask 22) is 150 nm
If it is less than the above value, the metal film 16 will not function as a mask during etching. In other words, when the film loss during etching is taken into consideration, it is too thin as a mask material. On the other hand, when the thickness of the hard mask film 18 is 300 n
If m exceeds m, on the contrary, the destruction and deterioration of the gate oxide film begin to be noticeable due to an increase in the charge amount during etching. For this reason, the above-mentioned range of the film is a preferable range that the inventors have found through experiments and considerations. As a result of a detailed study of the experimental data by the inventor, it has been found that a film thickness of 180 nm or more and 230 nm or less is more preferable.

After these layers 16, 18 have been deposited,
A hard mask is formed using a photolithography method. FIG. 2B is a sectional view showing a step after the hard mask 22 is formed. The formation of the hard mask 22 proceeds according to the following steps. First, the hard mask film 1
A resist layer 20 having a wiring pattern to be formed as a metal wiring by applying a photoresist on the
To form Using the resist layer 20 as a mask, the hard mask film 18 is etched. Hard mask film 18
Examples of conditions for etching are as follows. CHF ₃ flow rate: 10 sccm CF ₄ flow rate: 20 sccm Ar flow rate: 60 sccm O ₂ flow rate: 5 sccm Chamber pressure: 60 mTorr Power: 200 W The hard mask film 18 is etched using such conditions, and the hard mask 22 is etched. To form

Next, the metal film is etched using the hard mask 22 formed as described above as a mask. The etching of the metal film 16 using the hard mask 22 can be performed using a plasma etching apparatus. The details will be described later. FIG. 3A shows a hard mask 2.
2 is a sectional view showing a step after the metal wiring 16 is formed by etching the metal film 16 using FIG. Note that FIG.
(A) corresponds to a II-II cross section of FIG. 3B shown below. When the metal film 16 is etched using the hard mask 22 as described above, the destruction and deterioration of the gate oxide film 10 during the etching are reduced. FIG.
(B) shows that the metal film 16 is etched and the metal wiring 24 is formed.
Is a plan view in a step after the formation of. Referring to FIG. 3B, the control electrode 8a and the wiring layer 8b
Has a conductive path with the metal layer 16 during etching via a conductive portion 16d formed in the contact hole 12d,
After the etching, it has a metal wiring 24 and a conductive path. Therefore, even after the metal wiring 24 is formed, the control electrode 8a and the wiring layer 8b have different potentials from the substrate 2 depending on the charge amount of the etching mask when exposed to the etching plasma. . Details regarding this will be described later.

Since the hard mask 22 is a silicon-based inorganic film, it is advantageous that the hard mask 22 does not need to be removed even after the metal wiring 24 is formed.

After forming the metal wiring 24, a passivation film 26 is formed with the hard mask 22 left. FIG. 4 is a process sectional view after the passivation film 26 is formed. The passivation film 26 is achieved, for example, by depositing a low-concentration phosphorus (P) -doped silicon oxide film (PSG) using a CVD method and then forming a plasma nitride film.

Through the above steps, a semiconductor device to which the method of manufacturing a semiconductor device described in the embodiment of the present invention is applied has been completed. In this embodiment, a single metal wiring layer 24
However, it is needless to say that the present invention can be applied to a semiconductor device further including one or more metal wiring layers added on the metal wiring layer 24. In this case, the metal layer 16, the hard mask film 1
8, corresponding to each of the photoresist masks 20,
A separate metal layer, a separate hard mask film, and a separate photoresist mask are formed. These forming methods can be performed in the same manner as the above method, but are not limited thereto. Thereafter, the separate hard mask film is etched using the separate photoresist mask as a mask to form a separate hard mask. Then, using the separate hard mask as a mask, the separate metal layer is etched to form a metal wiring layer. Also in this case, the gate oxide film of the MOS transistor is less likely to be broken and deteriorated during etching.

The etching conditions used in the above-described metal film etching process will be described. The etching is performed by using a mixed gas of Cl ₂ gas and BCl ₃ gas as a main component of the etching gas and using CHF ₃ as an additional gas.

As an example of the etching conditions, the substrate 2 is placed on a susceptor of an etching apparatus and fixed, and then the pressure in the processing chamber is set to about 5 to 30 mTorr, for example, 1 to 30 mTorr.
Reduce the pressure to 2 mTorr. On the other hand, the gas flow valve is controlled so that the flow rate of Cl ₂ gas is 80 sccm (about 60% of the total amount), and the flow rate of BCl ₃ gas is 40 sccm (about 10 sccm).
%) And CHF ₃ gas at a flow rate of 15 sccm or less, respectively, and after mixing these, it is preferable to supply the mixed gas to a chamber to perform etching. When high frequency power is applied, high density plasma is generated and maintained in the chamber. The etching gas is dissociated and ionized by the plasma, and chlorine (Cl) present in the plasma
The active species and ions mainly contribute to the etching of the metal film 16. At this time, since the Cl ions travel toward the susceptor having a negative potential, anisotropic etching in the vertical direction becomes possible.

It is to be noted that the Cl ₂ gas and the BCl ₃ gas are conventionally mixed and used in the same mixing ratio as that generally used as an etching gas for a metal film. As the material of the metal film 16, Al and an Al alloy are exemplified and listed.
Any conductive material that can be etched with the Cl-containing gas for etching can be used as a wiring layer.

Next, when forming the metal wiring, the MOS
A mechanism for substantially preventing the destruction of the gate oxide film (control electrode) of the type transistor will be described with reference to FIGS. 5 (a) and 5 (b). FIG. 5A is a schematic diagram showing both the charged charges at the time of etching using the hard mask and the charges induced in the metal film by the charges. FIG. 5 (b) is a schematic diagram showing both the charged charges at the time of etching using a photoresist and the charges induced in the metal film by the charges.
The inventor considers this mechanism as follows.

First, when a hard mask is employed, the mask thickness can be reduced as compared with the case where a metal film having the same thickness is etched using a photoresist. For example, even when the thickness of the photoresist needs to be 1 μm or more and 2 μm or less, if a hard mask is adopted, as described above, the thickness of the hard mask becomes 150 μm.
When the thickness is in the range of 300 nm to 300 nm, the metal film can be favorably etched. That is, the volume of the mask material that causes charging is reduced. For this reason, the amount of charge of the mask material during the etching is reduced, so that the amount of induced charge of the metal film can be reduced. When the thickness of the hard mask is 1
It is more preferable that the thickness be 80 nm or more and 230 nm or less.

The mask material accumulates charges during etching and becomes negatively charged, and ions reaching the metal film for etching have positive charges, so that the conductor to be etched is relatively positively charged. I will be. Therefore, the potential of the metal film is different from that of the substrate. Control electrode (Fig. 1
(A) 8a) and the wiring layer (8b in FIG. 1 (a))
The metal film and an electrical connection path (for example, 16 in FIG. 2B)
c, 16d), a potential difference is generated between the control electrode 8a and the wiring layer 8b and the substrate facing these. The control electrode 8a insulated from the substrate via the thin gate insulating film causes dielectric breakdown of the gate insulating film when the potential difference increases. However, according to the present invention, the dielectric breakdown does not occur because the amount of charge of the mask material causing the charge can be reduced.

In addition to the fact that the charge amount of the hard mask is reduced, the use of the hard mask keeps the aspect ratio of the etched portion small as compared with the conventional case using a photoresist. For this reason, in the case where a photoresist is used, electrons in the plasma that have been rebounded due to shading caused by the charged negative charges can reach deep portions of the etched portions. Therefore, electrons that have reached the metal film being etched can reduce the charge amount of the positively charged metal film.
Therefore, it is useful to reduce the charge of the metal film generated during the etching.

As is clear from FIGS. 5A and 5B, according to the method described in the present embodiment,
During the etching, both the charge in the film and the charge induced by the charge are reduced. It is considered that the charging of the mask material becomes remarkable in a portion where the wiring is densely formed. However, according to the method described in the present embodiment, the charging of the mask material is reduced by the above-described two mechanisms even in such a dense wiring region.

FIG. 6 (a) is a conceptual diagram showing both of the charge at the time of etching using a photoresist and the charge induced by the charge using a capacitor. FIG. 6B is a conceptual diagram illustrating, using a capacitor, both a charge that is charged at the time of etching using a hard mask and a charge that is induced by the charge.

Referring to FIG. 6A, since the thickness of the photoresist is large, there are many charged charges. FIG.
Referring to (b), since the thickness of the hard mask is smaller, there are less charged charges. Therefore, the potential difference V1 between the nodes A and B is larger in absolute value than the potential difference V2 between the nodes C and D.

6A and 6B, the capacitor C1 is formed between the substrate and the polysilicon layer (for example, 8b in FIG. 1B) on the element isolation film. The capacitor C2 is formed between the polysilicon layer on the gate oxide film (for example, 8a in FIG. 1B) and the substrate.
Since the film thickness of the gate oxide film is smaller than the film thickness of the element isolation film, the capacitance value per unit area of both capacitors is C1 <C2.

The capacitors C1 and C2 shown in FIG.
Are provided at both ends of the capacitor C1 shown in FIG.
A voltage higher than C2 is applied. Since the thickness of the gate oxide film is small, it is considered that defects due to the manufacturing process are likely to occur. For this reason, when a large voltage is applied to some extent, it is considered that the defective portion causes dielectric breakdown. This is considered to appear as destruction of the control electrode (gate electrode).

FIG. 7 shows time-dependent dielectric breakdown (TDDB, Time Dependent Diode) which is one of the methods for evaluating the deterioration of the gate oxide film.
4 is a graph showing the results of electric breakdown.

In this method, first, Cl ₂ is 60
sccm, 90 sccm of BCl ₃ , 15 sc of CHF ₃
cm of gas at a flow rate of 10 mTorr until the etching of the Al film (metal film) is completed.
₁₂ sccm, BCl ₃ 45 sccm, CHF ₃
After the etching of the barrier metal layer is completed under a pressure of 7 mTorr at a flow rate of 15 sccm, the gas is further flowed for 10 seconds. The thickness of the gate oxide film of the used sample was 4.5 nm, and the gate area was 10 μm ² . The thickness of the hard mask is 150 nm.

FIG. 7 shows the results obtained by applying a constant current stress of 500 mA / cm ² to the control electrode formed under such conditions and measuring the time until destruction. In the graph of FIG. 7, the horizontal axis represents time, and the vertical axis represents the cumulative failure rate. The mark “」 ”indicates data when a photoresist is used (PR Process in FIG. 7), and the mark“ ● ”indicates data when a hard mask is used (Hard Mask Process in FIG. 7). In addition, "□" mark (Reference in Fig. 7)
Is data measured at control electrodes connected to a simple electrode-like pattern (a pattern having an area 100,000 times larger than the control electrode area) without a wiring pattern for comparison reference. This is a result that does not include the damage caused by.

As is clear from the results of the graph of FIG.
It can be seen that the cumulative failure rate when the hard mask is used is improved and good as compared with the result using the photoresist, and is almost the same as the result without the damage due to shading.

As described above in detail with reference to the drawings, according to the present invention, when performing the plasma dry etching of the wiring layer electrically connected to the control electrode of the MOS type semiconductor device, particularly the wiring interval In this case, it is possible to reduce the dielectric breakdown and deterioration of the gate oxide film caused by the promotion of the charging of the wiring film in the portion where the density is high.

[0050]

As described above, in the present invention,
A hard mask was used in place of the photoresist as a mask material used when forming a wiring layer having a conductive path between the control electrode and the wiring layer. When a hard mask is employed, the initial thickness of the mask material required for etching the metal film can be reduced.

For this reason, since the volume of the mask material can be reduced, the portion that captures electric charge during etching is reduced. Therefore, the amount of charge on the mask material can be reduced, and the voltage applied between the control electrode and the substrate can be reduced.

Therefore, there is provided a method of manufacturing a semiconductor device capable of reducing destruction and deterioration of a gate oxide film when forming a metal wiring on a semiconductor device having a control electrode.

[Brief description of the drawings]

1A is a process sectional view of a semiconductor device manufactured on a substrate by applying the semiconductor device manufacturing method of the present invention, and FIG. 1B is a sectional view of FIG. It is a top view corresponding to the shown process sectional view.

FIG. 2A is a process sectional view after a photoresist for forming a mask pattern is formed on a hard mask film. FIG. 2B is a cross-sectional view showing a step after forming a hard mask.

FIG. 3A is a cross-sectional view showing a step after forming a metal wiring by etching a metal film using a hard mask. FIG. 3B is a plan view showing a step after the metal film is etched to form the metal wiring.

FIG. 4 is a process sectional view after a passivation film is formed.

FIG. 5A is a schematic diagram showing both a charged charge and a charge induced by the charge at the time of etching using a hard mask. FIG. 5B is a schematic diagram showing both the charged electric charge and the electric charge induced by the electric charge at the time of etching using the photoresist.

FIG. 6 (a) is a conceptual diagram illustrating, using a capacitor, both a charge that is charged during etching using a photoresist and a charge induced by the charge. FIG. 6B is a conceptual diagram illustrating, using a capacitor, both a charge that is charged at the time of etching using a hard mask and a charge that is induced by the charge.

FIG. 7 is a graph showing the results of temporal dielectric breakdown, which is one of the methods for evaluating the deterioration of a gate oxide film.

[Explanation of symbols]

2 ... substrate, 4 ... element isolation film, 6 ... element region, 8 ... polysilicon layer, 10 ... gate oxide film, 12a, 12b, 12
c, 12d contact hole, 16 metal film, 18 hard mask film, 20 photoresist, 22 hard mask, 24 metal wiring, 26 passivation film

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor, Naoki Taniya 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor, Satohide Kogure 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo (72) Inventor Yuji Takaoka 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sonny Inc. (72) Inventor Park Seiretsu 14-3 Shinizumi Noizumi Industrial Park, Narita City, Chiba Prefecture Applied Materials Japan Co., Ltd. (72) Inventor ▲ Taka ▼ Yasushi Kurashi 14-3 Shingeizumi, Narita-shi, Chiba Applied Materials Japan Co., Ltd. (72) Inventor Hidetaka Yamauchi Niizumi, Narita-shi, Chiba 14-3 Nogedaira Industrial Park Applied Materials Japan Co., Ltd. F term (reference) 5F004 AA06 BB13 DA01 DA04 DA11 D A16 DA23 DA26 DB08 DB09 DB10 DB12 EA06 EA07 EA22 5F033 HH00 HH03 HH08 HH09 HH11 HH18 HH19 HH33 JJ01 JJ08 JJ09 JJ11 JJ18 JJ19 JJ33 KK01 KK04 MM05 MM08 MM13 NN07 Q09 Q10 Q10 Q12 Q09 TT02 WW02 XX00 XX31 5F040 DA00 DC01 EC07 EJ03 EK01 EL01 EL03 EL06 FB04 FC21

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device for forming a metal wiring of a predetermined pattern connected to a control electrode on an insulating layer formed on a substrate so as to be conductive, wherein a first metal film is formed. A second step of forming a hard mask having a thickness of 150 nm to 300 nm, having the predetermined pattern, and made of a silicon-based inorganic insulating film on the metal film; A third step of etching the metal film using a mask to form the metal wiring of the predetermined pattern, wherein during the third step, the amount of charge remaining on the metal film is reduced. A method of manufacturing a semiconductor device, which prevents breakage and deterioration of the insulating layer caused by the charge flowing into the control electrode. 2. The method according to claim 1, wherein the material of the hard mask is silicon oxide. 3. The method according to claim 1, wherein the metal film is an Al film or an Al alloy film. 4. The method according to claim 1, wherein the metal film is a tungsten film or a copper alloy film. 5. The method according to claim 1, wherein the thickness of the hard mask is 180 nm to 230 nm. 6. The etching gas contains Cl,
A method for manufacturing a semiconductor device according to claim 1. 7. The method according to claim 1, wherein a barrier metal film is provided in contact with the metal film. 8. The method according to claim 7, further comprising etching the barrier metal film using the hard mask. 9. The method according to claim 1, wherein an antireflection film is provided between the metal film and the hard mask. 10. The method according to claim 9, further comprising etching the antireflection film using the hard mask.