pt.ap732 21145twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種半導體元件及其製造方法，且特 別是有關於一種具有電容器的半導體元件及其製造方法。 【先前技術】 記憶體顧名思義是用以儲存資料或數據的半導體元 件’當電腦微處理器的功能愈來愈強大’而軟體所進行的 程式=運算愈來愈龐大時，記紐的需求也就愈來愈高。 因此製造容量大且便宜的記憶體以滿足上述的需求製作 記憶體的技術與製程已成為半導體科技持續往更高積集度 的驅動力。 正個5己憶體的結構主要由記憶胞、位址解碼器及其他 與，憶體操作相_周邊電賴構成。其周邊電路包括有PT.ap732 21145twf.doc/e IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a semiconductor device having a capacitor and a method of fabricating the same. [Prior Art] As the name suggests, memory is a semiconductor component used to store data or data. When the functions of a computer microprocessor become more and more powerful, and the software-implemented program = the operation becomes more and more large, the demand for the memory is also increased. More and more high. Therefore, the manufacture of large-capacity and inexpensive memory to meet the above-mentioned requirements for the production of memory technology and processes has become a driving force for semiconductor technology to continue to achieve higher integration. The structure of a positive memory is mainly composed of a memory cell, a address decoder, and the like. Its peripheral circuits include
金氧半導體元件(Metal Oxide Semiconductor Device，MOSMetal Oxide Semiconductor Device (MOS)
DeV1Ce)、電容器(capacitor)以及電阻(resistor)等。而記悻 可藉由周邊電路來騎域财㈣的存取)㈣/匕體 為了增加元件的性能，習知多半以將周邊電路區上的 …體元件與S己憶體的製作相整合為目標。然而，受限於 不同凡件之設計與製程，往往有其困難之處。 揮發性記憶體中之反及閘型快閃記憶體為例，若 極作兒令态與記憶體的製程相整合，以記憶體中的浮置閘 土為電谷器的下電極，則所形成的下電極插塞會因為可 罪又的問題’而無法形成於隔離結構之間的主動區上。 換。之’下電極插塞必須形成於隔離結構上才可以， pt.ap732 21145twf.doc/e 如此一來，必須額外使用一道光罩，移除部分顏離結構， 使原本僅位於隔離結構之間（即主動區上）的下電極，得 以心跨形成於隔離結構上，這樣才能夠製造出位於隔離結 構上的下電極插塞H這齡料要#耗卜道光罩 的製程’不但步驟較多、製程較複雜，且還會提高製作成 本、降低產量。 【發明内容】 有鑑於此’依據本發明提供實施例之目的就是在提供 -種具有電容器的半導體元件，此電容器的插塞不限於設 置在隔離結構上，且還可以避免發生可靠度的問題。 ，依據本發明提供實施例之另一目的是提供一種電容器 的製造方法，可以與記憶體的製程相整合。 本發明提出一種具有電容器的半導體元件，包括基 底、隔離結構、記憶體、電容器、介電層、下電極插塞與 上電極插塞。基底包括第—區與第二區。隔離結構設置於 ，底中，至少於第一區定義出主動區。記憶體設置於第二 區之基底上，記憶體由基底起包括一層穿隧介電層、一層 洋置閘極與一層控制閘極。電容器設置於第一區之基底 上，包括了下電極、電容介電層與上電極。下電極設置於 主動區之基底上，下電極與浮置閘極是由相同的材料層形 成的，電容介電層覆蓋住下電極，而上電極則設置於部分 電容介電層上，裸露出主動區之部分電容介電層，上電極 與控制閘極是由相同的材料層形成的。介電層設置於下電 極與基底之間，介電層的厚度大於穿隧介電層的厚度。下 1324389 p(.ap732 2ll45twf.doc/e 電極，塞設置於主動區上方，電性連接下 極插基則是電性連接上電極。 ;私 的頂導體元件中，第-區之隔離結構 離結構有電^的半導體元件’ ’上電_塞位於隔 電層上電Γ的半導體元件$，更包括—層間間介 層α置於洋置間極與控制開極之間。 介電容器的半導體元件中，問間介電層與電容 3疋由相同的材料層形成的。 於上it有電容器的半導體元件令，金屬石夕化物層設置 電極β ι上電極插塞藉由金屬♦化物層電性連接上 質包括Hi電容器的半導體元件中’金屬石夕化物層的材 y化鎢、矽化鈦或矽化鈷。 包括氣電容器的半導體元件中’電容介電層的材質 氮化矽·氧化矽。 摻雜有電容器的半導體元件中’下電極的材質包括 曰0 7。上電極的材質包括摻雜多晶矽。 快閃記有電容器的半導體元件中，記憶體為反及閘型 區，第二=有電谷器的半導體元件中，第一區為周邊電路 一區為記憶胞區。 上述具有電容器的半導體元件，可以在記憶體旁設置 8 1324389 pt.ap732 21145iwf.doc/e f電容器，且由於基底上的介電層厚度足夠，可以容許電 容器的插塞形成在主動區上，而不會產生可靠度的問題， 可能夠增加產品佈局上的彈性。 本發明提出一種具有電容器的半導體元件之製造方 法，此方法包括提供一基底，基底包括第一區與第二區。 於第一區之基底上形成一層介電層，然後於第二區之基底 f形成一層穿隧介電層，介電層的厚度大於穿隧介電層的 φ 厚度。接著，於基底上形成第一導體層，覆蓋住介電層與 穿隨介電層。而後，於第—導體層、介電層、穿隨介電層 與基底中形成多個隔離結構，以至少於第一區定義出主^ 區。接著於第一區之基底上形成一層電容介電層與一層第 二導體層。圖案化二導體層，於第二區的基底上形成控制 閑極’於第-區的基底上形成上電極，上電極裸露出主動 區上的部分電容介電層。繼而圖案化第一導體層於第一 區的基底上形成下電極，於第二區的基底上形成浮置閘極。 上述具有電容器的半導體元件之製造方法中更包括 釀於圖案化第-導體層的步驟之後，於基底上形成一層層間 介電層，然後於層間介電層中形成第一插塞盘第_ :二 其中第-插塞設置於第-區之主動區上，與連 接，第二插塞則與上電極電性連接。 上述具有電容器的半導體元件之製造方法中，形成第 一插塞與第二插塞的方法包括先於主動區形成第一開口， 第一開口延伸穿越層間介電層與電容介電層，而停止於下 電極，並且於第二導體層上形成第二開口，第二開口延伸 9DeV1Ce), capacitor (capacitor), and resistor (resistor). In addition, in order to increase the performance of the components, it is customary to integrate the body components on the peripheral circuit area with the production of the S memory. aims. However, it is often limited by the design and process of different parts. For example, in the case of volatile memory, the gate flash memory is an example. If the polar state is integrated with the memory process, the floating gate soil in the memory is the lower electrode of the electric cell. The formed lower electrode plugs cannot be formed on the active area between the isolation structures because of the guilty problem. change. The 'lower electrode plug must be formed on the isolation structure. pt.ap732 21145twf.doc/e As a result, an additional mask must be used to remove part of the structure so that it is only between the isolation structures ( That is, the lower electrode of the active region is formed on the isolation structure by the heart span, so that the lower electrode plug H located on the isolation structure can be manufactured, and the process of the mask is not only a lot of steps, The process is more complicated, and it will increase production costs and reduce production. SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a semiconductor device having a capacitor which is not limited to being disposed on an isolation structure and which can avoid the problem of reliability. Another object of an embodiment provided in accordance with the present invention is to provide a method of fabricating a capacitor that can be integrated with the process of a memory. The present invention provides a semiconductor device having a capacitor including a substrate, an isolation structure, a memory, a capacitor, a dielectric layer, a lower electrode plug, and an upper electrode plug. The substrate includes a first region and a second region. The isolation structure is disposed in the bottom, and at least the active area is defined in the first area. The memory is disposed on the substrate of the second region, and the memory comprises a tunneling dielectric layer, a layer of gate electrodes and a layer of control gates from the substrate. The capacitor is disposed on the substrate of the first region and includes a lower electrode, a capacitor dielectric layer and an upper electrode. The lower electrode is disposed on the substrate of the active region, the lower electrode and the floating gate are formed by the same material layer, the capacitor dielectric layer covers the lower electrode, and the upper electrode is disposed on a portion of the capacitor dielectric layer, exposed A portion of the capacitive dielectric layer of the active region, the upper electrode and the control gate are formed of the same material layer. The dielectric layer is disposed between the lower electrode and the substrate, and the thickness of the dielectric layer is greater than the thickness of the tunneling dielectric layer. The lower 1324389 p (.ap732 2ll45twf.doc/e electrode, the plug is placed above the active area, the electrical connection of the lower pole is electrically connected to the upper electrode. In the private top conductor element, the isolation structure of the first-area A semiconductor device having a structure of 'electrical power_plug' is placed on the electrical layer of the semiconductor element $, and further includes an inter-layer dielectric layer α interposed between the inter-electrode and the control opening. In the device, the intervening dielectric layer and the capacitor 3疋 are formed of the same material layer. The semiconductor element having the capacitor on the upper layer, the metal-lithium layer is provided with the electrode β1, and the electrode plug is electrically connected by the metal layer. In the semiconductor device including the Hi capacitor, the material of the metal-lithium layer is y-tungsten, titanium-telluride or cobalt-deposited cobalt. In the semiconductor device including the gas capacitor, the material of the capacitor dielectric layer is tantalum nitride and yttrium oxide. In the semiconductor component with capacitors, the material of the lower electrode includes 曰0 7. The material of the upper electrode includes doped polysilicon. In the semiconductor component with flash capacitor, the memory is the anti-gate region, and the second = electric valley In the semiconductor device, the first region is a memory cell region of the peripheral circuit. The above semiconductor device having a capacitor can be provided with a memory of 8 1324389 pt.ap732 21145iwf.doc/ef capacitor, and due to the dielectric on the substrate The layer thickness is sufficient to allow the plug of the capacitor to be formed on the active region without causing reliability problems, and the flexibility in product layout can be increased. The present invention provides a method of manufacturing a semiconductor device having a capacitor, the method comprising Providing a substrate, the substrate comprising a first region and a second region. Forming a dielectric layer on the substrate of the first region, and then forming a tunneling dielectric layer on the substrate f of the second region, the thickness of the dielectric layer being greater than Φ thickness of the tunnel dielectric layer. Next, a first conductor layer is formed on the substrate to cover the dielectric layer and the traversing dielectric layer. Then, the first conductor layer, the dielectric layer, the traversing dielectric layer and the substrate Forming a plurality of isolation structures to define a main region at least in the first region. Then forming a capacitor dielectric layer and a second conductor layer on the substrate of the first region. a bulk layer is formed on the substrate of the second region to form a control electrode on the substrate of the first region, and the upper electrode exposes a portion of the capacitor dielectric layer on the active region. The first conductor layer is patterned in the first region Forming a lower electrode on the substrate to form a floating gate on the substrate of the second region. The method for fabricating a semiconductor device having a capacitor further includes forming a layer on the substrate after the step of patterning the first conductor layer a dielectric layer, and then forming a first plug disk in the interlayer dielectric layer _: two, wherein the first plug is disposed on the active region of the first region, and the second plug is electrically connected to the upper electrode In the above method for manufacturing a semiconductor device having a capacitor, the method of forming the first plug and the second plug includes forming a first opening before the active region, the first opening extending through the interlayer dielectric layer and the capacitor dielectric layer, and Stopping at the lower electrode and forming a second opening on the second conductor layer, the second opening extending 9
Ptap732 21145twf.doc/e 牙越層間介電層’而停止於上電極，然後於第一開口與第 二開口中填入導體材料，分別形成第一插塞與第二插塞。 上述具有電容器的半導體元件之製造方法中，更包括 於形成電容介電層的步驟中，於第二區之基底上形成一層 閑間介電層’其中閘間介電層與電容介電層是由相同的材 料層形成的。 上述具有電容器的半導體元件之製造方法中，第二插 塞位於隔離結構上方。 上述具有電容器的半導體元件之製造方法中，更包括 於形成這些隔離結構之後，移除部分隔離結構，使隔離結 構的頂面低於第一導體層的頂面。 上述具有電容器的半導體元件之製造方法中，更包括 於形成第二導體層的步歡後’於基底上軸-金屬石夕化 物層。 上述具有t容器的半導體元件之製造方法中，更包括 於圖案化第二導體層的步驟中，—併移除部分金屬石夕化物 ，金屬石夕 ’電容介 ’記憶體 ’第一區 上述具有電容器的半導體元件之製造方法中 化物層的材質包㈣倾、雜鈦切化話。 上述具有電容器的半導體元件之製造方法中 電層的材質包括氧切_氮化化氧化石夕。 上述具有電容器的半導體元件之製造方法中 為反及閘型快閃記憶體。 上述具有電容器的半導體元件之製造方法中 pt.ap732 21145t\vf.doc/e 為周邊電路區，第二區為記憶胞區。 本發明提出之電容器的製造方法，可以與記憶體的梦 程，整合’而無須_額外的光罩來製作電容器，不但^ 以簡化製造流程、降低製造成本，且由於電容器不限於設 ^在隔離結構上方，更能夠減少對於製程設計的限制，提 向產品佈局的彈性。 ^為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 明如下。 ° 【實施方式】 圖1是繪示本發明一實施例之一種具有電容器的半導 體元件的剖面示意圖。 。月參照圖1 ’本發明之實施例提出一種具有電容器的 半導體元件’包括基底100、記憶體110、電容器12〇、介 電層123、下電極插塞135與上電極插塞145。基底100 例如是半導體基底，如矽基底。基底100包括第一區103 與第二區1〇5。在一實施例中，第一區1〇3例如是周邊電 路區’第二區105例如是記憶胞區。基底1〇〇中設置有多 個隔離結構107，分隔出主動區109。 記憶體110設置於第二區105，記憶體11〇例如是反 及閘$快閃記憶韙，由基底1〇〇起包括一層穿隨介電層 113、—層浮置閘極115、一層閘間介電層U7與一層控制 閘極119。穿隧介電層113的材質例如是氧化矽；浮置閘 極115與控制閘極119的材質例如是摻雜多晶矽；閘間介 11 1324389 pt.ap732 21145twf,doc/e :層H:的材質可以是氧切 也可以是如圖1所示之氧化 枓 no 虱化矽-乳化矽所組成之複 電層控制閘極119上還可以 層130,以降低控制閘極119 曰金屬夕化物 可以是石夕化鶴、石夕化鈦或石夕化^電阻。金屬石夕化物層⑽ 電容器120設置於第—卩1Λ m, 107 ^ μ 品 ，匕括了下電極125、電 二，?與上電極129。下電極125設置於主動區職 二θ3之主動區1〇9)之基底100上。下電極 、 物是掺雜多晶碎，其與浮置問極119例如是 =f?f所形成的。在-實施例中，隔離上 的頂面例如疋低於下電極125的頂面。 電容介電層127覆蓋住下電極125，電容介電層127 ^才，例如是氧切_氮化化氧切，其與閘間介電層ιΐ7 例如疋以相同的材料層所形成的。 上電極129設置於部分電容介電層127上，裸露出主 曰:109a之部分電容介電層127。上電極129的材質例如 疋捧雜多晶碎’其與控糊極119例如是以相同的材料層 所形成的。 上電極129與控制閘才圣119上還可以設置有一層金屬 石夕化物層130 ’用來降低阻值。下電極125與基底刚之 間設置有-層介電層123,其材質例如是氧化石夕，介電層 123的厚度大於穿隧介電層113的厚度。 下電極插塞135設置於第一區1〇3之主動區i〇9a上， 穿越電谷介電層127而電性連接下電極125。上電極插塞 12 1324389 pt.ap732 2H45twf.doc/e 145則是電性連接上電極129。在一實施例中，上電極插塞 145可以是設置於金屬矽化物層130上，藉由金屬矽化物 層130電性連接上電極129。下電極插塞135與上電極插 塞145的材質可以是摻雜多晶矽、金屬或金屬矽化物等導 體材料。 上述實施例，可以於記憶體110旁設置此電容器120， 且由於電容器120下方之介電層123厚度足夠，可以在隔 離結構107之間（即主動區）的基底1〇〇上設置電容器12〇 的插塞（下電極插塞135)，而不會產生可靠度的問題。 如此一來，電容器120的接點（插塞）就不限於設置在隔 離結構107上，對於產品佈局也能夠更有彈性。 以下說明上述具有電容器的半導體元件之製造方法。 圖2A至圖2D是繪示本發明一實施例之一種具有電容器的 半導體元件之製造流程剖面圖。 明參照圖2A ’此製造方法例如是先提供基底2〇〇，基 底200例如是半導體基底，如石夕基底。基底2〇〇包括第一 區203與第二區205。在一實施例，第一區203例如是周 邊電路區’第二區例如是記憶胞區。 於第一區203之基底200上形成一層介電層223，於 第一區205之基底200上形成一層穿隧介電層213。介電 層223與穿隧介電層213的材質例如是氧化矽，其形成方 法例如是熱氧化法或化學氣相沈積法。在一實施例中，可 以是先形成一層罩幕層（未繪示）覆蓋住第二區2〇5的基 底200 ’然後利用熱氧化法或化學氣相沈積法，於第一區 13 1324389 pt.ap732 21145twf.doc/e 203的基底200上形成一層介電層223。之後，移除罩幕層， 於第二區205的基底200上形成穿隧介電層213。介電層 223的厚度大於穿隧介電層213的厚度。 然後於基底上形成一層導體層225。導體層225的材 質例如是摻雜多晶矽，其形成方法例如是利用化學氣相沈 積法形成一層未摻雜多晶矽層後，進行離子植入步驟以形 成之，當然也可以採用臨場植入摻質的方式以化學氣相沈 積法形成摻雜多晶石夕層。在一實施例中，導體層225在第 203之中，是作為後續形成之電容器的下電極，在第 一區205之中，則是作為後續形成之記憶體的浮置閘極。 也就是說，下電極與浮置閘極是由相同的材料層所形成的。 接著，於導體層225、介電層223、穿隨介電層213 ，基底200中形成多個隔離結構2〇7，定義出主動區2〇9。 =離結構207的形成方法例如是移除部分導體層225、介 =層223、穿隧介電層213，形成多個溝渠206，之後於溝 a 206中填入絕緣材料而形成的。絕緣材料例如是氧化 矽，其形成方法例如是高密度化學氣相沈積法。 繼而，請參照圖2B，移除部分隔離結構2〇7，使得隔 ，結構207的頂面低於導體層225的頂&。移除部分隔離 結構207的方法例如是乾式钱刻法或濕式钱刻法。 然後，於第一區203之基底200上形成一層電容介電 :227。電谷介電層227的材質可以是氧化矽等的介電材 ;斗，或疋由氧化矽-氮化矽_氧化矽所形成的複合介電層， 如圖2B所示。這些介電材料的形成方法例如是化學氣相 pt.ap732 21145t\vf.doc/e 沈積法。在形成電容介電層227的 =層’於第二區205中形成閉間介二= 就22:表不）’用來分隔記憶體的控制閘極與浮置間極。 接下來’請參照圖2C，於電容介電層227上形 層導體層229。導體層229的材質例如是摻雜多晶矽，盆 形成方法請參照上述導體層225的形成方法。在^ 中’導體層229在第一區2〇3之中，是作為電容器的上電 極，其與第一區203中的電容介電層227、導體層225 ( 電極）曰’構成了電容器220。在第二區2〇5之中θ，導體層 229則是作為控制閘極，與電容介電層227(閉間介電、 導體層225 (浮置閘極）及穿隧介電層213，構成了記 210。記憶體210可以是反及閘型快閃記憶體。 μ — 換言之，導體層229在第一區2〇3之中，是作為電容 益的上電極，在第二區205之中，是作為記憶體的控制閘 極。亦即，上電極與控制閘極是由同一層導體層229形成 的。 在一實施例中，還可以於導體層229上形成一層金屬 矽化物層230。金屬矽化物層230的材質包括矽化鈦、矽 化鈕或矽彳匕鎢，其形成方法包括濺鍍法或化學氣相沈積 法。這層金屬矽化物層23〇可以降低阻值，提高元件的操 作速度。 之後’請繼續參照圖2C，圖案化導體層229，於第二 區205上形成控制閘極（導體層229 )，於第一區203上 形成上電極（導體層229)。圖案化導體層229的方法例 如是以圖案化光阻層（未繪示）覆蓋住部分金屬魏物層 15 pt.ap732 21145twf.d〇c/e 230 ’然後利用乾式蝕刻法或濕式蝕刻法以移除主動區 209a (位於第一區203之主動區209)上部分導體層229 與金屬矽化物層230。上電極（導體層229)會裸露出主動 區209a上的部分電容介電層227。 在一實施例中，還可以於上述圖案化導體層229之 後，進一步圖案化導體層225，而於第一區203的基底200 上形成下電極（導體層225)，於第二區205形成塊狀的 浮置閘極（導體層225)。當然，圖案化導體層225以形 成下電極與浮置閘極的這個步驟，也可以是在其他步驟之 後進行，端視元件的製程而定。 繼而’請參照圖2D ’於基底200上形成一層層間介電 層233。層間介電層233的材質例如是氧化矽，其形成方 法例如是化學氣相沈積法。然後，於主動區209a上形成開 口 235 ’其延伸穿越該層間介電層233與電容介電層227， 而停止於導體層225。同時於導體層229上形成開口 237， 其延伸穿越層間介電層233，而停止於導體層229。當然， 若導體層229上還設置了金屬矽化物層23〇，則開口 237 便停止於金屬矽化物層230上。 形成開口 235、開口 237的方法例如是先於層間介電 層233上形成一層圖案化罩幕層（未繪示），裸露出部分 層間電層233，之後再利用乾式钱刻法，如反應性離子 蝕刻法，移除裸露出的層間介電層233。在主動區2〇%的 區域，更包括進一步移除電容介電層227 ,而形成裸露出 導體層225的開口 235。 接著，於開口 235與開口 237中填入導體材料，分別 1324389 pt.ap732 21145t\vf.doc/e 形成插塞243與插塞245。導體材料例如是摻雜多晶矽、 金屬或金屬矽化物，其形成方法例如是化學氣相沈積法。 所形成的插塞243位於主動區209&上，延伸穿越電容介電 層227，與導體層225電性連接。而插塞245則是與導體 層229電性連接。 值得一提的是，在形成插塞243、插塞245的同時， 還可以在第二區205之層間介電層233中形成另一個插塞 247’電性連接導體層230。至於後續完成記憶體與整個半 導體元件的方法應為熟知本領域者所週知，於此不再贅述。 上述提出之電容器的製造方法，可以與記憶體的製程 相整合，而無須利用額外的光罩來形成此電容器，不但可 以簡化製造流程、降低製造成本，且由於連接電容哭^插 塞可以形成於主動區上，不限於形成在隔離結構上^， 能夠減少對於製程設計的限制，提高產品佈局的彈性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精^ =範圍内，當可作些許之更動與潤飾，因此本發明之^ 範圍當視後附之申請專利範圍所界定者為準。 ，'5 【圖式簡單說明】 圖1是繪示本發明一實施例之一種具有電容器 體元件之剖面示意圖。 圖2A至圖2D是繪示本發明一實施例之一種具 器的半導體元件之製造流程剖面圖。 备 【主要元件符號說明】 17 1324389 pt.ap732 21145tvvf.doc/e 100、200 :基底 103、203 :第一區 105、205 :第二區 107、207 :隔離結構 109、 109a、209、209a :主動區 110、 210:記憶體 113、213 :穿隧介電層 115 :浮置閘極 * 117:閘間介電層 119 :控制閘極 120、220 :電容器 123、223 :介電層 125 :下電極 127、227 :電容介電層 129 :上電極 130 :金屬矽化物層 • 135:下電極插塞 145 :上電極插塞 206 :溝渠 225、229 :導體層 233 :層間介電層 235、237 :開口 243、245、247 :插塞 18The Ptap732 21145twf.doc/e interdental dielectric layer stops at the upper electrode, and then the conductor material is filled in the first opening and the second opening to form a first plug and a second plug, respectively. In the method for fabricating a semiconductor device having a capacitor, the method further includes forming a dummy dielectric layer on the substrate of the second region in the step of forming the capacitor dielectric layer, wherein the inter-gate dielectric layer and the capacitor dielectric layer are Formed from the same material layer. In the above method of manufacturing a semiconductor device having a capacitor, the second plug is located above the isolation structure. In the above method for fabricating a semiconductor device having a capacitor, after the formation of the isolation structures, a portion of the isolation structure is removed such that a top surface of the isolation structure is lower than a top surface of the first conductor layer. In the above method of manufacturing a semiconductor device having a capacitor, the method further comprises forming a second conductor layer after the step of the substrate-axis-metallization layer. In the above method for manufacturing a semiconductor device having a t-container, the method further includes: in the step of patterning the second conductor layer, and removing a portion of the metal lithium compound, the metal shi s capacitor 'memory' first region has the above In the manufacturing method of the semiconductor element of the capacitor, the material layer of the compound layer is (four) tilted, and the titanium is cut. In the above method for manufacturing a semiconductor device having a capacitor, the material of the electric layer includes oxygen cut-nitrided oxidized oxide. In the above method of manufacturing a semiconductor device having a capacitor, it is a gate-type flash memory. In the above method of manufacturing a semiconductor device having a capacitor, pt.ap732 21145t\vf.doc/e is a peripheral circuit region, and the second region is a memory cell region. The manufacturing method of the capacitor proposed by the invention can be integrated with the memory of the memory, without the need for an additional mask to make the capacitor, not only to simplify the manufacturing process, reduce the manufacturing cost, but also because the capacitor is not limited to the isolation. Above the structure, it is possible to reduce the restrictions on the process design and the flexibility of the product layout. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] Fig. 1 is a cross-sectional view showing a semiconductor device having a capacitor according to an embodiment of the present invention. . Referring to Fig. 1 'an embodiment of the present invention, a semiconductor device having a capacitor' includes a substrate 100, a memory 110, a capacitor 12A, a dielectric layer 123, a lower electrode plug 135, and an upper electrode plug 145. The substrate 100 is, for example, a semiconductor substrate such as a germanium substrate. The substrate 100 includes a first region 103 and a second region 1〇5. In one embodiment, the first zone 1 〇 3 is, for example, a peripheral circuit zone. The second zone 105 is, for example, a memory cell zone. A plurality of isolation structures 107 are disposed in the substrate 1 to separate the active regions 109. The memory 110 is disposed in the second area 105, and the memory 11 is, for example, a reverse flash memory. The substrate 1 includes a transparent dielectric layer 113, a floating gate 115, and a gate. The dielectric layer U7 and the first layer of the control gate 119. The material of the tunneling dielectric layer 113 is, for example, yttrium oxide; the material of the floating gate 115 and the control gate 119 is, for example, doped polysilicon; the material of the gate is 11 1324389 pt.ap732 21145twf, doc/e: layer H: It may be oxygen-cut or may be a ruthenium oxide ruthenium-emulsified ruthenium as shown in FIG. 1 and the photovoltaic layer control gate 119 may also have a layer 130 to reduce the control gate 119. Shi Xihua crane, Shi Xihua titanium or Shi Xihua ^ resistance. The metal-lithium layer (10) The capacitor 120 is disposed on the first Λ1Λ m, 107 μ μm, including the lower electrode 125, the second electrode, and the upper electrode 129. The lower electrode 125 is disposed on the substrate 100 of the active area 1〇9) of the active area θ3. The lower electrode, the material is doped polycrystalline, which is formed, for example, by =f?f with the floating pole 119. In an embodiment, the top surface of the isolation, such as 疋, is lower than the top surface of the lower electrode 125. The capacitor dielectric layer 127 covers the lower electrode 125, and the capacitor dielectric layer 127 is, for example, an oxygen cut-nitrided oxygen cut, which is formed by the same material layer as the inter-gate dielectric layer ι7, for example. The upper electrode 129 is disposed on the portion of the capacitor dielectric layer 127 to expose a portion of the capacitor dielectric layer 127 of the host: 109a. The material of the upper electrode 129 is, for example, a heteropolycrystalline powder, which is formed, for example, with the same material layer as the control paste 119. A layer of metal lithium layer 130' may also be disposed on the upper electrode 129 and the control gate 119 to reduce the resistance. A dielectric layer 123 is disposed between the lower electrode 125 and the substrate, and the material thereof is, for example, oxidized oxide, and the thickness of the dielectric layer 123 is greater than the thickness of the tunneling dielectric layer 113. The lower electrode plug 135 is disposed on the active region i〇9a of the first region 1〇3, and electrically connected to the lower electrode 125 through the electric valley dielectric layer 127. The upper electrode plug 12 1324389 pt.ap732 2H45twf.doc/e 145 is electrically connected to the upper electrode 129. In one embodiment, the upper electrode plug 145 may be disposed on the metal telluride layer 130, and the upper electrode 129 is electrically connected by the metal halide layer 130. The material of the lower electrode plug 135 and the upper electrode plug 145 may be a conductor material such as doped polysilicon, metal or metal telluride. In the above embodiment, the capacitor 120 can be disposed beside the memory 110, and since the thickness of the dielectric layer 123 under the capacitor 120 is sufficient, the capacitor 12 can be disposed on the substrate 1 between the isolation structures 107 (ie, the active region). The plug (lower electrode plug 135) does not cause reliability problems. As a result, the contacts (plugs) of the capacitor 120 are not limited to being disposed on the isolation structure 107, and are more flexible for product layout. A method of manufacturing the above-described semiconductor device having a capacitor will be described below. 2A to 2D are cross-sectional views showing a manufacturing process of a semiconductor device having a capacitor according to an embodiment of the present invention. Referring to Fig. 2A', the manufacturing method is, for example, first providing a substrate 2, for example, a semiconductor substrate such as a stone substrate. The substrate 2 includes a first region 203 and a second region 205. In one embodiment, the first region 203 is, for example, a peripheral circuit region. The second region is, for example, a memory cell region. A dielectric layer 223 is formed on the substrate 200 of the first region 203, and a tunneling dielectric layer 213 is formed on the substrate 200 of the first region 205. The material of the dielectric layer 223 and the tunnel dielectric layer 213 is, for example, ruthenium oxide, and the formation method is, for example, a thermal oxidation method or a chemical vapor deposition method. In an embodiment, a mask layer (not shown) may be formed to cover the substrate 200' of the second region 2〇5 and then used in the first region 13 1324389 pt by thermal oxidation or chemical vapor deposition. A dielectric layer 223 is formed on the substrate 200 of .ap732 21145twf.doc/e 203. Thereafter, the mask layer is removed, and a tunneling dielectric layer 213 is formed on the substrate 200 of the second region 205. The thickness of the dielectric layer 223 is greater than the thickness of the tunneling dielectric layer 213. A layer of conductor layer 225 is then formed on the substrate. The material of the conductor layer 225 is, for example, doped polysilicon. The formation method is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form the implant. The method forms a doped polycrystalline layer by chemical vapor deposition. In one embodiment, conductor layer 225 is the lower electrode of the subsequently formed capacitor in 203, and is the floating gate of the subsequently formed memory in first region 205. That is, the lower electrode and the floating gate are formed of the same material layer. Next, a plurality of isolation structures 2〇7 are formed in the conductor layer 225, the dielectric layer 223, the traversing dielectric layer 213, and the substrate 200, and the active regions 2〇9 are defined. The method of forming the isolation structure 207 is, for example, removing a portion of the conductor layer 225, the dielectric layer 223, and the tunneling dielectric layer 213, forming a plurality of trenches 206, and then forming the trenches a 206 with an insulating material. The insulating material is, for example, cerium oxide, and the forming method thereof is, for example, a high-density chemical vapor deposition method. Next, referring to Fig. 2B, a portion of the isolation structure 2〇7 is removed such that the top surface of the spacer 207 is lower than the top & The method of removing a portion of the isolation structure 207 is, for example, a dry money engraving or a wet money engraving. Then, a capacitor dielectric is formed on the substrate 200 of the first region 203: 227. The material of the electric valley dielectric layer 227 may be a dielectric material such as ruthenium oxide or the like, or a composite dielectric layer formed of yttrium oxide-yttria-yttria, as shown in FIG. 2B. The formation method of these dielectric materials is, for example, a chemical vapor phase pt.ap732 21145t\vf.doc/e deposition method. The = layer ' forming the capacitor dielectric layer 227 is formed in the second region 205 to form a closed gate 2 = 22: not shown' to separate the control gate and the floating interlayer of the memory. Next, please refer to FIG. 2C to form a conductor layer 229 on the capacitor dielectric layer 227. The material of the conductor layer 229 is, for example, doped polysilicon, and the method of forming the basin is referred to the method of forming the conductor layer 225. In the first region 2〇3, the conductor layer 229 acts as the upper electrode of the capacitor, and forms a capacitor 220 with the capacitor dielectric layer 227 and the conductor layer 225 (electrode) 曰' in the first region 203. . θ in the second region 2〇5, the conductor layer 229 serves as a control gate, and a capacitor dielectric layer 227 (closed dielectric, conductor layer 225 (floating gate) and tunnel dielectric layer 213, The memory 210 may be a reverse-gate type flash memory. μ - In other words, the conductor layer 229 is in the first region 2 〇 3 as the upper electrode of the capacitor, and in the second region 205 The control gate is used as the memory. That is, the upper electrode and the control gate are formed by the same conductor layer 229. In an embodiment, a metal halide layer 230 may also be formed on the conductor layer 229. The material of the metal telluride layer 230 comprises titanium telluride, germanium or germanium tungsten, and the method for forming the metal telluride layer 230 includes sputtering or chemical vapor deposition. The metal halide layer 23 can reduce the resistance and improve the component. Operating speed. Then, referring to FIG. 2C, the conductor layer 229 is patterned, a control gate (conductor layer 229) is formed on the second region 205, and an upper electrode (conductor layer 229) is formed on the first region 203. Patterning The method of the conductor layer 229 is, for example, a patterned photoresist layer (not shown). Covering a portion of the metal wafer layer 15 pt.ap732 21145twf.d〇c/e 230 'and then using a dry etch or wet etch to remove a portion of the conductor on active region 209a (active region 209 in first region 203) The layer 229 and the metal telluride layer 230. The upper electrode (the conductor layer 229) exposes a portion of the capacitor dielectric layer 227 on the active region 209a. In an embodiment, the patterned conductor layer 229 may be further patterned. The conductor layer 225 is formed, and a lower electrode (conductor layer 225) is formed on the substrate 200 of the first region 203, and a bulk floating gate (conductor layer 225) is formed in the second region 205. Of course, the patterned conductor layer 225 is formed. This step of forming the lower electrode and the floating gate may also be performed after the other steps, depending on the process of the device. Then, please refer to FIG. 2D to form an interlayer dielectric layer 233 on the substrate 200. The material of the dielectric layer 233 is, for example, ruthenium oxide, and the formation method thereof is, for example, chemical vapor deposition. Then, an opening 235' is formed on the active region 209a, which extends through the interlayer dielectric layer 233 and the capacitor dielectric layer 227. Stop at conductor layer 225 At the same time, an opening 237 is formed on the conductor layer 229, which extends through the interlayer dielectric layer 233 and stops at the conductor layer 229. Of course, if the metal halide layer 23 is provided on the conductor layer 229, the opening 237 stops at The method for forming the opening 235 and the opening 237 is, for example, forming a patterned mask layer (not shown) on the interlayer dielectric layer 233, exposing a portion of the interlayer electrical layer 233, and then using the dry layer. The exposed interlayer dielectric layer 233 is removed by a magnetic etching method such as reactive ion etching. Further, in the region of 2% of the active region, the capacitor dielectric layer 227 is further removed to form an opening 235 where the conductor layer 225 is exposed. Next, a conductor material is filled in the opening 235 and the opening 237, and the plug 243 and the plug 245 are formed by 1324389 pt.ap732 21145t\vf.doc/e, respectively. The conductor material is, for example, a doped polysilicon, a metal or a metal telluride, which is formed, for example, by chemical vapor deposition. The formed plug 243 is located on the active region 209 & and extends through the capacitor dielectric layer 227 to be electrically connected to the conductor layer 225. The plug 245 is electrically connected to the conductor layer 229. It is worth mentioning that, while forming the plug 243 and the plug 245, another plug 247' can be electrically connected to the conductor layer 230 in the interlayer dielectric layer 233 of the second region 205. The method of subsequently completing the memory and the entire semiconductor component is well known in the art and will not be described again. The above-mentioned capacitor manufacturing method can be integrated with the memory process without using an additional mask to form the capacitor, which not only simplifies the manufacturing process, reduces the manufacturing cost, but also can be formed by the connection capacitor crying plug The active area is not limited to being formed on the isolation structure, which can reduce the restriction on the process design and improve the flexibility of the product layout. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a capacitor body element according to an embodiment of the present invention. 2A to 2D are cross-sectional views showing a manufacturing process of a semiconductor device of an embodiment of the present invention. [Main component symbol description] 17 1324389 pt.ap732 21145tvvf.doc/e 100, 200: substrate 103, 203: first region 105, 205: second region 107, 207: isolation structure 109, 109a, 209, 209a: Active regions 110, 210: memory 113, 213: tunneling dielectric layer 115: floating gate * 117: gate dielectric layer 119: control gates 120, 220: capacitors 123, 223: dielectric layer 125: Lower electrodes 127, 227: capacitor dielectric layer 129: upper electrode 130: metal germanide layer • 135: lower electrode plug 145: upper electrode plug 206: trench 225, 229: conductor layer 233: interlayer dielectric layer 235, 237: openings 243, 245, 247: plug 18