JP2004128134A - Ceramic multilayer substrate and its manufacturing method - Google Patents

Ceramic multilayer substrate and its manufacturing method Download PDF

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Publication number
JP2004128134A
JP2004128134A JP2002288707A JP2002288707A JP2004128134A JP 2004128134 A JP2004128134 A JP 2004128134A JP 2002288707 A JP2002288707 A JP 2002288707A JP 2002288707 A JP2002288707 A JP 2002288707A JP 2004128134 A JP2004128134 A JP 2004128134A
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cavity
ceramic
semiconductor element
laminated
laminated substrate
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JP4006686B2 (en
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Mitsuhiro Azumaguchi
東口　光博
Makoto Ota
太田　誠
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Proterial Ltd
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Hitachi Metals Ltd
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic multilayer substrate that prevents cracks with the corner of a cavity as a starting point and reliably achieves the solder junction between an electrode and a semiconductor device at a cavity bottom. <P>SOLUTION: In the ceramic multilayer substrate, baking is made after a ceramic green sheet having a suitably formed conductive material is laminated, a rectangular cavity for accommodating the semiconductor device is formed at one portion on the ceramic multilayer substrate, the electrode for heat radiation of the semiconductor device is formed on the bottom surface of the cavity, the land for I/O connection of the semiconductor device is formed at a circumference section in the upper section of the cavity, a cutout from the upper section to the bottom surface of the cavity is formed at the corner of the cavity, and an electrode for making continuity with the electrode for heat radiation formed on the bottom surface of the cavity is formed on the bottom surface of the cutout. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子などの電子部品を搭載する為のキャビティを具備したセラミック積層基板に関する。
【０００２】
【従来の技術】
従来からプラスチックやセラミックなどからなる回路基板の表面に、トランジスタ、ＦＥＴ、ダイオード、ＩＣ等の半導体素子や抵抗素子、コンデンサ素子、インダクタ素子などの電子部品を搭載した回路基板が知られている。この様な回路基板は、半導体素子や電子部品の機械的応力からの保護、電気的特性の向上、熱的な保護が要求される。最近になり、半導体素子の動作時発熱が大きくなって来ているが、この発熱は半導体素子自身及び、他の電子部品の動作に影響を及ぼすことから、前記発熱を効率的に放熱することが重要となっている。
一般的に用いられている放熱構造としては、半導体素子が実装される回路基板にキャビティを設けて、その底面に伝熱用ビアホール（以下サーマルビアと呼ぶ）を設け、前記サーマルビアを回路基板の実装面側まで延出させ、実装基板とはんだ接合して熱容量の大きな実装基板に熱を逃す構造がある。
【０００３】
上述したような回路基板においては、放熱性、電気的特性、信頼性等をはじめとして総合的に優れたセラミックが、回路基板材料として多用される。この様なセラミックとして主にＡｌ２Ｏ３が用いられて来た。
一方、携帯電話などの移動体通信分野においては、用いられる回路部品を小型化する要求が強く、コンデンサ素子、インダクタ素子などをＬＴＣＣ（ｌｏｗ　ｔｅｍｐｅｒａｔｕｒｅ　ｃｏ−ｆｉｒｅａｂｌｅ　ｃｅｒａｍｉｃｓ　ｕｓｅｄ）技術により回路基板に内蔵させたＬＣフィルタ等が広く用いられる様になってきている。
このような回路部品は、例えば１０００℃以下で焼成可能な低温焼成セラミック材料を用いて、ドクターブレード等によりキャリアフィルムに塗こう形成（キャスティング）してセラミックグリーンシートとし、所望形状に切断した前記シートに、コンデンサ素子やインダクタンス素子を構成する所望の回路パターンをＡｇやＣｕなどの導体ペーストで形成し、さらに孔開け装置によりシートの上下を貫通するビアホールを形成し、次いで、各シートに形成したビアホールに、前記回路パターンを形成した導体パターンと同じＡｇやＣｕなどの金属を主成分とする導体ペーストを印刷充填し、そして前記セラミックグリーンシートを必要枚数重ね、積層、圧着し、その後、必要な寸法に切断し、セラミックグリーンシートと導体ペーストとの同時焼成を行う事によって得られる。
【０００４】
最近、このようなＬＴＣＣ技術を前記回路基板に採用し、コンデンサ素子、インダクタ素子の一部を積層内蔵するとともにキャビティを形成して、このキャビティにベアチップ状態の半導体素子を実装する回路基板が提案されている。
以下このようなＬＴＣＣ技術を用いて構成した回路基板をセラミック積層基板と呼ぶ。
【０００５】
図５に従来のセラミック積層基板の斜視図を示す。
セラミック積層基板５１は、キャビティ５２を備え、その底面にサーマルビア５３を有し、前記キャビティ５２に半導体素子を収容して、半導体素子とサーマルビア５３とをはんだ接続するとともに、半導体素子はキャビティ５２の周縁に設けられたランド５４とワイヤボンディングを介して電気的に接続される。
キャビティに収容される半導体素子は、例えばマザー基板からダイシング加工により個片化されるため平面形状で矩形状であって、その角部はほぼ直角に形成される。前記のようなセラミック積層基板の小型化の要請や、ワイヤボンディングのワイヤによる寄生インダクタンスなどの低減による電気的特性の安定化の観点から、キャビティの内側面とそこ収容される半導体素子の外側面との間隔を小さくするように、キャビティの角部を半導体素子の様にほぼ直角となし、限られた空間の中で効率的に半導体素子を収容することが行われていた。
【０００６】
また実用新案文献１には、セラミック基板の中央部に設けた正方形又は長方形の四隅に円弧状の切欠部を有する素子搭載用のキャビティと、前記キャビティの周囲の断面上に設けた内部リードと、前記内部リードと電気的に接続する前記セラミック基板の周縁部近傍に設けた外部リードを有し、このように構成することにより、共晶接合ダイボンディング時にキャビティの四隅に生じる熱ストレス集中を緩和しクラックの発生を防止することが記載されている。
【０００７】
上述したようなセラミック積層基板を得るには、複数のセラミックグリーンシートを積層し、得られた積層体を圧着する工程を経て製造される。そして、複数のセラミックグリーンシートを順次ねる際、積層の途中から、キャビティ穴が既に設けられたセラミックグリーンシートを積重ねることが行なわれる。このようにして得られたセラミック積層体は、複数のセラミックグリーンシートの互いの間の密着性を高めデラミネーションなどの不具合が生じないように、特許文献１にはキャビティ内に所望の圧力が及ぼされるようにセラミックグリーンシートと外形寸法が同等の弾性体を用いて圧着することが開示されている。
【０００８】
【実用新案文献１】
実開平４−６５４３９号公報
【特許文献１】
特開平６−２２４５５９号公報
【０００９】
【発明が解決しようとする課題】
上述したようにキャビティの角部はほぼ直角をなしているので、セラミックグリーンシートに設けられるキャビティ穴の角部を直角となっている。セラミックグリーンシートの厚みは数十μｍ〜数百μｍと比較的薄く、かつ機械的にも弱い。このためその取り扱いによっては、キャビティの角部に亀裂が生じることがある。例えば、キャビティ穴をセラミックグリーンシートから打ち抜く際に、キャビティ穴の角部に亀裂が生じたり、圧着時にキャビティ内に作用する圧力が角部に集中し、これによって亀裂が生じることがある。
このような亀裂は、焼成後のセラミック積層基板に残り、セラミック積層基板の機械的強度を低下させたり、電気的特性の劣化を招く場合があった。
また、セラミックグリーンシートやセラミック積層体の状態で亀裂が生じない場合であっても、セラミック積層基板に衝撃が加えられたりする場合には、前記キャビティの角部に応力集中が生じて、直角となっている角部を起点として亀裂が生じたりする場合もあった。
【００１０】
また、キャビティの限られた空間の中で効率的に半導体素子を収容するように、半導体素子とキャビティ内側面との間隔を小さくすると、前記半導体素子とキャビティ底面にサーマルビアを覆うように形成された電極とはんだ接合において、十分なはんだフィレットを確保出来ないばかりか、はんだ塗布量のばらつきにより、前記電極へのはんだ塗布量が多くなる場合には、前記半導体素子とキャビティ内側面との間に余剰のはんだが流入してセラミック積層基板の表面にまで至り、ワイヤボンディングのワイヤ等との短絡を生じたりする場合もあった。
【００１１】
実用新案文献１には、キャビティの四隅に円弧状の切欠部形成することが開示されているものの、製造過程における、キャビティの角部における亀裂の発生については何等考慮されておらず、ましてや、前記半導体素子とキャビティ内側面との間に余剰のはんだが流入して生じる、ワイヤボンディングのワイヤ等との短絡についても何等考慮されていない。
このように従来、キャビティの角部を起点とした亀裂を防止し、かつキャビティ底部の電極と半導体素子とのはんだ接合を信頼性よく行えるセラミック積層基板はなかった。そこで本発明は、上述した問題点を解決し得るセラミック積層基板を得ることを目的とする。
【００１２】
【課題を解決するための手段】
本発明は、適宜導電体を形成されたセラミックグリーンシートを積層した後、焼成されてなるセラミック積層基板であって、そのセラミック積層基板の一部に半導体素子を収容する矩形状のキャビティが形成されたセラミック積層基板において、前記キャビティの底面に、前記半導体素子の放熱用電極が形成され、前記キャビティ上部の周縁部に前記半導体素子の入出力接続用ランドが形成され、前記キャビティの角部にキャビティの上部から底面に至る切欠きが形成され、前記キャビティの底面に形成された放熱用電極に導通する電極が前記切欠きの底面に形成されていることを特徴とするセラミック積層基板である。
また、本発明は、適宜導電体を形成されたセラミックグリーンシートを積層した後、焼成されてなるセラミック積層基板であって、そのセラミック積層基板の一部に半導体素子を収容する矩形状のキャビティが形成されたセラミック積層基板の製造方法において、内部に所定電極が形成された第１の積層圧着体と第２の積層圧着体を用意し、前記第１の積層圧着体の所定位置にキャビティ形成用の穴部を形成し、その後該キャビティ形成用の穴部の各角部に、円筒形状の切欠きを形成した後、前記第１の積層圧着体と第２の積層圧着体とを圧着し焼成することを特徴とするセラミック積層基板の製造方法である。
【００１３】
【発明の実施の形態】
以下、本発明を図面を参照して具体的に説明する。なおここでは説明の簡略化から、一つのセラミック積層基板に着目して図示するが、実際にはセラミックグリーンシートの同一平面上に、複数の同じ導体パターンが形成され、これを積層体とし焼成したマザー基板を分割して複数個のセラミック積層基板が得られるように構成される。
【００１４】
本発明に係る一実施例のセラミック積層基板の斜視図を図１に、その断面図を図２に、そのセラミック積層基板に半導体を実装した状態を示す模式図を図３に示す。
このセラミック積層基板１は、相対向する第１および第２の主面と当該主面間を連結する側面を備え、前記第１の主面にキャビティ２が形成され、その底部には半導体素子の放熱用電極３が形成され、また第１の主面のキャビティ２の周縁部には半導体素子とワイヤ接続される半導体素子の入出力接続用ランド４が形成されている。なお前記第１の主面にチップインダクタやチップコンデンサ、チップ抵抗などの電子部品を実装する場合には、そのための電極パターン（図示せず）が形成されてもよい。そして、キャビティ２の角部に、キャビティ２の上部から底面に至る切欠き５が形成されている。この切欠き５は、円筒形状のものであり、断面形状として３／４円状の外形に形成されている。
【００１５】
このセラミック積層基板１は、焼成により多層一体化された複数のセラミック層６を有し、前記キャビティ２の底面に形成され半導体素子用の放熱用電極３と、前記第２の主面に形成された導体パターン７とを接続する複数のサーマルビア８が形成されている。
また、セラミック層６にはコンデンサ素子やインダクタンス素子を構成する内部導体パターンが形成され、これらを電気的に接続する接続線路、ビアホールが設けられている。セラミック積層基板１の第１の主面に、電子部品を搭載するように電極パターンを適宜形成する。前記キャビティの角部には、円弧上の切欠きが形成され、前記切欠部の底面にはキャビティ２の底面に形成された放熱用電極３が延長形成されている。
そして、このセラミック積層基板１のキャビティ２に半導体素子９を搭載し、その半導体素子の底面と放熱用電極３とが半田付けされ、半導体素子の入出力とセラミック積層基板１の入出力接続用ランド４とがワイヤ１０で接続される。このとき、半導体素子の底面と放熱用電極３との半田付け用の半田１０の余分は切欠き５に収容される。
【００１６】
本発明に係る一実施例のセラミック積層基板の製造方法のフロー図を図４に示す。
まず、低温焼成セラミック材料と適量の有機バインダや有機溶剤と共に混合し、これをキャリアフィルム上にドクターブレート法によってキャスティングして、セラミックグリーンシートを成形した。前記キャリアフィルムは、例えばポリエステル、ポリエチレンテレフタレートで出来ており、熱的安定性、機械的強度にすぐれており、柔らかいセラミックグリーンシートを保持するのに適している。前記低温焼成セラミック材料として、Ａｌ−Ｓｉ−Ｂａ−Ｏ系誘電体材料を用いた。セラミックグリーンシートの厚さは、コンデンサ素子が形成される場合にはセラミック層厚さで２５μｍとし、他の層には１００〜１５０μｍのものを用いた。なお、セラミック層厚さは適宜設定されるものであり、前記厚さに限定されるものではないが、好ましくは１０〜１５０μｍの範囲で選択する。
【００１７】
低温焼成セラミック材料として、例えば低誘電率（比誘電率５〜１０）のＡｌ−Ｍｇ−Ｓｉ−Ｇｄ−Ｏ系誘電体材料、Ｍｇ２ＳＯ４からなる結晶相とＳｉ−Ｂａ−Ｌａ−Ｂ−Ｏ系からなるガラス等からなる誘電体材料、Ａｌ−Ｓｉ−Ｓｒ−Ｏ系誘電体材料、Ａｌ−Ｓｉ−Ｂａ−Ｏ系誘電体材料、高誘電率（比誘電率５０以上）のＢｉ−Ｃａ−Ｎｂ−Ｏ系誘電体材料等様々な材料が開発されている。セラミック積層基板には、これらの低温焼成セラミック材料を単独で使用する場合もあるし、インダクタンス素子、コンデンサ素子を構成するセラミック層に応じて低誘電率の材料、高誘電率の材料を選択的に用いる場合もある。
【００１８】
次に、キャスティングされたセラミックグリーンシートをキャリアフィルムごと切断し、その一部のセラミックグリーンシートにビアホールを形成する。ビアホールは、セラミックグリーンシート側からＣＯ２レーザを照射して、照射面側の孔径がセラミック層としたときに０．０５ｍｍ〜０．３ｍｍとなる、円筒又は略円錐形状を有するビアホールを形成する。前記ビアホールは、積層配置される回路素子間の接続とともに、キャビティ底部に形成される電極と接続され、電気的な接続と放熱の為のサーマルビアに用いられる。
【００１９】
サーマルビアの孔径はレーザのスポット径により決定され、またサーマルビアの断面形状は、レーザ出力により台形状から矩形状など適宜設定できる。またセラミックグリーンシート及び支持フィルムは可撓性を有するものであるから、セラミックグリーンシートに撓みなどが生じないように前記孔開けの際には、非可撓性の支持板を用い、前記支持板に支持フィルム一体のセラミックグリーンシートを配置し、セラミックグリーンシート側からレーザを照射するのが好ましい。
【００２０】
次に、セラミックグリーンシートに形成されたビアホールに導体ペーストを埋込む。導体ペーストとしては銀，銅等が用いられ、メタルマスク又はメッシュマスクによるスクリーン印刷によってビアホール部に埋込まれる。
【００２１】
次に、セラミックグリーンシートの表面にインダクタンス素子やコンデンサ素子を構成する回路パターン、インダクタンス素子やコンデンサ素子等を接続する接続電極を形成するとともに、セラミックグリーンシートに形成されたビアホールの内、サーマルビアとなる複数のビアホールを電気的接続するように、内部金属導体層を形成する。信号配線、及び電源配線の導体パターンを形成する導体ペースト材はビアホール部と同じものを用いても良いし、異なるものを用いても良い。なお、導体パターンの形成と前記ビアホールへの導体ペーストの充填を同時に行ってもよい。
【００２２】
以上の様にして、キャリアフィルムを付けたままセラミックグリーンシートを作成した。そして、これを積層用金型に配置するが、前記金型の下側金型には吸着孔が形成されており、これにより最下層となるセラミックグリーンシートをキャリアフィルムが付いたまま、かつキャリアフィルムを積層治具側として吸着固定する。
【００２３】
そして、キャリアフィルムを付けたままセラミックグリーンシートを、セラミックグリーンシートが相対向するようにして積層し、熱圧着させ、キャリアフィルムをとり除く。これを数次繰り返し、さらにサーマルビアを覆うように、かつ後述する第１の積層圧着体に形成される切欠きの底面となる部分をも覆うように放熱用電極３を印刷形成した。これをＣＩＰして第２の積層圧着体４２とした。この第２の積層圧着体４２を図４（ｃ）に示す。
なお、最下層となるセラミックグリーンシートは、粘着性を備えるフィルムを積層用金型に固定し、セラミックグリーンシートを粘着面に積層し、貼着させて固定しても良い。
【００２４】
第２の積層圧着体４２と同様の製造方法を用いて、表面に半導体素子の入出力接続用ランド４が形成された第１の積層圧着体４１を構成する。（図４（ａ））次いで、第１の積層圧着体４１を金型で打ち抜いてキャビティ部４３を形成した。（図４（ｂ））
そしてキャビティ部４３の４隅をφ０．４のパンチを用いて打ち抜き、切欠き４４を形成した。（図４（ｃ））
【００２５】
各セラミックグリーンシートの状態でキャビティ部を形成すると、シートが薄いため、キャビティ部の角部で亀裂が生じ易いが、この積層圧着体を形成した後に、キャビティ部を形成することにより、キャビティ部の角部の亀裂を生じ難くしている。
また、多少亀裂が生じても、切欠きを形成することにより、取り除くことができる。
また、切欠きを後で形成することにより、キャビティ打ち抜き金型の角部と対応する稜部のＲを大きくとることができ、亀裂の発生防止が出来る。
この切欠き部はレーザで形成してもよく、形状も適宜変更できる。
【００２６】
その後、第１の積層圧着体と第２の積層圧着体を金型に配置して、５０℃、１４０ｋｇ／ｃｍ２の圧力で圧着して一体化し、セラミックグリーンシート積層体を形成した。（図４（ｄ））
この第１の積層圧着体と第２の積層圧着体とは既にＣＩＰされており、この第１の積層圧着体と第２の積層圧着体を重ねて圧着する場合、キャビティ内部まで圧力を作用させる必要がない。これによってもセラミック積層基板に亀裂が発生しにくくできる。
【００２７】
そして、セッタ等の焼成治具上に配置して大気中９００℃で焼成した。なお導体ペーストとしてＣｕを用いる場合には、所定のガス雰囲気中（還元雰囲気）で焼成する。このようにして、セラミックグリーンシートと導体ペーストとを同時焼成することで、本発明のセラミック積層基板１を得た。（図４（ｅ））
【００２８】
このセラミック積層基板１に半導体素子を搭載し、キャビティ２底部の放熱用電極３と半導体素子を３００℃ではんだ接合し、キャビティ２の角部を４０倍の実体顕微鏡で確認したが、亀裂の発生は認められなかった。
また、前記キャビティ２の４隅部にはんだフィレットが形成され、半導体素子との接続を信頼性良く行うことが出来た。
【００２９】
本発明によれば、キャビティの角部に切欠きを設けたことにより、キャビティ寸法を搭載される半導体素子寸法に近づけることができる。これは、セラミック積層基板にキャビティを形成する場合、その角部を９０度に形成することは困難であり、半導体素子の角を収納するためにキャビティ幅を大きくする必要があること、またセラミック積層基板のキャビティの角部を９０度に近づけて行くと、亀裂を生じ易くなるが、キャビティの角部に切欠きを形成することにより、これらを改善し、キャビティの幅を狭く出来る。これにより、本発明のセラミック積層基板では、キャビティの幅をＡとし、半導体素子の幅Ｂとしたとき、キャビティの幅ＡをＢ＋０．０４ｍｍ〜Ｂ＋０．１ｍｍの範囲に設定することができた。
【００３０】
【発明の効果】
本発明によれば、キャビティの角部を起点とする亀裂を防止し、かつキャビティ幅と半導体素子とのクリアランスを小さくする事が可能となる。また、半導体素子の放熱性を高める電極をキャビティ底部に形成し、その放熱用電極と半導体素子との半田付けの際、半田が流出し、不具合を生じさせることを防止することができる。これにより、半導体素子を搭載するためのキャビティを有するセラミック積層基板として、有用なものを提供することができる。
【図面の簡単な説明】
【図１】本発明に係る一実施例のセラミック積層基板の斜視図である。
【図２】本発明に係る一実施例のセラミック積層基板の断面図である。
【図３】本発明に係る一実施例のセラミック積層基板に半導体を実装した状態を示す模式図である。
【図４】本発明に係る一実施例のセラミック積層基板の製造方法のフロー図である。
【図５】従来のセラミック積層基板の斜視図である。
【符号の説明】
１　セラミック積層基板
２　キャビティ
３　放熱用電極
４　入出力接続用ランド
５　切欠き
６　セラミック層
７　導体パターン
８　サーマルビア
９　半導体素子
１０　ワイヤ
１１　半田
４１　第１の積層圧着体
４２　第２の積層圧着体
４３　キャビティ部
４４　切欠き[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ceramic laminated substrate having a cavity for mounting an electronic component such as a semiconductor element.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a circuit board on which a semiconductor element such as a transistor, an FET, a diode, and an IC and electronic components such as a resistor element, a capacitor element, and an inductor element are mounted on a surface of a circuit board made of plastic or ceramic. Such a circuit board is required to protect semiconductor elements and electronic components from mechanical stress, to improve electrical characteristics, and to thermally protect them. Recently, heat generation during operation of a semiconductor element has been increasing. However, since this heat affects the operation of the semiconductor element itself and other electronic components, the heat can be efficiently radiated. It is important.
As a generally used heat radiation structure, a cavity is provided in a circuit board on which a semiconductor element is mounted, and a via hole for heat transfer (hereinafter referred to as a thermal via) is provided on a bottom surface thereof, and the thermal via is connected to the circuit board. There is a structure that extends to the mounting surface side and solders to the mounting substrate to release heat to the mounting substrate having a large heat capacity.
[0003]
In the circuit board as described above, ceramics which are comprehensively excellent in heat dissipation, electrical characteristics, reliability and the like are frequently used as circuit board materials. Al 2 O 3 has been mainly used as such a ceramic.
On the other hand, in the field of mobile communications such as mobile phones, there is a strong demand for miniaturization of circuit components used, and capacitor elements, inductor elements, and the like are built in circuit boards using low temperature co-fireable ceramics (LTCC) technology. LC filters and the like have been widely used.
Such a circuit component is formed, for example, by coating a carrier film with a doctor blade or the like using a low-temperature fired ceramic material that can be fired at 1000 ° C. or less to form a ceramic green sheet, and cutting the sheet into a desired shape. Then, a desired circuit pattern for forming a capacitor element or an inductance element is formed of a conductive paste such as Ag or Cu, and further, a via hole is formed through a top and a bottom of the sheet by a punching device, and then a via hole formed on each sheet is formed. Is printed and filled with a conductive paste mainly composed of a metal such as Ag or Cu, which is the same as the conductive pattern on which the circuit pattern has been formed. Cut into ceramic green sheets and conductive paste Obtained by performing the time of firing.
[0004]
Recently, a circuit board has been proposed in which such LTCC technology is adopted for the circuit board, a part of the capacitor element and the inductor element is stacked and formed, a cavity is formed, and a semiconductor element in a bare chip state is mounted in the cavity. ing.
Hereinafter, a circuit board formed using such LTCC technology is referred to as a ceramic laminated board.
[0005]
FIG. 5 shows a perspective view of a conventional ceramic laminated substrate.
The ceramic laminated substrate 51 has a cavity 52 and a thermal via 53 on the bottom surface. A semiconductor element is accommodated in the cavity 52, and the semiconductor element and the thermal via 53 are connected by soldering. Are electrically connected to the lands 54 provided on the peripheral edge thereof through wire bonding.
The semiconductor elements housed in the cavities are singulated by dicing from a mother substrate, for example, so that the semiconductor elements are planar and rectangular in shape, and the corners are formed substantially at right angles. From the viewpoint of the demand for miniaturization of the ceramic laminated substrate as described above and the stabilization of the electrical characteristics by reducing the parasitic inductance and the like caused by wire bonding, the inner surface of the cavity and the outer surface of the semiconductor element housed therein are reduced. The corners of the cavity are made substantially perpendicular like semiconductor elements so as to reduce the distance between the semiconductor elements, and the semiconductor elements are efficiently accommodated in a limited space.
[0006]
Further, Utility Model Document 1 discloses a device mounting cavity having an arc-shaped notch at each of four square or rectangular corners provided at the center of a ceramic substrate, an internal lead provided on a cross section around the cavity, It has external leads provided in the vicinity of the periphery of the ceramic substrate electrically connected to the internal leads.With this configuration, it is possible to reduce the concentration of thermal stress generated at the four corners of the cavity during eutectic bonding die bonding. It is described that the occurrence of cracks is prevented.
[0007]
In order to obtain the above-described ceramic laminated substrate, a plurality of ceramic green sheets are laminated, and the resulting laminated body is subjected to pressure bonding. Then, when a plurality of ceramic green sheets are successively kneaded, the ceramic green sheets having the cavity holes already provided are stacked in the middle of the lamination. In the ceramic laminate obtained in this way, a desired pressure is applied to the cavity in Patent Literature 1 so that a plurality of ceramic green sheets can be adhered to each other so that a problem such as delamination does not occur. It is disclosed that an elastic body having the same outer dimensions as the ceramic green sheet is used for pressure bonding.
[0008]
[Utility model document 1]
Japanese Utility Model Publication No. 4-65439 [Patent Document 1]
JP-A-6-224559
[Problems to be solved by the invention]
As described above, since the corners of the cavity are substantially perpendicular, the corners of the cavity holes provided in the ceramic green sheet are perpendicular. The thickness of the ceramic green sheet is relatively thin, several tens μm to several hundred μm, and is mechanically weak. For this reason, cracks may occur at the corners of the cavity depending on the handling. For example, when the cavity hole is punched from the ceramic green sheet, a crack may be generated at the corner of the cavity hole, or the pressure acting in the cavity at the time of pressing may be concentrated on the corner, which may cause a crack.
Such cracks may remain on the fired ceramic laminated substrate, resulting in a decrease in mechanical strength of the ceramic laminated substrate or deterioration of electrical characteristics.
Further, even when cracks do not occur in the state of the ceramic green sheet or the ceramic laminate, when an impact is applied to the ceramic laminated substrate, stress concentration occurs at the corners of the cavity, and In some cases, cracks were formed starting from the corners where they were formed.
[0010]
Further, when the space between the semiconductor element and the inner surface of the cavity is reduced so that the semiconductor element is efficiently accommodated in the limited space of the cavity, the semiconductor element and the bottom surface of the cavity are formed so as to cover the thermal via. In addition to not being able to secure a sufficient solder fillet in the electrode and solder joints, if the amount of solder applied to the electrode increases due to the variation in the amount of solder applied, the gap between the semiconductor element and the inner surface of the cavity is increased. In some cases, excess solder flows in and reaches the surface of the ceramic laminated substrate, causing a short circuit with a wire or the like for wire bonding.
[0011]
Although Utility Model Document 1 discloses that arc-shaped notches are formed at the four corners of the cavity, no consideration is given to the occurrence of cracks at the corners of the cavity during the manufacturing process. No consideration is given to a short circuit between the semiconductor element and the inner surface of the cavity, which occurs when excess solder flows in between the semiconductor element and the wire bonding wire.
As described above, there has hitherto been no ceramic laminated substrate that can prevent cracks originating from the corners of the cavity and that can reliably connect the electrode at the bottom of the cavity to the semiconductor element by soldering. Therefore, an object of the present invention is to provide a ceramic laminated substrate that can solve the above-mentioned problems.
[0012]
[Means for Solving the Problems]
The present invention is a ceramic laminated substrate obtained by appropriately laminating ceramic green sheets on which conductors are formed, and firing the green sheets, wherein a rectangular cavity for housing a semiconductor element is formed in a part of the ceramic laminated substrate. In the ceramic laminated substrate, a heat radiation electrode of the semiconductor element is formed on a bottom surface of the cavity, an input / output connection land of the semiconductor element is formed on a peripheral portion of an upper portion of the cavity, and a cavity is formed on a corner of the cavity. A notch extending from the upper portion to the bottom surface, and an electrode that is connected to a heat radiation electrode formed on the bottom surface of the cavity is formed on the bottom surface of the notch.
Further, the present invention is a ceramic laminated substrate obtained by laminating ceramic green sheets on which conductors are appropriately formed and then firing the laminated ceramic green sheets, and a rectangular cavity for accommodating a semiconductor element is provided in a part of the ceramic laminated substrate. In the method for manufacturing the formed ceramic laminated substrate, a first laminated pressure-bonded body and a second laminated pressure-bonded body each having a predetermined electrode formed therein are prepared, and a cavity is formed at a predetermined position of the first laminated pressure-bonded body. Then, after forming a cylindrical notch at each corner of the cavity forming hole, the first laminated pressure-bonded body and the second laminated pressure-bonded body are pressed and fired. This is a method for manufacturing a ceramic laminated substrate.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings. Here, for the sake of simplicity of description, the illustration is made by focusing on one ceramic laminated substrate, but actually, a plurality of the same conductor patterns are formed on the same plane of the ceramic green sheet, and this is laminated and fired. The mother substrate is divided so that a plurality of ceramic laminated substrates can be obtained.
[0014]
FIG. 1 is a perspective view of a ceramic laminated substrate according to an embodiment of the present invention, FIG. 2 is a cross-sectional view thereof, and FIG. 3 is a schematic diagram showing a state where a semiconductor is mounted on the ceramic laminated substrate.
The ceramic laminated substrate 1 includes first and second main surfaces opposed to each other and side surfaces connecting the main surfaces, a cavity 2 is formed in the first main surface, and a bottom of the cavity 2 A heat radiation electrode 3 is formed, and an input / output connection land 4 of the semiconductor element to be connected to the semiconductor element by wire is formed on a peripheral portion of the cavity 2 on the first main surface. When electronic components such as a chip inductor, a chip capacitor, and a chip resistor are mounted on the first main surface, an electrode pattern (not shown) for that may be formed. At the corner of the cavity 2, a notch 5 is formed from the top to the bottom of the cavity 2. The notch 5 has a cylindrical shape, and is formed in a 3/4 circular outer shape as a cross-sectional shape.
[0015]
The ceramic laminated substrate 1 has a plurality of ceramic layers 6 integrated by firing, and is formed on a bottom surface of the cavity 2 and a heat radiation electrode 3 for a semiconductor element, and formed on the second main surface. A plurality of thermal vias 8 connecting the conductive patterns 7 are formed.
Further, the ceramic layer 6 is formed with an internal conductor pattern constituting a capacitor element and an inductance element, and is provided with connection lines and via holes for electrically connecting these. An electrode pattern is appropriately formed on the first main surface of the ceramic laminated substrate 1 so as to mount electronic components. An arc-shaped notch is formed at the corner of the cavity, and a radiation electrode 3 formed on the bottom of the cavity 2 is extended from the bottom of the notch.
Then, the semiconductor element 9 is mounted in the cavity 2 of the ceramic laminated substrate 1, and the bottom surface of the semiconductor element and the heat radiation electrode 3 are soldered, so that the input / output of the semiconductor element and the input / output connection land of the ceramic laminated substrate 1 are formed. 4 are connected by a wire 10. At this time, the excess solder 10 for soldering between the bottom surface of the semiconductor element and the heat radiation electrode 3 is accommodated in the notch 5.
[0016]
FIG. 4 shows a flowchart of a method for manufacturing a ceramic laminated substrate according to one embodiment of the present invention.
First, a low temperature fired ceramic material was mixed with an appropriate amount of an organic binder and an organic solvent, and this was cast on a carrier film by a doctor blade method to form a ceramic green sheet. The carrier film is made of, for example, polyester or polyethylene terephthalate, has excellent thermal stability and mechanical strength, and is suitable for holding a soft ceramic green sheet. An Al-Si-Ba-O-based dielectric material was used as the low-temperature fired ceramic material. The thickness of the ceramic green sheet was 25 μm in the thickness of the ceramic layer when the capacitor element was formed, and the thickness of the other layers was 100 to 150 μm. The thickness of the ceramic layer is appropriately set and is not limited to the above-mentioned thickness, but is preferably selected in the range of 10 to 150 μm.
[0017]
Examples of the low-temperature fired ceramic material include an Al-Mg-Si-Gd-O-based dielectric material having a low dielectric constant (relative dielectric constant of 5 to 10), a crystal phase composed of Mg2SO4, and a Si-Ba-La-BO-based material. Dielectric material made of glass or the like, Al-Si-Sr-O-based dielectric material, Al-Si-Ba-O-based dielectric material, Bi-Ca-Nb- having a high dielectric constant (relative dielectric constant of 50 or more) Various materials such as O-based dielectric materials have been developed. These low-temperature fired ceramic materials may be used alone for the ceramic laminated substrate, or a material with a low dielectric constant or a material with a high dielectric constant may be selectively used according to the ceramic layers constituting the inductance element and the capacitor element. Sometimes used.
[0018]
Next, the cast ceramic green sheet is cut together with the carrier film, and a via hole is formed in a part of the ceramic green sheet. The via hole is formed by irradiating a CO2 laser from the ceramic green sheet side to form a via hole having a cylindrical or substantially conical shape having a hole diameter on the irradiation surface side of 0.05 mm to 0.3 mm when a ceramic layer is formed. The via hole is connected to an electrode formed at the bottom of the cavity together with connection between the circuit elements arranged in a stack, and is used as a thermal via for electrical connection and heat radiation.
[0019]
The hole diameter of the thermal via is determined by the spot diameter of the laser, and the cross-sectional shape of the thermal via can be appropriately set from a trapezoidal shape to a rectangular shape depending on the laser output. In addition, since the ceramic green sheet and the support film have flexibility, a non-flexible support plate is used when the hole is formed so that the ceramic green sheet does not bend, and the support plate is used. It is preferable that a ceramic green sheet integrated with a support film is disposed on the substrate and the laser is irradiated from the ceramic green sheet side.
[0020]
Next, a conductive paste is buried in the via holes formed in the ceramic green sheet. Silver, copper, or the like is used as the conductive paste, and is embedded in the via hole by screen printing using a metal mask or a mesh mask.
[0021]
Next, on the surface of the ceramic green sheet, a circuit pattern for forming the inductance element and the capacitor element, connection electrodes for connecting the inductance element and the capacitor element, etc. are formed. An internal metal conductor layer is formed so as to electrically connect the plurality of via holes. The conductor paste material for forming the conductor pattern of the signal wiring and the power supply wiring may be the same as or different from that of the via hole. The formation of the conductive pattern and the filling of the via hole with the conductive paste may be performed simultaneously.
[0022]
As described above, a ceramic green sheet was prepared with the carrier film attached. Then, this is arranged in a lamination mold, and a suction hole is formed in the lower mold of the mold, so that the ceramic green sheet to be the lowermost layer is provided with the carrier film, and The film is suction-fixed as the stacking jig side.
[0023]
Then, the ceramic green sheets are laminated with the carrier film attached so that the ceramic green sheets are opposed to each other, and thermocompression-bonded to remove the carrier film. This was repeated several times, and the heat radiation electrode 3 was formed by printing so as to cover the thermal via and also to cover a portion serving as a bottom surface of a notch formed in a first laminated pressure-bonded body described later. This was subjected to CIP to obtain a second laminated pressure-bonded body 42. FIG. 4C shows the second laminated pressure-bonded body 42.
The ceramic green sheet serving as the lowermost layer may be fixed by fixing a film having an adhesive property to a laminating mold, laminating the ceramic green sheet on an adhesive face, and attaching and sticking.
[0024]
Using the same manufacturing method as that of the second laminated pressure-bonded body 42, the first laminated pressure-bonded body 41 having the input / output connection lands 4 of the semiconductor element formed on the surface thereof is formed. (FIG. 4A) Next, the first laminated pressure-bonded body 41 was punched out with a mold to form a cavity 43. (FIG. 4 (b))
Then, four corners of the cavity 43 were punched out using a φ0.4 punch to form a notch 44. (FIG. 4 (c))
[0025]
If the cavity is formed in the state of each ceramic green sheet, cracks are likely to occur at the corners of the cavity because the sheet is thin, but after forming the laminated pressure-bonded body, the cavity is formed, so that the cavity is formed. Cracks in corners are less likely to occur.
Also, even if some cracks occur, they can be removed by forming notches.
In addition, by forming the notch later, it is possible to increase the R of the ridge corresponding to the corner of the cavity punching die, thereby preventing the occurrence of cracks.
This notch may be formed by laser, and the shape may be changed as appropriate.
[0026]
After that, the first laminated pressure-bonded body and the second laminated pressure-bonded body were placed in a mold, pressed and integrated at 50 ° C. and a pressure of 140 kg / cm 2 to form a ceramic green sheet laminated body. (FIG. 4 (d))
The first laminated pressure-bonded body and the second laminated pressure-bonded body have already been subjected to CIP. When the first laminated pressure-bonded body and the second laminated pressure-bonded body are laminated and pressure-bonded, pressure is applied to the inside of the cavity. No need. This also makes it difficult for the ceramic laminated substrate to crack.
[0027]
Then, it was placed on a firing jig such as a setter and fired at 900 ° C. in the atmosphere. When Cu is used as the conductor paste, firing is performed in a predetermined gas atmosphere (reducing atmosphere). Thus, the ceramic green sheet and the conductive paste were simultaneously fired, whereby the ceramic laminated substrate 1 of the present invention was obtained. (FIG. 4 (e))
[0028]
A semiconductor element was mounted on the ceramic laminated substrate 1, and the heat radiation electrode 3 at the bottom of the cavity 2 and the semiconductor element were soldered at 300 ° C., and the corners of the cavity 2 were confirmed with a stereoscopic microscope of 40 ×. Was not found.
Further, solder fillets were formed at the four corners of the cavity 2, so that the connection with the semiconductor element could be performed with high reliability.
[0029]
According to the present invention, by providing the notch at the corner of the cavity, the size of the cavity can be made close to the size of the semiconductor element to be mounted. This is because, when a cavity is formed in a ceramic laminated substrate, it is difficult to form the corner at 90 degrees, and it is necessary to increase the cavity width to accommodate the corner of the semiconductor element. When the corners of the cavity of the substrate are made closer to 90 degrees, cracks tend to occur. However, by forming notches in the corners of the cavity, these can be improved and the width of the cavity can be reduced. Thus, in the ceramic laminated substrate of the present invention, when the width of the cavity is A and the width of the semiconductor element is B, the width A of the cavity can be set in the range of B + 0.04 mm to B + 0.1 mm.
[0030]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to prevent the crack originating from the corner part of a cavity, and to reduce the clearance between a cavity width and a semiconductor element. In addition, an electrode that enhances the heat dissipation of the semiconductor element is formed at the bottom of the cavity, and when the heat dissipation electrode is soldered to the semiconductor element, it is possible to prevent the solder from flowing out and causing a problem. Thereby, a useful ceramic laminated substrate having a cavity for mounting a semiconductor element can be provided.
[Brief description of the drawings]
FIG. 1 is a perspective view of a ceramic laminated substrate according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a ceramic laminated substrate according to one embodiment of the present invention.
FIG. 3 is a schematic view showing a state in which a semiconductor is mounted on a ceramic laminated substrate according to one embodiment of the present invention.
FIG. 4 is a flowchart of a method for manufacturing a ceramic laminated substrate according to one embodiment of the present invention.
FIG. 5 is a perspective view of a conventional ceramic laminated substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Ceramic laminated board 2 Cavity 3 Heat radiation electrode 4 I / O connection land 5 Notch 6 Ceramic layer 7 Conductive pattern 8 Thermal via 9 Semiconductor element 10 Wire 11 Solder 41 First laminated crimped body 42 Second laminated crimped body 43 Cavity 44 Notch

Claims (2)

適宜導電体を形成されたセラミックグリーンシートを積層した後、焼成されてなるセラミック積層基板であって、そのセラミック積層基板の一部に半導体素子を収容する矩形状のキャビティが形成されたセラミック積層基板において、前記キャビティの底面に、前記半導体素子の放熱用電極が形成され、前記キャビティ上部の周縁部に前記半導体素子の入出力接続用ランドが形成され、前記キャビティの角部にキャビティの上部から底面に至る切欠きが形成され、前記キャビティの底面に形成された放熱用電極に導通する電極が前記切欠きの底面に形成されていることを特徴とするセラミック積層基板。A ceramic laminated substrate formed by appropriately laminating ceramic green sheets on which conductors are formed and then firing, wherein a rectangular cavity for accommodating a semiconductor element is formed in a part of the ceramic laminated substrate. A heat radiation electrode of the semiconductor element is formed on a bottom surface of the cavity, an input / output connection land of the semiconductor element is formed on a peripheral portion of an upper portion of the cavity, A ceramic laminate substrate, wherein a notch leading to a bottom surface of the cavity is formed, and an electrode conducting to a heat radiation electrode formed on a bottom surface of the cavity is formed on a bottom surface of the notch. 適宜導電体を形成されたセラミックグリーンシートを積層した後、焼成されてなるセラミック積層基板であって、そのセラミック積層基板の一部に半導体素子を収容する矩形状のキャビティが形成されたセラミック積層基板の製造方法において、内部に所定電極が形成された第１の積層圧着体と第２の積層圧着体を用意し、前記第１の積層圧着体の所定位置にキャビティ形成用の穴部を形成し、その後該キャビティ形成用の穴部の各角部に、円筒形状の切欠きを形成した後、前記第１の積層圧着体と第２の積層圧着体とを圧着し焼成することを特徴とするセラミック積層基板の製造方法。A ceramic laminated substrate formed by appropriately laminating ceramic green sheets on which conductors are formed and then firing, wherein a rectangular cavity for accommodating a semiconductor element is formed in a part of the ceramic laminated substrate. In the manufacturing method, a first laminated pressure-bonded body and a second laminated pressure-bonded body each having a predetermined electrode formed therein are prepared, and a hole for forming a cavity is formed at a predetermined position of the first laminated pressure-bonded body. Then, after forming a cylindrical notch at each corner of the cavity forming hole, the first laminated pressure-bonded body and the second laminated pressure-bonded body are pressed and fired. A method for manufacturing a ceramic laminated substrate.
JP2002288707A 2002-10-01 2002-10-01 Ceramic multilayer substrate and manufacturing method thereof Expired - Lifetime JP4006686B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192863A (en) * 2007-02-06 2008-08-21 Sumitomo Metal Electronics Devices Inc Ceramic cover
JP2009105345A (en) * 2007-10-25 2009-05-14 Ngk Spark Plug Co Ltd Wiring substrate with built-in plate-like component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192863A (en) * 2007-02-06 2008-08-21 Sumitomo Metal Electronics Devices Inc Ceramic cover
JP2009105345A (en) * 2007-10-25 2009-05-14 Ngk Spark Plug Co Ltd Wiring substrate with built-in plate-like component

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