JP2009105345A - Wiring substrate with built-in plate-like component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate with a built-in plate-like component which is superior in reliability, by increasing the contact area of a housing hole and resin filler, and thereby surely absorbing the stress acting between the housing hole and a plate-like member. <P>SOLUTION: A wring substrate with a built-in ceramic capacitor comprises a core substrate 11 and a ceramic capacitor 101, which is housed in a housing hole 91 of the core substrate 11. The ceramic capacitor 101 is fixed to the core substrate 11, by filling the clearance between the inner surface of the housing hole 91 and the side surface of the ceramic capacitor 101 with resin filler 92. The visible outline of the housing hole 91 is formed into a concavo-convex shape, in plan view. A concave recess 93, the aperture width L1 of which is set to be larger than the width L2 of a chamfer 107, is provided at a position opposed to the chamfer 107 of the ceramic capacitor 101, in the inner surface of the housing hole 91. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board with a built-in plate-like component in which a plate-like component is accommodated inside a core substrate.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, generally, a technique is adopted in which an IC chip is mounted on an IC chip mounting wiring board, and the IC chip mounting wiring board is mounted on a motherboard. In this type of IC chip mounting wiring board, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and to stabilize the power supply voltage. As an example, a wiring substrate in which a ceramic capacitor is embedded in a core substrate made of a polymer material and buildup layers are formed on the front surface and the back surface of the core substrate has been conventionally proposed (for example, see Patent Documents 1 and 2). .

FIG. 15 shows a conventional IC chip mounting wiring board 200 described in Patent Document 1. In FIG. The IC chip mounting wiring substrate 200 includes a flat core substrate 201 made of glass epoxy, and build-up layers 202 and 203 formed on the upper and lower surfaces of the core substrate 201. The core substrate 201 has a housing hole 205 that opens at the upper surface and the lower surface, and the ceramic chip 206 is housed in the housing hole 205. In this IC chip mounting wiring board 200, the ceramic chip 206 is fixed by filling a gap between the inner surface of the accommodation hole 205 and the side surface of the ceramic chip 206 with a resin filler 207. When the IC chip 208 is mounted on the wiring board 200, a stress is generated between the ceramic chip 206 and the receiving hole 205 due to a temperature change after soldering. By interposing the resin filler 207 between the two, the stress is absorbed. As shown in FIGS. 15 and 16, the accommodation hole 205 is a through-hole penetrating in the thickness direction of the wiring board 200, and is formed in a substantially rectangular shape in plan view. The accommodation hole 205 has a linear quadrilateral shape with no irregularities on the inner periphery, and chamfered portions 209 are formed at the corners. By forming the chamfered portion 209, bubbles are prevented from being formed at the corners of the accommodation hole 205 when the resin filler 207 is filled.
JP 2006-253668 A JP 200495851 A

  However, in order to reliably absorb stress due to temperature change or the like in the wiring substrate 200, it is necessary to enlarge the accommodation hole 205 and fill the gap with the ceramic chip 206 with a sufficient resin filler 207. If the accommodation hole 205 is enlarged, a space for providing a wiring pattern on the wiring board 200 is reduced. For this reason, the gap between the accommodation hole 205 and the ceramic chip 206 is desired to be as narrow as possible. However, if the gap is narrowed, it becomes difficult to fill the resin filler 207, and the resin filler 207 can be reliably filled to the lower part of the gap. become unable. In this case, the absorption of stress acting between the ceramic chip 206 and the accommodation hole 205 becomes insufficient, and the reliability of the wiring board 200 is lowered.

  Incidentally, in the wiring board of Patent Document 2, a concave groove and a concave groove conductor are formed on the side surface of the accommodation hole for accommodating the capacitor. These concave grooves are formed for the purpose of conduction and are relatively small in size. Therefore, even if the inner side of the concave groove (concave groove conductor) is filled with the filler, the stress cannot be sufficiently absorbed. Further, in the ceramic chip built-in wiring board, stress is concentrated most at the corner of the ceramic chip, but no concave groove is formed at a position corresponding to the corner.

  The present invention has been made in view of the above problems, and its purpose is to increase the contact area between the accommodation hole and the resin filler, thereby ensuring the stress acting between the accommodation hole and the plate-like member. It is an object of the present invention to provide a wiring board with a built-in plate-like component that absorbs heat and has excellent reliability.

  And as means (means 1) for solving the above-mentioned problems, there are a core substrate having a core main surface and a core back surface, and having an accommodation hole opening at the core main surface and the core back surface, and a component first It has a substantially rectangular shape in plan view having a main surface and a component second main surface, its four corners are chamfered, the component first main surface faces the core main surface side, and the component second main surface faces the core back surface. The plate-like component is fixed to the core substrate by filling a gap between the plate-like component housed in the housing hole portion in a state directed toward the side and the inner surface of the housing hole portion and the side surface of the plate-like component. And the resin filler, the outer shape line of the accommodation hole is formed in a concavo-convex shape in a plan view, and at the position facing the chamfered portion of the plate-shaped part at least on the inner surface of the accommodation hole, A recess whose opening width is set longer than the width of the chamfered portion. The relief portion is provided there is a plate-like component-incorporated wiring substrate according to claim.

  Therefore, according to the plate-like component built-in wiring board of means 1, since the outline of the accommodation hole is formed in an uneven shape in plan view, the contact area between the inner surface of the accommodation hole and the resin filler is increased. be able to. In addition, the stress is most concentrated on the chamfered portions formed at the four corners of the plate-like component, but at the position corresponding to the chamfered portion, a concave relief portion having an opening width longer than the width of the chamfered portion is provided. ing. If comprised in this way, the stress which acts between a plate-shaped component and an accommodation hole part can be reliably absorbed with a resin filler. In addition, the adhesion between the resin filler and the inner surface of the accommodation hole is increased, and the plate-like component can be reliably fixed to the core substrate by the anchor effect.

  It is preferable that the opening in the concave relief portion has a curvilinear shape. In this way, stress does not concentrate on the opening in the concave relief portion, and the stress can be reliably absorbed by the entire concave relief portion.

  It is preferable that the outer shape line of the accommodation hole portion has a wavy shape composed of a continuous curve. In this way, since there is no corner on the contact surface between the accommodation hole and the resin filler, it is possible to reliably fill the resin filler without generating voids. Therefore, stress can be reliably absorbed by the resin filler, and generation of cracks can be prevented.

  It is preferable that the accommodation hole portion is formed so that an opening area becomes wider toward a filling side where the resin filler is filled. If it does in this way, the resin filler can be reliably filled in the clearance gap between an accommodation hole part and plate-shaped components. Further, when the semiconductor integrated circuit element is flip-chip connected to the wiring board, the core substrate tends to warp to the back side of the core during cooling after soldering, and the plate-like component cannot follow the warpage. In this case, the stress concentrates on the back side of the core, but since the resin filler interposed between the receiving hole and the plate-like component becomes thicker on the back side of the core, the stress can be absorbed with certainty. The reliability of the wiring board can be improved.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is formed mainly of an organic material. Specific examples of the organic material forming the core substrate include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), and the like. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  Examples of the plate-like parts include inorganic plate-like parts such as ceramic plate-like parts, metal plate-like parts, and glass plate-like parts. Examples of the ceramic material constituting the ceramic plate-like component include low-temperature fired materials such as alumina, glass ceramic, and crystallized glass, aluminum nitride, silicon carbide, and silicon nitride. Examples of the metal material constituting the metal plate-like component include iron, gold, silver, copper, copper alloy, iron nickel alloy, silicon, and gallium arsenide. Examples of the metal plate-like component include a semiconductor integrated circuit chip (IC chip) and a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process. Here, “semiconductor integrated circuit chip” refers to an element mainly used as a microprocessor of a computer.

  On the other hand, examples of suitable ceramic plate-like parts include a chip capacitor and a via array type ceramic capacitor having a plurality of via conductors in the capacitor. In the ceramic capacitor, it is preferable that a plurality of via conductors in the capacitor are arranged in an array as a whole. With such a structure, the inductance of the ceramic capacitor can be reduced, and high-speed power supply for noise absorption and power supply fluctuation smoothing can be performed. In addition, the entire ceramic capacitor can be easily reduced in size, and as a result, the entire wiring board can be easily reduced in size. Moreover, a high electrostatic capacity is easily achieved for a small amount, and a more stable power supply can be achieved.

  As the ceramic dielectric layer constituting the ceramic capacitor, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and borosilicate glass or borosilicate is used. A sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to lead acid glass is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  The resin filler is for fixing the plate-like component, and can be appropriately selected in consideration of stress relaxation characteristics, insulation properties, heat resistance, and the like. Preferred examples of the resin material for forming the resin filler include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, polyimide resins, polycarbonate resins, acrylic resins, polyacetal resins, e-polypropylene resins. And thermoplastic resins. Moreover, as this resin filler, you may use the material etc. which added the glass filler to the said thermosetting resin or a thermoplastic resin.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a ceramic capacitor built-in wiring board 10 (plate-like component built-in wiring board) of the present embodiment is a wiring board for mounting an IC chip, and is a substantially rectangular plate-shaped core made of glass epoxy. It is formed on the substrate 11, the first buildup layer 31 formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, and the core back surface 13 (lower surface in FIG. 1) of the core substrate 11. And a second buildup layer 32. Through holes 15 penetrating in the thickness direction are formed at a plurality of locations in the core substrate 11, and an inner diameter of the through hole 15 is copper plated to give an outer diameter of 300 μm and a thickness of 20 μm. Through-hole conductors 16 are formed. The through-hole conductor 16 connects and connects the core main surface 12 side and the core back surface 13 side of the core substrate 11. Note that the inside of the through-hole conductor 16 is filled with a closing body 17 made of an insulating material (for example, an epoxy resin containing a silica filler). A conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  The first buildup layer 31 formed on the core main surface 12 of the core substrate 11 has a structure in which two resin insulating layers 33 and 35 made of epoxy resin and conductor layers 42 made of copper are alternately laminated. Have. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the resin insulation layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. The terminal pads 44 are flip-chip connected to the surface connection terminals 22 of the IC chip 21 via a plurality of solder bumps 45. The IC chip 21 is, for example, a semiconductor integrated circuit element having a function as an MPU, and is formed in a rectangular flat plate shape having a length of 14.0 mm × width of 14.0 mm × thickness of 0.7 mm.

  A region where each terminal pad 44 and each solder bump 45 is located is a component mounting region 23 in which the IC chip 21 can be mounted. The component mounting area 23 is set on the surface 39 of the buildup layer 31 and is a square area in plan view of 14.0 mm in length × 14.0 mm in width. That is, the component mounting area 23 is an area arranged immediately below the lower surface of the IC chip 21 and has the same outer shape and area as the lower surface of the IC chip 21 when viewed from the thickness direction. Further, via conductors 43 and 47 are provided in the resin insulation layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.

  The buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the buildup layer 31 described above. That is, the buildup layer 32 has a structure in which two resin insulating layers 34 and 36 made of an epoxy resin and the conductor layer 50 are alternately laminated. BGA pads 48 that are electrically connected to the conductor layer 50 through via conductors 47 are formed in a plurality of locations on the lower surface of the resin insulating layer 36 in a lattice shape. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 for electrical connection with the mother board 60 are disposed. The wiring board 10 is mounted on the mother board 60 by the solder bumps 49.

  The core substrate 11 has one accommodation hole 91 that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 91 is a through hole.

  The ceramic capacitor 101 shown in FIGS. 2 and 3 is housed in the housing hole 91 in an embedded state. The ceramic capacitor 101 has a component first main surface 102 (upper surface in FIGS. 1 and 2) facing the same side as the core main surface 12 of the core substrate 11, and a component second main surface 103 (lower surface in FIGS. 1 and 2). ) Is directed to the same side as the core back surface 13 of the core substrate 11. The ceramic capacitor 101 of the present embodiment is a plate-like member having a substantially rectangular shape with a length of 10.0 mm × width of 10.0 mm × thickness of 0.80 mm, with four corners chamfered.

  Further, a gap between the inner surface of the accommodation hole 91 and the side surface of the ceramic capacitor 101 is filled with a resin filler 92 made of a polymer material (thermosetting resin in the present embodiment). The resin filler 92 has a function of fixing the ceramic capacitor 101 to the core substrate 11 and absorbing the deformation of the ceramic capacitor 101 and the core substrate 11 in the surface direction and the thickness direction by its own elastic deformation.

  As shown in FIG. 4, the receiving hole 91 of the present embodiment has an outer shape that is formed in a concavo-convex shape in plan view, and has an opening width at a position facing the chamfered portion 107 of the ceramic capacitor 101. A concave relief portion 93 is provided in which L1 is set longer than the width L2 of the chamfered portion 107. Specifically, the opening width L1 of the concave relief portion 93 is about 1.0 mm, and the width L2 of the chamfered portion 107 is about 0.7 mm. The concave relief portion 93 is a concave portion that is recessed in a curved shape, and the opening 94 in the concave relief portion 93 has a curvilinear shape. Further, the outline of the accommodation hole 91 has a wavy shape consisting of a continuous curve.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. A ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like component having a component first main surface 102 (upper surface) and a component second main surface 103 (lower surface). The ceramic sintered body 104 has a structure in which the first internal electrode layers 141 and the second internal electrode layers 142 are alternately stacked via the ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 130, a plurality of via conductors 131 and 132 (via conductors in a capacitor) penetrating between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each first via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each second via conductor 132 penetrates each second internal electrode layer 142 and electrically connects them to each other.

  A plurality of first external terminal electrodes 111 and 112 protrude from the upper surface 102 of the ceramic sintered body 104. A plurality of second external terminal electrodes 121 and 122 protrude from the lower surface 103 of the ceramic sintered body 104. The first external terminal electrodes 111 and 112 on the upper surface 102 side are connected to the surface connection terminals 22 of the IC chip 21 via via conductors 43, conductor layers 42, via conductors 47, terminal pads 44 and solder bumps 45. Are electrically connected. On the other hand, the second external terminal electrodes 121 and 122 on the lower surface 103 side have via conductors 43, conductor layers 50, via conductors 47, BGA pads 48 and solder bumps 49 with respect to the electrodes (contactors) included in the mother board 60. It is electrically connected via. In addition, the substantially central portions of the bottom surfaces of the first external terminal electrodes 111 and 112 are directly connected to the end surfaces of the via conductors 131 and 132 on the top surface 102 side, and the substantially central portions of the bottom surfaces of the second external terminal electrodes 121 and 122. Are directly connected to the end surfaces of the via conductors 131 and 132 on the lower surface 103 side. Therefore, the external terminal electrodes 111 and 121 are electrically connected to the via conductor 131 and the first internal electrode layer 141, and the external terminal electrodes 112 and 122 are electrically connected to the via conductor 132 and the second internal electrode layer 142.

  The external terminal electrodes 111, 112, 121, and 122 have a layer structure in which a copper plating layer is formed on a metallized layer containing nickel as a main material. A copper plating layer consists of a metal softer than the metal which comprises a metallization layer, and the surface is roughened. For this reason, the surfaces of the first external terminal electrodes 111 and 112 are rougher than the upper surface 102 of the ceramic sintered body 104. Similarly, the surfaces of the second external terminal electrodes 121 and 122 are also rougher than the lower surface 103 of the ceramic sintered body 104. Further, the external terminal electrodes 111, 112, 121, 122 when viewed from the direction perpendicular to the upper surface 102 (part thickness direction) are substantially circular (see FIG. 3).

  In the ceramic capacitor built-in wiring board 10 having the above configuration, when energization is performed from the mother board 60 side through the second external terminal electrodes 121 and 122 and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, For example, positive charges are accumulated in the first internal electrode layer 141, and negative charges are accumulated in the second internal electrode layer 142, for example. As a result, the ceramic capacitor 101 functions as a capacitor. Further, in the ceramic capacitor 101, the first via conductors 131 and the second via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the first via conductors 131 and the second via conductors 132 are opposite to each other. It is set to face. Thereby, the inductance component is reduced. In addition, current is supplied to the IC chip 21 through the via conductors 131 and 132, and current is supplied to the IC chip 21 through the through-hole conductor 16, whereby the IC chip 21 operates.

  Next, a method for manufacturing the ceramic capacitor built-in wiring board 10 of the present embodiment will be described.

  In the substrate preparation step, the core substrate 11 is manufactured by a conventionally known method. In the ceramic chip preparation step, the ceramic capacitor 101 is manufactured by a conventionally known method, and the core substrate 11 and the ceramic capacitor 101 are prepared in advance.

  In the substrate preparation process, the core substrate 11 is manufactured as follows. First, a copper clad laminate is prepared in which a copper foil having a thickness of 35 μm is bonded to both surfaces of a base having a length of 400 mm × width of 400 mm × thickness of 0.80 mm. Next, drilling is performed on the copper-clad laminate using a drill, and a through hole for forming the through-hole conductor 16 is formed in advance at a predetermined position. And the through-hole conductor 16 is formed by performing electroless copper plating and electrolytic copper plating according to a conventionally well-known method. Next, after the paste which has an epoxy resin as a main component is printed in the cavity part of the through-hole conductor 16, the obstruction | occlusion body 17 is formed by hardening. Further, the copper foil on both sides of the copper clad laminate is etched to pattern the conductor layer 41 by, for example, a subtractive method (see FIG. 5). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, after removing unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil by etching, the dry film is peeled off.

  Next, a hole processing step is performed on the core substrate 11 using a router, and the accommodation hole 91 is formed at a predetermined position (see FIG. 6). In this hole machining step, the housing hole 91 (see FIG. 4) having concave and convex relief portions 93 at the four corners is formed as the contour line is uneven in plan view.

  In the ceramic chip preparation process, the ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and metallized layers of the first external terminal electrodes 111 and 112 are formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. Further, a paste is printed on the lower surface of the green sheet laminate, and the metallized layers of the second external terminal electrodes 121 and 122 are formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate.

  Thereafter, the green sheet laminate is dried to solidify the surface terminal part to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104. Then, electrolytic copper plating (thickness of about 10 μm) is performed on each external terminal electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each external terminal electrode 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  After that, in the component housing step, a peelable adhesive tape 152 as a masking material is disposed in close contact with the opening 96 on the core main surface 12 side of the housing hole 91, and the opening 96 is sealed (FIG. 7). reference). The adhesive tape 152 is supported by a support base (not shown). Next, the ceramic capacitor 101 is accommodated in the accommodation hole 91 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 8). At this time, the ceramic capacitor 101 is attached to the adhesive tape 152 and temporarily fixed. Here, when the chip is mounted (the state shown in FIG. 1), the component first main surface 102 which is the upper surface is in close contact with the adhesive tape 152 in a state where the first main surface 102 is directed downward (the upper surface and the lower surface are reversed). . Similarly, the core substrate 11 is also in a state where the core main surface 12 which is the upper surface when the chip is mounted faces downward.

  In the component fixing step, a resin made of a thermosetting resin is provided from the opening 97 on the core back surface 13 side using a dispenser device (manufactured by Asymtek) in the gap between the inner surface of the accommodation hole 91 and the side surface of the ceramic capacitor 101. Filler 92 (Namics Co., Ltd.) is filled (see FIG. 9). Thereafter, when heat treatment is performed, the resin filler 92 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 91. At this time, the positions of the core main surface 12, the component first main surface 102, and the surface of the resin filler 92 on the side in contact with the adhesive tape 152 are aligned and formed flat. Accordingly, there is almost no step between the component first main surface 102 and the core main surface 12, which is smaller than the step between the component second main surface 103 and the core back surface 13.

  Then, after fixing the ceramic capacitor 101, the adhesive tape 152 is peeled off. After that, the core main surface 12 of the core substrate 11 and the component first main surface 102 of the ceramic capacitor 101 are washed with a solvent by acid degreasing and then polished, thereby sticking to the core main surface 12 and the component first main surface 102. Remove any remaining adhesive.

  Further, the surface of the copper plating layer on the external terminal electrodes 111, 112, 121, 122 is roughened (CZ treatment). At the same time, the surface of the conductor layer 41 formed on the core main surface 12 and the core back surface 13 is also roughened. Thereafter, a cleaning process is performed, and if necessary, the core main surface 12 and the core back surface 13 may be subjected to a coupling treatment using a silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd.).

  Next, in the buildup layer forming step, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known technique. (See FIG. 10). Furthermore, by forming solder bumps 45 on the terminal pads 44, solder bumps 49 on the BGA pads 48, etc., the ceramic capacitor built-in wiring board 10 is completed. In FIG. 10, the upper and lower surfaces of the core substrate 11 and the ceramic capacitor 101 in FIG. 9 are inverted (in a state where the chip is mounted). Here, there is almost no step between the component first main surface 102 and the core main surface 12, which is smaller than the step between the component second main surface 103 and the core back surface 13. Is formed flat without any irregularities. As a result, the IC chip 21 can be reliably flip-chip connected to the plurality of terminal pads 44 formed in the first buildup layer 31.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the ceramic capacitor built-in wiring substrate 10 according to the present embodiment, the housing hole 91 has an outer shape that is formed in an uneven shape in plan view, so that the inner surface of the housing hole 91, the resin filler 92, The contact area can be increased. Further, the stress is concentrated most at the four corners (the chamfered portion 107) of the ceramic capacitor 101, but a concave relief portion 93 is provided at a position corresponding to the chamfered portion 107 in the accommodation hole portion 91. The concave relief portion 93 is set such that the opening width L 1 is longer than the width L 2 of the chamfered portion 107. If formed in this way, the stress acting between the ceramic capacitor 101 and the accommodation hole 91 can be reliably absorbed by the resin filler 92. Further, the adhesion between the resin filler 92 and the inner surface of the accommodation hole 91 is increased, and the ceramic capacitor 101 can be reliably fixed to the core substrate 11 by the anchor effect.

  (2) In the ceramic capacitor built-in wiring board 10 of the present embodiment, since the opening 94 in the concave relief portion 93 has a curved shape, the stress does not concentrate on the opening 94, and the concave relief portion. The whole of 93 can absorb the stress reliably.

  (3) In the ceramic capacitor built-in wiring board 10 of the present embodiment, the accommodation hole 91 has a wave shape whose outer contour line is a continuous curve. In this case, since there is no corner on the contact surface between the accommodation hole 91 and the resin filler 92, the resin filler 92 can be reliably filled without any voids. Therefore, the resin filler 92 can reliably absorb the stress and prevent the occurrence of cracks.

  (4) In the ceramic capacitor built-in wiring substrate 10 of the present embodiment, the via array type ceramic capacitor 101 is housed in the housing hole 91 as a plate-like component. In this ceramic capacitor 101, since the plurality of via conductors 131 and 132 are arranged in an array as a whole, the inductance of the ceramic capacitor 101 can be reduced, and high-speed power supply for noise absorption and power fluctuation smoothing can be achieved. Is possible. In addition, the entire ceramic capacitor 101 can be easily reduced in size, and as a result, the entire wiring board can be easily reduced in size. In addition, a high capacitance is easily achieved for a small amount, and more stable power supply to the IC chip 21 is possible.

  (5) In the present embodiment, by performing router processing, it is possible to accurately form the wavy accommodation hole portion 91 whose contour line is a continuous curve.

  In addition, you may change embodiment of this invention as follows.

  In the ceramic capacitor built-in wiring substrate 10 of the above embodiment, the housing hole 91 is formed in a wave shape whose outer shape is a continuous curve, but is not limited to this. For example, the shape is changed to a shape having a linear unevenness 95A such as a housing hole 91A shown in FIG. 11 or a shape having a semicircular recess 95B such as a housing hole 91B shown in FIG. May be. By forming the outer shape of the housing holes 91A and 91B so as to be uneven, the contact area with the resin filler 92 can be increased, and the housing holes 91A and 91B and the ceramic capacitor 101 The stress acting between them can be reliably absorbed by the resin filler 92.

  In the ceramic capacitor built-in wiring substrate 10 of the above embodiment, the accommodation hole 91 has the same opening area on the core main surface 12 side and the core back surface 13 side, but is not limited thereto. Instead, it may be changed to the accommodation hole 91C as shown in FIGS. That is, the accommodating hole portion 91 </ b> C is formed so that the cross-sectional shape that appears when the core substrate 11 is cut in the thickness direction gradually widens from the core main surface 12 side to the core back surface 13 side. By forming the accommodation hole 91 in this manner, the opening area becomes larger toward the core back surface 13 side where the resin filler 92 is filled, so that the resin filler 92 is surely placed in the gap between the accommodation hole 91C and the ceramic capacitor 101. Can be filled.

  Further, when the IC chip 21 is mounted on the wiring board 10 with a built-in ceramic capacitor, the second buildup layer 32 positioned on the core back surface 13 side contracts during cooling after bonding the IC chip, but is positioned on the core main surface 12 side. The first buildup layer 31 that does not shrink almost because the IC chip 21 exists. As a result, the core substrate 11 warps to the core back surface 13 side. Further, since the ceramic capacitor 101 is less plastic than the core substrate 11 and the build-up layers 31 and 32, the ceramic capacitor 101 cannot follow the warpage. Therefore, stress concentrates on the core back surface 13 side, but the resin filler 92 interposed between the accommodation hole 91 and the ceramic capacitor 101 is formed so that the thickness in the plane direction is thicker on the core back surface 13 side. Therefore, the stress concentration can be absorbed reliably.

  In the above embodiment, the resin filler 92 is filled in the gap between the inner surface of the accommodation hole portion 91 and the side surface of the ceramic capacitor 101 using the dispenser device, but is positioned at the lowermost layer of the second buildup layer 32. The ceramic capacitor 101 may be fixed to the core substrate 11 by dropping a part of the resin insulation layer 34 to be filled into the gap and filling the gap. In this case, since the resin insulating layer 34 also serves as the resin filler 92, it is not necessary to prepare a material different from the resin insulating layer 34 when forming the resin filler 92, and the manufacturing cost can be reduced.

  In the ceramic capacitor built-in wiring substrate 10 of the above embodiment, one ceramic capacitor 101 is accommodated in the accommodation hole 91 of the core substrate 11, but a plurality of plate-like components (for example, chip capacitors) are accommodated in the accommodation hole 91. ) May be embedded.

  In the above embodiment, the package form of the ceramic capacitor built-in wiring board 10 is BGA (ball grid array), but is not limited to BGA alone, for example, PGA (pin grid array), LGA (land grid array), etc. There may be.

1 is a schematic sectional view showing a ceramic capacitor built-in wiring board according to an embodiment of the present invention. Similarly, the schematic sectional drawing which shows a ceramic capacitor. Similarly, the top view which shows a ceramic capacitor. Similarly, explanatory drawing which shows the accommodation hole part in a core board | substrate. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Similarly, explanatory drawing which shows the manufacturing method of a wiring board. Explanatory drawing which shows the accommodation hole part in the core board | substrate of other embodiment. Explanatory drawing which shows the accommodation hole part in the core board | substrate of other embodiment. Explanatory drawing which shows the accommodation hole part in the core board | substrate of other embodiment. Explanatory drawing which shows the accommodation hole part in the core board | substrate of other embodiment. The schematic sectional drawing which shows the wiring board of a prior art. Explanatory drawing which shows the accommodation hole part in the core board | substrate of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Ceramic capacitor built-in wiring board as a board | substrate with built-in plate-shaped components 11 ... Core board 12 ... Core main surface 13 ... Core back surface 21 ... IC chip as a semiconductor integrated circuit element 91, 91A, 91B, 91C ... Accommodating hole part 92 ... Resin filler 93 ... Recessed relief part 94 ... Opening part 101 ... Ceramic capacitor as a plate-like part 102 ... Part first main surface 103 ... Part second main surface 107 ... Chamfered part 131, 132 ... As via conductor in capacitor Via conductor L1 ... Opening width of concave relief L2 ... Width of chamfer

Claims (5)

A core substrate having a core main surface and a core back surface, and having an accommodation hole opening at the core main surface and the core back surface;
It has a substantially rectangular shape in plan view having a component first main surface and a component second main surface, its four corners are chamfered, the component first main surface faces the core main surface side, and the component second main surface is A plate-like component housed in the housing hole in a state directed toward the back side of the core;
A resin filler that fixes the plate-like component to the core substrate by filling a gap between the inner surface of the accommodation hole and the side surface of the plate-like component, and the outline of the accommodation hole is in plan view And a concave relief portion whose opening width is set to be longer than the width of the chamfered portion at least at a position facing the chamfered portion of the plate-like component on the inner surface of the accommodation hole portion. A wiring board with a built-in plate-like component, which is provided.   The plate-like component built-in wiring board according to claim 1, wherein the opening in the concave relief portion has a curvilinear shape.   3. The plate-like component built-in wiring board according to claim 1 or 2, wherein an outline of the accommodation hole portion has a wave shape composed of a continuous curve.   4. The wiring board with a built-in plate-like component according to claim 1, wherein the accommodation hole portion is formed so that an opening area becomes larger toward a filling side filled with the resin filler. 5. .   The plate-like component built-in wiring board according to any one of claims 1 to 4, wherein the plate-like component is a via array type ceramic capacitor having a plurality of via conductors in the capacitor.

Images