JP2004128038A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which enables formation of a trench in the STI element separation region in different depths in the dense and coarse regions of pattern while controlling drop of throughput due to the increase in the number of processes and processing time. <P>SOLUTION: In the method of manufacturing a semiconductor device, after a coating film is formed on a semiconductor substrate where a mask material is formed in the predetermined pattern including the dense and coarse regions of pattern, the etching process is executed. Accordingly, the trench is formed in different depths at the dense and coarse regions of the pattern. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for forming STI (Shallow Trench Isolation) element isolation regions having different depths on the same semiconductor substrate.
[0002]
[Prior art]
In a semiconductor device such as a flash memory, an STI element isolation region may be formed as an element isolation region.
[0003]
FIG. 2 shows a process of forming an STI element isolation region in a conventional method of manufacturing a semiconductor device with respect to a dense pattern portion (FIGS. 2A1 and 2A2) and a loose pattern portion (FIGS. 2B1 and 2B2). FIG.
[0004]
When etching the semiconductor substrate 2 to form a trench in the STI element isolation region, as shown in FIGS. 2A1 and 2B1, first, resist and silicon are formed in accordance with the pattern of the trench to be formed. A mask material 1 such as a nitride film or a silicon oxide film is formed.
[0005]
When the semiconductor substrate 2 is etched using the mask material 1, according to the current technology, as shown in FIGS. 2 (A2) and 2 (B2), both the dense and sparse portions of the pattern are processed to substantially the same depth. Can be. When a loading effect occurs during this etching, the trench in the pattern sparse portion becomes slightly shallower, and when a microloading effect occurs, the trench in the pattern dense portion becomes slightly shallower. The difference is not so large.
[0006]
In the manufacture of semiconductor devices up to now, it has been required that the trench in the STI element isolation region be processed to the same depth in both the dense pattern portion and the sparse pattern portion.
[0007]
By the way, with the recent rapid miniaturization of semiconductor devices, voids are generated in the silicon oxide film 3 formed by HDP (High Density Plasma), particularly in dense pattern portions, as a filling material for trenches in STI element isolation regions. It is becoming increasingly difficult to embed without them.
[0008]
FIG. 3 is a cross-sectional view showing voids that may be generated in the filling material of the trench in the dense pattern portion (FIG. 3A) and the loose pattern portion (FIG. 3B) of the STI element isolation region.
[0009]
After forming trenches in the pattern dense portion and the pattern sparse portion, as shown in FIGS. 3A and 3B, when the silicon oxide film 3 is formed by HDP as a filling material of the trench in the STI element isolation region, particularly, Voids 4 may be generated in the pattern dense portion shown in FIG. The voids 4 tend to be more likely to occur as the aspect ratio, which is the ratio of the height to the gap width of the pattern, increases.
[0010]
FIG. 4 is an explanatory diagram schematically showing the definition of the pattern aspect ratio.
[0011]
Since the aspect ratio of a pattern is the ratio of the height to the gap width of the pattern, if the gap width of the pattern is a and the height is b, the aspect ratio is b / a. As the aspect ratio b / a increases, that is, as the height b with respect to the gap width a of the pattern increases, the voids 4 shown in FIG.
[0012]
Voids have an adverse effect on the characteristics of the semiconductor device and cause defects. Therefore, it is necessary to suppress the occurrence of voids as much as possible. As described above, voids are more likely to occur as the aspect ratio b / a of the pattern increases, so that the aspect ratio b / a may be reduced to suppress the occurrence of voids. Reducing the aspect ratio b / a means reducing the height b with respect to the gap width a of the pattern, and reducing the depth of the trench in the STI element isolation region.
[0013]
Therefore, in the STI element isolation region, the generation of voids can be suppressed by reducing the etching amount of the semiconductor substrate and reducing the depth of the trench.
[0014]
However, if the trench in the STI element isolation region is made too shallow, the element isolation becomes insufficient in the sparsely patterned portion, which causes a failure such as deterioration of withstand voltage.
[0015]
Therefore, in order to suppress the generation of voids in the dense pattern portion and to perform sufficient element isolation in the coarse pattern portion, a design is performed in which the trench in the dense pattern portion is formed shallow and the trench in the coarse pattern portion is formed deep. It is becoming.
[0016]
Conventionally, when a semiconductor device is manufactured in accordance with such a design, the etching of the semiconductor substrate in the pattern dense portion and the pattern coarse portion is separately performed, so that a shallow trench in the pattern dense portion and a deeper trench in the pattern coarse portion are formed. The trench was realized.
[0017]
FIG. 5 shows a conventional semiconductor device in which trenches are formed at different depths in a dense pattern portion (FIGS. 5A1 to 5A5) and a sparse pattern portion (FIGS. 5B1 to 5B5). It is sectional drawing which shows the process of a manufacturing method.
[0018]
Either the etching of the dense pattern portion or the etching of the coarse pattern portion may be performed first. Here, an example in which the etching of the dense pattern portion is performed first will be described.
[0019]
When etching the pattern dense portion, as shown in FIGS. 5A1 and 5B1, first, only the pattern sparse portion is covered with a resist. When etching is performed in this state, as shown in FIG. 5A2, only the dense portion of the semiconductor substrate 2 is etched, and a trench is formed. At this time, the depth of the trench in the dense pattern portion is set to be shallow so that the aspect ratio of the dense pattern portion is a value that suppresses the generation of voids.
[0020]
After the formation of the trench in the pattern dense portion, as shown in FIGS. 5A3 and 5B3, the resist 5 in the pattern sparse portion is peeled off, and only the pattern dense portion is covered with the resist. When etching is performed in this state, as shown in FIG. 5B4, only the sparse pattern portion of the semiconductor substrate 2 is etched to form a trench. At this time, the trench depth of the pattern sparse portion is set to be large so that sufficient element isolation is ensured in the pattern sparse portion and the breakdown voltage is not deteriorated.
[0021]
Finally, when the resist 5 in the dense pattern portion is peeled off, as shown in FIGS. 5A5 and 5B, trenches in the STI element isolation region having different depths in the dense pattern portion and the sparse pattern portion are formed. You.
[0022]
In addition, in a conventional method of manufacturing a semiconductor device, a part of a resist formed on a semiconductor substrate is peeled off and etched, and another step of peeling off another part of the resist and etching is performed. There is also an example in which trenches having different depths are formed (for example, see Patent Document 1).
[0023]
In still another example, the trenches of the pattern dense portion and the pattern sparse portion are simultaneously formed at substantially the same depth, and then heat treatment is performed to reduce the depth of the trenches of the pattern dense portion to reduce the pattern dense portion and the pattern dense portion. There is also an example in which trenches having different depths are formed between the pattern sparse portions (for example, see Patent Document 2).
[0024]
[Patent Document 1]
JP-A-2-246330 [Patent Document 2]
JP 2000-323564 A
[Problems to be solved by the invention]
However, in the above-described conventional method of manufacturing a semiconductor device, the trench forming step of the STI element isolation region is performed separately for the dense pattern portion and the sparse pattern portion, stepwise, or using heat treatment. There is a problem that the number of processes and the processing time increase by that amount, leading to a decrease in throughput.
[0026]
The present invention has been made in view of the above problems, and minimizes a decrease in throughput due to an increase in the number of steps and processing time, while forming a trench in an STI element isolation region between a pattern dense portion and a pattern sparse portion. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be formed at different depths.
[0027]
[Means for Solving the Problems]
According to one embodiment of a method of manufacturing a semiconductor device according to the present invention, after a coating film is formed on a semiconductor substrate on which a mask material is formed in a desired pattern including a pattern dense portion and a pattern sparse portion, etching is performed. Thereby, trenches having different depths are formed in the pattern dense portion and the pattern sparse portion.
[0028]
According to a specific embodiment of the method for manufacturing a semiconductor device according to the present invention,
Forming a mask material on a semiconductor substrate in a desired pattern including a pattern dense portion and a pattern sparse portion,
Forming a coating film on the semiconductor substrate on which the mask material is formed,
Etching the coating film until the semiconductor substrate surface in the pattern sparse portion is exposed,
In a state where the coating film in the pattern dense portion remains, the semiconductor substrate in the pattern sparse portion is etched,
If the coating film in the dense pattern portion remains even after the etching of the semiconductor substrate in the pattern sparse portion, remove the coating film,
The semiconductor substrate in the dense pattern portion and the sparse pattern portion is etched to form trenches having different depths in the dense pattern portion and the sparse pattern portion.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
In the method for manufacturing a semiconductor device according to the present invention, when a coating film is formed on a semiconductor substrate after patterning of a mask material formed on the semiconductor substrate and before etching of the semiconductor substrate, the coating film is formed in a dense portion of the pattern due to surface tension. Taking advantage of the fact that the film is formed thickly and thinly in the sparse pattern area, the trench is etched at different depths in the dense pattern area and the sparse pattern area by etching the trench using the applied film as an additional mask material. Is what you do.
[0030]
Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
[0031]
FIG. 1 shows a process of forming a trench in an STI element isolation region in one embodiment of a method of manufacturing a semiconductor device according to the present invention, in which a pattern dense portion (FIGS. 1 (A1) to (A6)) and a pattern sparse portion (FIG. It is sectional drawing shown about (B1) thru | or (B6)).
[0032]
When the semiconductor substrate 2 is etched to form a trench in the STI element isolation region, first, as shown in FIGS. 1A and 1B, a resist, silicon, A mask material 1 such as a nitride film or a silicon oxide film is formed.
[0033]
After forming the mask material 1 according to the pattern of the trench, as shown in FIGS. 1A2 and 1B2, a coating film 6 such as a resist or an anti-reflection film is applied. Are formed relatively thick by surface tension in such a manner as to fill the gaps between the patterns, and are formed relatively thin in the sparse pattern portions.
[0034]
After the formation of the coating film 6, the difference in the thickness of the coating film 6 between the pattern dense portion and the pattern sparse portion is used to substantially remove the coating film 6 in the pattern sparse portion as shown in FIGS. 1 (A3) and (B3). Etching by CDE is performed until completely removed. Then, the coating film 6 remains on the bottom surface of the gap in the dense pattern portion by the thickness difference.
[0035]
When the semiconductor substrate 1 is etched by plasma etching in a state where the coating film 6 remains on the bottom surface of the gap portion in the dense pattern portion, as shown in FIGS. Only the substrate 1 is etched, and the semiconductor substrate 1 in the pattern dense portion covered with the coating film 6 is not etched. At this time, the amount of etching of the semiconductor substrate 1 in the sparse pattern portion is set to be equal to the difference in the final depth of the trench between the dense pattern portion and the sparse pattern portion. The etching amount can be arbitrarily set, and is, for example, about 100 nm to 150 nm.
[0036]
If the coating film 6 remains in the gaps between the dense pattern portions when the etching for the difference in the trench depth between the dense pattern portions and the sparse pattern portions is completed, FIGS. 1 (A5) and (B5) 2), the coating film 6 is removed by CDE.
[0037]
When the coating film 6 is completely removed, the semiconductor substrate of the dense pattern portion and the sparse pattern portion is so formed that the depth of the trench in the dense pattern portion is such that the generation of voids in the filling material to be embedded later can be avoided. 1 is etched by plasma etching to form a trench as shown in FIGS. 1 (A6) and 1 (B6). In the second etching, the semiconductor substrate 1 in the pattern dense portion and the pattern sparse portion is simultaneously etched, so that the trench in the pattern sparse portion is larger than the trench in the pattern dense portion by the first etching amount. Formed deeply.
[0038]
As described above, in the method for manufacturing a semiconductor device according to the present invention, in a dense pattern portion and a sparse pattern portion, a series of steps of resist formation, etching, and resist removal are not separately performed, and heat treatment is also performed. Without using them, trenches of different depths can be formed simultaneously.
[0039]
【The invention's effect】
According to one embodiment of a method of manufacturing a semiconductor device according to the present invention, after a coating film is formed on a semiconductor substrate on which a mask material is formed in a desired pattern including a pattern dense portion and a pattern sparse portion, etching is performed. Accordingly, trenches having different depths are formed in the pattern dense portion and the pattern sparse portion, so that a decrease in throughput due to an increase in the number of steps and processing time is minimized, and the STI element isolation region is formed. The trench can be formed at different depths between the dense pattern portion and the sparse pattern portion.
[Brief description of the drawings]
FIG. 1 shows a trench forming step of an STI element isolation region in one embodiment of a method of manufacturing a semiconductor device according to the present invention, in which a pattern dense portion (FIGS. 1 (A1) to (A6)) and a pattern sparse portion (FIG. It is sectional drawing shown about (B1) thru | or (B6)).
FIG. 2 shows a process of forming an STI element isolation region in a conventional method of manufacturing a semiconductor device for a dense pattern portion (FIGS. 2A1 and 2A) and a sparse pattern portion (FIGS. 2B1 and 2B2). FIG.
FIG. 3 is a cross-sectional view showing voids that may be generated in a filling material of a trench in a pattern dense portion (FIG. 3A) and a pattern sparse portion (FIG. 3B) in an STI element isolation region.
FIG. 4 is an explanatory diagram schematically showing a definition of an aspect ratio of a pattern.
FIG. 5 shows a conventional semiconductor device in which trenches are formed at different depths in a dense pattern portion (FIGS. 5 (A1) to (A5)) and a sparse pattern portion (FIGS. 5 (B1) to (B5)). It is sectional drawing which shows the process of a manufacturing method.
[Explanation of symbols]
Reference Signs List 1 mask material 2 semiconductor substrate 3 filling material 4 void 5 resist 6 coating film

Claims (7)

After a coating film is formed on a semiconductor substrate on which a mask material is formed in a desired pattern including a pattern dense portion and a pattern coarse portion, trenches having different depths are formed in the pattern dense portion and the pattern coarse portion by performing etching. Forming a semiconductor device. Forming a mask material on a semiconductor substrate in a desired pattern including a pattern dense portion and a pattern sparse portion,
Forming a coating film on the semiconductor substrate on which the mask material is formed,
Etching the coating film until the semiconductor substrate surface in the pattern sparse portion is exposed,
In a state where the coating film in the pattern dense portion remains, the semiconductor substrate in the pattern sparse portion is etched,
If the coating film in the pattern dense portion remains even after etching the semiconductor substrate in the pattern sparse portion, remove the coating film,
A method for manufacturing a semiconductor device, comprising: etching the semiconductor substrate in the dense pattern portion and the sparse pattern portion to form trenches having different depths in the dense pattern portion and the sparse pattern portion. The method according to claim 1, wherein the coating film is formed to be thick in the pattern dense portion and thin in the pattern sparse portion. 4. The method according to claim 1, wherein the etching is performed by plasma etching. The method of manufacturing a semiconductor device according to claim 1, wherein the coating film is a resist. The method according to claim 1, wherein the coating film is an anti-reflection film. 7. The method according to claim 1, wherein the trench is a trench for forming an STI element isolation region.

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