JP2004119731A - Fuse circuit in hybrid integrated circuit device - Google Patents
Fuse circuit in hybrid integrated circuit device Download PDFInfo
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- JP2004119731A JP2004119731A JP2002281890A JP2002281890A JP2004119731A JP 2004119731 A JP2004119731 A JP 2004119731A JP 2002281890 A JP2002281890 A JP 2002281890A JP 2002281890 A JP2002281890 A JP 2002281890A JP 2004119731 A JP2004119731 A JP 2004119731A
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Abstract
Description
【0001】
【発明の属する技術分野】
本発明は回路素子と電極となる導電パターンを接続する金属細線を用いてヒューズ回路を構成した混成集積回路のヒューズ回路に関する。
【0002】
【従来の技術】
最近特に、携帯用のコンピュータあるいはプリンター等の電子機器に使用される半導体回路装置は小型化、薄型化及び軽量化が一段と求められている。そのため半導体回路装置として、半導体基板に半導体素子を取付け、その半導体基板を絶縁樹脂でモールドしたパッケージ型半導体装置がある。
【0003】
図4は従来のパッケージ型半導体装置である。パッケージ型半導体装置は基板1上に形成したダイボンディングパッド2にLSI等のベアチップ3を取付け、そのベアチップ3の電極4、4とリード端子5、5を金属細線6、6で接続する。さらにリード端子5、5をプリント基板7に印刷したプリント配線8、8にハンダ付して取付ける。
【0004】
そして基板1及びベアチップ3の周囲を絶縁性樹脂層9で被覆している。このパッケージ型半導体装置は、リード端子5、5が絶縁性樹脂層9から外部に露出されているため、全体のサイズが大きく、小型化、薄型化および軽量化に難点がある。
【0005】
図5及び図6は前述したパッケージ型半導体装置を改良した混成集積回路装置の一部分の平面図及び断面図である。
【0006】
ICあるいはLSIの回路素子のベアチップ10を導電パターン11上に形成したダイボンディングパッド11Aに取付ける。LSI等のベアチップ10の電極13A1、13A2、13A3・・・13A7・・・は導電パターン14A1、14A7・・・に設けられたワイヤーボンデイングパッド15A1・・・15A7・・・にボンディングされた金属細線16A1、162A2・・・16A7・・・でもって接続されている。
【0007】
図6(A)に示すように、前述の状態では導電パターン11、14A1・・・14A7・・・は分離溝18A、18B・・・で上部は電気的に分離されているが、下部はまだ連続されている。
【0008】
導電パターン11と導電パターン14A1・・・14A7・・・、導電パターン11に取付けられたベアチップ10および金属細線16A1・・・16A7・・・を絶縁性樹脂20でモールドし全体を被覆すると共に一体に固定する。然る後導電パターン11と導電パターン14A1・・・14A7・・・の下部の連続する部分を絶縁性樹脂20と共に点線で示すように切断し、導電パターン11と導電パターン14A1・・・14A7・・・を完全に電気的に分離する。
【0009】
図6(B)のごとく、導電パターン11、14A1・・・14A7・・・の下面に於いては、絶縁性樹脂20から露出する形になる。導電パターン11、14A1、14A2・・・の露出部分は外部との電気的・熱的な接続を行うために、半田等を設けて外部電極21A・・・21A7・・・及び電極22が形成される。さらに、導電パターン11、14A1・・・14A7・・・の外部電極を設けない個所は、導電パターンの保護等を目的としてレジスト23により被覆し、混成集積回路装置を形成している。
【0010】
前述のようにして形成した混成集積回路は外部電極21A・・・21A7・・・、22を印刷基板に必要な配線を施された印刷配線に直接接合し、モータ回路等を構成する。
【0011】
【特許文献1】
特開平04−162691
【0012】
【発明が解決しようとする課題】
一般にモータ回路等の大きな電流が流れる混成集積回路では回路ではヒューズを設ける。
【0013】
しかし前述したように、上部は分離しているが下部は連続する導電パターンにICあるいはLSI等のベアチップおよびチップ抵抗及びチップコンデンサ等を取付け、且つボンディングされた金属細線でベアチップの電極と導電パターンに設けたワイヤーボンディングパッドを接続する。然る後絶縁性樹脂でモールドした後前記導電パターンの下部連続する部分を切断し、基板を用いることなく作成した混成集積回路においては、薄型化、小型化及び安価が要求されるため、前述したヒューズ回路を設けることは不適当である。
【0014】
【課題を解決するための手段】
本発明は特別なヒューズ回路を設けることなくヒューズ機能を持たせた混成集積装置で、分離溝で分離され、ベアチップが載置されるダイボンディングパッド及びワイヤーボンディングパッドが設けられた複数の導電パターンと、前記ダイボンディングパッドに載置されたベアチップと、前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、アース端子となる前記一の導電パターンとアース間に設けられた補助導電パターンとよりなり、前記アース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続した混成集積装置のヒューズ回路を提供する。
【0015】
また分離溝で分離され、ベアチップが載置されるダイボンディングパッド及びワイヤーボンディングパッドが設けられた複数の導電パターンと、前記ダイボンディングパッドに載置されたベアチップと、前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、電源端子となる一の導電パターンと電源間に設けられた補助導電パターンとよりなり、前記電源端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続した混成集積装置のヒューズ回路を提供する。
【0016】
本発明は前記金属細線は金線であり、ベアチップの電極とワイヤーボンディングパッドとを直径38μmの金線で接続し、前記電源端子用の導電パターンと補助導電パターン間を直径23μmの金線で接続した混成集積装置のヒューズ回路を提供する。
【0017】
【発明の実施の形態】
本発明の混成集積装置のヒューズ回路を図1〜図3に従って説明する。
【0018】
図1及び図2は本発明の混成集積装置のヒューズ回路の平面図及び断面図である。
【0019】
ワイヤーボンディングパッド31A・・31F・・を上部に形成した多くの導電パターン32A・・32F・・とダイボンディングパッド33A等を形成した導電パターン34A及びワイヤーボンディングパッド35Aを形成したアース端子となる導電パターン35さらにワイヤーボンディングパッド37Aを形成した補助導電パターン37を有する。導電パターン32A・・32F・・とアース端子となる導電パターン35さらに補助導電パターン37とは図2(A)に示すように上部は分離溝36、36で電気的に分離されているが、下部は連続されている。
【0020】
導電パターン34Aに形成されたダイボンディングパッド33Aにはモータ回路のコントロールを行うLSIのベアチップ40が取付けられている。ベアチップ40の各電極41A、41B・・41F・・・等と導電パターン32A・・・32F・・・に形成されたワイヤーボンディングパッド31A、31B・・・31F・・・はワイヤーボンディングされた金属細線42A、42B・・・42F・・・で接続される。
【0021】
ベアチップ40の電極41Aと金属細線42Aで接続されたワイヤーボンディングパッド31Aはアース端子となる導電パターン35に形成されたワイヤーボンディングパッド35Aとワイヤーボンディングされた金属細線42Tで接続されている。
【0022】
さらに導電パターン35のワイヤーボンディングパッド35Aは補助導電パターン37に設けられたワイヤーボンディングパッド37Aと金属細線42A、42B・・・42F・・・より径を小さくし溶断電流を小さくしたヒューズとなる金属細線43で接続されている。本実施例では金属細線42A、42B・・・42F・・・42T・・・は直径38μmの金線が使用され、ヒューズとなる金属細線43は直径23μmの金線が使用さている。
【0023】
モータ制御用のICのベアチップ44は同じく他のダイボンディングパッドに取り付けられ、各電極45A・・・は金属細線42G・・・でワイヤーボンディングパッド31G・・・に接続されている。同様に入力トランジスタのベアチップ46はダイボンディングパッドに取り付けられ、電極47A・・・は金属細線42R・・・で各ワイヤーボンディングパッド31R・に接続されている。さらにチップ抵抗48A、48B・・・の電極がダイボンディングパッド33B、33C・・・に直接取付けられている。
【0024】
ダイボンディングパッド33AにLSIのベアチップ40を取付け、ベアチップ40の各電極31A、31B・・・31F・・・と導電パターン32A・・・32F等を金属細線42A、42B・・・42F・・・で接続する等して、各回路素子を取付けると共に電気的接続した後、これら回路素子、導電パターン及び金属細線を絶縁性樹脂50でモールドし固定する。
【0025】
回路素子、導電パターン及び金属細線を絶縁性樹脂20でモールドし固定した後、図2(A)に示す点線で導電パターン32A、32F、35、37・・・を絶縁性樹脂50と共に切断する。図2(B)のごとく、この状態では導電パターン32A、32F、35、37・・・の下端は外部に露出されているので、露出されている部分に半田でもって外部電極49A、49B、49C・・・49Eを形成する。そして導電パターン32A、32F、35、37・・・の残りの露出部分をレジスト50・・で被覆することにより混成集積装置51が完成する。
【0026】
前述のようにして形成された混成集積装置51はプリンタ−等のモータ回路を完成させるために所定の印刷配線が施された印刷基板に載置される。すると補助導電端子37の外部電極49Eが印刷基板のアース印刷配線に接触する。
【0027】
金属細線42A、42B・・・等は直径38μmの金線で形成されており1.9Aの直流電流まで溶断することなく流せるが、ヒューズとなる金属細線43は直径23μmの金線で形成されている。そのため1.0A以上の直流電流が流れると溶断する。従ってモータ回路に1.0A以上の過大電流が流れた時、ヒューズとなる金属細線43が切断され、LSI等のベアチップには過大電流が流れるのを防止し、これら回路素子が破壊されるのを防止する。
【0028】
上述の実施例ではヒューズとなる金属細線43をアース端子となる導電パターンと補助導電パターン間に接続したが、ヒューズとなる金属細線43を電源端子となる導電パターンを設け、電源端子となる導電パターンと補助導電パターン間に接続してもよい。
【0029】
図3は前述した混成集積回路51を用いたプリンターのモータ回路である。混成集積回路51にはCPU52、モータ53、電源54及びコンデンサ55等が外付けされている。
【0030】
混成集積回路51はベアチップ40で形成したコントロール部56、ICのベアチップ44で形成した制御回路57及びベアチップ46よりなる入力トランジスタ部58よりなる。
【0031】
CPU52から入力信号IN1が入力されると、トランジスタTR1で増幅されコントロール回路56に加わる。すると端子Sからハイレベルの信号を発生し、トランジスタTR3をオンする。それによりトランジスタTR4、TR5はオンする。このときトランジスタTR6はオフされているので、端子TはローレベルであるためトランジスタTR7、TR8はオフされている。
【0032】
従って電源54から端子VCCに加わった直流電圧VDDはトランジスタTR4を経て端子OUT1よりモータ53に加わり、再び端子OUT2からトランジスタTR5を経て端子35Aに加わり、ヒューズとなる金属細線43を経て印刷基板のアース印刷配線(図示せず)に流れ、モータ53を回転させる。
【0033】
次にCPU52から入力信号IN2が入力されると、トランジスタTR2で増幅されコントロール回路56に加わる。今度は端子Tからハイレベルの信号を発生し、トランジスタTR6をオンする。それによりトランジスタTR7、TR8はオンする。このときトランジスタTR3はオフされているので、トランジスタTR4、TR5はオフされている。
【0034】
そのため電源54から端子VCCに加わった直流電圧VDDはトランジスタTR7を経て端子OUT2よりモータ53に加わり、再び端子OUT1からトランジスタTR8を経て端子35Aに加わり、ヒューズとなる金属細線43を経て印刷基板のアース印刷配線(図示せず)に流れ、モータ53を回転させるが、前述とモータ53に流れる電流の向き逆となるので、モータ53は前述と逆に回転する。
【0035】
何らかの原因で制御回路57に過大電流が流れる。すると各ベアチップ40、44、46とワイヤーボンディングパッド31A、31F・・・等を接続する金属細線42A、42B・・・よりヒューズとなる金属細線43の径が細くされ溶断され易くしているので、金属細線43が溶断し、回路素子が過大電流で破壊されるのを防止する。
【0036】
前述においてヒューズとなる金属細線をアース導電端子と補助導電端子間に接続したが、ヒューズとなる金属細線を電源導電端子と補助導電端子間に接続してもよい。
【0037】
【発明の効果】
本発明の混成集積装置のアース回路はアース端子又は電源端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断するヒューズ用の金属細線で接続したので、特別なヒューズ回路を設けることなくヒューズ効果を得ることができる。従って安価で且つ小型化されるので、基板を用いず各導電端子及びチップ部品をモールドし一体化して形成する混成集積回路として好適である。
【図面の簡単な説明】
【図1】本発明の混成集積装置のヒューズ回路の平面図である。
【図2】本発明の混成集積装置のヒューズ回路の断面図で、図2(A)は製造過程を示す断面図、図2(B)は完成した断面図である。
【図3】本発明の混成集積装置のヒューズ回路の回路図である。
【図4】従来のパッケージ型半導体装置の断面図である。
【図5】従来の混成集積装置の平面図である。
【図6】従来の混成集積装置の断面図で、図6(A)は製造過程を示す断面図、図6(B)は完成した断面図である。
【符号の説明】
31A、31F ワイヤーボンディングパッド
32A、32F 導電パターン
35 アース端子となる導電パターン
37 補助導電パターン
40 ベアチップ
41A、41B 電極
42A、42F 金属細線
43 ヒューズ用の金属細線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a fuse circuit of a hybrid integrated circuit in which a fuse circuit is formed using a thin metal wire connecting a circuit element and a conductive pattern serving as an electrode.
[0002]
[Prior art]
In recent years, semiconductor circuit devices used in electronic devices such as portable computers and printers are particularly required to be further reduced in size, thickness and weight. Therefore, as a semiconductor circuit device, there is a package type semiconductor device in which a semiconductor element is mounted on a semiconductor substrate and the semiconductor substrate is molded with an insulating resin.
[0003]
FIG. 4 shows a conventional package type semiconductor device. In the package type semiconductor device, a bare chip 3 such as an LSI is attached to a
[0004]
The periphery of the substrate 1 and the bare chip 3 is covered with an insulating resin layer 9. Since the package type semiconductor device has the lead terminals 5 and 5 exposed to the outside from the insulating resin layer 9, the overall size is large and there is a problem in miniaturization, thinning and weight reduction.
[0005]
5 and 6 are a plan view and a cross-sectional view, respectively, of a part of a hybrid integrated circuit device obtained by improving the above-described package type semiconductor device.
[0006]
A
[0007]
As shown in FIG. 6A, in the above-mentioned state, the upper portions of the conductive patterns 11, 14A1... 14A7... Are electrically separated by the
[0008]
The conductive pattern 11 and the conductive patterns 14A1... 14A7..., The
[0009]
As shown in FIG. 6B, the lower surfaces of the conductive patterns 11, 14A1... 14A7. The exposed portions of the conductive patterns 11, 14A1, 14A2,... Are provided with external electrodes 21A... 21A7. You. Further, portions of the conductive patterns 11, 14A1... 14A7... Where no external electrodes are provided are covered with a
[0010]
In the hybrid integrated circuit formed as described above, the external electrodes 21A... 21A7..., 22 are directly joined to the printed wiring provided with the necessary wiring on the printed board to constitute a motor circuit and the like.
[0011]
[Patent Document 1]
JP-A-04-162691
[0012]
[Problems to be solved by the invention]
Generally, in a hybrid integrated circuit in which a large current flows, such as a motor circuit, a fuse is provided in the circuit.
[0013]
However, as described above, the upper part is separated, but the lower part is a continuous conductive pattern, where a bare chip such as IC or LSI, a chip resistor, a chip capacitor, etc. are attached, and a bare metal wire is used to connect the bare chip electrode and conductive pattern. The provided wire bonding pads are connected. Then, after molding with an insulating resin, the lower continuous portion of the conductive pattern is cut, and the hybrid integrated circuit made without using a substrate is required to be thin, small, and inexpensive. Providing a fuse circuit is inappropriate.
[0014]
[Means for Solving the Problems]
The present invention is a hybrid integrated device having a fuse function without providing a special fuse circuit, a plurality of conductive patterns provided with a die bonding pad and a wire bonding pad which are separated by a separation groove and on which a bare chip is mounted. A bare chip mounted on the die bonding pad, a thin metal wire connecting an electrode of the bare chip and a wire bonding pad, and an auxiliary conductive pattern provided between the one conductive pattern serving as a ground terminal and ground. The present invention provides a fuse circuit of a hybrid integrated device in which the conductive pattern serving as the ground terminal and the auxiliary conductive pattern are connected by a thin metal wire that blows with a smaller current than a thin metal wire connecting the bare chip and the conductive pattern.
[0015]
A plurality of conductive patterns separated by separation grooves and provided with a die bonding pad and a wire bonding pad on which a bare chip is mounted; a bare chip mounted on the die bonding pad; an electrode of the bare chip and a wire bonding pad; And a conductive pattern provided as a power supply terminal and an auxiliary conductive pattern provided between a power supply. The bare chip and the conductive pattern are connected between the conductive pattern serving as the power supply terminal and the auxiliary conductive pattern. Provided is a fuse circuit of a hybrid integrated device connected by a thin metal wire that blows with a smaller current than a thin metal wire.
[0016]
In the present invention, the thin metal wire is a gold wire, the bare chip electrode and the wire bonding pad are connected by a gold wire having a diameter of 38 μm, and the conductive pattern for the power terminal and the auxiliary conductive pattern are connected by a gold wire having a diameter of 23 μm. And a fuse circuit for the hybrid integrated device.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
The fuse circuit of the hybrid integrated device according to the present invention will be described with reference to FIGS.
[0018]
1 and 2 are a plan view and a sectional view, respectively, of a fuse circuit of a hybrid integrated device according to the present invention.
[0019]
A
[0020]
A
[0021]
The
[0022]
Further, the
[0023]
The
[0024]
The
[0025]
After the circuit elements, the conductive patterns, and the fine metal wires are molded and fixed with the insulating
[0026]
The hybrid
[0027]
The
[0028]
In the above embodiment, the
[0029]
FIG. 3 shows a motor circuit of a printer using the hybrid
[0030]
The hybrid
[0031]
When the input signal IN1 is input from the CPU 52, the signal is amplified by the transistor TR1 and applied to the
[0032]
Therefore, the DC voltage VDD applied from the
[0033]
Next, when the input signal IN2 is input from the CPU 52, it is amplified by the transistor TR2 and applied to the
[0034]
Therefore, the DC voltage VDD applied from the
[0035]
An excessive current flows through the
[0036]
In the above description, the thin metal wire serving as a fuse is connected between the ground conductive terminal and the auxiliary conductive terminal, but the thin metal wire serving as a fuse may be connected between the power supply conductive terminal and the auxiliary conductive terminal.
[0037]
【The invention's effect】
Since the ground circuit of the hybrid integrated device of the present invention is connected between the conductive pattern serving as the ground terminal or the power supply terminal and the auxiliary conductive pattern with a metal thin wire for a fuse that blows with a smaller current than the metal thin wire connecting the bare chip and the conductive pattern, The fuse effect can be obtained without providing a special fuse circuit. Therefore, since it is inexpensive and miniaturized, it is suitable as a hybrid integrated circuit in which each conductive terminal and chip component are molded and integrated without using a substrate.
[Brief description of the drawings]
FIG. 1 is a plan view of a fuse circuit of a hybrid integrated device according to the present invention.
2A and 2B are cross-sectional views of a fuse circuit of the hybrid integrated device of the present invention. FIG. 2A is a cross-sectional view showing a manufacturing process, and FIG. 2B is a completed cross-sectional view.
FIG. 3 is a circuit diagram of a fuse circuit of the hybrid integrated device of the present invention.
FIG. 4 is a sectional view of a conventional package type semiconductor device.
FIG. 5 is a plan view of a conventional hybrid integrated device.
6A and 6B are cross-sectional views of a conventional hybrid integrated device. FIG. 6A is a cross-sectional view showing a manufacturing process, and FIG. 6B is a completed cross-sectional view.
[Explanation of symbols]
31A, 31F
Claims (3)
前記ダイボンディングパッドに載置されたベアチップと、
前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、
アース端子となる前記一の導電パターンとアース間に設けられた補助導電パターンとよりなり、
前記アース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続したことを特徴とする混成集積装置のヒューズ回路。A plurality of conductive patterns provided with a die bonding pad and a wire bonding pad on which a bare chip is mounted, separated by a separation groove,
A bare chip mounted on the die bonding pad,
A thin metal wire connecting the bare chip electrode and a wire bonding pad,
It comprises an auxiliary conductive pattern provided between the one conductive pattern serving as a ground terminal and the ground,
A fuse circuit for a hybrid integrated device, wherein the conductive pattern serving as the ground terminal and the auxiliary conductive pattern are connected by a thin metal wire that blows with a smaller current than a thin metal wire connecting the bare chip and the conductive pattern.
前記ダイボンディングパッドに載置されたベアチップと、
前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、
電源端子となる一の導電パターンと電源間に設けられた補助導電パターンとよりなり、
前記電源端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続したことを特徴とする混成集積装置のヒューズ回路。A plurality of conductive patterns provided with a die bonding pad and a wire bonding pad on which a bare chip is mounted, separated by a separation groove,
A bare chip mounted on the die bonding pad,
A thin metal wire connecting the bare chip electrode and a wire bonding pad,
It consists of one conductive pattern that becomes a power supply terminal and an auxiliary conductive pattern provided between the power supplies,
A fuse circuit for a hybrid integrated device, wherein the conductive pattern serving as the power supply terminal and the auxiliary conductive pattern are connected by a thin metal wire that blows with a smaller current than a thin metal wire connecting the bare chip and the conductive pattern.
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JP2002281890A JP4093835B2 (en) | 2002-09-26 | 2002-09-26 | Motor driver fuse circuit incorporated in hybrid integrated circuit device |
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JP2002281890A JP4093835B2 (en) | 2002-09-26 | 2002-09-26 | Motor driver fuse circuit incorporated in hybrid integrated circuit device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100401420C (en) * | 2004-05-05 | 2008-07-09 | 台湾积体电路制造股份有限公司 | Fuse circuit |
US10707153B2 (en) | 2016-04-29 | 2020-07-07 | Stmicroelectronics S.R.L. | Semiconductor device having die pad |
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2002
- 2002-09-26 JP JP2002281890A patent/JP4093835B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100401420C (en) * | 2004-05-05 | 2008-07-09 | 台湾积体电路制造股份有限公司 | Fuse circuit |
US10707153B2 (en) | 2016-04-29 | 2020-07-07 | Stmicroelectronics S.R.L. | Semiconductor device having die pad |
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