JP4093835B2 - Motor driver fuse circuit incorporated in hybrid integrated circuit device - Google Patents

Motor driver fuse circuit incorporated in hybrid integrated circuit device Download PDF

Info

Publication number
JP4093835B2
JP4093835B2 JP2002281890A JP2002281890A JP4093835B2 JP 4093835 B2 JP4093835 B2 JP 4093835B2 JP 2002281890 A JP2002281890 A JP 2002281890A JP 2002281890 A JP2002281890 A JP 2002281890A JP 4093835 B2 JP4093835 B2 JP 4093835B2
Authority
JP
Japan
Prior art keywords
conductive pattern
bare chip
hybrid integrated
integrated circuit
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2002281890A
Other languages
Japanese (ja)
Other versions
JP2004119731A (en
Inventor
寛 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2002281890A priority Critical patent/JP4093835B2/en
Publication of JP2004119731A publication Critical patent/JP2004119731A/en
Application granted granted Critical
Publication of JP4093835B2 publication Critical patent/JP4093835B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Fuses (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はモータードライバーのアース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続した混成集積回路装置に組み込んだモータードライバーのヒューズ回路に関する。
【０００２】
【従来の技術】
最近特に、携帯用のコンピュータあるいはプリンター等の電子機器に使用される半導体回路装置は小型化、薄型化及び軽量化が一段と求められている。そのため半導体回路装置として、半導体基板に半導体素子を取付け、その半導体基板を絶縁樹脂でモールドしたパッケージ型半導体装置がある。
【０００３】
図４は従来のパッケージ型半導体装置である。パッケージ型半導体装置は基板１上に形成したダイボンディングパッド２にＬＳＩ等のベアチップ３を取付け、そのベアチップ３の電極４、４とリード端子５、５を金属細線６、６で接続する。さらにリード端子５、５をプリント基板７に印刷したプリント配線８、８にハンダ付して取付ける。
【０００４】
そして基板１及びベアチップ３の周囲を絶縁性樹脂層９で被覆している。このパッケージ型半導体装置は、リード端子５、５が絶縁性樹脂層９から外部に露出されているため、全体のサイズが大きく、小型化、薄型化および軽量化に難点がある。
【０００５】
図５及び図６は前述したパッケージ型半導体装置を改良した混成集積回路装置の一部分の平面図及び断面図である。
【０００６】
ＩＣあるいはＬＳＩの回路素子のベアチップ１０を導電パターン１１上に形成したダイボンディングパッド１１Ａに取付ける。ＬＳＩ等のベアチップ１０の電極１３Ａ１、１３Ａ２、１３Ａ３・・・１３Ａ７・・・は導電パターン１４Ａ１、１４Ａ７・・・に設けられたワイヤーボンデイングパッド１５Ａ１・・・１５Ａ７・・・にボンディングされた金属細線１６Ａ１、１６２Ａ２・・・１６Ａ７・・・でもって接続されている。
【０００７】
図６（Ａ）に示すように、前述の状態では導電パターン１１、１４Ａ１・・・１４Ａ７・・・は分離溝１８Ａ、１８Ｂ・・・で上部は電気的に分離されているが、下部はまだ連続されている。
【０００８】
導電パターン１１と導電パターン１４Ａ１・・・１４Ａ７・・・、導電パターン１１に取付けられたベアチップ１０および金属細線１６Ａ１・・・１６Ａ７・・・を絶縁性樹脂２０でモールドし全体を被覆すると共に一体に固定する。然る後導電パターン１１と導電パターン１４Ａ１・・・１４Ａ７・・・の下部の連続する部分を絶縁性樹脂２０と共に点線で示すように切断し、導電パターン１１と導電パターン１４Ａ１・・・１４Ａ７・・・を完全に電気的に分離する。
【０００９】
図６（Ｂ）のごとく、導電パターン１１、１４Ａ１・・・１４Ａ７・・・の下面に於いては、絶縁性樹脂２０から露出する形になる。導電パターン１１、１４Ａ１、１４Ａ２・・・の露出部分は外部との電気的・熱的な接続を行うために、半田等を設けて外部電極２１Ａ・・・２１Ａ７・・・及び電極２２が形成される。さらに、導電パターン１１、１４Ａ１・・・１４Ａ７・・・の外部電極を設けない個所は、導電パターンの保護等を目的としてレジスト２３により被覆し、混成集積回路装置を形成している。
【００１０】
前述のようにして形成した混成集積回路は外部電極２１Ａ・・・２１Ａ７・・・、２２を印刷基板に必要な配線を施された印刷配線に直接接合し、モーター回路等を構成する。
【００１１】
【特許文献１】
特開平０４−１６２６９１
【００１２】
【発明が解決しようとする課題】
一般にモーター回路等の大きな電流が流れる混成集積回路ではヒューズを設ける。
【００１３】
しかし前述したように、上部は分離しているが下部は連続する導電パターンにＩＣあるいはＬＳＩ等のベアチップおよびチップ抵抗及びチップコンデンサ等を取付け、且つボンディングされた金属細線でベアチップの電極と導電パターンに設けたワイヤーボンディングパッドを接続する。然る後絶縁性樹脂でモールドした後前記導電パターンの下部連続する部分を切断し、基板を用いることなく作成した混成集積回路においては、薄型化、小型化及び安価が要求されるため、前述したヒューズ回路を設けることは不適当である。
【００１４】
【課題を解決するための手段】
本発明は特別なヒューズ回路を設けることなくヒューズ機能を持たせた混成集積回路装置に組み込んだモータードライバーのヒューズ回路で、
モータードライバーの入力信号増幅用のトランジスタ、コントロール信号発生用のコントロール回路と制御回路とを構成するベアチップが載置されるダイボンディングパッドを有するベアチップ用の導電パターンと、前記ベアチップ用の導電パターンの周囲に設けられ該ベアチップ用の導電パターン及び夫々が分離溝で分離されたワイヤーボンディングパッドを有するワイヤーボンデンィング用の導電パターンと、前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、前記ワイヤー用の導電パターンのうち前記トランジスタ、コントロール回路と制御回路からのアースとなる導電パターンが接続されたアース端子となる導電パターンと、前記アース端子となる導電パターンに対応される補助導電パターンとにて混成集積回路装置を形成し、アース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続し、前記混成集積回路を前記補助導電パターンの外部電極が外部電極のアース端子に接続されたアース印刷配線に接触するように印刷基板に載置した混成集積回路装置に組み込んだモータードライバーのヒューズ回路を提供する。
【００１５】
【発明の実施の形態】
本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路を図１〜図３に従って説明する。
【００１６】
図１及び図２は本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路の平面図及び断面図である。
【００１７】
ワイヤーボンディングパッド３１Ａ・・３１Ｆ・・を上部に形成した多くの導電パターン３２Ａ・・３２Ｆ・・とダイボンディングパッド３３Ａ等を形成した導電パターン３４Ａ及びワイヤーボンディングパッド３５Ａを形成したアース端子となる導電パターン３５さらにワイヤーボンディングパッド３７Ａを形成した補助導電パターン３７を有する。導電パターン３２Ａ・・３２Ｆ・・とアース端子となる導電パターン３５さらに補助導電パターン３７とは図２（Ａ）に示すように上部は分離溝３６、３６で電気的に分離されているが、下部は連続されている。
【００１８】
導電パターン３４Ａに形成されたダイボンディングパッド３３Ａにはモーター回路の制御を行うＬＳＩのベアチップ４０が取付けられている。ベアチップ４０の各電極４１Ａ、４１Ｂ・・４１Ｆ・・・等と導電パターン３２Ａ・・・３２Ｆ・・・に形成されたワイヤーボンディングパッド３１Ａ、３１Ｂ・・・３１Ｆ・・・はワイヤーボンディングされた金属細線４２Ａ、４２Ｂ・・・４２Ｆ・・・で接続される。
【００１９】
ベアチップ４０の電極４１Ａと金属細線４２Ａで接続されたワイヤーボンディングパッド３１Ａはアース端子となる導電パターン３５に形成されたワイヤーボンディングパッド３５Ａとワイヤーボンディングされた金属細線４２Ｔで接続されている。
【００２０】
さらに導電パターン３５のワイヤーボンディングパッド３５Ａは補助導電パターン３７に設けられたワイヤーボンディングパッド３７Ａと金属細線４２Ａ、４２Ｂ・・・４２Ｆ・・・より径を小さくし溶断電流を小さくしたヒューズとなる金属細線４３で接続されている。本実施例では金属細線４２Ａ、４２Ｂ・・・４２Ｆ・・・４２Ｔ・・・は直径３８μｍの金線が使用され、ヒューズとなる金属細線４３は直径２３μｍの金線が使用さている。
【００２１】
モーターコントロール用のＩＣのベアチップ４４は同じく他のダイボンディングパッドに取り付けられ、各電極４５Ａ・・・は金属細線４２Ｇ・・・でワイヤーボンディングパッド３１Ｇ・・・に接続されている。同様に入力トランジスタのベアチップ４６はダイボンディングパッドに取り付けられ、電極４７Ａ・・・は金属細線４２Ｒ・・・で各ワイヤーボンディングパッド３１Ｒ・に接続されている。さらにチップ抵抗４８Ａ、４８Ｂ・・・の電極がダイボンディングパッド３３Ｂ、３３Ｃ・・・に直接取付けられている。
【００２２】
ダイボンディングパッド３３ＡにＬＳＩのベアチップ４０を取付け、ベアチップ４０の各電極３１Ａ、３１Ｂ・・・３１Ｆ・・・と導電パターン３２Ａ・・・３２Ｆ等を金属細線４２Ａ、４２Ｂ・・・４２Ｆ・・・で接続する等して、各回路素子を取付けると共に電気的接続した後、これら回路素子、導電パターン及び金属細線を絶縁性樹脂５０でモールドし固定する。
【００２３】
回路素子、導電パターン及び金属細線を絶縁性樹脂２０でモールドし固定した後、図２（Ａ）に示す点線で導電パターン３２Ａ、３２Ｆ、３５、３７・・・を絶縁性樹脂５０と共に切断する。図２（Ｂ）のごとく、この状態では導電パターン３２Ａ、３２Ｆ、３５、３７・・・の下端は外部に露出されているので、露出されている部分に半田でもって外部電極４９Ａ、４９Ｂ、４９Ｃ・・・４９Ｅを形成する。そして導電パターン３２Ａ、３２Ｆ、３５、３７・・・の残りの露出部分をレジスト５０・・で被覆することにより混成集積回路装置５１のモータードライバー部分が完成する。
【００２４】
前述のようにして形成された混成集積回路装置５１はプリンタ-等のモーター回路を完成させるために所定の印刷配線が施された印刷基板に載置される。すると補助導電端子３７の外部電極４９Ｅが印刷基板のアース印刷配線に接触する。
【００２５】
金属細線４２Ａ、４２Ｂ・・・等は直径３８μｍの金線で形成されており１．９Ａの直流電流まで溶断することなく流せるが、ヒューズとなる金属細線４３は直径２３μｍの金線で形成されている。そのため１．０Ａ以上の直流電流が流れると溶断する。従ってモーター回路に１．０Ａ以上の過大電流が流れた時、ヒューズとなる金属細線４３が切断され、ＬＳＩ等のベアチップには過大電流が流れるのを防止し、これら回路素子が破壊されるのを防止する。
【００２６】
上述の実施例ではヒューズとなる金属細線４３をアース端子となる導電パターンと補助導電パターン間に接続したが、ヒューズとなる金属細線４３を電源端子となる導電パターンを設け、電源端子となる導電パターンと補助導電パターン間に接続してもよい。
【００２７】
図３は前述した混成集積回路装置５１を用いたプリンターのモーター回路である。混成集積回路装置５１にはＣＰＵ５２、モーター５３、電源５４及びコンデンサ５５等が外付けされている。
【００２８】
混成集積回路装置５１はベアチップ４４で形成したコントロール部５６、ベアチップ４０で形成した制御回路５７及びベアチップ４６よりなる入力トランジスタ部５８よりなる。
【００２９】
ＣＰＵ５２から入力信号ＩＮ１が入力されると、トランジスタＴＲ１で増幅されコントロール回路５６に加わる。すると端子Ｓからハイレベルの信号を発生し、トランジスタＴＲ３をオンする。それによりトランジスタＴＲ４、ＴＲ５はオンする。このときトランジスタＴＲ６はオフされているので、端子ＴはローレベルであるためトランジスタＴＲ７、ＴＲ８はオフされている。
【００３０】
従って電源５４から端子ＶＣＣに加わった直流電圧ＶＤＤはトランジスタＴＲ４を経て端子ＯＵＴ２よりモーター５３に加わり、再び端子ＯＵＴ１からトランジスタＴＲ５を経て端子３５Ａに加わり、ヒューズとなる金属細線４３を経て印刷基板のアース印刷配線（図示せず）に流れ、モーター５３を回転させる。
【００３１】
次にＣＰＵ５２から入力信号ＩＮ２が入力されると、トランジスタＴＲ２で増幅されコントロール回路５６に加わる。今度は端子Ｔからハイレベルの信号を発生し、トランジスタＴＲ６をオンする。それによりトランジスタＴＲ７、ＴＲ８はオンする。このときトランジスタＴＲ３はオフされているので、トランジスタＴＲ４、ＴＲ５はオフされている。
【００３２】
そのため電源５４から端子ＶＣＣに加わった直流電圧ＶＤＤはトランジスタＴＲ７を経て端子ＯＵＴ１よりモーター５３に加わり、再び端子ＯＵＴ２からトランジスタＴＲ８を経て端子３５Ａに加わり、ヒューズとなる金属細線４３を経て印刷基板のアース印刷配線（図示せず）に流れ、モーター５３を回転させるが、前述とモーター５３に流れる電流の向き逆となるので、モーター５３は前述と逆に回転する。
【００３３】
何らかの原因で制御回路５７に過大電流が流れる。すると各ベアチップ４０、４４、４６とワイヤーボンディングパッド３１Ａ、３１Ｆ・・・等を接続する金属細線４２Ａ、４２Ｂ・・・よりヒューズとなる金属細線４３の径が細くされ溶断され易くしているので、金属細線４３が溶断し、回路素子が過大電流で破壊されるのを防止する。
【００３４】
前述においてヒューズとなる金属細線をアース導電端子と補助導電端子間に接続したが、ヒューズとなる金属細線を電源導電端子と補助導電端子間に接続してもよい。
【００３５】
【発明の効果】
本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路はモータードライバーのアース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断するヒューズ用の金属細線で接続したので、モーターがロック等して大電流が流れても特別なヒューズ回路を設けることなくヒューズ効果を得ることができる。従って安価で且つ小型化されるので、各導電端子及びチップ部品をモールドし一体化したモータードライバーを組み込んだ混成集積回路として好適である。
【図面の簡単な説明】
【図１】本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路の平面図である。
【図２】本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路の断面図で、図２（Ａ）は製造過程を示す断面図、図２（Ｂ）は完成した断面図である。
【図３】本発明の混成集積回路装置に組み込んだモータードライバーのヒューズ回路の回路図である。
【図４】従来のパッケージ型半導体装置の断面図である。
【図５】従来の混成集積回路装置の平面図である。
【図６】従来の混成集積回路装置の断面図で、図６（Ａ）は製造過程を示す断面図、図６（Ｂ）は完成した断面図である。
【符号の説明】
３１Ａ、３１Ｆ ワイヤーボンディングパッド
３２Ａ、３２Ｆ 導電パターン
３５ アース端子となる導電パターン
３７ 補助導電パターン
４０ ベアチップ
４１Ａ、４１Ｂ 電極
４２Ａ、４２Ｆ 金属細線
４３ ヒューズ用の金属細線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fuse circuit for a motor driver incorporated in a hybrid integrated circuit device in which a conductive pattern serving as a ground terminal of a motor driver and an auxiliary conductive pattern are connected by a thin metal wire fused with a smaller current than the thin metal wire connecting the bare chip and the conductive pattern. About.
[0002]
[Prior art]
Recently, semiconductor circuit devices used in electronic devices such as portable computers or printers are increasingly required to be smaller, thinner and lighter. Therefore, as a semiconductor circuit device, there is a package type semiconductor device in which a semiconductor element is attached to a semiconductor substrate and the semiconductor substrate is molded with an insulating resin.
[0003]
FIG. 4 shows a conventional package type semiconductor device. In the package type semiconductor device, a bare chip 3 such as an LSI is attached to a die bonding pad 2 formed on a substrate 1, and electrodes 4, 4 of the bare chip 3 and lead terminals 5, 5 are connected by thin metal wires 6, 6. Further, the lead terminals 5 and 5 are attached to the printed wirings 8 and 8 printed on the printed circuit board 7 by soldering.
[0004]
The periphery of the substrate 1 and the bare chip 3 is covered with an insulating resin layer 9. Since this package type semiconductor device has the lead terminals 5 and 5 exposed to the outside from the insulating resin layer 9, the overall size is large, and there are difficulties in miniaturization, thinning, and weight reduction.
[0005]
5 and 6 are a plan view and a sectional view of a part of a hybrid integrated circuit device obtained by improving the package type semiconductor device described above.
[0006]
A bare chip 10 of an IC or LSI circuit element is attached to a die bonding pad 11 A formed on a conductive pattern 11. The electrodes 13A1, 13A2, 13A3,... 13A7,. , 162A2... 16A7.
[0007]
As shown in FIG. 6A, in the above-described state, the conductive patterns 11, 14A1,... 14A7, etc. are electrically separated by the separation grooves 18A, 18B,. It is continuous.
[0008]
The conductive pattern 11 and the conductive patterns 14A1,... 14A7, the bare chip 10 attached to the conductive pattern 11 and the fine metal wires 16A1,. Fix it. After that, the conductive pattern 11 and the conductive patterns 14A1,... 14A7,. • Isolate completely completely.
[0009]
As shown in FIG. 6B, the lower surfaces of the conductive patterns 11, 14A1,... 14A7,. The exposed portions of the conductive patterns 11, 14A1, 14A2,... Are provided with external electrodes 21A... 21A7. The Further, the portions of the conductive patterns 11, 14 A 1... 14 A 7... That are not provided with external electrodes are covered with a resist 23 for the purpose of protecting the conductive patterns, thereby forming a hybrid integrated circuit device.
[0010]
In the hybrid integrated circuit formed as described above, the external electrodes 21A... 21A7... 22 are directly joined to the printed wiring provided with the necessary wiring on the printed circuit board to constitute a motor circuit or the like.
[0011]
[Patent Document 1]
JP 04-162691
[0012]
[Problems to be solved by the invention]
Generally, a hybrid is provided in a hybrid integrated circuit in which a large current flows, such as a motor circuit.
[0013]
However, as described above, a bare chip such as IC or LSI, a chip resistor and a chip capacitor are attached to a continuous conductive pattern while the upper part is separated, and the bare chip electrode and the conductive pattern are bonded with a thin metal wire. Connect the provided wire bonding pads. Then, after molding with an insulating resin, the lower continuous portion of the conductive pattern is cut, and the hybrid integrated circuit prepared without using the substrate is required to be thin, downsized, and inexpensive. It is inappropriate to provide a fuse circuit.
[0014]
[Means for Solving the Problems]
The present invention is a fuse circuit for a motor driver incorporated in a hybrid integrated circuit device having a fuse function without providing a special fuse circuit.
A conductive pattern for a bare chip having a die bonding pad on which a bare chip constituting a transistor for forming an input signal of a motor driver, a control circuit for generating a control signal and a control circuit is placed, and the periphery of the conductive pattern for the bare chip The conductive pattern for the bare chip and the conductive pattern for wire bonding having the wire bonding pad separated by the separation groove, the metal wire connecting the electrode of the bare chip and the wire bonding pad, and the wire A conductive pattern serving as a ground terminal to which a conductive pattern serving as a ground from the transistor, the control circuit and the control circuit is connected, and an auxiliary conductive pattern corresponding to the conductive pattern serving as the ground terminal. Hybrid To form a product circuit device, and connected to the conductive pattern serving as ground terminals between auxiliary conductive pattern by a metal thin wire for fusing with a small current from the fine metal wire for connecting the bare chip and the conductive pattern, the hybrid integrated circuit of the auxiliary conductive pattern Provided is a motor driver fuse circuit incorporated in a hybrid integrated circuit device mounted on a printed circuit board so that an external electrode contacts a ground printed wiring connected to a ground terminal of the external electrode.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
A motor driver fuse circuit incorporated in the hybrid integrated circuit device of the present invention will be described with reference to FIGS.
[0016]
1 and 2 are a plan view and a sectional view of a fuse circuit of a motor driver incorporated in the hybrid integrated circuit device of the present invention.
[0017]
Conductive patterns 34A, 31F,... With a plurality of conductive patterns 32A,... 32F,..., A die bonding pad 33A, etc., and a wire bonding pad 35A. 35. Furthermore, it has an auxiliary conductive pattern 37 on which a wire bonding pad 37A is formed. As shown in FIG. 2A, the upper portion of the conductive patterns 32A, 32F,..., And the auxiliary conductive pattern 37 are electrically separated by the separation grooves 36, 36. Are continuous.
[0018]
An LSI bare chip 40 for controlling the motor circuit is attached to the die bonding pad 33A formed on the conductive pattern 34A. The electrodes 41A, 41B,... 41F, etc. of the bare chip 40 and the wire bonding pads 31A, 31B,. 42A, 42B... 42F.
[0019]
The wire bonding pad 31A connected to the electrode 41A of the bare chip 40 and the metal thin wire 42A is connected to the wire bonding pad 35A formed on the conductive pattern 35 serving as a ground terminal by the wire thin metal wire 42T.
[0020]
Further, the wire bonding pad 35A of the conductive pattern 35 is a metal thin wire serving as a fuse having a diameter smaller than that of the wire bonding pad 37A provided on the auxiliary conductive pattern 37 and the metal thin wires 42A, 42B,. 43 is connected. In this embodiment, the fine metal wires 42A, 42B,... 42F,... 42T,... Use gold wires with a diameter of 38 .mu.m, and the fine metal wires 43 used as fuses use gold wires with a diameter of 23 .mu.m.
[0021]
The bare chip 44 of the motor control IC is similarly attached to another die bonding pad, and the electrodes 45A... Are connected to the wire bonding pads 31G. Similarly, the bare chip 46 of the input transistor is attached to the die bonding pad, and the electrodes 47A... Are connected to the wire bonding pads 31R. Further, the electrodes of the chip resistors 48A, 48B... Are directly attached to the die bonding pads 33B, 33C.
[0022]
The LSI bare chip 40 is attached to the die bonding pad 33A, and the electrodes 31A, 31B,... 31F, etc. and the conductive patterns 32A,. After each circuit element is attached and electrically connected, for example, by connection, these circuit elements, conductive patterns, and fine metal wires are molded and fixed with an insulating resin 50.
[0023]
After the circuit element, the conductive pattern, and the fine metal wire are molded and fixed with the insulating resin 20, the conductive patterns 32A, 32F, 35, 37,... Are cut along with the insulating resin 50 along the dotted lines shown in FIG. As shown in FIG. 2B, in this state, the lower ends of the conductive patterns 32A, 32F, 35, 37... Are exposed to the outside, so that the exposed portions are soldered to the external electrodes 49A, 49B, 49C. ... 49E is formed. The remaining exposed portions of the conductive patterns 32A, 32F, 35, 37,... Are covered with a resist 50, so that the motor driver portion of the hybrid integrated circuit device 51 is completed.
[0024]
The hybrid integrated circuit device 51 formed as described above is placed on a printed board on which a predetermined printed wiring is provided in order to complete a motor circuit such as a printer. Then, the external electrode 49E of the auxiliary conductive terminal 37 comes into contact with the ground printed wiring of the printed board.
[0025]
The fine metal wires 42A, 42B, etc. are formed of gold wires with a diameter of 38 μm and can flow up to a 1.9 A direct current without fusing, but the fine metal wires 43 that serve as fuses are formed of gold wires with a diameter of 23 μm. Yes. Therefore, it melts when a direct current of 1.0 A or more flows. Therefore, when an excessive current of 1.0 A or more flows in the motor circuit, the metal thin wire 43 serving as a fuse is cut, preventing an excessive current from flowing in a bare chip such as an LSI, and destroying these circuit elements. To prevent.
[0026]
In the above-described embodiment, the thin metal wire 43 serving as the fuse is connected between the conductive pattern serving as the ground terminal and the auxiliary conductive pattern. However, the thin metal wire 43 serving as the fuse is provided with the conductive pattern serving as the power supply terminal, and the conductive pattern serving as the power supply terminal. And an auxiliary conductive pattern.
[0027]
FIG. 3 shows a motor circuit of a printer using the hybrid integrated circuit device 51 described above. A CPU 52, a motor 53, a power supply 54, a capacitor 55, and the like are externally attached to the hybrid integrated circuit device 51.
[0028]
The hybrid integrated circuit device 51 includes a control unit 56 formed of a bare chip 44 , a control circuit 57 formed of a bare chip 40 , and an input transistor unit 58 including a bare chip 46.
[0029]
When the input signal IN1 is input from the CPU 52, it is amplified by the transistor TR1 and applied to the control circuit 56. Then, a high level signal is generated from the terminal S, and the transistor TR3 is turned on. Thereby, the transistors TR4 and TR5 are turned on. At this time, since the transistor TR6 is turned off, the terminals T are at a low level, so that the transistors TR7 and TR8 are turned off.
[0030]
Accordingly, the DC voltage VDD applied from the power source 54 to the terminal VCC is applied to the motor 53 from the terminal OUT 2 through the transistor TR4, and is applied again to the terminal 35A from the terminal OUT 1 through the transistor TR5, and through the fine metal wire 43 serving as a fuse. To the ground printed wiring (not shown), and the motor 53 is rotated.
[0031]
Next, when the input signal IN2 is input from the CPU 52, it is amplified by the transistor TR2 and applied to the control circuit 56. This time, a high level signal is generated from the terminal T to turn on the transistor TR6. Thereby, the transistors TR7 and TR8 are turned on. At this time, since the transistor TR3 is turned off, the transistors TR4 and TR5 are turned off.
[0032]
Therefore, the DC voltage VDD applied from the power source 54 to the terminal VCC is applied to the motor 53 from the terminal OUT 1 through the transistor TR7, and is applied again to the terminal 35A from the terminal OUT 2 through the transistor TR8, and through the fine metal wire 43 serving as a fuse. In this case, the motor 53 rotates in the direction of the ground printed wiring (not shown), but the direction of the current flowing through the motor 53 is opposite to that described above, so the motor 53 rotates in the opposite direction.
[0033]
An excessive current flows through the control circuit 57 for some reason. Then, the diameter of the fine metal wire 43 that becomes a fuse is made thinner than the fine metal wires 42A, 42B,... Connecting the bare chips 40, 44, 46 and the wire bonding pads 31A, 31F, etc. The thin metal wire 43 is melted and the circuit element is prevented from being destroyed by an excessive current.
[0034]
In the above description, the fine metal wire serving as the fuse is connected between the ground conductive terminal and the auxiliary conductive terminal. However, the fine metal wire serving as the fuse may be connected between the power supply conductive terminal and the auxiliary conductive terminal.
[0035]
【The invention's effect】
The fuse circuit of the motor driver incorporated in the hybrid integrated circuit device of the present invention is a metal for a fuse that fuses between a conductive pattern serving as a ground terminal of the motor driver and an auxiliary conductive pattern with a smaller current than a metal thin wire connecting the bare chip and the conductive pattern. Since the connection is made with a thin wire, the fuse effect can be obtained without providing a special fuse circuit even if a large current flows due to the motor locking or the like. Therefore, since it is inexpensive and downsized, it is suitable as a hybrid integrated circuit incorporating a motor driver in which each conductive terminal and chip component are molded and integrated.
[Brief description of the drawings]
FIG. 1 is a plan view of a fuse circuit of a motor driver incorporated in a hybrid integrated circuit device of the present invention.
2A and 2B are cross-sectional views of a fuse circuit of a motor driver incorporated in a hybrid integrated circuit device of the present invention, FIG. 2A is a cross-sectional view showing a manufacturing process, and FIG. 2B is a completed cross-sectional view.
FIG. 3 is a circuit diagram of a fuse circuit of a motor driver incorporated in the hybrid integrated circuit device of the present invention.
FIG. 4 is a cross-sectional view of a conventional package type semiconductor device.
FIG. 5 is a plan view of a conventional hybrid integrated circuit device .
6A and 6B are cross-sectional views of a conventional hybrid integrated circuit device , in which FIG. 6A is a cross-sectional view showing a manufacturing process, and FIG. 6B is a completed cross-sectional view.
[Explanation of symbols]
31A, 31F Wire bonding pads 32A, 32F Conductive pattern 35 Conductive pattern 37 serving as ground terminal Auxiliary conductive pattern 40 Bare chip 41A, 41B Electrode 42A, 42F Metal fine wire 43 Metal fine wire for fuse

Claims (1)

モータードライバーの入力信号増幅用のトランジスタ、コントロール信号発生用のコントロール回路と制御回路とを構成するベアチップが載置されるダイボンディングパッドを有するベアチップ用の導電パターンと、前記ベアチップ用の導電パターンの周囲に設けられ該ベアチップ用の導電パターン及び夫々が分離溝で分離されたワイヤーボンディングパッドを有するワイヤーボンデンィング用の導電パターンと、前記ベアチップの電極とワイヤーボンディングパッドとを接続する金属細線と、前記ワイヤー用の導電パターンのうち前記トランジスタ、コントロール回路と制御回路からのアースとなる導電パターンが接続されたアース端子となる導電パターンと、前記アース端子となる導電パターンに対応し設けられた補助導電パターンとにて混成集積回路装置を形成し、
前記アース端子となる導電パターンと補助導電パターン間をベアチップと導電パターンを接続する金属細線より小電流で溶断する金属細線で接続し、
前記混成集積回路を前記補助導電パターンの外部電極が電源のアース端子に接続されたアース印刷配線に接触するように印刷基板に載置したことを特徴とする混成集積回路装置に組み込んだモータードライバーのヒューズ回路。 A conductive pattern for a bare chip having a die bonding pad on which a bare chip constituting a transistor for forming an input signal of a motor driver, a control circuit for generating a control signal and a control circuit is placed, and the periphery of the conductive pattern for the bare chip The conductive pattern for the bare chip and the conductive pattern for wire bonding having the wire bonding pad separated by the separation groove, the metal wire connecting the electrode of the bare chip and the wire bonding pad, and the wire A conductive pattern serving as a ground terminal to which a conductive pattern serving as a ground from the transistor, the control circuit and the control circuit is connected, and an auxiliary conductive pattern provided corresponding to the conductive pattern serving as the ground terminal In The hybrid integrated circuit device is formed,
Between the conductive pattern serving as the ground terminal and the auxiliary conductive pattern is connected by a thin metal wire that blows with a smaller current than the thin metal wire that connects the bare chip and the conductive pattern,
A motor driver incorporated in a hybrid integrated circuit device, wherein the hybrid integrated circuit is placed on a printed circuit board so that an external electrode of the auxiliary conductive pattern is in contact with a ground printed wiring connected to a ground terminal of a power source. Fuse circuit.
JP2002281890A 2002-09-26 2002-09-26 Motor driver fuse circuit incorporated in hybrid integrated circuit device Expired - Lifetime JP4093835B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002281890A JP4093835B2 (en) 2002-09-26 2002-09-26 Motor driver fuse circuit incorporated in hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002281890A JP4093835B2 (en) 2002-09-26 2002-09-26 Motor driver fuse circuit incorporated in hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JP2004119731A JP2004119731A (en) 2004-04-15
JP4093835B2 true JP4093835B2 (en) 2008-06-04

Family

ID=32276220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002281890A Expired - Lifetime JP4093835B2 (en) 2002-09-26 2002-09-26 Motor driver fuse circuit incorporated in hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP4093835B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196570B2 (en) * 2004-05-05 2007-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-time programmable resistance circuit
ITUA20163031A1 (en) 2016-04-29 2017-10-29 St Microelectronics Srl SEMICONDUCTOR DEVICE AND CORRESPONDENT PROCEDURE

Also Published As

Publication number Publication date
JP2004119731A (en) 2004-04-15

Similar Documents

Publication Publication Date Title
US6610923B1 (en) Multi-chip module utilizing leadframe
KR960019670A (en) Semiconductor chip package and manufacturing method thereof
JP2001196529A (en) Semiconductor device and wiring method therefor
WO2007026944A1 (en) Circuit device and method for manufacturing same
JPH1174433A (en) Semiconductor device
JP4645832B2 (en) Semiconductor device and manufacturing method thereof
JP4093835B2 (en) Motor driver fuse circuit incorporated in hybrid integrated circuit device
JPH05121644A (en) Electronic circuit device
US5422515A (en) Semiconductor module including wiring structures each having different current capacity
US6590284B2 (en) Semiconductor device and method of manufacturing same
JP3423174B2 (en) Chip-on-board mounting structure and method of manufacturing the same
JP4296916B2 (en) Semiconductor device
KR20010074816A (en) Thermal head and thermal head unit
JPH10256308A (en) Structure and method for mounting semiconductor chip
JP2503984Y2 (en) Hybrid integrated circuit
JP3203157B2 (en) Hybrid integrated circuit device
JPH079969B2 (en) High power hybrid integrated circuit device
JPH0430565A (en) High power output hybrid integrated circuit device
JPH06140535A (en) Tape-carrier-package type semiconductor device
JPH08298272A (en) Manufacture of semiconductor device
JP2547565B2 (en) Manufacturing method of hybrid integrated circuit
JP2000124251A (en) Semiconductor device, manufacture thereof, circuit board and electronic equipment
JP3172292B2 (en) Hybrid integrated circuit device
JPH0766955B2 (en) High power hybrid integrated circuit device
JPH0451488Y2 (en)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050926

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070410

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070508

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070703

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080205

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080304

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110314

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110314

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110314

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130314

Year of fee payment: 5