TWI632655B - Power semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention relates to a power management device capable of realizing voltage switching, in particular to a low A gold-oxide half-field effect transistor (MOSFET) chip and a high-order MOSFET chip are integrated into a voltage conversion device that controls an integrated circuit (IC) and a method of fabricating the same. a first wafer is flip-chip mounted on the first mounting region, the metal pad on the front surface of the first wafer is mated with the pad located in the first mounting region; and a second wafer is flip-chip mounted in the second mounting region in a flip chip manner a metal pad on the front surface of the second wafer is mated with the pad pad located in the second mounting region; and a conductive structure is connected between the bonding pad and the metal layer on the back surface of the first wafer, and a package covering the front surface of the substrate A wafer, a second wafer, and a conductive structure are covered.

Description

Power device and preparation method

The invention relates to a power management device capable of realizing voltage switching, in particular to a low-order metal oxide half field effect transistor (MOSFET) chip and a high-order MOSFET chip and integrated into a voltage conversion device for controlling an integrated circuit (IC) and Preparation.

In a voltage converter such as a DC-DC converter, the operating state of the metal oxide half-field effect transistor (MOSFET) consumes a relatively large amount of power, requiring the source terminal or the drain of the MOSFET to have better heat dissipation. The effect is usually to expose part of the lead frame to the outside of the package. As in the prior art shown in FIG. 6 of the present invention, the high-order MOSFET 11 and the low-order MOSFET 13 are integrated in a DC-DC converter 10, which further includes a control wafer 12 that controls the output pulse width of the wafer 12. PWM (Pulse Width Modulation) or Pulse Frequency Modulation (PFM) signals are sent to the MOSFETs 11 and 13 and receive their feedback signals. A part of the electrode plates and control wafers 12 of the MOSFETs 11 and 13 are arranged in the structure. The I/O metal pads are electrically connected by a plurality of leads. The MOSFETs 11 and 13 are respectively attached to the separated metal pedestals 21, 23, the source terminal of the MOSFET 11 is connected to the metal pedestal 23 through the metal piece 15, and the source of the MOSFET 13 is connected to the pin 24 through the metal piece 16. Above, the control wafer 12 is pasted on another independent metal base 22, and the bottom surfaces of the metal bases 21 and 23 are exposed to the outside of the package not shown in the figure for electrical connection with external circuits. Contact signal and heat sink Ways to go. The obvious disadvantage is that the metal bases 21 to 23 themselves occupy a large area, which not only causes costly but also fails to meet the mainstream requirements of the market for the lightness of power devices.

In addition, U.S. Patent No. US2012061813A1 also discloses a DC-DC voltage converter for power conversion, in which high-order MOSFETs and low-order MOSFETs connected in parallel are placed on a metal pedestal, and devices for controlling the wafer are completely superimposed on the high-order MOSFET and Above the low-order MOSFET, this requires that the leads of the lower-order MOSFETs and lower-order MOSFETs below must have lower line-arc height values, otherwise the control wafer can easily reach the metal leads underneath it, causing another undesirable consequence of high-order and The heat dissipation path of the low-order MOSFET wafers on the respective upper sides is completely blocked by the control wafer. Based on the above considerations, the present application proposes various subsequent embodiments.

A power device disclosed in the present invention includes: a substrate and first and second mounting regions defined on a front surface thereof, wherein a bonding pad is disposed on a front surface of the substrate; and a first metal pad is disposed on a back surface of the substrate a pad pad, and also having a plurality of wires disposed on the substrate and a plurality of interconnect structures having a through substrate; a portion of the pads disposed in the first mounting region and a portion of the pads disposed in the second mounting region are connected by wires a portion of the pad of the first mounting region is connected to the first metal pad through the interconnect structure, and a portion of the pad of the second mounting region is connected to the pin pad through the wiring and the interconnect structure; a first wafer of a mounting region, a metal pad on the front surface of the first wafer is mated with a pad located in the first mounting region; a second wafer flip-chip mounted on the second mounting region, and a metal on the front surface of the second wafer The pad is mated with the pad located in the second mounting region; further comprising a conductive structure connected between the bond pad and the metal layer on the back side of the first wafer; and covering A front substrate of the first wafer, second wafer and the conductive clad structure including a package body.

In the above power device, the first mounting area is arranged with a first set of pads and a second set of pads, and the second mounting area is provided with a third set of pads to a sixth set of pads; wherein a part of the third set of pads The pad is electrically connected to one or more pads of the first set of pads, and a part of the pad of the third set is electrically connected to one or more pads of the second set of pads; One or more of the four sets of pads are electrically connected to one or more of the lead pads in a one-to-one manner by wiring and an interconnect structure embedded in the substrate; each of the fifth set of pads is soldered The pads are electrically connected to the bonding pads through the wiring on the substrate, and the bonding pads are electrically connected to the one or more lead pads via an interconnect structure embedded in the substrate; and each of the sixth set of pads Each of the pads is electrically connected to the one or more pin pads in a one-to-one manner through the wiring on the substrate and the interconnect structure disposed within the substrate.

In the above power device, a second metal pad is further disposed on the back surface of the substrate, and one or more of the fifth pads are connected to the second metal pad through the interconnection structure.

In the above power device, a second metal pad is further disposed on the back surface of the substrate, and one or more of the sixth set of pads are connected to the second metal pad through the interconnection structure.

In the above power device, a first metal pad on the front surface of the first wafer is correspondingly soldered to one or more of the first set of pads, and a second metal pad on the front surface of the first wafer is soldered to the first One or more of the two sets of pads.

In the above power device, one or more third metal pads on the front side of the second wafer are correspondingly soldered to one or more of the fifth set of pads in a one-to-one manner, one or more of the front faces of the second wafer a fourth metal pad correspondingly soldered to one or more of the sixth set of pads; and a plurality of fifth metal pads on the front side of the second wafer are soldered to the one-to-one A plurality of pads in the third and fourth sets of pads.

In the above power device, the first chip includes a first metal oxide half field effect transistor (MOSFET), the first metal pad is the gate of the first MOSFET, and the second metal pad is the source of the first MOSFET, The metal layer on the back side of a wafer is the drain of the first MOSFET.

In the above power device, the second chip is integrated with a control circuit and a second MOSFET, the third metal pad is the source of the second MOSFET, the fourth metal pad is the drain of the second MOSFET, and the fifth metal pad To control the input or output terminals of the circuit.

The present invention also provides a method of fabricating a power device, comprising the steps of: providing a substrate defining first and second mounting regions on a front surface thereof, a bonding pad disposed on a front surface of the substrate, and a first surface disposed on a back surface of the substrate a metal pad and a plurality of pin pads, and further comprising a plurality of wires disposed on the substrate and a plurality of interconnect structures having a through substrate; flipping a first wafer to the first mounting region, the front surface of the first wafer The metal pad is mated with the pad located in the first mounting area; the second wafer is flip-chip mounted to the second mounting area, and the metal pad on the front side of the second wafer is mated with the pad located in the second mounting area; And mounting one or more conductive structures between the metal layers on the back side of the first wafer; and forming a package covering the front surface of the substrate, the package covering the first wafer, the second wafer, and the conductive structure; wherein the layout is a portion of the pad of the first mounting region and a portion of the pad disposed in the second mounting region are connected by wiring, and a portion of the pad of the first mounting region passes through the interconnecting junction Metal bonding pad connected to the first portion of the second bonding pad region connected to the mounting pad through the pin and interconnection structure.

The present invention also provides a method of fabricating a power device, comprising the steps of: providing a substrate defining first and second mounting regions on a front surface thereof, a bonding pad disposed on a front surface of the substrate, and a first surface disposed on a back surface of the substrate a metal pad and a plurality of pin pads, and further comprising a plurality of wires disposed on the substrate and a plurality of interconnect structures having a through substrate; flipping the first wafer in a flip chip manner to the first mounting region, a metal pad on the front side of the wafer is mated with the pad located in the first mounting area; and a second chip is flip-chip mounted to the second mounting area in a flip chip manner a metal pad on the front side of the second wafer is mated with a pad located in the second mounting region; one or more conductive structures are mounted between the bonding pad and the metal layer on the back side of the first wafer; and a front surface is formed over the substrate a package, the package encapsulating the first wafer, the second wafer, and the conductive structure; wherein a portion of the pads disposed in the first mounting region and a portion of the pads disposed in the second mounting region are connected by wiring, the first mounting A portion of the pad of the region is connected to the first metal pad via the interconnect structure, and a portion of the pad of the second mounting region is connected to the pin pad by routing and interconnect structures.

In the above method, a second metal pad is further disposed on the back surface of the substrate, and one or more of the fifth pads are electrically connected to the second metal pad through the interconnection structure.

In the above method, a second metal pad is further disposed on the back surface of the substrate, and one or more of the sixth pads are connected to the second metal pad through the interconnection structure.

The above method, wherein a first metal pad on the front side of the first wafer is correspondingly soldered to one or more of the first set of pads, wherein a second metal pad on the front side of the first wafer is soldered to the second One or more pads on the pad.

In the above method, one or more third metal pads on the front side of the second wafer are correspondingly soldered to one or more of the fourth set of pads in one-to-one manner, one or more of the front faces of the second wafer a fourth metal pad correspondingly soldered to one or more of the sixth set of pads; and a plurality of fifth metal pads on the front side of the second wafer are soldered one to one Three pads and a plurality of pads in the fourth set of pads.

The present invention provides a power device including: a substrate and a first mounting region to a third mounting region defined on a front surface thereof, wherein a bonding pad is disposed on a front surface of the substrate and a first metal pad is disposed on a back surface of the substrate And a plurality of pin pads, and further comprising a plurality of wires disposed on the substrate and a plurality of interconnect structures having a through substrate; a portion of the pads disposed in the first mounting region and a portion of the pads disposed in the second mounting region pass Wiring connection, in the first installation area A portion of the pad is connected to the first metal pad through the interconnect structure; a portion of the pad of the second mounting region is connected to the pin pad through the wiring and the interconnect structure, and a portion of the pad of the second mounting region is also connected to the device by wiring a plurality of bonding pads in the vicinity of the third mounting region; a first wafer flip-chip mounted on the first mounting region, the metal pads on the front surface of the first wafer are butted to the pads in the first mounting region; a flip chip is flipped over the second wafer in the second mounting region, the metal pad on the front side of the second wafer is mated with the pad located in the second mounting region; a third wafer mounted on the third mounting region, the third wafer is back The metal layer is butted to a carrier pad located in the third mounting region; the metal layer connected to the back surface of the first wafer, a metal pad on the front surface of the third wafer, and a conductive structure between the bonding pads are connected to the bonding pad and the a lead between the metal pads on the front side of the second wafer; and a first, second and third wafer and the conductive structure and the lead covered on the front surface of the substrate Within the package.

In the above power device, the first mounting area is arranged with a first pad and a second set of pads, and the second mounting area is provided with a third set of pads to a sixth set of pads; wherein a part of the third set of pads is soldered The pad is electrically connected to one or more of the first set of pads, and a part of the third pad is electrically connected to one or more of the second set of pads; the fourth set One or more pads in the pad are electrically connected to one or more pin pads in a one-to-one manner by wiring and an interconnect structure embedded in the substrate; and a fifth set of pads, a sixth set of pads Each of the pads is electrically connected to a bonding pad through a wiring on the substrate; wherein the bonding pad and the carrier pad are each electrically connected to the one or more pin pads via the interconnection structure.

The power device described above, wherein one or more of the first set of pads are connected to the second metal pad via an interconnect structure.

In the above power device, a second metal pad is further disposed on the back surface of the substrate, and the carrier pad is connected to the second metal pad through the interconnection structure.

In the above power device, a first metal pad on the front surface of the first wafer is correspondingly soldered to one or more of the first set of pads, and a second metal pad on the front surface of the first wafer is soldered to the first One or more of the two sets of pads.

In the above power device, a third metal pad on the front surface of the third wafer is connected to the metal layer on the back surface of the first wafer, the bonding pad through the conductive structure, and the third metal pad is further connected to a bonding pad through the lead, and the third A fourth metal pad on the front side of the wafer is connected to the other bond pad by a wire.

In the above power device, a plurality of fifth metal pads on the front surface of the second wafer are soldered to the plurality of pads of the third set of pads to the sixth set of pads in a one-to-one manner.

In the above power device, the first chip includes a first MOSFET, the first metal pad is the gate of the first MOSFET, the second metal pad is the source of the first MOSFET, and the metal layer on the back side of the first chip is The drain of a MOSFET.

In the above power device, the third wafer includes a second MOSFET, the third metal pad is the source of the second MOSFET, the fourth metal pad is the gate of the second MOSFET, and the metal layer on the back side of the third chip is The drain of the second MOSFET.

In the above power device, the second mounting area and the third mounting area are arranged side by side, and the first mounting area is located on an extension line of the dividing line between the second mounting area and the third mounting area, thereby the first mounting area, The second mounting area and the third mounting area are arranged in a finished glyph.

In the above power device, the conductive structure is an L-shaped metal piece spanning over the first wafer and the third wafer, including a lateral portion on the first wafer and a longitudinal portion on the third wafer, the longitudinal portion There is an extension extending obliquely downward, the extension being pressed against the bond pad.

The present invention also provides a method of fabricating a power device, comprising the steps of: providing a substrate having a first mounting region to a third mounting region defined on a front surface of the substrate, wherein the substrate The front surface is provided with a bonding pad and a first metal pad and a plurality of pin pads are disposed on the back surface of the substrate, and a plurality of wires are disposed on the substrate and a plurality of interconnect structures having a through substrate are disposed; The first wafer is flip-chip mounted on the first mounting region, and the metal pad on the front surface of the first wafer is mated with the pad located in the first mounting region; and a second wafer is flip-chip mounted on the second mounting region in a flip chip manner. a metal pad on the front surface of the second wafer is mated with the pad located in the second mounting region; a third wafer is mounted on the third mounting region, and the metal layer on the back surface of the third wafer is docked with a carrier pad located in the third mounting region Installing a conductive structure over the first wafer and the third wafer, the conductive structure is connected between the metal layer on the back surface of the first wafer, a metal liner on the front surface of the third wafer, and the bonding pad; on the bonding pad and the second wafer Bonding of the leads between the front metal pads, connecting the leads between the bond pads and the metal pads on the front side of the second wafer; and forming a package covering the front side of the substrate Thereby covering the first wafer, the second wafer and the third wafer and the conductive structure and the lead; wherein a part of the solder pads disposed in the first mounting area and a part of the solder pads disposed in the second mounting area are connected by wiring, A portion of the pad of a mounting region is connected to the first metal pad through the interconnect structure; a portion of the pad of the second mounting region is connected to the pin pad through the wiring and the interconnect structure, and a portion of the pad of the second mounting region also passes The wiring is connected to a plurality of bonding pads disposed near the third mounting area.

In the above method, the first mounting area is arranged with a first pad and a second set of pads, and the second mounting area is provided with a third set of pads to a sixth set of pads; wherein a part of the third set of pads is One or more pads of the first set of pads are electrically connected, and a part of the pads of the third set of pads are electrically connected to one or more pads of the second set of pads; the fourth set of pads One or more solder pads are electrically connected to one or more pin pads in a one-to-one manner through wiring and an interconnect structure embedded in the substrate; and a fifth set of pads and a sixth set of pads are respectively Each of the pads is electrically connected to a bonding pad through a wiring on the substrate; wherein the bonding pads and the carrier pads are each electrically connected to the one or more pin pads via the interconnection structure.

In the above method, one or more of the first set of pads are connected to the second metal pad through the interconnect structure.

In the above method, a second metal pad is further disposed on the back surface of the substrate, and the carrier pad is connected to the second metal pad through the interconnection structure.

The above method, wherein a first metal pad on the front surface of the flipped first wafer is correspondingly soldered to one or more of the first set of pads, and a second metal pad on the front side of the first wafer is soldered to One or more of the second set of pads.

In the above method, a third metal pad on the front surface of the non-flip-mounted third wafer is connected to the metal layer on the back surface of the first wafer, the bonding pad through the conductive structure, and the third metal pad is further connected to the bonding pad through the lead. A fourth metal pad on the front side of the third wafer is connected to the other bond pad by a lead.

In the above method, the plurality of fifth metal pads on the front side of the second wafer flip-chip flip-chip are soldered in a one-to-one manner to the plurality of pads of the third set of pads to the sixth set of pads.

100, 300‧‧‧ substrate

101‧‧‧Metal wiring

102‧‧‧Interconnect structure

110, 310‧‧‧First installation area

110a, 310a‧‧‧ first set of pads

110b, 310b‧‧‧Second set of pads

120, 340‧‧‧Second installation area

320‧‧‧ Third installation area

121a~121b, 341a~341b‧‧‧ third set of pads

124a~124e, 343a‧‧‧ fourth set of pads

122a, 342a‧‧‧ fifth set of pads

123a, 342b‧‧‧ sixth set of pads

130, 330‧‧‧ bonding pads

141a~141b, 142a~142d‧‧‧ solder pads

151a~151d, 352a, 352b‧‧‧ lead pads

161, ‧ ‧ ‧ first metal pads

162, 462‧‧‧ second metal pad

201, 301‧‧‧ first chip

202, 302‧‧‧ second chip

303‧‧‧ Third chip

211, 450‧‧‧ conductive structure

450a‧‧‧lateral part

450b‧‧‧ longitudinal part

450c‧‧‧Extension

S1‧‧‧ source

G1‧‧‧ gate

S2, 303‧‧‧ source metal pad

D1, D2‧‧‧汲 金属 金属

321‧‧‧Metal bearing mat

321a‧‧‧Slim metal parts

351a~351e‧‧‧First set of lead pads

352a~352e‧‧‧Second set of lead pads

361, 362‧‧‧ joint pads

442a, 442b‧‧‧ pads

LX‧‧‧ node

The features and advantages of the present invention will become apparent from the following detailed description of the appended claims.

2A-2I illustrate the process of attaching a wafer to a circuit board in accordance with the teachings of the present invention.

3A-3C illustrate metal pads provided with a large heat dissipation area on the back side of the circuit board in accordance with the disclosed technology.

4A-4C illustrate a technique of the present invention, in which a plurality of metal pads for heat dissipation are disposed on the back surface of the circuit board.

5A-5F are diagrams showing an embodiment employing three separate wafers in accordance with the teachings of the present invention.

Figure 6 is a basic manner of the package structure involved in the prior art.

The technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments, but the described embodiments are merely examples of the embodiments used in the description of the present invention and not all of the embodiments, based on the embodiments, The solutions obtained by those skilled in the art without creative efforts are within the scope of the present invention.

Referring to Fig. 1A, there is shown a schematic diagram of a substrate 100 or a printed circuit board. The substrate 100 is a provider of electrical connections for electronic components. Since printed circuit boards are well known to those skilled in the art, they will not be described. . A designated first mounting area 110 and a second mounting area 120 are reserved on the front surface of the substrate 100. The two areas are adjacent to each other and arranged side by side, mainly for mounting the wafer, and at least the substrate is disposed on the back surface of the substrate 100. A set of pin pads 151a-151d near one edge of 100 and another set of pin pads 152a-152d located near the other opposite edge of the substrate 100. The arrangement of the pad pads on the back surface of the substrate 100 can be seen in FIG. 1B. Show. In FIG. 1B, pin pads 151a to 151d arranged in a row and pin pads 152a to 152d arranged in another row are taken as an example. In order to know in more detail the distribution of the pads in the first mounting region 110 and the second mounting region 120 disclosed in the present invention, FIG. 1C scales the first mounting region 110 to be enlarged, and FIG. 1D is proportionally The second mounting area 120 is enlarged. In FIG. 1C, the first mounting region 110 is disposed with a first set of pads 110a and a second set of pads 110b. The plurality of pads and the second set of pads 110b are temporarily provided by the first set of pads 110a. Take a solder pad as an example. In FIG. 1D, the second mounting region 120 is laid out with a third set of pads 121a-121b and a fourth set of pads. 124a~124e and a fifth set of pads 122a and a sixth set of pads 123a. It should be noted that although the respective pads included in the third set of pads 121a-121b are not interconnected, and the pads included in the fourth set of pads 124a-124e are not interconnected, as an option, The respective pads included in the fifth set of pads 122a may be interconnected with each other through the metal wires 101 on the front surface of the substrate 100. The respective pads included in the sixth set of pads 123a may also pass through the metal wires 101 on the front side of the substrate 100 to each other. interconnection.

1A and FIG. 1C to FIG. 1D, we can obtain that one of the second set of pads 110b of the first mounting region 110 directly interacts with one of the third sets of pads 121a of the second mounting region 120 through the metal wiring 101. And a certain first set of pads 110a in the first mounting region 110 are directly interconnected with one of the third sets of pads 121b of the second mounting region 120 via the metal wiring 101.

Referring to FIG. 1D and FIG. 1A to FIG. 1B, each of the fourth set of pads 124a-124e is correspondingly connected to a pin pad through the wiring 101. Specifically, for example, one of the pads 124a to 124e of the fourth set of pads 124a to 124e (see FIG. 1D) is connected to a pad 142a on the front surface of the substrate 100 through the wiring 101, and the pad 142a on the front side is substantially And the lead pads 152a (see FIG. 1B) on the back surface of the substrate 100 are aligned and overlap each other, and the through holes penetrating the thickness of the substrate 100 can be disposed between the pads 142a on the front side and the pad pads 152a on the back side, and The hole is embedded with a metal material (ie, the interconnect structure 102), so the front pad 142a and the back pad pad 152a are electrically connected, which also means that the fourth set of pads 124a-124e A pad 124a is electrically connected to the pad pad 152a. In the same manner, one of the fourth set of pads 124a-124e (see FIG. 1D) is connected by wiring 101 to a pad 142b (see FIG. 1A) on the front side of the substrate 100, and the fourth of the front side. One of the pads 124a-124e is aligned with the pad pad 152b (see FIG. 1B), and the two are electrically connected through the interconnect structure 102, and one of the fourth pads 124a-124e is soldered. 124b is electrically connected to the lead pad 152b. Accordingly, one of the fourth set of pads 124a-124e (see FIG. 1D) is connected to the substrate by the wiring 101. On a front surface of a pad 142c (see FIG. 1A), the front pad 142c is aligned with the pad pad 152c (see FIG. 1B) and electrically connected through the interconnect structure 102, so the fourth pad 124a~124e The solder pad 124c is electrically connected to the pad pad 152c. One of the fourth pads 124a-124e (see FIG. 1D) is connected by wiring 101 to a pad 142d (see FIG. 1A) on the front surface of the substrate 100, and the pad 142d and the pad pad 152d (see 1B) is aligned and electrically connected through the interconnect structure 102, and the pads 124d of the fourth set of pads 124a-124e are electrically connected to the pad pads 152d. In addition, one of the fourth pads 124a-124e (see FIG. 1D) is also connected to a pad 141b (see FIG. 1A) on the front surface of the substrate 100 through the wiring 101, the pad 141b and the pad pad 151d. (See FIG. 1B) Aligned and electrically connected through the interconnect structure 102, the pads 124e of the fourth set of pads 124a-124e are electrically connected to the pad pads 151d.

1A and FIG. 1D, we can obtain that each of the fifth pads 122a is electrically connected to the metal bonding pad 130 through the wiring 101 on the front surface of the substrate 100, and the bonding pad 130 is disposed on the front surface of the substrate 100, and Adjacent to the first mounting area 110. Further, it is preferable to arrange the bonding pads 130 in a strip shape, and it is preferable to arrange the pads 141a, 141b on the front surface of the substrate 100 on the extension line of the length direction of the bonding pad 130, in order to bond the pads near one edge of the substrate 100. 130 and pads 141a, 141b and the first row of pad pads 151a-151d of FIG. 1B may be disposed to overlap one another, and pads 142a-142d near the other edge of substrate 100 are aligned with the second row of FIG. 1B. The pin pads 152a to 152d may be disposed to overlap each other. It has been described above that a set of pads 142a-142d on the front side of the substrate 100 and a row of pin pads 152a-152d on the back side of the substrate 100 are aligned and overlapped in a one-to-one manner, and the bond pads 130 on the front side of the substrate 100 (see 1A) is in alignment with two pin pads 151a and 151b (see FIG. 1B) of another row of pad pads 151a to 151d on the back surface of the substrate 100, and the bonding pad 130 and the two pin pads 151a and 151b The interconnect structure 102 is buried between the via holes, so that the bond pad 130 and the two pin pads 151a and 151b are electrically connected. In addition, each of the pads included in the fifth set of pads 122a is not only interconnected, but each of the fifth set of pads 122a The pad is also connected to the metal bond pad 130 through the wiring 101, as shown in FIG. 1A, which also means that the respective pads, the bond pads 130 included in the fifth set of pads 122a are simultaneously and the two leads in FIG. 1B. The pads 151a and 151b are electrically connected. In addition, the respective pads included in the sixth set of pads 123a may also be interconnected with each other through the metal wiring 101 on the front side of the substrate 100, see FIGS. 1A and 1D, and in addition, each of the sixth set of pads 123a is included. The pad is also connected to a pad 141a through the wiring 101. The pad 141a on the front surface of the substrate 100 shown in FIG. 1A is overlapped with a pin pad 151c on the back surface of the substrate 100 shown in FIG. 1B, and the pad is overlapped. Between the 141a and the pin pad 151c, the interconnect structure 102 is embedded in the via hole, so that the pad 141a and the pad pad 151c are electrically connected, meaning that each solder included in the sixth set of pads 123a The pad and the lead pad 151c are electrically connected. Therefore, each of the metal pin pads on the back surface of the substrate 100 and the first set of pads 110a to the sixth set of pads 123a of the metal material on the front surface of the substrate 100 or the bonding pads 130 of the metal material have the electrical connection relationship described above.

Referring to FIG. 2A, slightly different from FIG. 1B, a first row of pin pads 151a-151d and a second row of pin pads 152a-152d are disposed substantially at the edge regions of the back surface of the substrate 100, and also on the substrate. A first metal pad 161 is disposed on a lower intermediate portion of the back surface of 100, and as an alternative, another second metal pad 162, a first metal pad 161 and a second metal pad 161 may be disposed in a more intermediate portion of the back surface of the substrate 100. The second metal pads 162 are preferably arranged side by side. In order to more clearly understand the position of the first metal pad 161, referring to FIG. 1A and FIG. 2A, one or more pads in the first set of pads 110a of the first mounting region 110 of the front surface of the substrate 100 are substantially The first metal pads 161 on the back surface of the substrate 100 are aligned and overlapped, so that the substrate 100 can embed a via hole in a region between the pads and the first metal pad 161 and provide an interconnection structure 102 in the via hole, thereby Those pads of the first set of pads 110a that overlap with the first metal pads 161 are electrically connected to the first metal pads 161. However, it should be noted that the second set of pads 110b disposed in the first mounting region 110 cannot be electrically connected to the first metal pad 161. If a second metal is also disposed on the back side of the substrate 100 The pad 162 is separated from the second metal pad 162 and the first metal pad 161. Moreover, in the embodiment of FIG. 2A, one or more of the fifth set of pads 122a of the second mounting region 120 are aligned with the second metal pads 162, and the same substrate 100 is in the pads and the first A via hole may be buried in a region between the two metal pads 162 and an interconnect structure 102 may be disposed in the via hole to electrically connect those pads of the fifth set of pads 122a that overlap with the second metal pad 162 to The second metal pad 162 is on.

Referring to FIG. 2B, a first wafer 201 is mounted in the first mounting region 110 and a second wafer 202 is mounted in the second mounting region 120. The first wafer 201 and the second wafer 202 are flip-chip mounted in a flip-chip manner (FLIP-CHIP) such that their faces face down, that is, toward the front side of the substrate 100, and FIG. 2C deliberately flips the first wafer. The 201 and second wafers 202 are arranged to be transparent so that we can observe their positional alignment with the first mounting area 110 and the second mounting area 120, respectively. In a conventional DC-DC voltage conversion circuit, a low-order power MOSFET and a high-order power MOSFET are typically connected in series between the supply voltage (VIN) and the ground (GND), and a control circuit (CONTROL CIRCUIT) controls The turn-off and turn-on of the low-order power MOSFET and the high-order power MOSFET, the first wafer 201 can now be directly a low-order power MOSFET, and the second wafer 202 integrates the control circuit and the high-order power MOSFET on the same wafer. In FIG. 2D, a conductive structure 211 is adhered between the bonding pad 130 and the metal layer on the back side of the first wafer 201. The conductive structure 211 embodied here as a metal piece may also be replaced with another lead 212 in FIG. 2E. The lead 212 needs to be implemented by a bonding technique. In general, the metal layer on the back surface of the bonding pad 130 and the first wafer 201 needs to be electrically connected. Of course, in other embodiments, the metal strip conductive structure 211 may also be a conductive strip. Or any similar structure to replace. 2F is an embodiment in which the conductive structure 211 is a metal piece. The upper end of the metal piece used in the conductive structure 211 is adhered to the metal layer on the back surface of the first wafer 201 by a conductive adhesive material, and the lower end of the metal piece is formed. Then, the conductive bonding material is adhered to the bonding pad 130, and the upper end of the metal piece is There is a height drop between the lower end and the lower end. As is known to those skilled in the art, power MOSFETs generally have a gate and a source and a drain. The electrical connection relationship between the first wafer 201 and the second wafer 202 and the substrate 100 herein will be explained with reference to FIGS. 1D and 2C.

In an alternative embodiment, a metal pad (PAD) on the front side of the first wafer 201 is embodied as a source S1 of the low-side MOSFET, and the other metal pad on the front side is embodied as a gate G1, the first chip. The metal layer on the back of the 201 is bungee. In FIG. 2C, the source S1 of the first wafer 201 is docked with the first set of pads 110a of the first mounting region 110, such as solder balls or other similar metal bumps soldered through the source S1 of the first wafer 201. Blocks and so on achieve docking. The gate G1 of the first wafer 201 is docked with the second set of pads 110b of the first mounting region 110, such as solder balls or other similar metal bumps soldered on the gate G1 of the first wafer 201. The second wafer 202 integrates a high-order MOSFET and a control circuit module. In FIG. 2C, a plurality of source metal pads S2 belonging to the high-order MOSFET on the front surface of the second wafer 202 and a plurality of fifth layouts of the second mounting region 120 are disposed. The solder pads 122a are butted, and each of the source metal pads S2 is docked with one of the fifth pads 122a, for example, by solder balls or other similar metal bumps. A plurality of drain metal pads D2 belonging to the high-order MOSFET on the front surface of the second wafer 202 are butted against the sixth set of pads 123a of the second mounting region 120, and each of the drain metal pads D2 corresponds to the sixth set of pads. One of the pads in 123a is butted, for example, by solder balls or other similar metal bumps. Since the high-order MOSFET and the control circuit in the second wafer 202 are integrated on the same wafer, it also means that the gate of the high-order MOSFET in the second wafer 202 can be directly coupled to the control circuit in the wafer without the need for the second chip. An additional pad pad is provided on the top. Referring to FIG. 2C, a portion of the third set of pads 121a-121b (eg, pad 121a) and one or more pads of the first set of pads 110a have been mentioned above (eg, in FIG. 2C). One of the pads 110a is electrically connected, and the third set of pads 121a-121b has a part of the pads (for example, the pads 121b) and one or more pads of the second pads 110b ( For example, in the picture One of the pads 110b is electrically connected, and the pads 124a-124b of the fourth set of pads 124a-124e are respectively connected to the lead pads 142a-142d in a one-to-one manner, and the fourth set of soldering The pads 124e of the pads 124a-124e are connected to the pin pads 151d, and the metal pads IO1 to IO7 of the respective input or output terminals I/O of the control circuit integrated by the second chip 202 may be disposed on the second chip. The front surface of the 202, and the metal pads IO1~IO7 are soldered in a one-to-one manner corresponding to the third set of pads 121a-121b and the fourth set of pads 124a-124e, and are soldered by solder balls or metal bumps.

Referring to FIG. 2C, specifically, the source S1 of the low-order MOSFET of the first wafer 201 is soldered to the first set of pads 110a, and the gate G1 of the low-order MOSFET is soldered to the second set of pads 110b, and the first The solder pad 110a is connected to the first metal pad 161 (see FIG. 2A) on the back surface of the substrate 100. In fact, the source S1 of the low-order MOSFET is also electrically connected to the first metal pad 161 on the back surface of the substrate 100. The drain of the lower-order MOSFET, that is, the metal layer on the back side of the first wafer 201, is connected to the bond pad 130 through the conductive structure 211. And the source S2 of the high-order MOSFET integrated in the second chip 202 is electrically connected to the bonding pad 130 through the fourth set of pads 122a, so the source S2 of the high-order MOSFET and the drain of the low-order MOSFET are electrically interconnected. Considering that the pin pads 151a and 151b on the back side of the substrate 100 are electrically connected to the bonding pad 130, the source S2 of the high-order MOSFET and the node (LX) of the drain interconnection of the low-order MOSFET are embodied in Pin pads 151a and 151b. The drain metal pad D2 of the high-order MOSFET integrated in the second wafer 202 is connected to the pad 141a at one edge of the square substrate 100 through the fifth set of pads 123a, and the pad 141a and the back surface of the substrate 100 A pin pad 151c is connected to each other, so if the power supply voltage (VIN) is input to the drain metal pad D2 of the high-order MOSFET, since the gate metal pad D2 of the high-order MOSFET is electrically connected to one pin on the back side of the substrate 100 The pad 151c is placed so that the power supply voltage (VIN) can be supplied to the drain metal pad D2 of the higher order MOSFET through the pin pad 151c. In addition, the integrated control circuit in the second wafer 202 can pass through the metal if it is to control the turning on or off of the low-order MOSFET. The driving signal from the substrate IO1 is used to perform the driving because the metal substrate 101 of the control circuit is soldered to the third set of pads 121a, and the third set of pads 121a is connected to the second set of pads 110b via the wiring 101 ( The gate G1 of the low-order MOSFET is soldered to the pad 110b), so the metal substrate IO1 of the control circuit is coupled to the gate G1 of the low-order MOSFET by this path. The metal substrate IO2 of the integrated control circuit in the second wafer 202 is soldered to the third set of pads 121b, and the third set of pads 121b is in turn connected to one or more first sets of pads 110a via the wiring 101 (low The source S1 of the step MOSFET is soldered on the pad 110a), and the one or more first pad pads 110a may also be electrically connected to the first metal pad 161 on the back surface of the substrate 100 (see FIG. 2A), so the control circuit The metal substrate IO2 can also be electrically coupled to the first metal pad 161 on the back side of the substrate 100. The other metal pads IO3 IO IO6 of the control circuit integrated in the second chip 202 are electrically connected to the pads 142a 142d near the edge of the substrate 100 through the wires 101, and the second chip 202 is electrically connected to the pads 142a to 142d near one edge of the substrate 100. The other metal pads 107 of the integrated control circuit are electrically connected to the pads 141b near the other opposite edge of the substrate 100 through the wiring 101, and the pads 142a-142d on the front surface of the substrate 100 are correspondingly connected to the back surface of the substrate 100. The pads 152a to 152d and the pads 141b on the front surface of the substrate 100 are correspondingly connected to the pad pads 151d on the back surface of the substrate 100, so that the metal pads IO3 to IO6 as input or output of the integrated control circuit in the second wafer 202 correspond to each other. Electrically connected to the lead pads 152a-152d on the back side of the substrate 100, the metal pad 107 as an input or output of the control circuit is electrically connected to the pad pad 151d electrically connected to the back surface of the substrate 100. A large-sized first metal pad 161 (see FIG. 2A) is disposed on the back surface of the substrate 100 because the high-order MOSFET and the low-order MOSFET generate a large amount of heat during the high-frequency switching phase between on and off, and the first The metal pad 161 can be used not only as a ground GND pin (at the source S1 of the low-order MOSFET) but also as a preferred heat dissipation path, as will be appreciated by those skilled in the art.

2F and 2G, a straight cross-sectional view along the broken line A-A in Fig. 2D is shown in Fig. 2F, and a cross-sectional view along the broken line B-B in Fig. 2D is as shown in Fig. 2G. As shown in FIG. 2D, the first wafer 201 Docking with the pads 110a and 110b is achieved by solder balls 220 soldered on the source S1 and the gate G1 or other similar metal bumps or the like. The high-order MOSFET integrated by the second wafer 202 is connected to the fifth set of pads to the sixth set of pads by the solder balls 220 soldered on the source S2 and the drain metal pad D2, or other similar metal bumps, and the like. The metal pads 101 to IO7 as terminals of the control circuit integrated by the two wafers 202 are connected to the third set of pads to the fourth set of pads by solder balls 220 or other similar metal bumps or the like. After the installation of the wafer is completed, a mold closing process (MOLDING) is finally required to form a package body 230 covering the first wafer 201 and the second wafer 202 and the conductive structure 211 to prevent external moisture or contaminant pairs. The erosion of electronic components and the role of physical protection. Referring to FIG. 2F and FIG. 2G, after completing the molding process to form the package 230, a straight cross-sectional view along the broken line AA in FIG. 2D is as shown in FIG. 2H, and a cross-sectional view along the broken line BB in FIG. 2D is as shown in FIG. 2I. .

2A and 2C, in an alternative embodiment, another second metal pad 162 is disposed in a more intermediate region of the back side of the substrate 100, and one of the fifth sets of pads 122a is known above. Or a plurality of pads are aligned and overlapped with the second metal pad 162, and a via hole and an interconnect structure 102 located in the via hole are buried in the region of the substrate 100 between the pads 122a and the second metal pad 162, Therefore, the second metal pad 162 is connected to one or more of the fifth set of pads 122a, and the fifth set of pads 122a is connected to the bond pad 130 through the wiring 101, so the source metal of the high-order MOSFET is actually The pad S2 and the drain metal pad D1 of the low-order MOSFET are not only interconnected but also connected to the second metal pad 162, which means that the second metal pad 162 can be used not only as an interconnection node LX pin ( The low-order MOSFET's drain metal pad D1 and the high-order MOSFET's source metal pad S2), the larger size and area can also be used as a better heat dissipation path, which is well known to those skilled in the art. of.

Referring to the embodiment of FIGS. 3A-3C, substantially the same as the embodiment of FIGS. 2A-2I, but the middle portion of the back surface of the substrate 100 is not provided with any metal similar to the second metal pad 162. The layer, but instead a relatively long first metal pad 161 is disposed in a relatively intermediate portion of the back surface of the substrate 100. The embodiment increases the size of the first metal pad 161 of FIG. 2A and discards the second metal bond. The pad 162, that is, the space of the original second metal pad 162 is occupied by the first metal pad 161 which is increased, which is clearly illustrated in FIGS. 3B and 3C.

Referring to the embodiment of FIGS. 4A-4C, substantially the same as the embodiment of FIGS. 2A-2I, a slight difference is that one or more pads of the fifth set of pads 122A of FIG. 2A pass through the interconnect structure 102. Connected to the second metal pad 162, but in the embodiment of FIG. 4B, the fifth set of pads 122a are not connected to the second metal pad 162, but instead one or more of the sixth set of pads 123a The pads are aligned with and overlap with the second metal pads 162 such that the vias and the regions can be buried in the region of the substrate 100 between the one or more pads of the sixth set of pads 123a and the second metal pads 162 The interconnect structure 102 is located in the via hole, such that the pads and the second metal pad 162 of the sixth set of pads 123a aligned with the second metal pad 162 are connected by the interconnect structure 102, such as As shown in FIG. 4B, in consideration of the fact that the gate metal pad D2 and the sixth pad pad 123a of the high-order MOSFET integrated in the second wafer 202 are electrically connected through the wiring 101, the second metal pad 162 at this time is also connected to The high-order MOSFET's drain metal pad D2, while the supply voltage (VIN) is from the high-order MOSFET's drain metal pad D2 The input of one of the lead pads 151c, where the second metal pad 162 is also connected to the drain metal pad D2 of the high-order MOSFET, is equivalent to the input of the power supply voltage (VIN) directly from the second metal pad 162, and The second metal pad 162 having a larger area is also a preferred heat dissipation path.

Referring to FIG. 5A and FIG. 5B, a designated first mounting area 310 and a second mounting area 340 and a third mounting area 320 are reserved on the front surface of the substrate 300, and a bonding pad 330 is disposed on the front surface of the substrate 100. A first metal pad 461 is disposed on the back surface of the substrate 300. Referring to FIG. 5B, a plurality of lead pads are disposed on the back surface of the substrate 100, wherein the first set of lead pads 351a-351e are disposed at a first edge position of the square substrate 100, and the second set of lead pads 352a-352e are disposed at a second edge position of the square substrate 100 opposite to the first edge, the first set of lead pads 351a-351e are arranged in a row, and the second set of lead pads 352a-352e are also arranged. In a row. The second mounting area 340 and the third mounting area 320 are arranged side by side, and the first mounting area 310 is located on an extension line of the dividing line or the gap between the second mounting area 340 and the third mounting area 320, which means that we can The first mounting area 310 and the second mounting area 340 and the third mounting area 320 are arranged in a compact zigzag shape so that the area of the board can be saved. 5A is a schematic view of a substrate 300 or a printed circuit board. The first mounting area 310 and the second mounting area 340 and the third mounting area 320 reserved on the front side of the substrate 300 are mainly used to mount different three wafers and the three areas. Close to each other. As shown in FIG. 5A, the first mounting area 310 is disposed with a first set of pads 310a and a second set of pads 310b. The plurality of pads provided by the first set of pads 110a and the second set of pads 110b are temporarily provided. Some of the pads are exemplified, but the number is not limited to the number shown in the figure. In FIG. 5A, the second mounting region 340 is provided with a third set of pads 341a-341b and a fourth set of pads 343a and a fifth set of pads 342a and a sixth set of pads 342b.

Referring to FIG. 5A, we can obtain that one of the second set of pads 110b of the first mounting region 310 directly passes through the metal wiring 101 of the front surface of the substrate 300 with one of the third sets of pads 341a of the second mounting region 340. The interconnect, and one of the first set of pads 110a in the first mounting region 310 is directly interconnected with a third set of pads 341b of the second mounting region 340 through the metal wiring 101 on the front side of the substrate 300.

Referring to FIG. 5A, each of the fourth set of pads 343a is connected to a pin pad via a wiring 101. Specifically, for example, one of the pads 343a of the fourth set of pads 343a is connected to a pad 442a on the front surface of the substrate 300 through the wiring 101, and the pad 442a on the front side of the substrate 300 is substantially opposite to the back surface of the substrate 300. The lead pads 352a (see FIG. 5B) are aligned and overlap each other, and the through holes penetrating the thickness of the substrate 100 may be disposed between the pads 442a on the front side and the pad pads 352a on the back side, and the via holes are buried and filled. Metal material (ie interconnect structure 102), Therefore, the front pad 442a and the back pad 352a are electrically connected, which means that the pad 343a of the fourth pad 343a is electrically connected to the pad pad 352a. In the same manner, one of the fourth pads 343a is connected to a pad 442b on the front surface of the substrate 300 via the wiring 101, and the pad 442b on the front side and the pad 352b (see FIG. 1B) are paired. The pads 343a of the fourth set of pads 343a are electrically connected to the pad pads 352b. Accordingly, the other of the fourth pads 343a is connected to a pad 442c on the front surface of the substrate 300 via the wiring 101, and the pad 442c and the pad 352c on the front surface (see FIG. 1B). In alignment, the two are electrically connected through the interconnect structure 102, and the pad 343a in the fourth set of pads 343a is electrically connected to the pad pad 352c. One of the fourth pads 343a is connected to a pad 442d on the front surface of the substrate 300 through the wiring 101, and the pad 442d is aligned and electrically connected to the pad pad 352c, and then one pad 343a is It is electrically connected to the lead pad 352d. One of the fourth pads 343a is connected to a pad 442e on the front surface of the substrate 300 through the wiring 101, and the pad 442e is aligned and electrically connected to the pad pad 352e, and then one pad 343a is It is electrically connected to the lead pad 352e.

Referring to FIG. 5A, a fifth set of pads 342a can be electrically connected to a bonding pad 361 through a wiring 101 on the front surface of the substrate 300, and a sixth set of pads 342b pass through the wiring 101 on the front surface of the substrate 300 and another. A bond pad 362 is electrically connected, and bond pads 361 and bond pads 362 are located adjacent the first edge of substrate 300. Also disposed in the third mounting region 320 is a metal carrier pad 321 having an elongated metal portion 321a extending toward one edge of the substrate 300. A bonding pad 330 is disposed on the front surface of the substrate 300 adjacent to the third mounting region 320 and adjacent to the first edge of the substrate 300. In FIG. 5A, the bonding pads 330 near the edge of the substrate 300 and the pad pads 351c-351d of the first group of the pad pads 351a-351e in FIG. 5B are disposed to overlap the top and bottom, and the purpose is to be in the pad pad 351c~ In the region of the substrate 300 between the 351d and the bonding pad 330, a via hole and an interconnection structure 101 are provided, thereby connecting the pad pads 351c to 351d and the bonding pad 330. Figure 5A Some of the wirings 101 that are interconnected with the first set of pads 310a on the front side of the substrate 300 are also extended to near one edge of the substrate 300 so as to be associated with the pad pads 351a-351b in the first row of pad pads in FIG. 5B. The upper and lower overlaps are set, so that the via hole and the interconnection structure 101 are disposed in the region of the substrate 300 between the wiring 101 and the lead pads 351a to 351b interconnected with the first set of pads 310a, and the first sleeve is soldered. Some of the wiring 101 and the pad pads 351a to 351b interconnected by the pad 310a are interconnected. In addition, FIG. 5A shows that the metal carrier pad 321 has an elongated metal portion 321a extending toward the first edge of the substrate 300, and the metal portion 321a and the pin pad 351e in the first row of the pad pads in FIG. 5B are disposed as The upper and lower portions are overlapped, and the via hole and the interconnection structure 101 are disposed in the region of the substrate 300 between the metal portion 321a and the lead pad 351e, so that the metal portion 321a and the lead pad 351e can be interconnected, so that the carrier pad 321 is also The pin pads 351e are interconnected.

Referring to FIG. 5B, a first row of pin pads 351a-351e and a second set of pin pads 352a-352e are disposed on the back surface of the substrate 300 except in the edge regions, and a middle portion of the back surface of the substrate 300 is disposed. A first metal pad 461, and as an option, another second metal pad 462 may be disposed in a middle portion of the back surface of the substrate 300, and the first metal pad 461 and the second metal pad 462 are preferably Side by side settings. One or more pads of the first set of pads 310a disposed on the front surface of the substrate 300 are substantially aligned with the first metal pads 461 on the back side of the substrate 300, such that the substrate 300 is on the pads and The vias may be buried in the regions between the first metal pads 461 and the interconnect structures 102 are disposed in the vias to electrically connect the pads of the first set of pads 310a that overlap the first metal pads 461. Go to the first metal pad 461. However, it should be noted that the second set of pads 310b disposed in the first mounting region 310 cannot be electrically connected to the first metal pad 461. If a second metal pad 462 is additionally disposed on the back side of the substrate 300, the second metal pad 462 and the first metal pad 461 are separated. Moreover, in the embodiment of FIG. 5A to FIG. 5B, the metal bearing pad 321 located in the third mounting region 320 and the second metal pad 462 on the back surface of the substrate 300 overlap at least partially, so that the substrate 300 is on the metal bearing pad 321 and A through hole can be buried in the area between the two metal pads 462 and passed through The interconnect structure 102 is disposed within the hole to interconnect the metal carrier pad 321 and the second metal pad 462.

Referring to FIG. 5C, the first wafer 301 is flip-chip mounted on the first mounting region 310 in a flip-chip (FLIP-CHIP) manner, and the second wafer 302 is flip-chip mounted in the second mounting region 340 in a flip chip manner. The front side of the first wafer 301 and the second wafer 302 are directed downward, that is, toward the front side of the substrate 300. The third wafer 303 is mounted in the third mounting region 320 in a normal manner (without flip chip flipping) such that the back side of the third wafer 303 faces downward, that is, toward the front side of the substrate 300. 5D is intended to make the first wafer 301 and the second wafer 302 and the third wafer 303 transparent so that we can observe the three wafers and the first mounting area 310 and the second mounting area 340 and the first The position alignment mode of the three mounting areas 320. In a conventional DC-DC voltage conversion circuit, a low-order power MOSFET and a high-order power MOSFET are typically connected in series between the supply voltage (VIN) and the ground (GND), and a control circuit (CONTROL CIRCUIT) controls The low-order power MOSFET and the high-order power MOSFET are turned off and on, the first chip 301 may directly be a low-order power MOSFET, and the second chip 302 may be integrated with a control circuit, and the third chip 303 may be a high-order power MOSFET. . In FIG. 5E, a conductive structure 450 is mounted on the first wafer 301 and the third wafer 303. The specific structure of the conductive structure 450 is substantially an L-shaped metal piece, including a lateral portion 450a and a vertical one perpendicular to each other. The longitudinal portion 450b, the lateral portion 450a is adhered to the metal layer on the back surface of the first wafer 301 by a conductive material, the longitudinal portion 450b is adhered to the source metal pad 303 on the front surface of the third wafer 303 by a conductive material, and the longitudinal portion 450b There is also an extension 450c extending downwardly, the free front end of the extension 450c being directly pressed against and adhered to the bond pad 330 by a conductive material, the extension 450c being opposite the coplanar lateral portion 450a and the longitudinal portion 450b The downward oblique extension is because the lateral portion 450a and the longitudinal portion 450b are located above the first wafer 301 and the third wafer 303, and the bonding pad 330 is located on the front surface of the substrate 300, so the extension portion 450c has adhesion to the bonding pad 330. Together The free front end and the lateral portion 450a and the longitudinal portion 450b have a height drop. In summary, the source metal pad 303b on the front side of the bonding pad 330 and the third wafer 303, and the drain metal layer on the back side of the first wafer 301 need to be electrically connected through the conductive structure 450. As is known to those skilled in the art, power MOSFET wafers typically have gates and sources and drains. The electrical connection relationship between the first wafer 301 and the third wafer 303 and the substrate 300 herein will be explained with reference to FIGS. 5D and 5E.

In an alternative embodiment, one metal pad (PAD) on the front side of the first wafer 301 is embodied as the source S1 of the low-order MOSFET, and the other metal pad on the front side of the first wafer 301 is embodied as the gate G1. And the metal layer on the back side of the first wafer 301 is embodied as a drain. As shown in FIG. 5D, when the first wafer 301 is flipped to the first mounting region 310, the source S1 of the front surface of the first wafer 301 is soldered to the first sleeve of the first mounting region 301 by solder balls or other metal bumps or the like. The pad 310a is butted, and the gate G1 on the front surface of the first wafer 301 is butted against the second set of pads 310b of the first mounting region 310 by solder balls or other metal bumps or the like.

Referring to FIG. 5D, as already mentioned above, a portion of the third set of pads 341a-341b (eg, pad 121a) and one or more pads of the first set of pads 310a (eg, FIG. 5D) One of the pads 310a is exemplarily electrically connected, and the third set of pads 341a-341b further includes a part of the pads (for example, the pads 341b) and one or more pads of the second set of pads 310b ( For example, in FIG. 5D, one of the pads 310b is taken as an example for electrical connection. In addition, in FIG. 5A and FIG. 5D, the metal pads 101 to 109 and the like of the respective input or output terminals I/O of the control circuit integrated by the second wafer 302 may be disposed on the front surface of the second wafer 302, and the metal pad 101~ IO9 needs to interface with the third set of pads 341a-341b to the sixth set of pads 342b. Specifically, the plurality of pads 343a of the fourth set of pads 343a and the plurality of pad pads 352a-352e (see FIG. 5B) are respectively connected in a one-to-one manner, such as one pad 343a in FIG. 5D (with IO9). Soldering) is connected to a pad 442a overlapping the lead pad 352a on the front surface of the substrate 300 via the wiring 101, and the pad 442a and the pad pad 352a are connected Therefore, it is connected to the IO9 solder pad 343a and the lead pad 352a. A pad 343a (welded to IO8) is connected to a pad 442b on the front surface of the substrate 300 overlapping the pad pad 352b via a wiring 101, and the pad 442b and the pad pad 352b are connected, so the pad 343a soldered to the IO8 and Pin pads 352b are connected. And so on, a pad 343a and a pad pad 352c soldered to the IO7 are connected, and are connected to the IO6 solder pad 343a and the pad pad 352d, and are connected to the IO6 solder pad 343a and the pad pad 352e.

Referring to FIG. 5D, a metal pad 101 of the control circuit integrated by the second die 302 is soldered to a designated pad 341b of the third set of pads 341a-341b by solder balls or other metal bumps, and The pad 341b is further connected to the second pad 310b via the wiring 101. Therefore, the driving signal sent by the control circuit integrated by the second chip 302 can be transmitted to the gate of the low-order MOSFET through the pad 341b to the second pad 310b. Extreme G1. In addition, a metal pad 102 of the control circuit integrated by the second chip 302 is soldered to the designated pad 341a of the third set of pads by solder balls or other metal bumps, and the pad 341a is soldered to the first sleeve. The pads 310a are connected by the wiring 101, and the terminal IO2 of the control circuit integrated with the second wafer 302 and the first set of pads 310a are connected together to the first metal pad 461 in FIG. 5B. In addition, a fifth set of pads 342a (welded with IO3) in FIG. 5D is connected to a bond pad 361 on the front side of the substrate 300 via a wiring 101, and a sixth set of pads 342b (welded with IO4) in FIG. 5D. It is connected to one of the bonding pads 362 on the front surface of the substrate 300 through the wiring 101.

As shown in FIG. 5D to FIG. 5E, the source S1 of the low-order MOSFET of the first wafer 201 is soldered to the first set of pads 310a, and the gate G1 of the low-order MOSFET is soldered to the second set of pads 310b, and the first set is The pad 310a is connected to the first metal pad 461 on the back surface of the substrate 300 (see FIG. 5B). Actually, the source S1 of the low-order MOSFET is also electrically connected to the first metal pad 461 on the back surface of the substrate 300. The drain of the lower-order MOSFET, that is, the metal layer on the back side of the first wafer 301 is connected to the source metal substrate 303b of the third wafer 303 through the conductive structure 450, in consideration of the conductive structure 450. The extending portion 450c extending obliquely downward is soldered to the bonding pad 330, so that the node (LX) of the drain metal pad D1 of the low-order MOSFET and the source S2 of the high-order MOSFET is embodied in the bonding pad 330 and the pad pad 351c. At 351d. The source S1 of the low-order MOSFET is embodied at the pad pads 351a and 351b connected to the source S1. The metal layer on the back side of the high-order MOSFET in the third wafer 302 is the metal-plated pad D2 soldered to the metal carrier pad 321 of the third mounting region 320 through the conductive bonding material, and the metal carrier pad 321 and the metal extended by the substrate 300. The portion 321a is connected to the pad pad 351e through the interconnect structure 102, if the power supply voltage (VIN) is input to the gate metal pad D2 of the high-order MOSFET, because the gate metal pad D2 of the high-order MOSFET is electrically connected to the back surface of the substrate 300. On one of the pin pads 351e, the power supply voltage (VIN) can be supplied to the gate metal pad D2 of the high-order MOSFET through the pin pad 351e. In addition, in FIG. 5B, the metal carrier pad 321 is also connected to the second metal pad 462 on the back surface of the substrate 300 through one or more interconnect structures 102, so the second metal pad 462 can be used not only as a ground (GND) pin. It can also be used as a better heat dissipation path, which is well known to those skilled in the art. The first metal pad 461 can be used not only as a ground (GND) pin (connected to the source S1 of the low-order MOSFET) but also as a preferred heat dissipation path.

As shown in FIG. 5D and FIG. 5E, the fifth set of pads 342a are electrically connected to one of the bonding pads 361 through the wiring 101 on the front surface of the substrate 300, and the sixth set of pads 342b pass through the wiring 101 on the front side of the substrate 300 and the other bonding pad 362. Electrically connected, one or more leads 451 may be connected between a bond pad 361 and a source metal pad 303b on the front side of the third wafer 303, or before a conductive structure 450, and at a bond pad 362. One or more leads 451 are connected between a gate metal pad 303a on the front side of the third wafer 303, which means that the fifth set of pads 342a (welded with IO3) in FIG. 5D is connected to the source metal of the high order MOSFET. The pad 303b, and the sixth set of pads 342b (welded with IO4) in FIG. 5D are connected to the gate metal pad 303a of the high order MOSFET, so that the integrated control circuit in the second die 302 can pass through the sixth set of pads 342b. And bonding The path of the pad 362 drives the turn-on or turn-off of the high-order MOSFET, and the potential change of the source metal pad 303b is sensed by the path of the fifth set of pads 342a and the bond pads 361.

Referring to FIG. 5F and FIG. 5E, a cross-sectional view along the broken line CC in FIG. 5E is as shown in FIG. 5F. After the mounting of the wafer is completed, the mold sealing process (MOLDING) is finally required to form a package 230. A wafer 301 and a second wafer 302, a third wafer 303, and a conductive structure 450 and a lead 451 are covered to prevent external moisture or contaminants from eroding the electronic components and function as physical protection.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

Claims (30)

A power device includes: a substrate and a first mounting area and a second mounting area defined on a front surface; a bonding pad is disposed on the front surface of the substrate; and a first metal pad is disposed on a back surface of the substrate And a plurality of pin pads, and further comprising a plurality of wires disposed on the substrate and a plurality of interconnect structures extending through the substrate, the first mounting region being provided with a first set of pads and a second set of pads The second mounting area is disposed with a third set of pads to a sixth set of pads; a portion of the pads disposed in the first mounting area and a portion of the pads disposed in the second mounting area are connected by the wires, a portion of the pads of the first mounting region are connected to the first metal pads through the interconnect structures, and a portion of the pads of the second mounting region are connected to the pin pads through the wires and the interconnect structures; Flip-chip-mounted a first wafer in the first mounting region, a metal pad on a front surface of the first wafer is mated with the pads located in the first mounting region; Loading a second wafer of the second mounting region, a metal pad of a front surface of the second wafer is mated with the pads located in the second mounting region; and connected to the bonding pad and a back surface of the first wafer a conductive structure between a metal layer; and a package covering the front surface of the substrate, and the package encapsulating the first wafer, the second wafer, and the conductive structure, wherein: the first One of the three sets of pads is electrically connected to one or more pads of the first set of pads, and the third set of pads further includes a part of the pads and the second set of pads Or a plurality of pads electrically connected; One or more of the fourth set of pads are electrically connected to the or the lead pads in a one-to-one manner through the wires and the interconnect structures embedded in the substrate; Each of the five sets of pads is electrically connected to the bond pad through the wires on the substrate, and the bond pads are electrically connected to the device via the interconnect structures embedded in the substrate The lead pads; and one or more of the pads of the sixth set of pads are electrically connected in a one-to-one manner through the wires on the substrate and the interconnect structures disposed in the substrate Go to the or some of the pin pads. The power device of claim 1, wherein a second metal pad is further disposed on the back surface of the substrate, and the pads or pads in the fifth set of pads are connected through the interconnect structures. To the second metal pad. The power device of claim 1, wherein a second metal pad is further disposed on the back surface of the substrate, and the pads or pads in the sixth set of pads are connected through the interconnect structures. To the second metal pad. The power device of claim 1, wherein a first metal pad of the front surface of the first wafer is soldered to the or the pads in the first set of pads and the first crystal A second metal pad of the front surface corresponds to the solder pad or pads soldered to the second set of pads. The power device of claim 1, wherein the one or more third metal pads of the front surface of the second wafer correspond to the one of the fifth set of pads in a one-to-one manner. Soldering the one or more fourth metal pads on the pads and the front side of the second wafer to the one or the pads of the sixth set of pads in a one-to-one manner; A plurality of fifth metal pads of the front side of the second wafer are soldered to the pads of the third set of pads and the fourth set of pads in a one-to-one manner. The power device of claim 4, wherein the first wafer comprises a first metal oxide half field effect transistor (MOSFET), and the first metal pad is one of the first metal oxide half field effect transistor a gate, the second metal pad is a source of the first metal oxide half field effect transistor and a metal layer of the back surface of the first chip is a drain of the first metal oxide half field effect transistor. The power device of claim 5, wherein the second chip is integrated with a control circuit and a second metal oxide half field effect transistor (MOSFET), the third metal pad is a second metal oxide half field effect a source of the transistor, the fourth metal pad being a drain of the second metal oxide half field effect transistor and the fifth metal pad being an input or output terminal of the control circuit. A method for fabricating a power device, comprising the steps of: providing a substrate, a first mounting region and a second mounting region are defined on a front surface of the substrate, the front surface of the substrate is provided with a bonding pad and a back surface of the substrate a first metal pad and a plurality of pin pads are disposed, and a plurality of wires are disposed on the substrate and a plurality of interconnect structures extending through the substrate, the first mounting region is provided with a first set of pads, a second set of pads and a second set of pads are disposed with a third set of pads to a sixth set of pads; a first wafer is flip-chip mounted to the first mounting area of the substrate in a flip chip manner, a metal pad on a front side of the first wafer is mated with a plurality of pads located in the first mounting region; and a second wafer is flip-chip mounted to the second mounting region of the substrate in a flip chip manner, the first a metal pad on a front side of the two wafers is mated with a plurality of pads located in the second mounting region; one or more conductive structures are mounted between a bond pad and a metal layer on the back side of the first wafer; as well as Forming a package covering the front surface of the substrate, the package covering the first wafer, the second wafer, and the conductive structure; a portion of the pads and layout disposed in the first mounting region a portion of the solder pads of the second mounting region are connected by the wires, and the portions of the first mounting region are connected to the first metal pad through the interconnect structures and the pads of the second mounting region Connecting to the pin pads through the wires and the interconnect structures; a portion of the pads of the third set of pads are electrically connected to one or more pads of the first set of pads, the third And some of the pads are electrically connected to one or more pads of the second set of pads; one or more pads of the fourth set of pads pass through the wires and are buried in the pads The interconnect structures in the substrate are electrically connected to the lead pads or the pads in a one-to-one manner; each of the fifth sets of pads passes through the plurality of wires on the substrate Bonding pads are electrically connected, and a plurality of bonding pads are embedded in the base The interconnect structures are electrically connected to the or the lead pads; and one or more of the sixth set of pads pass through the wires on the substrate and the one disposed in the substrate The interconnect structures are electrically connected to the or the pad pads in a one-to-one manner. The method of claim 8, wherein a second metal pad is further disposed on the back surface of the substrate, and one or more of the fifth pads are connected to the On the second metal pad. The method of claim 8, wherein a second metal pad is further disposed on the back surface of the substrate, and one or more pads of the sixth pad are connected to the On the second metal pad. The method of claim 8, wherein a first metal pad of the front surface of the first wafer is soldered to one or more pads of the first set of pads, the first wafer A second metal pad of the front side is correspondingly soldered to one or more of the second set of pads. The method of claim 8, wherein the one or more third metal pads of the front side of the second wafer are correspondingly welded to one or more of the fourth set of pads in a one-to-one manner. One or more fourth metal pads of the front surface of the second wafer are soldered to one or more of the sixth set of pads in a one-to-one manner on the pads; and the second wafer The plurality of fifth metal pads of the front surface are soldered to the plurality of pads of the third set of pads and the fourth set of pads in a one-to-one manner. A power device includes: a substrate and a first mounting region defined on a front surface of the substrate to a third mounting region, wherein a bonding pad is disposed on the front surface of the substrate and a first surface is disposed on a back surface of the substrate a metal pad and a plurality of pin pads, and further comprising a plurality of wires disposed on the substrate and a plurality of interconnect structures extending through the substrate; a portion of the pads and layouts disposed in the first mounting region are a portion of the solder pads of the second mounting region are connected by the wires, and the portions of the first mounting region are connected to the first metal pad through the interconnect structures; a portion of the pads of the second mounting region pass through the The wires and the interconnect structures are connected to the pin pads, and portions of the second mounting region are further connected to the plurality of bond pads disposed adjacent the third mounting region through the wires; a first wafer of the first mounting region is flip-chip mounted, and a gate and a source of a front surface of the first wafer are butted to the pads located in the first mounting region; a metal wafer flip-chip mounted on a second wafer in the second mounting region, a metal pad on a front side of the second wafer is mated with the pads located in the second mounting region; a third wafer is mounted on the chip a third mounting region, a drain of a back surface of the third wafer is mated with a carrier pad located in the third mounting region; and a conductive structure for connecting to the back surface of the first wafer a drain, a gate and a source of the front surface of the third wafer, and a bonding pad; a lead for connecting a bonding pad and a metal pad on the front surface of the second wafer; a package for covering the front surface of the substrate, and covering the first wafer, the second wafer and the third wafer, and the conductive structure and the lead. The power device of claim 13, wherein the first mounting area has a first set of pads and a second set of pads, and the second mounting area has a third set of pads to a sixth a soldering pad, wherein a part of the third set of pads is electrically connected to one or more pads of the first set of pads, and some of the pads of the third set of pads are One or more pads of the second set of pads are electrically connected; one or more of the pads of the fourth set of pads pass through the wires and the interconnect structures embedded in the substrate Electrically connecting to one or the plurality of pin pads; and each of the fifth set of pads and the sixth set of pads passes through the pads and a bonding pad on the substrate An electrical connection; wherein the bond pad and a carrier pad are each electrically connected to the or the lead pads via an interconnect structure. The power device of claim 14, wherein one or more of the first set of pads are connected to the second metal pad via the interconnect structures. The power device of claim 14, wherein a second metal pad is further disposed on the back surface of the substrate, and the carrier pad is connected to the second metal pad through the interconnect structures. The power device of claim 14, wherein a first metal pad of the front surface of the first wafer is soldered to one or more pads of the first set of pads, the first chip A second metal pad of the front side is correspondingly soldered to one or more of the second set of pads. The power device of claim 14, wherein a third metal pad of the front surface of the third wafer is connected to the metal layer of the back surface of the first wafer, the bonding pad through the conductive structure, and The third metal pad is further connected to a bonding pad through the leads, and a fourth metal pad of the front surface of the third chip is connected to the other bonding pad through the leads. The power device of claim 14, wherein the plurality of fifth metal pads of the front surface of the second wafer are soldered to the third set of pads to the sixth set of pads in a one-to-one manner. In the solder pad. The power device of claim 17, wherein the first wafer comprises a first metal oxide half field effect transistor (MOSFET), and the first metal pad is a gate of the first metal oxide half field effect transistor The second metal pad is a source of the first metal oxide half field effect transistor and the metal layer of the back surface of the first wafer is a drain of the first metal oxide half field effect transistor. The power device of claim 18, wherein the third wafer comprises a second metal oxide half field effect transistor (MOSFET), and the third metal pad is the second metal oxide half field effect a source of the crystal, the fourth metal pad is a gate of the second metal oxide half field effect transistor, and the metal layer of the back surface of the third wafer is one of the second metal oxide half field effect transistor Bungee jumping. The power device of claim 13, wherein the second mounting area and the third mounting area are arranged side by side, and the first mounting area is located between the second mounting area and the third mounting area An extension line of a dividing line, thereby arranging the first mounting area, the second mounting area, and the third mounting area in a shape of a line. The power device of claim 22, wherein the conductive structure is an L-shaped metal piece spanning over the first wafer and the third wafer, including a lateral portion on the first wafer and A longitudinal portion on the third wafer, the longitudinal portion having an extension extending obliquely downward, and the extension is pressed against the bond pad. A method for fabricating a power device includes the steps of: providing a substrate, a first mounting region to a third mounting region defined on a front surface of the substrate, wherein a bonding pad and a substrate are disposed on the front surface of the substrate a first metal pad and a plurality of pin pads are disposed on a back surface, and a plurality of wires are disposed on the substrate and a plurality of interconnect structures extending through the substrate; and a first wafer is poured in a flip chip manner Mounted in the first mounting region, a gate and a source of a front surface of the first wafer are butted to a plurality of pads located in the first mounting region; and a second wafer is flipped over in a flip chip manner a second mounting region, a metal pad on a front surface of the second wafer is mated with a plurality of pads located in the second mounting region; and a third wafer is mounted on the third mounting region, the third wafer a drain of a back surface is mated with a carrier pad located in the third mounting area; Mounting a conductive structure over the first wafer and the third wafer, the conductive structure is connected to a drain of the back surface of the first wafer and a gate and a source of the front surface of the third wafer and Between a bonding pad; bonding a plurality of leads between a bonding pad and the metal pad of the front surface of the second wafer, the wires being connected to the bonding pad and the front surface of the second wafer Between the metal pads; and forming a package covering the front surface of the substrate, and the package covers the first wafer, the second wafer and the third wafer, and the conductive structure and the leads a portion of the pads disposed in the first mounting region and a portion of the pads disposed in the second mounting region are connected by the wires, and the portions of the first mounting region are connected to the via structures through the interconnect structures a first metal pad; a portion of the pad of the second mounting region is connected to the pin pads through the wires and the interconnect structures, and portions of the second mounting region pass the pads Wiring connection In the vicinity of the third plurality of bonding pad mounting region. The method of claim 24, wherein the first mounting area has a first set of pads and a second set of pads, and the second mounting area has a third set of pads to a sixth set. a solder pad, wherein a part of the third set of pads is electrically connected to one or more pads of the first set of pads, and some of the pads are further included in the third set of pads One or more pads of the second set of pads are electrically connected; one or more of the pads of the fourth set of pads pass through the wires and a plurality of interconnect structures embedded in the substrate One way electrically connected to the or the pin pads; Each of the fifth set of pads and the sixth set of pads is electrically connected to a bonding pad through the wires on the substrate; wherein the bonding pads and a carrier pad are respectively connected to each other The connection structure is electrically connected to the or the pin pads. The method of claim 25, wherein one or more of the first set of pads are connected to the second metal pad via the interconnect structures. The method of claim 25, wherein a second metal pad is further disposed on the back surface of the substrate, and a carrier pad is connected to the second metal pad through the interconnect structures. The method of claim 24, wherein a first metal pad of the front surface of the first wafer is soldered to one or more pads of the first set of pads, the first wafer A second metal pad of the front side is correspondingly soldered to one or more of the second set of pads. The method of claim 24, wherein a third metal pad of the front surface of the third wafer is connected to the drain pad, the bonding pad of the back surface of the first wafer through the conductive structure, and The third metal pad is further connected to a bonding pad through the leads, and a fourth metal pad of the front surface of the third chip is connected to the other bonding pad through the leads. The method of claim 24, wherein the plurality of fifth metal pads of the front surface of the second wafer are soldered to the third set of pads to the sixth set of pads in a one-to-one manner Multiple pads on the pad.