【０００１】
【発明の属する技術分野】
本発明は、ＬＳＩや電界効果型トランジスタ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｒｔｏｒ：ＦＥＴ）などの半導体素子を収容するための半導体素子収納用パッケージおよび半導体装置に関する。
【０００２】
【従来の技術】
近年、無線通信に使用される携帯電話等の通信機器の発達に伴って、高周波帯域で高出力で作動するＩＣ，ＬＳＩ，ＦＥＴ等の半導体素子の需要が大幅に伸びている。特に、携帯電話の基地局に用いられる情報機器等では、限られた電力で高出力が得られ長時間の信号変換ができるように高効率で動作する半導体素子と、これを収納する半導体素子収納用パッケージ（以下、半導体パッケージともいう）が重要となってきている。即ち、内部の電力損失が小さく、入力された直流電力を効率よく高周波電力に変換する半導体素子と、この半導体素子を収納して、その性能を最大限引き出せる半導体パッケージが望まれている。
【０００３】
このようなことから、ガリウム砒素（ＧａＡｓ）化合物半導体を用いたＭＥＳＦＥＴ（Ｍｅｔａｌ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）の開発が進められてきたが、低電圧時の特性および変換効率が悪く、また大電流を流せないという点で問題があった。しかしながら、近年、ＧａＡｓ化合物半導体を用いたＨＢＴ（Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等の半導体素子が、ＭＥＳＦＥＴに比し優れた低電圧時の特性を有し、大きな直流電力を効率よく高周波電力に変換できるものとして注目されてきている。また、このような半導体素子は作動時に大量の熱を発生するため、熱放散性の良好な半導体パッケージが強く望まれている。
【０００４】
そして、ＨＢＴ等の半導体素子を搭載した半導体パッケージが、近年、産業用および民生用として開発され、例えば通信機器などに数多く使用されている。このような半導体パッケージを用いた半導体装置の一例を図３に示す。同図に示すように、アルミナ（酸化アルミニウム：Ａｌ２Ｏ３）質焼結体（アルミナセラミックス）等から成るとともに上面や内部に配線導体２ａが形成された回路基板２が、鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金等からなる基体１１上に取着され、回路基板２上面の載置部２ａに半導体素子４が取着されている。また、半導体素子４は、回路基板２の上面に形成された配線導体２ｂにボンディングワイヤを介して電気的に接合され、さらに枠体３の取付部３ａに嵌着された入出力端子３ｂにボンディングワイヤを介して電気的に接続されている。そして、蓋体６が枠体３の上面に接合されることにより半導体装置Ｂとなる（例えば、下記の特許文献１参照）。
【０００５】
アルミナセラミックスから成る回路基板２は、回路基板２の内部にタングステン（Ｗ）等から成る配線導体２ｂを形成することができ、また他の能動素子や受動素子を搭載して回路基板２に電気回路を形成することができる。従って、小型化および高密度化をともに満足させることができる。また、回路基板２を用いることにより、半導体パッケージに半導体素子４を収容した状態で性能試験で不良品が発見された場合、半導体素子４を回路基板２ごと取り替えれば良く、生産性に大きく寄与することができる。
【０００６】
【特許文献１】
特開２０００−１２４５５９号公報（第３−５頁、図１）
【０００７】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体パッケージにおいては、Ｆｅ−Ｎｉ−Ｃｏ合金等からなる基体１１と回路基板２との熱膨張係数差に起因して、回路基板２にクラックが発生するという不具合を招来していた。このクラックは、例えばＦｅ−Ｎｉ−Ｃｏ合金からなる基体１が、４２０℃付近で熱膨張係数が大きく変化する熱膨張係数の変曲点を有していることに起因して発生する。
【０００８】
すなわち、Ｆｅ−Ｎｉ−Ｃｏ合金の熱膨張係数は４２０℃以下の温度域では約５．４×１０−６／℃で４２０℃を超える温度域では約１１×１０−６／℃であり、また例えばアルミナセラミックスから成る回路基板２の熱膨張係数は４２０℃を超える温度域で約７×１０−６／℃であることにより、回路基板２を基体１上面にロウ付けする際に８００℃程度の温度に晒された後に徐々に４２０℃付近まで冷却される過程において、回路基板２全体に水平方向に引張り応力が加わることになる。その結果、回路基板２の角部などの応力に対して弱い部分を起点としてクラックが発生し、配線導体２ｂが切れて電気回路として不良となるという不具合が発生することがあった。
【０００９】
また、基体１１を成すＦｅ−Ｎｉ−Ｃｏ合金の熱伝導率が約１７Ｗ／ｍ・Ｋであり、ＣｕやＣｕ合金に比して数十分の一程度であることから、半導体素子４の発熱量が増えると放熱性が劣化し易くなっていた。
【００１０】
そこで、図４に示すように、基体１１の半導体素子４が搭載される部位をＣｕ板１０１ｂに置き換えて熱を効率よく外部に放散させることが試みられた。この場合、Ｃｕ板１０１ｂは基体１０１ａの貫通孔にロウ材を介して取着され接合されるため、部分的に接伝導率が良好な複合基体１０１となり、またＣｕ板１０１ｂの熱膨張が周囲のＦｅ−Ｎｉ−Ｃｏ合金からなる基体１０１ａによって抑え込まれることとなる。その結果、半導体素子４をＣｕ板１０１ｂの上側主面に搭載して作動させるに際して不具合が発生することはなかった。
【００１１】
しかしながら、この複合基体１０１においては、Ｃｕ板１０１ｂの大きさを貫通孔に対して若干小さくすることにより、Ｃｕ板１０１ｂをロウ材を介して基体１０１ａの貫通孔に取着させる際にＣｕ板１０１ｂの熱膨張によって基体１０１ａに過大な応力を及ぼさないようにしているが、Ｃｕ板１０１ｂがロウ付け時に８００℃程度まで加熱された後に冷却していく過程で回路基板２に大きな引張り応力が加わり、回路基板２にクラックが発生したり、高温域（７５０〜９００℃程度）で固化したロウ材に低温域（室温〜数十℃程度）でクラックが発生する場合があり、複合基体１０１を量産するに際しての大きな障害となっていた。
【００１２】
そこで、回路基板２を厚くして応力に耐えるようにすることが試みられた。しかしながら、この場合、回路基板２において半導体素子４の熱に対する熱抵抗が大きくなり、半導体素子４の温度が上昇して、半導体素子４の動作性が劣化するといった不具合が発生した。また、回路基板２のクラック発生を防止するために強度の大きな炭化珪素（ＳｉＣ）セラミックス等から成るものを用いることが試みられた。しかしながら、この場合、回路基板２にクラックは発生しないものの、例えばＳｉＣセラミックスでは、熱膨張係数がアルミナ（Ａｌ２Ｏ３）の熱膨張係数（８×１０−６／℃）の約１／２程度であり、半導体素子４が作動したときに発生する熱によりＣｕ板１０１ｂが膨張したときに回路基板２がその膨張に追従しきれないために回路基板２を接合しているロウ材にクラックが発生し、その結果、回路基板２が基体１０１ａから外れるといった不具合が発生していた。
【００１３】
従って、本発明は上記従来の問題点に鑑みて完成されたものであり、その目的は、回路基板にクラックが発生するのを防止して、半導体素子を長期に亘り正常かつ安定に作動させることのできる半導体パッケージを提供することにある。
【００１４】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、中央部に貫通孔が形成された鉄を主成分とする鉄合金から成る枠状の基体と、前記基体の前記貫通孔に取着された銅または銅を主成分とする銅合金から成る板部材と、上面に半導体素子が搭載される載置部を有する、下面が前記板部材の上側主面の全面および前記上側主面の周囲の前記基体の上面に接合された回路基板と、前記基体の上面の外周部に前記回路基板を囲繞するように取着された枠体と、該枠体の側部に形成された貫通孔または切欠きからなる入出力端子の取付部と、該取付部に嵌着された入出力端子とを具備しており、前記板部材は、前記基体の前記貫通孔に０．５乃至２ｍｍの隙間をもって挿入されるとともに側面の下側に略等間隔で形成された複数の凸部が前記貫通孔の内面にロウ付けされることによって前記貫通孔に取着されていることを特徴とする。
【００１５】
本発明の半導体素子収納用パッケージは、板部材は基体の貫通孔に０．５乃至２ｍｍの隙間をもって挿入されるとともに側面の下側に略等間隔で形成された複数の凸部が貫通孔の内面にロウ付けされることによって貫通孔に取着されていることにより、半導体素子収納用パッケージの気密性が保持されるとともに基体は半導体素子の熱を良好に放熱できるものとなる。即ち、板部材の上側主面の面積が小さくなるため、板部材の熱膨張や収縮による回路基板への影響が小さくなり、回路基板にクラックが発生するのを抑制することができる。また、板部材を貫通孔に取着するためのロウ材にクラックが発生するのを防ぐことができ、その結果、半導体素子収納用パッケージの気密性が保持されるとともに半導体素子の熱を良好に放熱できることとなる。
【００１６】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記板部材の前記凸部は、厚さが前記板部材の厚さの１／４乃至１／２とされているとともに幅が前記板部材の厚さの１／４乃至１／２とされていることを特徴とする。
【００１７】
本発明の半導体素子収納用パッケージは、板部材の凸部は厚さが板部材の厚さの１／４乃至１／２とされているとともに幅が板部材の厚さの１／４乃至１／２とされていることから、凸部の剛性を保持して板部材を確実に貫通孔にロウ付けできるとともに板部材の上下主面と基体の上下面とを略面一に保持することができる。その結果、安定した基体の放熱性が得られ、これにより半導体素子を基体の上面に信頼性よく長期に亘って載置することができる。また、板部材による半導体素子の接地性が安定化し、高周波信号の伝送損失が改善された半導体素子収納用パッケージとなすことができる。
【００１８】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置固定されるとともに前記入出力端子に電気的に接続された半導体素子と、前記枠体の上面に接合された蓋体とを具備したことを特徴とする。
【００１９】
本発明の半導体装置は、上記の構成により、上記本発明の作用効果を有する、半導体素子を長期に亘り正常かつ安定して作動させることができる信頼性の高いものとなる。
【００２０】
【発明の実施の形態】
本発明の半導体素子収納用パッケージおよび半導体装置について以下に詳細に説明する。図１は本発明の半導体パッケージについて実施の形態の一例を示し、（ａ）は半導体パッケージの平面図、（ｂ）は（ａ）のＸ−Ｘ’線における断面図である。また、図２は本発明の半導体パッケージにおける板部材の凸部の拡大断面図である。
【００２１】
これらの図において、Ａは半導体パッケージ、１は複合基体、１ａは基体、１ｂは板部材、１ｃは基体１ａの貫通孔の内面、１ｄは隙間、１ｅは凸部、２は回路基板、２ａは半導体素子の載置部、２ｂは配線導体、２ｃはメタライズ層である。また、３は枠体、３ａは入出力端子３ｂの取付部、３ｂは入出力端子、４はＦＥＴ等の半導体素子、６は蓋体である。そして、複合基体１、回路基板２、枠体３および蓋体６とで半導体素子４を気密に収容する容器が基本的に構成される。
【００２２】
なお、図１，図２において、従来例を示す図３，図４と同じ部分には同じ符号を付した。
【００２３】
本発明の半導体パッケージＡは、中央部に貫通孔が形成された鉄を主成分とする鉄合金から成る枠状の基体１ａと、基体１ａの貫通孔に取着された銅または銅を主成分とする銅合金から成る板部材１ｂと、上面に半導体素子４が搭載される載置部２ａを有する、下面が板部材１ｂの上側主面の全面および上側主面の周囲の基体１ａの上面に接合された回路基板２と、基体１ａの上面の外周部に回路基板２を囲繞するように取着された枠体３と、枠体３の側部に形成された貫通孔または切欠きからなる入出力端子３ｂの取付部３ａと、取付部３ａに嵌着された入出力端子３ｂとを具備し、板部材１ｂは、基体１ａの貫通孔に０．５乃至２ｍｍの隙間１ｄをもって挿入されるとともに側面の下側に略等間隔で形成された複数の凸部１ｅが貫通孔の内面１ｃにロウ付けされることによって貫通孔に取着されている。
【００２４】
本発明の板部材１ｂは、例えば側面の対向する２隅部に凸部１ｅが形成されており、凸部１ｅの先端面と基体１ａの内面１ｃとが例えばＡｇ−Ｃｕ合金ロウ（ＢＡｇ−８：ＪＩＳ Ｚ ３２６１）によって接合され、一体となって複合基体１を構成する。
【００２５】
回路基板２の下面には略全面にメタライズ層２ｃが形成されており、そのメタライズ層２ｃが上記Ａｇ−Ｃｕ合金ロウ等のロウ材を介して板部材１ｂの上側主面にロウ付けされているとともに、隙間１ｄを塞ぐようにして貫通孔の周囲の基体１ａの上面にロウ付けされている。これにより、枠体３とその上面に接合される蓋体６とで半導体装置Ｂの内部を気密に封止することができる。
【００２６】
本発明の複合基体１は、上面に半導体素子４を載置する載置部２ａを有する回路基板２を搭載し、回路基板２および半導体素子４を支持する支持部材であり、半導体素子４の熱を回路基板２を介して外部に効率良く放散する機能を有する。複合基体１を構成する基体１ａは、外形形状が略正方形や略長方形の略四角形であり、Ｆｅ−Ｎｉ−Ｃｏ合金，Ｆｅ−Ｎｉ合金，ＳＵＳ（ステンレススチール）等の鉄を主成分とする鉄合金から成り、例えばＦｅ−Ｎｉ−Ｃｏ合金のインゴット（塊）に圧延加工や打ち抜き加工等の従来周知の金属加工法を施すことによって所定形状に作製される。
【００２７】
また、基体１ａの貫通孔の内側に貫通孔の内面との間に隙間１ｄをもって設置される板部材１ｂは、銅（Ｃｕ）またはＣｕ−亜鉛（Ｚｎ）合金、Ｃｕ−タングステン（Ｗ）合金等の銅を主成分とする銅合金から成る。そして、板部材１ｂは、例えば銅板に圧延加工や打抜き加工を施すことによって外形形状が概略的に成形され、次にエッチング法によって銅板の側面に所定の厚さおよび幅を有する凸部１ｅが形成される。この凸部１ｅは、銅板を上側主面側からエッチングすることによって形成される。また、板部材１ｂの大きさは半導体素子４の面積によって変動するが、隙間１ｄの大きさは半導体素子４の面積によって変動しない。
【００２８】
凸部１ｅは、板部材１ｂの側面に略等間隔で複数設けられ、先端面が基体１ａの内面１ｃにロウ付けされることによって基体１ａに板部材１ｂが接合される。板部材１ｂを基体１ａの貫通孔に凸部１ｅで接合することにより、板部材１ｂを確実に貫通孔にロウ付けできるとともに板部材１ｂの上下主面と基体１ａの上下面とを略面一に保持することができる。その結果、安定した基体１ａの放熱性が得られ、これにより半導体素子４を基体１ａの上面に信頼性よく長期に亘って載置することができる。
【００２９】
さらに、凸部１ｅの厚さを板部材１ｂの厚さの１／４乃至１／２とし、凸部１ｅの幅を板部材１ｂの厚さの１／４乃至１／２としていることにより、凸部１ｅの剛性が小さすぎたり大きすぎたりすることが無く、その結果、板部材１ｂにうねりが発生したり、応力によって凸部１ｅが変形するような不具合が発生することが無い。
【００３０】
凸部１ｅの厚さが板部材１ｂの厚さの１／４未満であるか、または凸部１ｅの幅が板部材１ｂの厚さの１／４未満である場合、凸部１ｅの剛性が小さくなり、板部材１ｂに応力や外力が加わると、凸部１ｅの付け根付近が折れたり屈曲するといった変形が生じ易くなる。また、凸部１ｅの厚さが板部材１ｂの厚さの１／４乃至１／２であるとしても、凸部１ｅの幅が板部材１ｂの厚さの１／４未満になると、凸部１ｅの剛性が小さくなり、板部材１ｂに応力や外力が加わると、凸部１ｅの付け根付近が折れたり屈曲するといった変形が生じ易くなる。
【００３１】
また、凸部１ｅの厚さが板部材１ｂの厚さの１／２を超え、凸部１ｅの幅が板部材１ｂの厚さの１／２を超えると、半導体素子４の熱等によって複合基体１が加熱されたときに、板部材１ｂにうねりや反り等が発生するとともに、凸部１ｅの剛性が大きいため板部材１ｂのうねりや反りによって回路基板２にクラック等が発生し易くなる。即ち、凸部１ｅの剛性が適度であると、板部材１ｂのうねりや反りが発生しても、そのうねりや反りを緩和し打ち消すように凸部１ｅが変形でき、その結果、うねりや反りによる回路基板２への影響を抑制することができるが、凸部１ｅの厚さが板部材１ｂの厚さの１／２を超え、凸部１ｅの幅が板部材１ｂの厚さの１／２を超えると、板部材１ｂのうねりや反りによる回路基板２への影響を抑制するという効果が小さくなる。
【００３２】
また、凸部１ｅは板部材１ｂの側面に略等間隔に複数設けられる必要がある。これにより、板部材１ｂを基体１ａに強固に接合できるとともに、板部材１ｂが上下方向にずれたりするのを防ぐことができる。また、例えば凸部１ｅを３ヶ所に設けると、たとえ板部材１ｂに大きな外力が作用したとしても、その位置ずれはほとんど発生しないことが確認できた。凸部１ｅを２ヶ所に設ける場合のそれら位置は、板部材１ｂの対向する２隅部、対向する２側面、または一方を隅部に他方をその隅部に略対向する側面とすることができ、実際にいずれの場合にも良好な結果が得られた。
【００３３】
本発明の複合基体１は、その表面に耐蝕性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ０．５〜９μｍのＮｉ層と厚さ０．５〜５μｍのＡｕ層をメッキ法により順次被着しておくのがよく、複合基体１が酸化腐蝕するのを有効に防止できるとともに複合基体１上に回路基板２を強固に接着固定することができる。
【００３４】
また、複合基体１を構成する基体１ａの上面には、回路基板２を囲繞するように、側部に入出力端子３ｂを嵌着するための貫通孔または切欠き部から成る取付部３ａが形成された枠体３が銀ロウ等のロウ材で接合されており、枠体３の内側に半導体素子４を収納するための空所が形成される。この枠体３は、基体１ａと同様の金属から成り半導体パッケージＡの側壁を成すものであり、その製作は基体１ａと同様の金属加工法により側部に取付部３ａを有する形状になるようにして行なわれる。
【００３５】
なお、枠体３の複合基体１の基体１ａへの接合は、基体１ａの上面の外周部と枠体３の下面とを、基体１ａの上面の外周部に敷設した適度なボリュームを有するプリフォームとされた銀ロウ等のロウ材を介して行なわれる。この枠体３の表面には、複合基体１と同様に厚さ０．５〜９μｍのＮｉ層と厚さ０．５〜５μｍのＡｕ層等の金属層をメッキ法により被着させておくと良い。
【００３６】
また、枠体３の取付部３ａには、半導体素子４と外部電気回路との高周波信号の入出力を行うとともに半導体パッケージＡの内外を遮断するための入出力端子３ｂが、その側面に設けられているメタライズ層を介して銀ロウ等のロウ材で接合される。この入出力端子３ａは、略長方形等の略四角形の平板部の上面に、横倒しにされた四角柱状の立壁部が積層されて成る構造を有している。
【００３７】
本発明の回路基板２は、Ａｌ２Ｏ３質焼結体等からなり、その形状は例えば略四角形である。この回路基板２は、以下のようにして作製される。先ず、Ａｌ２Ｏ３，酸化珪素（ＳｉＯ２），酸化マグネシウム（ＭｇＯ），酸化カルシウム（ＣａＯ）等の原料粉末に適当な有機バインダー、有機溶剤、可塑剤、分散剤等を添加混合してスラリー状となし、これを従来周知のドクターブレード法によってシート状となすことにより、複数枚のセラミックグリーンシートを得る。
【００３８】
次に、このセラミックグリーンシートに適当な打抜き加工を施すとともに、タングステン（Ｗ），モリブデン（Ｍｏ），マンガン（Ｍｎ），銅（Ｃｕ），銀（Ａｇ），ニッケル（Ｎｉ），パラジウム（Ｐｄ），金（Ａｕ）等の金属粉末に適当なバインダー、溶剤を混合してなる導体ペーストを、セラミックグリーンシートに予めスクリーン印刷法等により所定パターンに印刷塗布することによって、配線導体２ｂ、メタライズ層２ｃとなる印刷層をそれぞれ形成する。その後、セラミックグリーンシートを所定の順序で積層した後、所定の寸法に切断し、最後に約１６００℃の温度で焼成することによって、回路基板２が作製される。
【００３９】
また、回路基板２はセラミックグリーンシート積層法によって内層に配線導体２ｂを有するものであっても良い。そして、回路基板２は、下面にメタライズ層２ｃが形成されていることにより、セラミックグリーンシートとメタライズ層２ｃとの若干の収縮率や収縮挙動の差によって回路基板２に若干の反りが発生する。
【００４０】
また、配線導体２ｂ、メタライズ層２ｃの表面に、良導電性で耐食性およびロウ材との濡れ性が良好な金属、例えばＮｉメッキ層を０．５〜９μｍの厚さで被着させておくのがよく、配線導体２ｂ、メタライズ層２ｃの酸化腐食を有効に防止するとともに、メタライズ層２ｃと板部材１ｂとのロウ付けを容易かつ強固とすることができる。
【００４１】
本発明において、図１，図３に示すように、基体１ａの貫通孔の内面と板部材１ｂの側面との隙間１ｄは０．５乃至２ｍｍである。０．５ｍｍ未満では、凸部１ｅを貫通孔にロウ付けした際に隙間１ｄ全体が薄いロウ材で埋まってしまい、回路基板２で板部材１ｂの熱膨張がある程度抑え込まれているものの、板部材１ｂの熱膨張や収縮に際して発生する応力が薄いロウ材に直接作用し、その結果、ロウ材にクラックが発生して半導体パッケージＡの気密性が劣化し易くなる。一方、隙間１ｄが２ｍｍを超えると、基体１ａと回路基板２との接合面積が小さくなり、基体１ａ側のロウ付け部にクラックや割れ等が発生すると容易に気密性が損なわれる傾向がある。
【００４２】
このような半導体パッケージＡにおいて、載置部２ａに半導体素子４を錫（Ｓｎ）−鉛（Ｐｂ）半田などの低融点ロウ材で載置固定するとともに、配線導体２ｂと半導体素子４とをボンディングワイヤ等で電気的に接続し、配線導体２ｂと入出力端子３ｂとをボンディングワイヤで電気的に接続し、最後に枠体３の上面に蓋体６をシーム溶接法により接合することで、製品としての半導体装置となる。この半導体装置は、例えば外部電気回路から供給される高周波信号等の駆動信号によって半導体素子４を作動させ、大容量の情報を高速に伝送する通信装置などに用いられる。
【００４３】
【実施例】
本発明の半導体パッケージおよび半導体装置の実施例を以下に説明する。
【００４４】
まず、図１，図２に示す複合基体１を以下のように構成した。外形寸法が縦２０ｍｍ×横２０ｍｍ×厚さ１ｍｍであり、中央部に貫通孔を有し枠部の幅が４ｍｍである、Ｆｅ−Ｎｉ−Ｃｏ合金から成る枠状の基体１ａを準備した。そして、基体１ａの貫通孔に取着させる板部材１ｂとして、貫通孔に対応した形状の銅から成るものを用意した。この板部材１ｂの対向する２隅部にそれぞれ厚さが０．４ｍｍで幅が０．４ｍｍの凸部１ｅをエッチング法によって形成した。このとき、隙間１ｄが９種の値（表１）となるようにして各５個作製した。
【００４５】
また、予め内層および上面に配線導体２ｂおよび下面にメタライズ層２ｃを設けた、縦１６ｍｍ×横１６ｍｍ×厚さ０．６３５ｍｍの回路基板２を４５個（隙間９種×５個＝４５個）作製し、その下面を板部材１ｂの上側主面および基体１ａの上面にロウ付けして複合基体１上に設けた。このとき、基体１ａの上面における回路基板２下面のロウ付け部幅を２ｍｍとしてロウ付け部のクラックおよび気密性について調査した。その結果を表１に示す。
【００４６】
【表１】
【００４７】
表１より、隙間１ｄが０．５〜２ｍｍの場合に板部材１ｂと基体１ａとのロウ付け部にクラックの発生は見られず、また基体１ａと回路基板２とのロウ付け部における気密性が良好であり、本発明の有効性が確認できた。
【００４８】
次に、隙間１ｄを１ｍｍとして、凸部１ｅの厚さおよび幅を種々の値（表２）とし、１種につき５個すつ作製した。これらについて、凸部１ｅの変形と板部材１ｂの反りやうねり等の変形について調査した。その結果を表２に示す。
【００４９】
【表２】
【００５０】
表２より、凸部１ｅの厚さが板部材１ｂの厚さ（１ｍｍ）の１／４（０．２５ｍｍ）乃至１／２（０．５ｍｍ）であり、凸部１ｅの幅が板部材１ｂの厚さ１／４（０．２５ｍｍ）乃至１／２（０．５ｍｍ）である場合に、凸部１ｅの変形が発生せず、本発明の有効性が確認できた。またこの試験結果は、複合基体１の厚さ、すなわち板部材１ｂの厚さを通常用いられる範囲内で適宜変化させた場合にも同様であった。
【００５１】
なお、本発明は上記実施の形態および実施例に限定されず、本発明の要旨を逸脱しない範囲内で種々の変更を行うことは何等差し支えない。例えば、上記実施の形態では半導体素子をＦＥＴ等として説明したが、これを半導体レーザやフォトダイオード等の光半導体素子としても良く、そのときは枠体３の側部に光ファイバを取着するための貫通孔から成る取付部が形成される。
【００５２】
【発明の効果】
本発明の半導体素子収納用パッケージは、中央部に貫通孔が形成された鉄を主成分とする鉄合金から成る枠状の基体と、基体の貫通孔に取着された銅または銅を主成分とする銅合金から成る板部材と、上面に半導体素子が搭載される載置部を有する、下面が板部材の上側主面の全面および上側主面の周囲の基体の上面に接合された回路基板と、基体の上面の外周部に回路基板を囲繞するように取着された枠体と、枠体の側部に形成された貫通孔または切欠きからなる入出力端子の取付部と、取付部に嵌着された入出力端子とを具備し、板部材は、基体の貫通孔に０．５乃至２ｍｍの隙間をもって挿入されるとともに側面の下側に略等間隔で形成された複数の凸部が貫通孔の内面にロウ付けされることによって貫通孔に取着されていることにより、半導体素子収納用パッケージの気密性が保持されるとともに基体は半導体素子の熱を良好に放熱できるものとなる。即ち、板部材の上側主面の面積が小さくなるため、板部材の熱膨張や収縮による回路基板への影響が小さくなり、回路基板にクラックが発生するのを抑制することができる。また、板部材を貫通孔に取着するためのロウ材を必要としないことから、従来の半導体素子収納用パッケージに発生していたロウ材のクラックを解消することができ、その結果、半導体素子収納用パッケージの気密性が保持されるとともに半導体素子の熱を良好に放熱できることとなる。
【００５３】
本発明の半導体素子収納用パッケージにおいて、好ましくは、板部材の凸部は厚さが板部材の厚さの１／４乃至１／２とされているとともに幅が板部材の厚さの１／４乃至１／２とされていることにより、凸部の剛性を保持して板部材を確実に貫通孔にロウ付けできるとともに板部材の上下主面と基体の上下面とを略面一に保持することができる。その結果、安定した基体の放熱性が得られ、これにより半導体素子を基体の上面に信頼性よく長期に亘って載置することができる。また、板部材による半導体素子の接地性が安定化し、高周波信号の伝送損失が改善された半導体素子収納用パッケージとなすことができる。
【００５４】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部に載置固定されるとともに入出力端子に電気的に接続された半導体素子と、枠体の上面に接合された蓋体とを具備したことにより、上記本発明の作用効果を有する、半導体素子を長期に亘り正常かつ安定して作動させることができる信頼性の高いものとなる。
【図面の簡単な説明】
【図１】本発明の半導体素子収納用パッケージについて実施の形態の一例を示し、（ａ）は半導体素子収納用パッケージの平面図、（ｂ）は（ａ）のＸ−Ｘ’線における断面図である。
【図２】図１の半導体素子収納用パッケージにおける板部材の凸部を示す要部拡大断面図である。
【図３】従来の半導体素子収納用パッケージの一例を示す断面図である。
【図４】従来の半導体素子収納用パッケージの他の例を示す断面図である。
【符号の説明】
１：複合基体
１ａ：基体
１ｂ：板部材
１ｃ：貫通孔の内面
１ｄ：隙間
１ｅ：凸部
２：回路基板
２ａ：載置部
３：枠体
３ａ：入出力端子の取付部
３ｂ：入出力端子
４：半導体素子
Ａ：半導体素子収納用パッケージ
Ｂ：半導体装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device housing package for housing a semiconductor device such as an LSI or a field effect transistor (FET), and a semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the development of communication devices such as mobile phones used for wireless communication, demand for semiconductor devices such as ICs, LSIs, and FETs that operate with high output in a high-frequency band has been greatly increased. In particular, in information equipment and the like used for base stations of mobile phones, a semiconductor element that operates with high efficiency so that high power can be obtained with limited power and long-term signal conversion can be performed, and a semiconductor element housing that houses the semiconductor element Packages (hereinafter, also referred to as semiconductor packages) have become important. That is, there is a demand for a semiconductor element which has a small internal power loss and efficiently converts input DC power into high-frequency power, and a semiconductor package which accommodates the semiconductor element and can maximize its performance.
[0003]
For this reason, the development of MESFETs (Metal Semiconductor Field Effect Transistors) using gallium arsenide (GaAs) compound semiconductors has been advanced, but the characteristics and conversion efficiency at low voltages are poor, and large currents cannot be passed. There was a problem in that. However, in recent years, semiconductor devices such as HBTs (Heterojunction Bipolar Transistors) using GaAs compound semiconductors have excellent low-voltage characteristics as compared with MESFETs, and can convert large DC power to high-frequency power efficiently. It is getting attention. Further, since such a semiconductor element generates a large amount of heat during operation, a semiconductor package having good heat dissipation is strongly desired.
[0004]
In recent years, semiconductor packages on which semiconductor elements such as HBTs are mounted have been developed for industrial and consumer use in recent years, and are widely used in, for example, communication equipment. FIG. 3 shows an example of a semiconductor device using such a semiconductor package. As shown in the figure, alumina (aluminum oxide: Al 2 O 3 A circuit board 2 made of a sintered material (alumina ceramics) or the like and having a wiring conductor 2a formed on the upper surface or inside is formed on a substrate 11 made of an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or the like. The semiconductor element 4 is attached to the mounting portion 2a on the upper surface of the circuit board 2. The semiconductor element 4 is electrically connected to a wiring conductor 2b formed on the upper surface of the circuit board 2 via a bonding wire, and is further bonded to an input / output terminal 3b fitted to the mounting portion 3a of the frame 3. They are electrically connected via wires. Then, the semiconductor device B is obtained by joining the lid 6 to the upper surface of the frame 3 (for example, see Patent Document 1 below).
[0005]
In the circuit board 2 made of alumina ceramics, a wiring conductor 2b made of tungsten (W) or the like can be formed inside the circuit board 2, and an electric circuit is mounted on the circuit board 2 by mounting other active elements and passive elements. Can be formed. Therefore, both miniaturization and high density can be satisfied. In addition, by using the circuit board 2, when a defective product is found in a performance test in a state where the semiconductor element 4 is housed in the semiconductor package, the semiconductor element 4 may be replaced with the entire circuit board 2, greatly contributing to productivity. can do.
[0006]
[Patent Document 1]
JP-A-2000-124559 (page 3-5, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, in the above-mentioned conventional semiconductor package, a crack is generated in the circuit board 2 due to a difference in thermal expansion coefficient between the base 11 made of an Fe—Ni—Co alloy or the like and the circuit board 2. Was. This crack occurs because the base 1 made of, for example, an Fe—Ni—Co alloy has an inflection point of the thermal expansion coefficient at which the thermal expansion coefficient changes largely at around 420 ° C.
[0008]
That is, the thermal expansion coefficient of the Fe—Ni—Co alloy is about 5.4 × 10 in a temperature range of 420 ° C. or less. -6 About 11 × 10 in the temperature range exceeding 420 ° C./° C. -6 / ° C., and the thermal expansion coefficient of the circuit board 2 made of, for example, alumina ceramics is about 7 × 10 -6 / ° C., the circuit board 2 is exposed to a temperature of about 800 ° C. when brazing the circuit board 2 to the upper surface of the base 1 and is gradually cooled to around 420 ° C. Tensile stress will be applied. As a result, cracks may be generated starting from a portion of the circuit board 2 that is weak against stress, such as a corner, and the wiring conductor 2b may be broken to cause a failure as an electric circuit.
[0009]
The thermal conductivity of the Fe—Ni—Co alloy forming the base 11 is about 17 W / m · K, which is about several tenths of that of Cu or Cu alloy. When the amount was increased, the heat radiation was likely to deteriorate.
[0010]
Therefore, as shown in FIG. 4, an attempt has been made to efficiently dissipate heat to the outside by replacing the portion of the base 11 on which the semiconductor element 4 is mounted with a Cu plate 101b. In this case, since the Cu plate 101b is attached to and joined to the through hole of the base 101a through a brazing material, the composite base 101 has a partially good contact conductivity, and the thermal expansion of the Cu plate 101b is reduced by the surroundings. This is suppressed by the base 101a made of the Fe—Ni—Co alloy. As a result, no problem occurred when the semiconductor element 4 was mounted on the upper main surface of the Cu plate 101b and operated.
[0011]
However, in the composite substrate 101, the Cu plate 101b is slightly reduced in size with respect to the through hole, so that the Cu plate 101b is attached to the through hole of the substrate 101a via the brazing material. Does not exert an excessive stress on the substrate 101a due to thermal expansion of the substrate 101. However, a large tensile stress is applied to the circuit board 2 in the process of cooling after the Cu plate 101b is heated to about 800 ° C. during brazing, Cracks may occur in the circuit board 2 or cracks may occur in the low-temperature range (room temperature to about several tens of degrees Celsius) in the brazing material solidified in the high-temperature range (about 750 to 900 ° C.). It was a major obstacle for me.
[0012]
Therefore, an attempt was made to make the circuit board 2 thicker to withstand stress. However, in this case, the thermal resistance of the semiconductor element 4 to the heat in the circuit board 2 becomes large, and the temperature of the semiconductor element 4 rises, and the operability of the semiconductor element 4 deteriorates. Further, in order to prevent the occurrence of cracks in the circuit board 2, an attempt has been made to use a high strength silicon carbide (SiC) ceramic or the like. However, in this case, although cracks do not occur in the circuit board 2, for example, in the case of SiC ceramics, the coefficient of thermal expansion is alumina (Al). 2 O 3 ) (8 × 10 -6 / ° C.), and when the Cu board 101b expands due to heat generated when the semiconductor element 4 operates, the circuit board 2 cannot follow the expansion because the Cu board 101b expands. Cracks were generated in the brazing material, and as a result, there was a problem that the circuit board 2 came off the base 101a.
[0013]
Therefore, the present invention has been completed in view of the above-mentioned conventional problems, and an object of the present invention is to prevent a crack from occurring in a circuit board and to operate a semiconductor element normally and stably for a long period of time. It is to provide a semiconductor package which can be used.
[0014]
[Means for Solving the Problems]
The semiconductor device housing package of the present invention includes a frame-shaped base made of an iron alloy containing iron as a main component having a through hole formed in a central portion, and copper or copper attached to the through hole of the base. A plate member made of a copper alloy as a main component, and a mounting portion on which a semiconductor element is mounted on the upper surface, the lower surface is provided on the entire upper main surface of the plate member and on the upper surface of the base around the upper main surface. An input / output comprising a bonded circuit board, a frame attached to an outer peripheral portion of an upper surface of the base so as to surround the circuit board, and a through hole or notch formed in a side portion of the frame; A terminal attachment portion, and an input / output terminal fitted to the attachment portion, wherein the plate member is inserted into the through hole of the base with a gap of 0.5 to 2 mm, and a side surface of the plate member is provided. A plurality of convex portions formed at substantially equal intervals on the lower side are formed on the inner surface of the through hole. Characterized in that it is attached to the through hole by being attached.
[0015]
In the package for accommodating a semiconductor element of the present invention, the plate member is inserted into the through hole of the base with a gap of 0.5 to 2 mm, and a plurality of convex portions formed at substantially equal intervals below the side surface are formed in the through hole. By being attached to the through hole by being brazed to the inner surface, the airtightness of the semiconductor element storage package is maintained, and the base can satisfactorily radiate heat of the semiconductor element. That is, since the area of the upper main surface of the plate member is reduced, the influence of the thermal expansion and contraction of the plate member on the circuit board is reduced, and the occurrence of cracks in the circuit board can be suppressed. Further, it is possible to prevent cracks from being generated in the brazing material for attaching the plate member to the through-hole, and as a result, the airtightness of the semiconductor element housing package is maintained and the heat of the semiconductor element is satisfactorily reduced. Heat can be dissipated.
[0016]
In the package for accommodating a semiconductor element of the present invention, preferably, the projection of the plate member has a thickness of 1/4 to 1/2 of a thickness of the plate member and a width of the plate member. The thickness is set to １ ／ to の of the thickness.
[0017]
In the package for housing a semiconductor element according to the present invention, the projection of the plate member has a thickness of １ ／ to の of the thickness of the plate member and a width of ４ to 1 of the thickness of the plate member. / 2, the rigidity of the convex portion is maintained, the plate member can be securely brazed to the through hole, and the upper and lower main surfaces of the plate member and the upper and lower surfaces of the base are held substantially flush. it can. As a result, stable heat dissipation of the base is obtained, and the semiconductor element can be mounted on the upper surface of the base with high reliability over a long period of time. Further, the grounding property of the semiconductor element by the plate member is stabilized, and a semiconductor element housing package in which transmission loss of a high-frequency signal is improved can be provided.
[0018]
The semiconductor device of the present invention includes the semiconductor element housing package of the present invention, a semiconductor element mounted and fixed to the mounting portion and electrically connected to the input / output terminal, and an upper surface of the frame body. And a joined lid.
[0019]
According to the semiconductor device of the present invention having the above-described configuration, the semiconductor device having the above-described advantageous effects of the present invention can be normally and stably operated for a long time with high reliability.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
The package for housing a semiconductor element and the semiconductor device according to the present invention will be described in detail below. 1A and 1B show an example of an embodiment of a semiconductor package of the present invention. FIG. 1A is a plan view of the semiconductor package, and FIG. 1B is a cross-sectional view taken along line XX ′ of FIG. FIG. 2 is an enlarged sectional view of a convex portion of a plate member in the semiconductor package of the present invention.
[0021]
In these figures, A is a semiconductor package, 1 is a composite substrate, 1a is a substrate, 1b is a plate member, 1c is an inner surface of a through hole of the substrate 1a, 1d is a gap, 1e is a convex portion, 2 is a circuit board, and 2a is a circuit board. The mounting portion of the semiconductor element, 2b is a wiring conductor, and 2c is a metallized layer. Reference numeral 3 denotes a frame, 3a denotes a mounting portion of the input / output terminal 3b, 3b denotes an input / output terminal, 4 denotes a semiconductor element such as an FET, and 6 denotes a lid. The composite base 1, the circuit board 2, the frame 3, and the lid 6 basically constitute a container for hermetically housing the semiconductor element 4.
[0022]
In FIGS. 1 and 2, the same parts as those in FIGS. 3 and 4 showing the conventional example are denoted by the same reference numerals.
[0023]
The semiconductor package A of the present invention includes a frame-shaped base 1a made of an iron alloy containing iron as a main component and having a through-hole formed in the center, and copper or copper attached to the through-hole of the base 1a as a main component. A plate member 1b made of a copper alloy and a mounting portion 2a on the upper surface of which the semiconductor element 4 is mounted. The lower surface is formed on the entire upper main surface of the plate member 1b and on the upper surface of the base 1a around the upper main surface. It comprises a bonded circuit board 2, a frame 3 attached to the outer periphery of the upper surface of the base 1a so as to surround the circuit board 2, and a through hole or notch formed in a side portion of the frame 3. The plate member 1b includes a mounting portion 3a for the input / output terminal 3b and an input / output terminal 3b fitted to the mounting portion 3a. The plate member 1b is inserted into the through hole of the base 1a with a gap 1d of 0.5 to 2 mm. A plurality of protrusions 1e formed at substantially equal intervals below the side surface are formed in the through hole. It is attached to the through hole by being brazed to a surface 1c.
[0024]
In the plate member 1b of the present invention, for example, convex portions 1e are formed at two opposing corners of the side surface, and the tip surface of the convex portion 1e and the inner surface 1c of the base 1a are made of, for example, an Ag-Cu alloy brazing (BAg-8). : JIS Z 3261) to form the composite substrate 1 integrally.
[0025]
A metallized layer 2c is formed on substantially the entire lower surface of the circuit board 2, and the metallized layer 2c is brazed to the upper main surface of the plate member 1b via a brazing material such as the Ag-Cu alloy brazing. At the same time, it is brazed to the upper surface of the base 1a around the through hole so as to close the gap 1d. Thus, the inside of the semiconductor device B can be hermetically sealed by the frame 3 and the lid 6 joined to the upper surface thereof.
[0026]
The composite substrate 1 of the present invention is a support member on which the circuit board 2 having the mounting portion 2a on which the semiconductor element 4 is mounted is mounted on the upper surface, and is a support member for supporting the circuit board 2 and the semiconductor element 4. Is efficiently dissipated to the outside via the circuit board 2. The base 1a constituting the composite base 1 has an outer shape of a substantially square or a substantially rectangle and a substantially quadrangular shape, and is composed mainly of iron such as Fe-Ni-Co alloy, Fe-Ni alloy, and SUS (stainless steel). The ingot is formed into a predetermined shape by subjecting an ingot (a lump) of, for example, an Fe-Ni-Co alloy to a conventionally known metal working method such as rolling or punching.
[0027]
In addition, the plate member 1b provided with a gap 1d between the inside of the through hole of the base 1a and the inner surface of the through hole is made of copper (Cu), Cu-zinc (Zn) alloy, Cu-tungsten (W) alloy, or the like. Made of a copper alloy containing copper as a main component. The outer shape of the plate member 1b is roughly formed by, for example, rolling or punching a copper plate, and then a convex portion 1e having a predetermined thickness and width is formed on a side surface of the copper plate by an etching method. Is done. The projection 1e is formed by etching the copper plate from the upper main surface side. The size of the plate member 1 b varies depending on the area of the semiconductor element 4, but the size of the gap 1 d does not vary depending on the area of the semiconductor element 4.
[0028]
A plurality of protrusions 1e are provided at substantially equal intervals on the side surface of the plate member 1b, and the plate member 1b is joined to the base 1a by brazing the front end surface to the inner surface 1c of the base 1a. By joining the plate member 1b to the through hole of the base 1a with the projection 1e, the plate member 1b can be securely brazed to the through hole and the upper and lower main surfaces of the plate member 1b and the upper and lower surfaces of the base 1a are substantially flush. Can be held. As a result, stable heat dissipation of the base 1a is obtained, and the semiconductor element 4 can be mounted on the upper surface of the base 1a with high reliability over a long period of time.
[0029]
Further, the thickness of the projection 1e is set to １ ／ to の of the thickness of the plate member 1b, and the width of the projection 1e is set to １ ／ to の of the thickness of the plate member 1b. The rigidity of the convex portion 1e is not too small or too large. As a result, there is no occurrence of undulation in the plate member 1b or a problem that the convex portion 1e is deformed by stress.
[0030]
When the thickness of the projection 1e is less than 1/4 of the thickness of the plate member 1b, or when the width of the projection 1e is less than 1/4 of the thickness of the plate member 1b, the rigidity of the projection 1e is reduced. When the plate member 1b becomes smaller and a stress or an external force is applied to the plate member 1b, deformation such as bending or bending near the base of the convex portion 1e easily occurs. Further, even if the thickness of the projection 1e is １ ／ to の of the thickness of the plate member 1b, if the width of the projection 1e is less than １ ／ of the thickness of the plate member 1b, the projection is When the rigidity of 1e decreases and a stress or an external force is applied to the plate member 1b, deformation such as bending or bending near the base of the convex portion 1e is likely to occur.
[0031]
If the thickness of the projection 1e exceeds １ ／ of the thickness of the plate member 1b and the width of the projection 1e exceeds １ ／ of the thickness of the plate member 1b, the composite due to heat of the semiconductor element 4 or the like. When the base 1 is heated, undulation and warpage are generated in the plate member 1b, and cracks and the like are easily generated in the circuit board 2 due to undulation and warpage of the plate member 1b because the rigidity of the projection 1e is large. That is, if the stiffness of the convex portion 1e is appropriate, even if undulation or warpage of the plate member 1b occurs, the convex portion 1e can be deformed so as to reduce and cancel the undulation or warpage. Although the influence on the circuit board 2 can be suppressed, the thickness of the convex portion 1e exceeds 1/2 of the thickness of the plate member 1b, and the width of the convex portion 1e is 1/2 of the thickness of the plate member 1b. Is exceeded, the effect of suppressing the influence on the circuit board 2 due to the undulation or warpage of the plate member 1b is reduced.
[0032]
Further, it is necessary to provide a plurality of convex portions 1e on the side surface of the plate member 1b at substantially equal intervals. Thus, the plate member 1b can be firmly joined to the base 1a, and the plate member 1b can be prevented from shifting in the vertical direction. In addition, it was confirmed that, for example, when the protrusions 1e were provided at three places, even if a large external force was applied to the plate member 1b, the positional displacement hardly occurred. When the protrusions 1e are provided at two places, the positions may be two opposing corners, two opposing sides, or one side of the plate member 1b and one side substantially opposing the corner of the plate member 1b. In all cases, good results were obtained.
[0033]
The composite substrate 1 of the present invention has, on its surface, a metal having excellent corrosion resistance and excellent wettability with a brazing material, specifically a Ni layer having a thickness of 0.5 to 9 μm and an Au layer having a thickness of 0.5 to 5 μm. The layers are preferably sequentially applied by plating, so that the composite substrate 1 can be effectively prevented from being oxidized and corroded, and the circuit board 2 can be firmly adhered and fixed on the composite substrate 1.
[0034]
On the upper surface of the base 1a constituting the composite base 1, there is formed a mounting portion 3a formed of a through hole or a cutout for fitting the input / output terminal 3b to a side portion so as to surround the circuit board 2. The frame 3 thus formed is joined with a brazing material such as silver brazing, and a space for accommodating the semiconductor element 4 is formed inside the frame 3. The frame 3 is made of the same metal as the substrate 1a and forms the side wall of the semiconductor package A. The frame 3 is manufactured by the same metal working method as the substrate 1a so as to have the mounting portion 3a on the side. It is done.
[0035]
The joining of the frame body 3 to the base body 1a of the composite base 1 is performed by a preform having an appropriate volume in which the outer peripheral portion of the upper surface of the base body 1a and the lower surface of the frame body 3 are laid on the outer peripheral portion of the upper surface of the base body 1a. This is performed through a brazing material such as silver brazing. A metal layer such as a Ni layer having a thickness of 0.5 to 9 μm and an Au layer having a thickness of 0.5 to 5 μm is applied to the surface of the frame 3 by plating in the same manner as the composite substrate 1. good.
[0036]
An input / output terminal 3b for inputting / outputting a high-frequency signal between the semiconductor element 4 and an external electric circuit and for shutting off the inside and outside of the semiconductor package A is provided on a side surface of the attachment portion 3a of the frame 3. With a brazing material such as silver brazing via the metallized layer. The input / output terminal 3a has a structure in which a standing quadrangular prism-shaped wall portion is stacked on the upper surface of a substantially rectangular flat plate portion such as a substantially rectangular shape.
[0037]
The circuit board 2 of the present invention is made of Al 2 O 3 It is made of a porous sintered body or the like, and its shape is, for example, a substantially square shape. This circuit board 2 is manufactured as follows. First, Al 2 O 3 , Silicon oxide (SiO 2 ), Magnesium oxide (MgO), calcium oxide (CaO), and other suitable raw materials, and an appropriate organic binder, an organic solvent, a plasticizer, a dispersant, and the like are added and mixed to form a slurry. Thus, a plurality of ceramic green sheets are obtained.
[0038]
Next, the ceramic green sheet is subjected to an appropriate punching process, and tungsten (W), molybdenum (Mo), manganese (Mn), copper (Cu), silver (Ag), nickel (Ni), and palladium (Pd). And a metal paste such as gold (Au) mixed with an appropriate binder and a solvent. The conductor paste is printed and applied in a predetermined pattern on a ceramic green sheet by a screen printing method or the like in advance so that the wiring conductor 2b and the metallized layer 2c are formed. Are formed respectively. After that, the ceramic green sheets are laminated in a predetermined order, cut into a predetermined size, and finally fired at a temperature of about 1600 ° C., whereby the circuit board 2 is manufactured.
[0039]
Further, the circuit board 2 may have the wiring conductor 2b in the inner layer by a ceramic green sheet laminating method. Since the metallized layer 2c is formed on the lower surface of the circuit board 2, the circuit board 2 slightly warps due to a slight difference in shrinkage ratio and shrinkage behavior between the ceramic green sheet and the metallized layer 2c.
[0040]
Also, a metal having good conductivity, good corrosion resistance and good wettability with the brazing material, for example, a Ni plating layer having a thickness of 0.5 to 9 μm is applied to the surfaces of the wiring conductor 2b and the metallized layer 2c. It is possible to effectively prevent oxidative corrosion of the wiring conductor 2b and the metallized layer 2c, and to easily and firmly braze the metallized layer 2c and the plate member 1b.
[0041]
In the present invention, as shown in FIGS. 1 and 3, the gap 1d between the inner surface of the through hole of the base 1a and the side surface of the plate member 1b is 0.5 to 2 mm. If it is less than 0.5 mm, when the projection 1e is brazed to the through hole, the entire gap 1d is filled with a thin brazing material, and the thermal expansion of the plate member 1b is suppressed to some extent by the circuit board 2. The stress generated at the time of thermal expansion and contraction of the member 1b directly acts on the thin brazing material, and as a result, cracks are generated in the brazing material, and the airtightness of the semiconductor package A is easily deteriorated. On the other hand, if the gap 1d exceeds 2 mm, the bonding area between the base 1a and the circuit board 2 becomes small, and if cracks or cracks occur in the brazing portion on the base 1a side, the airtightness tends to be easily lost.
[0042]
In such a semiconductor package A, the semiconductor element 4 is mounted and fixed on the mounting portion 2a with a low melting point brazing material such as tin (Sn) -lead (Pb) solder, and the wiring conductor 2b and the semiconductor element 4 are bonded. The product is formed by electrically connecting with a wire or the like, electrically connecting the wiring conductor 2b and the input / output terminal 3b with a bonding wire, and finally joining the lid 6 to the upper surface of the frame 3 by seam welding. As a semiconductor device. This semiconductor device is used, for example, as a communication device that operates the semiconductor element 4 by a driving signal such as a high-frequency signal supplied from an external electric circuit and transmits large-capacity information at high speed.
[0043]
【Example】
Embodiments of a semiconductor package and a semiconductor device according to the present invention will be described below.
[0044]
First, the composite substrate 1 shown in FIGS. 1 and 2 was configured as follows. A frame-shaped base 1a made of an Fe-Ni-Co alloy having an outer dimension of 20 mm in length x 20 mm in width x 1 mm in thickness, having a through hole in the center and a width of 4 mm in the frame was prepared. And, as the plate member 1b attached to the through hole of the base 1a, a plate member made of copper having a shape corresponding to the through hole was prepared. Protrusions 1e each having a thickness of 0.4 mm and a width of 0.4 mm were formed at two opposing corners of the plate member 1b by an etching method. At this time, five pieces each were produced such that the gap 1d had nine values (Table 1).
[0045]
In addition, 45 circuit boards 2 each having a length of 16 mm, a width of 16 mm, and a thickness of 0.635 mm, in which wiring conductors 2b are provided on the inner layer and the upper surface and a metallization layer 2c is provided on the lower surface in advance (9 gaps × 5 = 45) are produced. Then, the lower surface was brazed to the upper main surface of the plate member 1b and the upper surface of the base 1a, and provided on the composite base 1. At this time, the width of the brazed portion on the lower surface of the circuit board 2 on the upper surface of the base 1a was set to 2 mm, and cracks and airtightness of the brazed portion were examined. Table 1 shows the results.
[0046]
[Table 1]
[0047]
According to Table 1, when the gap 1d is 0.5 to 2 mm, no crack is observed in the brazed portion between the plate member 1b and the base 1a, and the airtightness in the brazed portion between the base 1a and the circuit board 2 is obtained. Was good, and the effectiveness of the present invention was confirmed.
[0048]
Next, the gap 1d was set to 1 mm, and the thickness and width of the protrusion 1e were set to various values (Table 2), and five pieces were produced for each type. Regarding these, the deformation of the convex portion 1e and the deformation of the plate member 1b such as warpage and undulation were examined. Table 2 shows the results.
[0049]
[Table 2]
[0050]
From Table 2, the thickness of the projection 1e is 1/4 (0.25 mm) to 1/2 (0.5 mm) of the thickness (1 mm) of the plate member 1b, and the width of the projection 1e is When the thickness was 1/4 (0.25 mm) to 1/2 (0.5 mm), the deformation of the projection 1e did not occur, confirming the effectiveness of the present invention. The test results were the same when the thickness of the composite substrate 1, that is, the thickness of the plate member 1b was appropriately changed within a range normally used.
[0051]
It should be noted that the present invention is not limited to the above-described embodiments and examples, and various changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the semiconductor element is described as an FET or the like, but this may be an optical semiconductor element such as a semiconductor laser or a photodiode, in which case an optical fiber is attached to the side of the frame 3. Is formed.
[0052]
【The invention's effect】
The package for housing a semiconductor element of the present invention comprises a frame-shaped base made of an iron alloy containing iron as a main component having a through-hole formed in the center portion, and copper or copper attached to the through-hole of the base as a main component. A circuit board having a plate member made of a copper alloy and a mounting portion on which a semiconductor element is mounted on the upper surface, the lower surface being joined to the entire upper main surface of the plate member and to the upper surface of a base body surrounding the upper main surface A frame attached to the outer peripheral portion of the upper surface of the base so as to surround the circuit board; a mounting portion for an input / output terminal comprising a through hole or a cutout formed in a side portion of the frame; The plate member is inserted into the through-hole of the base with a gap of 0.5 to 2 mm, and a plurality of convex portions formed at substantially equal intervals on the lower side of the side surface. Is attached to the through hole by brazing to the inner surface of the through hole. The substrate with airtightness of the semiconductor device housing package is held is assumed to be well radiate heat of the semiconductor element. That is, since the area of the upper main surface of the plate member is reduced, the influence of the thermal expansion and contraction of the plate member on the circuit board is reduced, and the occurrence of cracks in the circuit board can be suppressed. Further, since no brazing material is required for attaching the plate member to the through-hole, cracks in the brazing material, which have occurred in the conventional package for housing semiconductor elements, can be eliminated. The airtightness of the storage package is maintained, and the heat of the semiconductor element can be radiated well.
[0053]
In the semiconductor element housing package of the present invention, preferably, the convex portion of the plate member has a thickness of 1/4 to 1/2 of the thickness of the plate member and a width of 1/4 to 1/2 of the thickness of the plate member. Since the thickness is set to 4 to 1/2, the rigidity of the convex portion is maintained, the plate member can be securely brazed to the through hole, and the upper and lower main surfaces of the plate member and the upper and lower surfaces of the base are maintained substantially flush. can do. As a result, stable heat dissipation of the base is obtained, and the semiconductor element can be mounted on the upper surface of the base with high reliability over a long period of time. Further, the grounding property of the semiconductor element by the plate member is stabilized, and a semiconductor element housing package in which transmission loss of a high-frequency signal is improved can be provided.
[0054]
The semiconductor device of the present invention is joined to the semiconductor device housing package of the present invention, a semiconductor element mounted and fixed on the mounting portion and electrically connected to the input / output terminals, and an upper surface of the frame. By providing the lid, the semiconductor device having the above-described effects of the present invention can be operated normally and stably for a long time with high reliability.
[Brief description of the drawings]
1A and 1B show an example of an embodiment of a package for housing a semiconductor element of the present invention, wherein FIG. 1A is a plan view of the package for housing a semiconductor element, and FIG. 1B is a cross-sectional view taken along line XX ′ of FIG. It is.
FIG. 2 is an enlarged sectional view of a main part showing a projection of a plate member in the package for housing a semiconductor element of FIG. 1;
FIG. 3 is a cross-sectional view showing an example of a conventional semiconductor element storage package.
FIG. 4 is a cross-sectional view showing another example of a conventional semiconductor element storage package.
[Explanation of symbols]
1: Composite substrate
1a: Substrate
1b: plate member
1c: Inner surface of through hole
1d: gap
1e: convex part
2: Circuit board
2a: mounting part
3: Frame
3a: Input / output terminal mounting part
3b: input / output terminal
4: Semiconductor element
A: Package for semiconductor device storage
B: Semiconductor device
