JP2004112241A - Lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an LSI for control that can automatically write an initial value to a universal LSI when power is turned on even without going through CPUs. <P>SOLUTION: There are three registers where it is necessary to perform setting to an external universal LSI as an initial value. A state machine control procedure controls the output of an initial setting value to the universal LSI from a register 3 for setting an automatic initial value in the LSI for control. An internal counter 2 becomes 0, and an address and data stored in an address (000) of the register 3 are outputted as a state 1 when the power of the LSI for control is turned on. Writing the data to the universal LSI (not illustrated) counts up the internal counter 2 by a transmission completion flag for advancing to a state 2. Data of an initial value setting resister address where an address outputted in the state 1 are incremented by one each till a state 3, and END is reached by outputting for three times to reach a state 4, thus completing the setting of the initial value to the universal LSI. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an LSI such as a control LSI used in an LSI control scanner, digital PPC, digital facsimile, and the like.
[0002]
[Prior art]
In a general-purpose LSI having a recorder (hereinafter referred to as a register) for writing data from the outside in the LSI, data may be written to the register at the time of initial setting to operate the LSI. This makes it possible to set a set value which is usually fixed inside a general-purpose LSI from the outside by providing a register.
With such a structure, even if the set value is changed due to a change in the system, it can be dealt with by changing the set value of the register from outside.
[0003]
As a method of externally setting data in a register, the above-described general-purpose LSI generally has a serial or parallel interface, and writes data externally. This method uses an LSI having a peripheral device control function (hereinafter referred to as a control LSI). After the CPU writes an initial setting value of the general-purpose LSI to a register in the control LSI, the CPU sets the initial setting value. Is written in a general-purpose LSI register in some cases.
[0004]
FIG. 14 shows the configuration of a general-purpose LSI control system.
In the figure, the CPU writes an initial setting value for writing to the register 1 of the general-purpose LSI into the register of the control LSI through a serial or parallel interface. The control LSI performs parallel / serial conversion of the initial setting value written in the register 1 and writes it into a register of a general-purpose LSI via a serial interface or as parallel data via a parallel interface.
[0005]
These operations are performed when the CPU, the control LSI, and the general-purpose LSI are turned on, and the initial setting values are set by software control from the CPU, so that the CPU does not transmit the initial setting values. In each of the registers of the control LSI and the general-purpose LSI, a unique initial value of the LSI itself is set, and each LSI operates according to the set value.
[0006]
FIG. 15 shows an example of the above system (for example, see Patent Document 1).
In FIG. 15, the output of the even-numbered stage and the output of the odd-numbered stage of the shift register 16 for taking in the system clock set or reset the flip-flop 21 via the OR circuits 23 and 24. The counter 22 inputs a signal having an opposite phase to the output of the flip-flop 21. The WR signal input from the outside and the output of the flip-flop 21 are selectively read into the register 25 in the LSI according to the state of the automatic read setting signal.
[0007]
[Patent Document 1]
JP-A-5-143752
[Problems to be solved by the invention]
However, when a serial or parallel interface via a CPU is used to write the initial setting values of a general-purpose LSI as described above, it is necessary to intervene control software for the CPU. Can not be set. Further, when the general-purpose LSI is an LSI having an analog function, there is a problem that it may be necessary to secure time until the analog output is stabilized.
Further, in a system in which the power of the general-purpose LSI is turned on before the CPU sets the initial value, the general-purpose LSI may output an analog signal different from a target value, thereby causing a problem to the system. was there.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a control LSI capable of setting an initial value corresponding to an arbitrary general-purpose device without using a CPU.
[0010]
[Means for Solving the Problems]
To achieve the above object, a control LSI according to the present invention counts a first register for storing one or more initial setting values of a general-purpose LSI, and counts the number of initial setting values stored in the first register. Control means for controlling the output of the initial setting value from the first register to the general-purpose LSI by performing state machine control using a counter which performs the operation.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment, and is a block diagram showing an automatic initial setting value output unit in a control LSI for automatically writing an initial value to a general-purpose LSI when power is turned on without using a CPU. FIG. This embodiment corresponds to claims 1 and 2.
In FIG. 1, the control LSI includes a power-on initial detection circuit 1 having an internal counter 2 and a register 3 for automatic initial value setting.
[0012]
The automatic initial value setting register 3 stores an initial setting value of a general-purpose LSI (not shown) which is a target of the control LSI. The power-on initial detection circuit 1 receives a system clock SYSCLK and a reset signal RST, and outputs predetermined signals shown in the figure.
[0013]
FIG. 2 is a diagram showing the configuration of the register 3 for automatic initial value setting.
Assuming that there are three registers that need to be set as initial values in the general-purpose LSI, the initial setting values (address + data) of the target general-purpose LSI are stored from (000) to (010) as shown in the figure. .
[0014]
FIG. 3 is a flowchart showing a state machine control procedure for controlling the output of the initial setting value from the register 3 for automatic initial value setting in the control LSI.
When the power of the control LSI is turned on, the initial value of the internal counter becomes 0, and the address and data stored in the address (000) of the automatic initial value setting register are output as state 1. When this data is written to the general-purpose LSI, the internal counter 2 is counted up by the transmission completion flag signal INI_WR_Flg, and the process proceeds to state 2. Until the state 3, the data of the initial value setting register address which is incremented by one from the address output in the state 1 is output. When the data is output three times and the state 4 is reached, the state becomes END, and the setting of the initial value in the general-purpose LSI is completed. .
[0015]
FIG. 4 shows a second embodiment, and is a block diagram of an automatic initial setting value output unit in a control LSI that automatically writes an initial value to a general-purpose LSI when power is turned on without using a CPU. The same reference numerals are given to portions corresponding to those in FIG. 1 and duplicate description will be omitted. This embodiment corresponds to claims 3, 4, and 5.
[0016]
In this embodiment, as shown, a configuration register 4 having initial value selection terminals A and B and an ON / OFF terminal 5 for selecting whether or not to set an initial value in a general-purpose LSI is provided. The register 4 is connected to the power-on initial detection circuit 1.
[0017]
According to the above configuration, it is possible to select initial values of a plurality of general-purpose LSIs and not to set initial values.
The automatic initial value setting register 3 stores initial values of a plurality of general-purpose LSIs which are targets of the control LSI. The selection of which of the general-purpose LSIs to output the initial value is performed by the initial value selection terminals A and B of the configuration register 4.
[0018]
Assume that there are two types of target general-purpose LSIs, LSI1 and LSI2, and there are three registers that need to be set as initial values in the general-purpose LSI. FIG. 5 is a diagram showing the configuration of the automatic initial value setting register 3 in that case.
As shown, the initial setting value (address + data) of LSI1 is stored from (000) to (010), and the initial setting value (address + data) of LSI2 is stored from (011) to (110).
[0019]
FIG. 6 is a flowchart showing a state machine control procedure for outputting the initial setting value of the LSI 2 from the automatic initial value setting register 3 in the control LSI.
If the initial value setting terminals A and B of the configuration register 4 are selected as [terminal A: 0, terminal B: 0] as the initial address corresponding to the terminal logic, the initial value of the LSI 1 is selected and output. Then, the address and data stored in the address (000) of the automatic initial value setting register 3 are output as state 1. If A and B are selected as [terminal A: 0, terminal B: 1], the initial value of the LSI 2 is selected and output and stored in the address (011) of the register 3 for automatic initial value setting. The output address and data are output as state 1.
For example, if the initial value setting terminals A and B of the configuration register 4 are selected as [terminal A: 0, terminal B: 1], the initial value of the LSI 2 is selected and output, and the automatic initial value setting is performed. The address and data stored in the address (011) of the register 3 are output as state 1. When this data is written to the general-purpose LSI 2, the internal counter 2 is counted up by the transmission completion flag signal INI_WR_Flg, and the process proceeds to state 2. Until the state 3, the data at the address incremented by one from the address output in the state 1 is output. When the data is output three times and the state 4 is reached, the state becomes END, and the setting of the initial value in the general-purpose LSI 2 is completed.
[0020]
In the above description, FIG. 7 shows the timing of each signal when the I / F format written in the general-purpose LSI is a serial I / F as an example. In the figure, SDCLK is a clock for writing data to the general-purpose LSI, DIN is data for writing to the general-purpose LSI, and XSEN is a chip selection signal of the general-purpose LSI.
[0021]
Next, the operation of writing the initial value to the general-purpose LSI when the initial value of the general-purpose LSI is output from the register 3 for automatic initial value setting and when the initial value is output from the CPU will be described.
(1) When the initial value of the general-purpose LSI is output from the automatic initial value setting register 3.
(1-1) The initial values of the target general-purpose LSI are determined by the initial value selection terminals A and B.
[0022]
In the block diagram of the initial setting value output unit shown in FIG. 4, RST is a reset signal from a reset IC outside the control LSI, SYSCLK is a system clock, and LM_INI_DAT [14: 0] is an automatic initial value setting register output. Yes, INI_WR is a Write signal at the time of automatic initial value setting, INI_CS is a chip select signal at the time of automatic initial value setting, LM_INI is an automatic initial value setting period signal (High during the setting period), and INI_WR_Flg is an initial value. This is a transmission completion flag signal.
[0023]
(1-2) When the signals RST and SYSCLK are input to the power-on initial detection circuit 1 while the power is on, the power-on initial detection circuit 1 enters state 1 and corresponds to the terminal logic determined by (1-1). The initial value of the internal counter 2 is determined. The output value of the internal counter 2 is connected to the register 3 for automatic initial value setting, and the register data decoded by the counter output is output as LM_INI_DAT [14: 0].
(1-3) The power-on initial detection circuit 1 generates INI_WR, INI_CS, and LM_INI from SYSCLK.
[0024]
(1-4) INI_WR and INI_CS are input to the timing generator 6 in FIG. 8 together with SYSCLK. The timing generator 6 generates SDCLK, XSEN, INI_WR_Flg, and WR_SEL from the input signal. Here, SDCLK is a data write to the general-purpose LSI and a shift clock of the shift register, CS is a chip select signal when the initial value of the general-purpose LSI is output from the CPU, and WR is an initial value of the general-purpose LSI from the CPU. This is a Write signal for output, INI_WR_Flg is an initial value transmission completion flag signal, and XSEN is a chip select of a general-purpose LSI.
[0025]
For WR_SEL, in the Read / Write determination unit 7 in FIG. 9, the selector B selects Read / Write in the Low period, and outputs the Read / Write signal selected up to the next Low level input from the flip-flop FF as LM_DAT [14]. Things.
[0026]
FIG. 10 shows a timing chart of the timing generator 6.
In FIG. 10, since the CPU is not used for setting the initial value of the general-purpose LSI, CS and WR are always at the Low level. LD rises at the next SYSCLK after INI_CS falls, and is output to the shift register 9 of the parallel / serial converter 8 in FIG. SDCLK is generated from XSEN and a clock obtained by dividing SYSCLK by 2 in the timing generator 6, and is output to the parallel / serial converter 8 of the control LSI and the serial data input register of the general-purpose LSI. In the present embodiment, SYSCLK is divided by two, but another divided clock may be used.
[0027]
Further, INI_WR_Flg rises at the next SYSCLK か ら after XSEN rises, and LM_INI and AND are taken and output to the internal counter 2 of the initial set value output unit. Since the LM_INI becomes “L” other than the initial setting operation, the internal counter 2 does not count up.
[0028]
(1-5) Next, the serial / parallel converter 8 for writing the output initial value to a general-purpose LSI will be described with reference to FIGS.
In FIGS. 10 and 11, LD is a signal for loading the selector output into the internal register of the shift register 9, and SDOUT is general-purpose LSI setting serial data.
[0029]
(1-6) The data LM_INI_DAT [14: 0] output from the automatic initial value setting register 3 is input to the selector A.
(1-7) The output of the selector A is connected to the data input terminal of the shift register 9. When the LD signal generated from the INI_WR and INI_CS by the timing generation unit 6 is input to the shift register 9, LM_INI is set to “H”, so that LM_INI_DAT [14: 0] is selected and the initial state of the general-purpose LSI is initialized. The value data is loaded into the shift register 9.
[0030]
(1-8) The shifted initial value of the general-purpose LSI is written into the register of the general-purpose LSI as the serial signal SDOUT in the shift register 9 by the SDCLK generated from XSEN and SYSCLK by the timing generation unit 6.
(1-9) The transmission completion flag signal INI_WR_Flg is output from the timing generator 6 at the timing shown in FIG.
[0031]
(1-10) INI_WR_Flg is ANDed with LM_INI as shown in FIG. LM_INI is a signal which becomes H during the automatic initialization period. Since it becomes L except H, the internal counter 2 does not count up except for the automatic initialization. Therefore, here, since LM_INI is “H”, the internal counter 2 of the power-on initial detection circuit 1 advances by one at the rise of INI_WR_Flg, and the state of the power-on initial detection circuit 1 advances by one. The data selected by the counter decode is output from the register 3.
[0032]
(1-11) Thereafter, the operations from (1-2) to (1-10) are repeated for the number of times required for setting the initial value of the general-purpose register, and when all the initial settings are completed, the state becomes END in the next state. Initial value setting is completed.
[0033]
(2) When the initial value of the general-purpose LSI is output from the CPU.
(2-1) Initial value setting By fixing the ON / OFF terminal 5 to L, the initial value of the general-purpose LSI can be output from the CPU without performing automatic initial value setting.
[0034]
(2-2) FIG. 12 shows the CPU interface 30 of the control LSI. LM_DAT [13: 0], WR, and CS are input from the CPU to the control LSI via the CPU interface 30.
In FIG. 12, LM_DAT [13: 0] is initial setting value data, CS is a chip select signal for outputting the initial value of the general-purpose LSI from the CPU, and WR outputs the initial value of the general-purpose LSI from the CPU. Write signal in this case.
[0035]
(2-3) WR and CS are input to the timing generator 6 in FIG. 8 together with SYSCLK. The timing generator 6 generates SDCLK, XSEN, INI_WR_Flg, and WR_SEL from the input clock.
[0036]
FIG. 13 shows a timing chart of the timing generator 6.
FIG. 13 shows the timing when the automatic initial value setting register of the general-purpose LSI is not used. INI_CS and INI_WR are always at the low level. The LD rises at the next SYSCLK after CS falls, and is output to the parallel / serial conversion unit 8 in FIG. SDCLK is generated from XSEN and a clock obtained by dividing SYSCLK by 2 in the timing generator 6, and is output to the parallel / serial converter 8 of the control LSI and the serial data input register of the general-purpose LSI.
[0037]
In the present embodiment, SYSCLK is divided by two, but another divided clock may be used. Further, INI_WR_Flg rises at the next SYSCLK か ら after XSEN rises, and LM_INI and AND are taken and output to the internal counter 2 of the initial set value output unit. Since the LM_INI becomes “L” other than the initial setting operation, the internal counter 2 does not count up.
[0038]
(2-4) FIG. 9 shows a block diagram and timing of the read / write determination unit 7. As shown in FIG. 7, LM_DAT [14] is data for controlling the operation of the Read if it is 1 and the Write and the operation of the general-purpose LSI if it is 0.
First, in the selector B, when the WR_SEL is in the L period, the signal WR input to the L terminal of the selector B is selected. If the WR signal is “H”, “H” is output from the FF by SYSCLK. Then, LM_DAT [14] becomes 1. When WR_SEL becomes “H”, the selector B selects the output of the FF as an input, and feeds back the output of the FF to the input of the FF. As described above, LM_DAT [14] is fixed to 1 and LM_DAT [14] is output to the serial / parallel converter 8.
[0039]
(2-5) Next, the serial / parallel converter 8 for writing the output initial value to a general-purpose LSI will be described with reference to FIGS.
(2-6) The data LM_DAT [13: 0] transmitted from the CPU and the output LM_DAT [14] of the read / write determination unit 7 are input to the selector A as data LM_DAT [14: 0].
[0040]
(2-7) The output of the selector A is connected to the data input terminal of the shift register 9. When the LD signal generated from WR and CS by the timing generation unit is input to the shift register, LM_INI is set to “H”, so that LM_DAT [14: 0] is selected and the initial value data of the general-purpose LSI is The data is loaded into the shift register 9.
[0041]
(2-8) The shifted initial value of the general-purpose LSI is written to the register of the general-purpose LSI as a serial signal SDOUT by the SDCLK generated from XSEN and SYSCLK by the timing generation unit 6 in the shift register 9, and the initial value of the general-purpose LSI is initialized. The value setting ends.
[0042]
As described above, the control LSI according to the present embodiment includes a terminal for selecting an initial value of a general-purpose LSI, an ON / OFF terminal for determining whether or not to set an initial value in the general-purpose LSI, and a plurality of terminals. A register for recording an initial value of the general-purpose LSI, and an initial value output from the register for automatic initial value setting in a serial or parallel I / F format corresponding to the general-purpose LSI. It has a function of writing to an LSI, and automatically writes an initial set value to a register of a general-purpose LSI when power is turned on. As a result, it is possible to realize an initial setting data automatic reading circuit for making it possible to use an LSI adopting a bus system for writing an internal register even in a system having no CPU.
[0043]
【The invention's effect】
According to the first and second aspects of the present invention, an initial value of an arbitrary general-purpose LSI can be automatically set immediately after power-on without intervening software, so that an analog signal different from a target value is output from the general-purpose LSI. By doing so, it is possible to prevent the system from malfunctioning. Further, since the LSI can be used even in a system without a CPU, miniaturization can be achieved.
[0044]
According to the third and fifth aspects of the present invention, since one control LSI can select a plurality of LSI initial values, the control LSI itself of the present invention can have versatility.
[0045]
According to the fourth aspect of the present invention, the initial value of the general-purpose LSI included in the control LSI of the present invention can not be set. Therefore, in a system having a CPU, the initial value can be set through software and the general-purpose LSI can be set. Various usage situations can be dealt with, such as using an initial setting value specific to the LSI.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an initial setting value output unit of a control LSI according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram showing an automatic initial value setting register.
FIG. 3 is a flowchart showing a state machine control procedure.
FIG. 4 is a block diagram illustrating an initial setting value output unit of a control LSI according to a second embodiment of the present invention;
FIG. 5 is a configuration diagram showing an automatic initial value setting register.
FIG. 6 is a flowchart showing a state machine control procedure.
FIG. 7 is a timing chart showing signals when the write format of the general-purpose LSI is a serial I / F.
FIG. 8 is a block diagram of a timing generator.
FIG. 9 is a block diagram of a Read / Write determination unit and a diagram showing timing.
FIG. 10 is a timing chart showing the operation of the timing generation unit.
FIG. 11 is a block diagram of a parallel / serial converter.
FIG. 12 is a block diagram of a CPU interface.
FIG. 13 is a timing chart showing the operation of the timing generation unit.
FIG. 14 is a block diagram of a conventional initial set value output unit.
FIG. 15 is a block diagram showing an example of a conventional general-purpose LSI control system.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 Power ON initial detection circuit 2 Internal counter 3 Automatic initial value setting register 4 Configuration register 5 Initial value setting ON / OFF terminal 6 Timing generation unit 7 Read / Write determination unit 8 Parallel / serial conversion unit 9 Shift register 30 CPU Interface SYSCLK System clock LM_INI_DAT [14: 0] Automatic initial value setting register output LM_DAT [13: 0] Initial setting value data A, B Initial value setting terminals

Claims (5)

A first register for storing one or more initial setting values of the general-purpose LSI;
By performing state machine control using a counter that counts the number of the initial setting values stored in the first register, control is performed to output the initial setting value from the first register to the general-purpose LSI. An LSI comprising control means. Frequency dividing means for generating a frequency-divided clock from a system clock; and a second register for reading the initial set value from the outside, wherein the first register outputs based on the generated frequency-divided clock. 2. The LSI according to claim 1, wherein: 2. The method according to claim 1, wherein the first register stores one or more of the initial setting values for a plurality of the general-purpose LSIs, and further includes a selection unit that selects one of the general-purpose LSIs. 3. The LSI according to 1 or 2. 4. The LSI according to claim 1, further comprising switching means for switching whether or not to output the initial setting value to the general-purpose LSI. A plurality of terminals are provided for selecting one of the one or more initial setting values stored in the register and for switching whether or not to make this selection, and selectively input to the plurality of terminals. The LSI according to any one of claims 1 to 4, wherein the selection and the switching are performed according to the logic of the signal.

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