JP2003273232A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit having a configuration in which a test mode is set without providing a terminal exclusive for the test mode. <P>SOLUTION: The integrated circuit provided with an external connection terminal and a functional block for performing prescribed operation on the basis of an input signal inputted from the external connection terminal is equipped with: a first storage part for sampling and storing the input signal at a first edge of a clock signal and outputting the stored input signal as a first output signal at a second edge after the first edge; a second storage part for sampling and storing the first output signal outputted by the first storage part at the second edge and outputting the stored first output signal as a second output signal at a third edge after the second edge; and a test mode setting circuit for producing a test mode signal indicating whether or not the functional block is set to the test mode on the basis of the first and second output signals. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test facilitation technique for testing the operation and function of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art After a semiconductor integrated circuit is manufactured, for example, before shipment, a test is performed to confirm whether its operation and function are normal. The test target is all or some of the internal functional blocks that realize the functions of the semiconductor integrated circuit. A testability technique has been conventionally introduced in order to make such a test executable or to facilitate the test.

FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit 90 which employs a general test facilitation technique. The semiconductor integrated circuit 90 has a configuration in which the functional block 9 is easily shifted to the test mode. That is,
The semiconductor integrated circuit 90 has a test mode terminal independently from the external input terminal M for inputting a signal during normal operation of the semiconductor integrated circuit 90. The test mode terminal is
This is used when setting the semiconductor integrated circuit 90 to a state (test mode) in which a test can be easily executed. When a predetermined signal is applied to the test mode terminal, the semiconductor integrated circuit 90 is set to the test mode. For example, when a “1” or “high level” signal is input to the test mode terminal, the semiconductor integrated circuit 90 is set to the test mode, and a “0” or “low level” signal is input to the test mode terminal. At this time, the semiconductor integrated circuit 90 is set to the normal mode (non-test mode).

In the shipping test of the semiconductor integrated circuit 90,
The test is performed by the semiconductor integrated circuit 90 alone. When the test of the semiconductor integrated circuit 90 is completed and it is confirmed that the intended operation and function are normally realized, the semiconductor integrated circuit 90 is attached to an electric circuit board or the like and shipped as a product. At this time, the semiconductor integrated circuit 90 is set to a state in which normal operation is performed (normal mode). In the case of the above example, in the normal mode, the signal applied to the test mode terminal is fixed to be "0" or "low level".

[0005]

In recent years, there is a tendency that the number of functional terminals (pins) for connecting a chip to an external substrate or the like and for inputting / outputting data increases. This is because there is an increasing demand for the technical semiconductor integrated circuit 90 to have many functions. However, as the number of functional terminals increases, it is becoming difficult to provide a test mode terminal that is required only for testing before shipment. Therefore, there is a need for a technique for setting a semiconductor integrated circuit in a test mode without providing a test mode terminal.

An object of the present invention is to provide an integrated circuit having a configuration capable of setting a test mode without providing a terminal dedicated to the test mode.

There is also a technique for setting a test mode without using a dedicated terminal. Japanese Patent Laid-Open No. 2000-1337
In Japanese Patent No. 81, the test mode is set when each circuit block is in the reset state, and the test circuit is set in the reset state in the normal state. JP 10-2
In Japanese Patent No. 56486, a voltage higher than the power supply voltage is detected at the input terminal and the test mode is entered. JP-A-7-24412
In the publication No. 4, the test mode terminal and the reset terminal are shared. In Japanese Patent Laid-Open No. 6-309475, the test mode is set by detecting a specific power supply voltage waveform or a specific power supply voltage value that is set only during a test. In Japanese Patent Laid-Open No. 6-66899, a test mode signal is generated inside the integrated circuit at two power-on timings, and the test mode signal is transferred to the test mode signal.

According to the following embodiments of the present invention, the difference between the present invention and the above-mentioned conventional technique will be clarified.

[0009]

An integrated circuit according to the present invention is an integrated circuit having an external connection terminal and a functional block which performs a predetermined operation based on an input signal input from the external connection terminal. And sampling and storing the input signal at a first edge of the clock signal, and
At a second edge after the first edge, a first storage unit that outputs the stored input signal as a first output signal, and at the second edge, the first storage unit outputs A second output signal for sampling and storing the stored first output signal, and outputting the stored first output signal as a second output signal at a third edge after the second edge. The functional block is set to a test mode based on a storage unit, the first output signal output from the first storage unit, and the second output signal output from the second storage unit. And a test mode setting circuit that generates a test mode signal that indicates whether or not the test mode signal is present. This achieves the above object.

In the test mode setting circuit, the first output signal output from the first storage section and the second output signal output from the second storage section show different values. In this case, the test mode signal for setting the functional block to the test mode may be generated.

A clock generation unit is further provided for generating a clock signal having an edge until the predetermined time based on the clock signal and a reset signal which is inverted from an active state to an inactive state at a predetermined time, and The third edge may be an edge of the clock signal generated by the clock generation unit.

The integrated circuit includes an external connection terminal, the first
Of a plurality of storage units, the second storage unit, and the test mode setting circuit, and calculates and outputs a logical sum of each of the test mode signals output from the test mode setting circuit. A circuit may be further provided, and the output of the arithmetic circuit may indicate whether to set the functional block to the test mode.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments 1 to 3 of the present invention will be described below with reference to the accompanying drawings. Embodiment 1 is
The basic configuration and the operation thereof according to the present invention will be described, and in the second and third embodiments, modified examples of the first embodiment will be described. In the figures, elements with the same reference numerals have the same function.

(First Embodiment) FIG. 1 is a block diagram showing a structure of a semiconductor integrated circuit 10 according to a first embodiment. The semiconductor integrated circuit 10 can be used for all digital circuits, and constitutes, for example, part or all of a microcomputer, a microprocessor, and a memory circuit.

The semiconductor integrated circuit 10 is the semiconductor integrated circuit 1.
It has a functional block 9 for realizing a predetermined function of 0, an external connection terminal M, first and second memory circuits 1 and 2, and a test mode setting circuit 3. The semiconductor integrated circuit 10 is
It operates based on a clock signal CLK generated by a clock signal generation circuit (not shown). The clock signal CLK may be an input clock supplied to the semiconductor integrated circuit 10 via the external connection terminal M. When the semiconductor integrated circuit 10 is a microprocessor, the functional block 9 constitutes one or all of a logical operation circuit, a register circuit, an instruction decoder and the like. When the semiconductor integrated circuit 10 is a random access memory (RAM) circuit, the functional block 9 constitutes one or all of a plurality of memory cells, a data latch circuit, a column and a row decoder.

The external connection terminal M is connected to the functional block 9 and supplies a signal necessary for a predetermined operation of the functional block 9. That is, when the semiconductor integrated circuit 10 is set to the normal mode in which the normal operation is performed, the semiconductor integrated circuit 1
0 receives data via the external connection terminal M and supplies it to the functional block 9. When the semiconductor integrated circuit 10 is used in the normal mode, the signal input to the external connection terminal M is fixed and does not change. An example of such a signal is the pin that selects the startup program when the microcomputer is reset,
Examples include a terminal for selecting a multiplication rate when the internal clock is being accelerated by using a phase locked loop (PLL) circuit.

The main feature of the present invention is that a plurality of circuits (first memory circuit 1, second memory circuit 2, and test mode) are provided for the wiring connecting the external connection terminal M and the functional block 9. A semiconductor integrated circuit 10 is added by adding a setting circuit 3).
Is to add a function to control whether or not to shift to the test mode. That is, the semiconductor integrated circuit 10 can be shifted to the test mode according to the signal from the external connection terminal M. The test mode refers to an operation mode for testing the operation and function of the semiconductor integrated circuit 10.
Specific details will be described later with reference to FIG. In addition,
A mode other than the test mode, for example, the above-mentioned normal mode is also referred to as a non-test mode.

The first storage circuit 1 stores the state of the external input terminal M, that is, the data input to the external connection terminal M by sampling at the timing of the clock signal CLK. The first memory circuit 1 also outputs the stored data to the wiring 11 and stores the newly input data in synchronization with the next clock signal CLK. The second memory circuit 2 stores the state of the first memory circuit 1, that is, the data output from the first memory circuit 1 by sampling at the timing of the clock signal CLK. The second memory circuit 2 also receives the next clock signal CLK.
In synchronization with the above, the stored data is output to the wiring 12, and the newly input data is stored. In FIG. 1, the memory circuits 1 and 2 are described as a general flip-flop FF.

The test mode setting circuit 3 receives the data stored in each of the first memory circuit 1 and the second memory circuit 2 and generates a test mode signal. The test mode signal generated by the test mode setting circuit 3 is input to the functional block 9. Based on the input test mode signal, it is determined whether to set the functional block 9 to the test mode. More specifically, if the test mode signal indicates the level for setting the transition to the test mode, the functional block 9 of the semiconductor integrated circuit 10 is set to the test mode.

FIG. 2 is a block diagram showing a specific configuration of the test mode setting circuit 3. The test mode setting circuit 3 calculates the exclusive OR of the two data input from the two input terminals IN1 and IN2, and outputs the output terminal OU.
Output from T. In the figure, a plurality of basic logical operation elements that realize exclusive OR operation are shown. Since the basic operation of the logical operation element and the connection between the elements are obvious to those skilled in the art, the description thereof will be omitted. The specific operation of the test mode setting circuit 3 is as shown in the following truth table (Table 1).

[0021]

[Table 1]

In this way, by detecting the difference between the signal levels of the inputs IN1 and IN2, the result of the exclusive OR operation can be output to the output OUT.

FIG. 3 is a timing chart showing the operation timing of the semiconductor integrated circuit 10 (FIG. 1). It is assumed that the clock signal CLK at the uppermost stage is always applied with rising and falling edges at a constant cycle. The first memory circuit 1 and the second memory circuit 2 sample the input signal at the rising edge of the clock signal CLK. For convenience of understanding, an arrow is shown at the rising edge of the clock signal CLK. Further, times T1, T2, ... Are added at the timing of the rising edge.

The second row shows a signal input to the external input terminal M. As described above, the signal input to the external connection terminal M does not change during operation in the normal mode. But,
When the semiconductor integrated circuit is tested alone, the signal state can be changed freely. In the example of FIG. 3, times T1 and T2
Change (fall) once during. Also, at time T
From 4 onwards, it has been changing continuously.

The third row shows the output signal of the first memory circuit 1. As described above, the first memory circuit 1 samples the signal input to the external connection terminal M at the rising edge of the clock signal CLK. Therefore, the change of the signal input to the external connection terminal M appears in synchronization with the subsequent rising of the clock signal CLK.

The fourth row shows the output signal of the second memory circuit 2. The second memory circuit 2 samples the output of the first memory circuit 1 at the rising edge of the clock signal CLK.
Therefore, the output of the second memory circuit 2 is the first memory shown in the third stage.
Changes with a delay of one clock from the output of the storage circuit 1.

As described with reference to Table 1, the test mode setting circuit 3 becomes high level when the output of the first memory circuit 1 and the second memory circuit 2 are different. , In the same case, it goes low. In other words, the test mode setting circuit 3 can detect the difference between the output level of the first storage circuit 1 and the output level of the second storage circuit 2.
The “difference” here means that when one is at a high level, the other is at a low level. At the timing shown in FIG. 3, the test mode setting circuit 3 sets time T2, T5,
The difference between the two output signals is detected at T6, T7, and T8. For ease of understanding, the figure shows "Detect Differences"
Is shown. When detecting the above-mentioned difference, the test mode setting circuit 3 outputs a high-level test mode signal to shift the semiconductor integrated circuit 10 (FIG. 1) to the test mode. On the other hand, when there is no difference, that is, when both are at the high level or the low level, the test mode setting circuit 3 outputs the test mode signal at the low level. As a result, the semiconductor integrated circuit 10 (FIG. 1) is set to the non-test mode. The test mode signal is maintained at the same level for at least one clock cycle until the next rising of the clock signal CLK.

As shown in the figure, after the difference is detected at time T2, at time T3, the outputs of the first memory circuit 1 and the second memory circuit 2 both become low level and there is no difference. Therefore, the test mode signal is from time T2 to time T2.
It goes high only for 1 clock of 3 and shifts to the test mode. From time T3, the mode changes to the non-test mode.

On the other hand, when a change is continuously detected at times T5, T6, T7, and T8, the test mode signal always maintains a high level. Therefore, during that period, the semiconductor integrated circuit 10 is continuously set to the test mode.

In the example described with reference to FIGS. 1 to 3, the change in the signal input to the external input terminal M is represented by the functional block 9.
It is assumed that the operation and functions of (Fig. 1) are not affected. That is, in the example shown in FIGS. 1 to 3, it is necessary to change the input to the external connection terminal M in order to switch the operation of the semiconductor integrated circuit 10 between the test mode and the non-test mode. At that time, the change in the input to the external connection terminal M is transmitted to the functional block 9 as it is, and thereafter, the input to the external connection terminal M is changed and transmitted to the functional block 9. Therefore, it is necessary that the operation and the function of the functional block 9 do not change depending on the level of the signal input to the external connection terminal M. In fact, in a system LSI such as a microprocessor, there is a terminal that is effective only at the time of startup and does not affect the operation in any state thereafter.

For example, the semiconductor integrated circuit 10 (FIG. 1) is
Download the program from the outside to the internal memory,
Assume that it is a microprocessor that executes programs. Internal CP when multiple download sources can be selected
It is necessary to provide a terminal that specifies the download source only when U is started. During the time when the download is completed and the CPU executes the downloaded program, no matter what input is applied to the terminal that specifies the download source,
Does not affect the operation of the system. Such a terminal,
If it is used as the external connection terminal M (FIG. 1), the above-described operation can be realized.

(Embodiment 2) Embodiment 2 describes a modification of Embodiment 1.

FIG. 4 is a block diagram showing the structure of the semiconductor integrated circuit 40 according to the second embodiment. The semiconductor integrated circuit 40 is different from the semiconductor integrated circuit 10 (FIG. 1) of the first embodiment in that the semiconductor integrated circuit 40 newly includes a clock generation unit 4. In addition, the second storage circuit 2
The output signal of is input to the functional block 9 via the wiring 12. The basic function of the other configuration of the semiconductor integrated circuit 40 is the same as that of the semiconductor integrated circuit 10 (FIG. 1). Therefore, their description is omitted here.

The clock generation section 4 has a reset signal RST.
And a clock signal for the storage device (hereinafter, referred to as "clock signal for the storage device") based on the clock signal CLK. The reset signal RST is a signal that resets the functional block 9 and further resets the entire system of the semiconductor integrated circuit 40. Here, when the reset signal RST is "1" or "high level" (that is, active state), the entire system is in the reset state, and when the reset signal RST is "0" or "low level" (that is, inactive state), reset release It is in a state. The clock generation unit 4 receives the reset signal RST and the clock signal CLK as described above, generates a clock signal for the storage device, and outputs the clock signal to the wiring 13.

The second memory circuit 2 is connected via the wiring 13 to
A clock signal for a storage device is received from the clock generation unit 4. The second memory circuit 2 samples and stores the data output from the first memory circuit 1 at the timing of the memory device clock signal.

FIG. 5 is a block diagram showing the configuration of the clock generator 4. As is clear from the figure, the clock generation unit 4 calculates the logical product of the signals input to the two input terminals IN1 and IN2, and outputs the logical product from the output terminal OUT. The specific operation of the test mode setting circuit 3 is as shown in the following truth table (Table 2).

[0037]

[Table 2]

As is clear from Table 2, the input terminal IN1
When the reset signal RST input to is “1”,
The clock generation unit 4 outputs the same clock signal as the clock signal CLK input to the input terminal IN2. on the other hand,
When the reset signal RST is “0”, the output of the clock generator 4 is fixed at “0”.

FIG. 6 is a timing chart showing the operation timing of the semiconductor integrated circuit 40 (FIG. 4). The highest stage is the clock signal CLK, which is the same as the clock signal CLK shown in FIG. The first memory circuit 1 and the second memory circuit 2 sample the input signal at the rising edge of the clock signal CLK.

The second stage shows the reset signal RST. The state of the reset signal RST is inverted between times T3 and T4. That is, until the time 3T, the reset state,
After time 4T, the reset is released.

The third row shows a signal input to the external connection terminal M.

The fourth row shows the output signal of the first memory circuit 1.

The fifth row shows the output of the clock generator 4, that is, the clock signal for the storage device. As mentioned above,
The clock generation unit 4 generates the storage device clock signal only when the reset signal RST is “1”. Therefore, in the clock signal for the memory device, the reset signal RST is “1”.
It becomes "1" only between time T3 and T4.

The sixth stage shows the output of the second memory circuit 2. The second storage circuit 2 samples the output of the first storage circuit 1 at the rising edge of the storage device clock signal generated by the clock generation unit 4. Since the output of the first memory circuit 1 changes to the low level at time T2,
The output of the memory circuit 2 of FIG.
At 3, it changes to low level. On the other hand, after time T4, the storage device clock signal does not rise, so that even if the output of the first storage circuit 1 changes, the output of the second storage circuit 2 does not change.

The test mode setting circuit 3 can detect the difference between the output level of the first storage circuit 1 and the output level of the second storage circuit 2. Therefore, the test mode setting circuit 3
At time T2, T5, T7, the difference between the two is detected,
A test mode signal that changes at that time is generated. Since the second storage circuit 2 does not sample the output of the first storage circuit 1 after time T4, the output of the second storage circuit 2 is fixed to "0". Therefore, while the output of the first memory circuit 1 is "1", the difference is detected and the test mode signal of "1" for setting the semiconductor integrated circuit 40 in the test mode is generated. On the contrary, while the output of the first memory circuit 1 is "0", the test mode signal of "0" which sets the semiconductor integrated circuit 40 to the non-test mode is generated. As shown in FIG. 4, in the semiconductor integrated circuit 40, the wiring 12 is used to transmit the input signal to the external connection terminal M to the functional block 9. Therefore, the contents transmitted to the block are fixed after the reset is released.

For example, as illustrated at the end of the first embodiment, it is assumed that the semiconductor integrated circuit 40 is a microprocessor that downloads a program from the outside to an internal memory and executes the program. At this time, when a plurality of download sources can be selected, if the terminal for designating the download source only when the internal CPU is started up is the external connection terminal M, for example, when it is "0", it is downloaded from the external ROM, and when it is "1", it is serial. Download from communication I / F. The download source is determined by the state of the signal applied to the external connection terminal M when the reset is released, and is fixed after the release.

(Third Embodiment) A third embodiment will be described as a modification of the first embodiment.

FIG. 7 is a block diagram showing a structure of a semiconductor integrated circuit 70 according to the third embodiment. The semiconductor integrated circuit 70 includes two external connection terminals Ma and Mb and first storage circuits 1a and 1b corresponding to the external connection terminals Ma and Mb.
, Second memory circuits 2a and 2b, and test mode setting circuits 3a and 3b. External connection terminal M
a, the first memory circuit 1a, the second memory circuit 2a, and the test mode setting circuit 3a are configured and connected by the external connection terminal M, the first memory circuit 1, and the second memory circuit shown in FIG. 2. The configuration and connection of the test mode setting circuit 3 are the same. Similarly, the external connection terminal Mb, the first memory circuit 1b, the second memory circuit 2b, and the test mode setting circuit 3b are configured and connected in the same manner as the external connection terminal M and the first memory circuit 1 shown in FIG. The second memory circuit 2 and the test mode setting circuit 3 have the same configurations and connections. Therefore, description of each component is omitted.

The semiconductor integrated circuit 70 further receives the output 14a of the test mode setting circuit 3a and the output 14b of the test mode setting circuit 3b and performs an OR operation.
It has a gate 5. In the semiconductor integrated circuit 70, OR
The output of the gate 5 is input to the functional block 9 as a test mode signal.

FIG. 8 is a timing chart showing the operation timing of the semiconductor integrated circuit 70 (FIG. 7). The highest stage is the clock signal CLK, which is the same as the clock signal CLK shown in FIG. The first memory circuit 1 and the second memory circuit 2 sample the input signal at the rising edge of the clock signal CLK.

In the second stage, a signal input to the external connection terminal Ma and a signal input to the external connection terminal Mb are represented by 2 bits.

The third row shows the signal 11a output from the first storage circuit 1a and the signal 11b output from the first storage circuit 1b in 2-bit notation.

The fourth row shows the signal 12a output from the second memory circuit 2a and the signal 12b output from the second memory circuit 2b in 2-bit notation.

The fifth stage shows the signal 14a output from the test mode setting circuit 3a and the signal 14b output from the test mode setting circuit 3b in 2-bit notation.

As described above, the test mode signal is obtained as a result of the logical sum (OR) operation of the output 14a of the test mode setting circuit 3a and the output 14b of the test mode setting circuit 3b. Therefore, if either one of the outputs 14a and 14b is "1", the test mode signal becomes "1". Therefore, due to various reasons, even when a signal cannot be input to a specific external connection terminal (for example, the external connection terminal Ma) or the operation cannot be performed, a plurality of external connection terminals like the semiconductor integrated circuit 70 (FIG. 7) can be connected. If provided, the test mode can be set using any of the external connection terminals. This increases the probability of avoiding the obstacle.

FIG. 9 is a block diagram showing a structure of a modification of the semiconductor integrated circuit 71 according to the third embodiment. The semiconductor integrated circuit 71 is configured so that the semiconductor integrated circuit 70 (FIG. 7) also operates based on the reset signal RST and the clock generation unit 4. The semiconductor integrated circuit 71 is configured by combining FIG. 4 and FIG. 7, and therefore,
Each component and its operation are the same as the description of each component described in relation to the semiconductor integrated circuit 40 (FIG. 4) and the semiconductor integrated circuit 70 (FIG. 7). Here, the clock generation unit 4 uses the reset signal RST and the clock signal C.
It receives LK and outputs a memory device clock signal.
The clock signal for the storage device is used for the second storage circuits 2a and 2b.
Is input to each of. Then, the second memory circuits 2a, 2
The output of b is input to the functional block 9 via the wirings 12a and 12b, respectively.

7 to 9, an example in which two external input terminals are provided has been described. However, the external connection terminal
You may have more than one. In this case, a first memory circuit, a second memory circuit, and
It suffices to provide a test mode setting circuit and an OR gate for performing an OR operation on the output signals of all the test mode setting circuits. The output signal of the OR gate can be used as a test mode signal.

[0058]

According to the signal input to the external connection terminal, the functional block performs a predetermined operation, while it can be determined whether or not to set the functional block to the test mode. That is, the integrated circuit can be set to the test mode by operating the input state of the existing external terminal without providing the test-dedicated terminal.

Since the content of the external input terminal transmitted to the block is fixed after the reset is released, the above-described effect can be obtained even for the external terminal having a specification in which the input information should not be changed after the reset is released. .

Even if there is an environment in which a certain external connection terminal cannot be operated, since a plurality of external connection terminals are provided, the test mode can be set with one of them. Therefore, the probability that the obstacle can be avoided increases.

[0061]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a block diagram showing a specific configuration of a test mode setting circuit.

FIG. 3 is a timing chart showing the operation timing of the semiconductor integrated circuit.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment.

FIG. 5 is a block diagram showing a configuration of a clock generation unit.

FIG. 6 is a timing chart showing the operation timing of the semiconductor integrated circuit.

FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment.

FIG. 8 is a timing chart showing the operation timing of the semiconductor integrated circuit.

FIG. 9 is a block diagram showing a configuration of a modification of the semiconductor integrated circuit according to the third embodiment.

FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit adopting a general testability technique.

[Explanation of symbols]

1 First memory circuit 2 Second memory circuit 3 Test mode setting circuit 4 Clock generator 5 OR gate 9 functional blocks 10 Semiconductor integrated circuits 40 Semiconductor integrated circuit 70 Semiconductor integrated circuits

Claims (4)

[Claims] 1. An integrated circuit including an external connection terminal and a functional block that performs a predetermined operation based on an input signal input from the external connection terminal, wherein the input is provided at a first edge of a clock signal. A signal is sampled and stored, and at a second edge after the first edge, the stored input signal is
A first storage unit for outputting the first output signal output from the first storage unit at the second edge, and storing the first output signal output from the first storage unit in the second edge; A second storage unit that outputs the stored first output signal as a second output signal at a later third edge; the first output signal that the first storage unit outputs; An integrated circuit further comprising: a test mode setting circuit that generates a test mode signal indicating whether to set the functional block to a test mode based on the second output signal output from the second storage unit. circuit. 2. The test mode setting circuit comprises:
Setting the functional block to the test mode when the first output signal output from the storage unit and the second output signal output from the second storage unit show different values. The integrated circuit of claim 1, which produces a test mode signal. 3. A clock generation unit for generating a clock signal having an edge until the predetermined time based on the clock signal and a reset signal which is inverted from an active state to an inactive state at a predetermined time. The integrated circuit according to claim 1, wherein the third edge is an edge of the clock signal generated by the clock generation unit. 4. The integrated circuit has a plurality of sets of external connection terminals, the first storage section, the second storage section, and the test mode setting circuit, and is output from the test mode setting circuit. 4. The operation circuit according to claim 1, further comprising an operation circuit that calculates and outputs a logical sum of each of the test mode signals, and an output of the operation circuit indicates whether to set the functional block to a test mode. The integrated circuit described.