JP2010112883A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having the fewest terminals for a scan test as possible, and easily configuring the scan test. <P>SOLUTION: The semiconductor integrated circuit includes: an analog circuit 22 for receiving a first positive power supply voltage through a first terminal, receiving a reference voltage through a second terminal, and receiving a ground voltage through a third terminal; a logic circuit operated by a second positive power supply voltage received through a fourth terminal, selectively implementing a normal operation and a scan test operation, and implementing the scan test operation in response to predetermined scan-test-related signals related to the scan test operation; and a first signal path for supplying at least one of the predetermined scan-test-related signals to the logic circuit through at least one of the first and second terminals when the scan test operation is implemented. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present disclosure relates generally to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a test function.

  In an LSI (Large Scale Integrated Circuit) scan test method, a plurality of flip-flops constituting an internal circuit of an LSI are connected in cascade to form a scan chain, and data is input / output via this scan chain to Perform the test. Each flip-flop constituting the internal circuit is provided with a scan input terminal and a scan output terminal. A scan output terminal of one flip-flop is coupled to a scan input terminal of another flip-flop, and a chain of flip-flops is configured by cascade connection of a plurality of flip-flops. During the test operation, each scan flip-flop in the scan path stores the input data from the scan input terminal in synchronization with the clock signal and stores from the scan output terminal in response to the application of a value that indicates the scan is valid from the outside. Operates to output data.

  FIG. 1 is a diagram illustrating an example of the configuration of an LSI employing a scan test method. The LSI 10 includes a logic unit 11 and an analog circuit 12. The logic unit 11 includes a logic circuit 13, an input buffer 14, and an output buffer 15. The logic circuit 13 has a scan chain in which internal flip-flops are cascaded as described above, and operates based on the external power supply VCC. The analog circuit 12 is an analog-digital converter (ADC), a digital-analog converter (DAC), or the like, for example, and operates by an analog positive power supply AVCC, an analog reference voltage AVR, and an analog ground power supply AVSS.

  The logic circuit 13 is provided with a terminal for inputting a test mode signal XTST, a scan clock signal XTCK, a scan-in signal SI, and a scan mode signal SM, and a terminal for outputting a scan-out signal SO as terminals related to the scan test. ing. Hereinafter, these terminals are referred to as an XTST terminal, an XTCK terminal, an SI terminal, an SM terminal, and an SO terminal, respectively. Further, as terminals used during normal operation other than the scan test, a CLK terminal for inputting a clock signal CLK, a P00 terminal and a P01 terminal for inputting data, and a P02 terminal for outputting data are provided. The number of data input / output terminals is not limited to this example, and an arbitrary number may be provided.

  The test mode signal XTST is a negated state (eg, 1) during normal operation of the system, and is an asserted state (eg, 0) both during scan shift and during pattern capture (capture) during the scan test operation. is there. The scan mode signal SM is asserted at the time of scan shift operation between the scan flip-flops during the scan test, and is negated at the time of data capture operation from the combinational logic circuit during the scan test to the scan flip-flop (at the time of capture). is there. During normal operation, the scan mode signal SM is negated. The scan clock signal XTCK is a synchronization signal supplied to each flip-flop during a scan test. The scan-in signal SI is input from one end of the scan chain and propagates through flip-flops constituting the scan chain by a scan shift operation synchronized with the clock signal XTCK. The scan-out signal SO is a signal output from one end of the scan chain in which data of each flip-flop propagates through the scan chain by a scan shift operation synchronized with the clock signal XTCK.

In an LSI having a small number of external terminals such as a microcontroller, it is difficult to secure a space for providing the scan test terminals. If a scan test terminal is provided, the cost of the chip will increase. Therefore, for example, a method of preparing a sequence for activating the test mode signal XTST in the logic inside the LSI and generating the test mode signal XTST internally is used. Alternatively, a method of preparing a register for the test mode signal XTST in the memory space of the microcontroller LSI is also used. However, these methods are not preferable because they place restrictions on the internal logic specifications and become complicated.
JP 2001-228220 A JP 2006-332456 A JP 2006-194727 A

  In view of the above, there is a demand for a semiconductor integrated circuit that can easily set a scan test while minimizing the number of external terminals for a scan test.

  The semiconductor integrated circuit includes: an analog circuit that receives a first positive power supply voltage via a first terminal, a reference voltage via a second terminal, and a ground voltage via a third terminal; and a fourth terminal The normal operation and the scan test operation are selectively executed, and the scan test operation is executed in response to a predetermined scan test related signal related to the scan test operation. And a first signal path for supplying at least one of the predetermined scan test related signals to the logic circuit via at least one of the first terminal and the second terminal during the scan test operation It is characterized by including.

  According to at least one embodiment of the present disclosure, it is possible to easily set a scan test while reducing the number of external terminals as much as possible by using an input terminal of an analog circuit that is not used during a scan test operation for a scan test setting. Can be performed. According to this configuration, since the scan test can be executed with a small number of terminals, it is extremely effective to adopt the above configuration particularly in a semiconductor integrated circuit with a small number of external terminals such as a microcontroller.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a diagram showing an example of the configuration of the first embodiment of the LSI. The LSI 20 includes a logic unit 21 and an analog circuit 22. The logic unit 21 includes a logic circuit 23, an input buffer 24, an output buffer 25, a logic gate 26, a logic gate 27, and a selector circuit 28. The logic circuit 23 forms a scan chain with internal flip-flops connected in cascade, and operates based on the external power supply VCC. The logic circuit 23 includes, for example, a CPU, a timer, various interfaces, and the like. The logic circuit 23 may include a memory. The analog circuit 22 is, for example, an analog-digital converter (ADC), a digital-analog converter (DAC), and the like, and operates by an analog positive power supply AVCC, an analog reference voltage AVR, and an analog ground power supply AVSS.

  The logic circuit 23 is provided with a terminal for inputting a test mode signal XTST, a scan clock signal XTCK, a scan-in signal SI, and a scan-mode signal SM, and a terminal for outputting a scan-out signal SO as scan-related terminals. ing. Hereinafter, these terminals are referred to as an XTST terminal, an XTCK terminal, an SI terminal, an SM terminal, and an SO terminal, respectively. Further, as terminals used during normal operation other than the scan test, a CLK terminal for inputting a clock signal CLK, a P00 terminal and a P01 terminal for inputting data, and a P02 terminal for outputting data are provided. The number of data input / output terminals is not limited to this example, and an arbitrary number may be provided.

  The analog circuit 22 has an analog positive power supply voltage AVCC of 3.3 V, for example, through the first terminal 31, an analog reference voltage AVR through the second terminal 32, and an analog ground voltage through the third terminal 33. Receive AVSS. The logic circuit 23 operates by a positive power supply voltage received via the fourth terminal 34 separately from the AVCC, and selectively executes a normal operation and a scan test operation. The logic circuit 23 executes the scan test operation according to predetermined scan test related signals XTST, XTCK, SI, and SM related to the scan test operation.

  The logic unit 21 is provided with a signal path for supplying at least one of predetermined scan test related signals to the logic circuit 23 via at least one of the terminal 31 and the terminal 32 during the scan test operation. In the configuration example of FIG. 2, a path for supplying the test mode signal XTST from the terminal 31 to the XTST terminal of the logic circuit 23 and a path for supplying the scan-in signal SI from the terminal 32 to the SI terminal of the logic circuit 23 are provided. Yes. The signal supplied through these signal paths may include a test mode signal XTST for selecting either a normal operation or a scan test operation.

  Further, the logic circuit 23 executes the normal operation according to the normal operation related signal CLK and the data signals P00 and P01 related to the normal operation received through the terminals 35 to 37. The logic unit 21 is provided with a signal path for supplying at least one of predetermined scan test related signals to the logic circuit 23 through the same terminals 35 and 36 as described above during the scan test operation. In the configuration example of FIG. 2, a path for supplying the scan clock signal XTCK from the terminal 35 to the XTCK terminal of the logic circuit 23 and a path for supplying the scan mode signal SM from the terminal 36 to the SM terminal of the logic circuit 23 are provided. Yes. These signal paths are provided with logic gates 26 and 27 that block the signal path in accordance with the signal XTST supplied from the terminal 31. Specifically, the logic gate 26 is a gate that ANDs the negative logic of XTST and the positive logic of the scan clock signal XTCK, and shuts off the scan clock signal XTCK when XTST is HIGH and scans when XTST is LOW. The clock signal XTCK is passed. Similarly, the logic gate 27 is a gate that takes an AND of the negative logic of XTST and the positive logic of the scan mode signal SM, shuts off the scan mode signal SM when XTST is HIGH, and scan mode signal when XTST is LOW. Let the SM pass.

  Further, the logic circuit 23 outputs the signal P02 generated at the time of executing the normal operation to the outside through the terminal 38. The logic unit 21 is provided with a signal path for outputting the signal SO generated when the scan test operation is performed to the outside through the same terminal 38. In this signal path, a signal line through which the signal P02 generated during execution of the normal operation in accordance with the signal XTST supplied from the terminal 31 propagates, and a signal line through which the signal SO generated during execution of the scan test operation propagates. A selector circuit 28 is provided for selecting one of the above.

  With the above configuration, the LSI 20 does not need to be provided with dedicated terminals for the test mode signal XTST, the scan clock signal XTCK, the scan-in signal SI, the scan mode signal SM, and the scan-out signal SO. As a result, the number of terminals can be reduced and the cost of the LSI chip can be reduced. Further, by using the input terminal of the analog circuit 22 that is not used during the scan test operation, it is possible to efficiently use the terminal. Although the analog circuit 22 is not used during the scan test operation, applying a scan test signal to the analog ground power supply voltage terminal may adversely affect the operation of the digital circuits on the same substrate. There is sex. Therefore, among the input terminals to the analog circuit 22, the third terminal 33 for receiving the ground voltage AVSS is not used even during the scan test operation. Thereby, stable circuit operation can be ensured. In the configuration example described above, all scan test related signals are input / output using terminals for other purposes, but at least one of these scan test related signals is used for other purposes. It is good also as a structure which inputs / outputs a signal using. In this case, the input terminal of the analog circuit 22 that is not used at the time of the scan test operation may be preferentially used as a terminal for another application to be used.

  FIG. 3 is a diagram illustrating an example of the configuration of the logic circuit 23. The logic circuit 23 shown in FIG. 3 includes a user logic unit 41, a mode control circuit 42, and n scan flip-flops 43-1 to 43-n. In this drawing, as a simple example, the data input terminal D and the data output terminal Q of each of the scan flip-flops 43-1 to 43-n are coupled to the same user logic unit 41. However, for example, the data input terminal D and the data output terminal Q of one scan flip-flop may be connected to different logic circuit units. Each of the scan flip-flops 43-1 to 43-n receives output data from a certain part of the user logic unit 41 at the data input terminal D, stores the data therein, and stores the stored data from the data output terminal Q to the user logic unit. It is supplied as input data to the other parts of 41.

  Each of the scan flip-flops 43-1 to 43-n has a scan input terminal SI and a scan output terminal SO for scan shift in addition to the data input terminal D and the data output terminal Q. In addition, a scan enable input terminal SE for instructing valid / invalid scan shift is provided. Either the data input terminal D or the scan input terminal SI is selected according to “0/1” of the scan enable input terminal SE. Data of the selected input terminal is stored in the flip-flop in synchronization with the scan clock signal XTCK. Data output terminal Q and scan output terminal SO are coupled to the same internal node and output the same data signal.

  Either the normal operation or the scan test operation is selected and executed in accordance with “0/1” of the test mode signal XTST supplied to the mode control circuit 42. The control operation of the mode control circuit 42 controls, for example, which of the clock signal CLK for normal operation and the scan clock signal XTCK for scan test operation is supplied to the scan flip-flops 43-1 to 43-n. .

  In the normal operation of the logic circuit 23, a scan mode signal SM having a value (for example, “0”) instructing scan invalidity is applied to the scan enable input SE. In this case, each of the scan flip-flops 43-1 to 43-n stores the input data from the data input terminal D in synchronization with the clock signal, and outputs the stored data from the data output terminal Q.

  In the scan test operation of the logic circuit 23, a scan mode signal SM having a value (for example, “1”) for instructing scan validity is applied to the scan enable input SE. In this case, each of the scan flip-flops 43-1 to 43-n stores the input data from the scan input terminal SI in synchronization with the scan clock signal XTCK, and outputs the stored data from the scan output terminal SO. A scan output terminal SO of one flip-flop is coupled to a scan input terminal SI of another flip-flop, and a scan chain is configured by cascade connection of a plurality of scan flip-flops 43-1 to 43-n.

  During the scan test operation, the scan mode signal SM is set valid (for example, “1”) by an external tester device, and the scan-in signal SI is input serially in synchronization with the scan clock signal XTCK. The input scan-in signal SI repeats data shift by the shift operation of the scan flip-flop synchronized with the scan clock signal XTCK, and finally sets predetermined data to each of the scan flip-flops 43-1 to 43-n. Can do.

  When the predetermined data is set in each of the scan flip-flops 43-1 to 43-n, the user logic unit 41 is operated. At this time, the scan enable signal SE is applied with a scan mode signal SM having a value (for example, “0”) instructing scan invalidity, and a pulse of the scan clock signal XTCK is supplied to execute the capture operation. That is, each of the scan flip-flops 43-1 to 43-n stores the input data from the data input terminal D in synchronization with the scan clock signal XTCK and outputs the stored data from the data output terminal Q. Thereby, the output data of the user logic unit 41 is stored in parallel in the scan flip-flops 43-1 to 43-n. Then, the scan-out signal SO is serially output from the SO terminal by shifting the data of the scan flip-flops 43-1 to 43-n by the scan clock signal XTCK. The serially output scan-out signal SO is observed by an external tester device, and is compared with expected value data for the input scan-in signal SI. A defect in the logic circuit 23 in the LSI 20 can be detected based on the comparison result between the scan-out signal SO and the expected value data.

  FIG. 4 is a diagram showing an example of the configuration of the second embodiment of the LSI. 4, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. In the configuration of the first embodiment shown in FIG. 2, the test mode signal XTST is applied from the AVCC terminal 31 and the scan-in signal SI is applied from the AVR terminal 32. That is, the terminal 31 is shared by AVCC and XTST, and the terminal 32 is shared by AVR and SI. On the other hand, in the configuration of the second embodiment shown in FIG. 4, the scan-in signal SI is applied from the AVCC terminal 31 of the LSI 20a, and the test mode signal XTST is applied from the AVR terminal 32. That is, the terminal 31 is shared by AVCC and SI, and the terminal 32 is shared by AVR and XTST. Other configurations are the same as those of the LSI 20 shown in FIG.

  FIG. 5 is a diagram showing an example of the configuration of the third embodiment of the LSI. In FIG. 5, the same components as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. In the configuration of the first embodiment shown in FIG. 2, the scan-in signal SI is applied from the AVR terminal 32, and the scan clock signal XTCK is applied from the X0 terminal 35 for the clock signal CLK. That is, the terminal 32 is shared by AVR and SI, and the terminal 35 is shared by the clock signal CLK (X0) and the scan clock signal XTCK. On the other hand, in the configuration of the third embodiment shown in FIG. 5, the scan-in signal SI is applied from the P01 terminal 37 of the LSI 20b, and the scan clock signal XTCK is applied from the AVR terminal 32. That is, the terminal 37 is shared by P01 and SI, and the terminal 32 is shared by AVR and XTCK. Accordingly, instead of providing the logic gate 26 at the XTCK input portion of the logic circuit 23 as shown in FIG. 2, the logic portion 26b is provided at the SI input portion of the logic circuit 23 as shown in FIG. 21b is configured. The logic gate 26b is an AND gate of the negative logic of XTST and the positive logic of the scan-in signal SI. The logic gate 26b blocks the scan-in signal SI when XTST is HIGH and passes the scan-in signal SI when XTST is LOW. Let Other configurations are the same as those of the LSI 20 shown in FIG.

  FIG. 6 is a diagram showing an example of the configuration of the fourth embodiment of the LSI. In FIG. 6, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. The LSI 20c in FIG. 6 includes a logic unit 21c, an analog circuit 22, and an FeRAM (ferroelectric memory) 51. The FeRAM 51 is a nonvolatile memory using a ferroelectric as a storage element, and operates based on the power supply voltage VDDF from the terminal 52. In the configuration of the first embodiment shown in FIG. 2, the scan mode signal SM is applied from the terminal 36 for data P00. That is, the terminal 36 is shared by the data P00 and SM. On the other hand, in the configuration of the fourth embodiment shown in FIG. 6, the scan mode signal SM is applied from the VDDF terminal 52 of the LSI 20c. That is, the terminal 52 is shared by VDDF and SM. Accordingly, as shown in FIG. 6, instead of the logic gate 27 that takes the AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 36 in the logic unit 21 as shown in FIG. Is provided. As shown in FIG. 6, the logic gate 27 c of the logic unit 21 c takes an AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 52. Other configurations are the same as those of the LSI 20 shown in FIG.

  Similar to the analog circuit 22, the FeRAM 51 is generally not used during the scan test operation. Therefore, efficient utilization of the terminals can be achieved by using the input terminals of the FeRAM 51.

  FIG. 7 is a diagram showing an example of the configuration of the fifth embodiment of the LSI. In FIG. 7, the same components as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. The LSI 20d in FIG. 7 includes a logic unit 21d, an analog circuit 22, a regulator 61, and analog switch circuits 63 and 64. The regulator 61 generates a stable internal power supply voltage VCC based on the external power supply voltage supplied from the terminal 34. During normal operation, the signal line from which the regulator 61 outputs the internal power supply voltage VCC is coupled to the external capacitive element C via the terminal 62. By coupling the capacitive element C to the internal power supply voltage VCC in this way, it is possible to avoid the internal power supply voltage VCC output from the regulator 61 from oscillating when the external power supply voltage vibrates.

  When the scan test operation of the LSI 20d is executed, the external power supply voltage is supplied from the tester, so that the power supply voltage is sufficiently stable. Therefore, it is not necessary to connect the capacitive element C to the terminal 62 during the scan test operation. In the configuration of the fifth embodiment shown in FIG. 7, a signal path for outputting the scan-out signal SO generated at the time of executing the scan test operation to the outside through the terminal 62 is provided. This signal path is provided with an analog switch circuit 64 that cuts off the signal path in accordance with the test mode signal XTST supplied from the first terminal 31. The analog switch circuit 64 becomes conductive when the test mode signal XTST is asserted during the scan test operation, and connects the SO output of the logic circuit 23 to the terminal 62. At this time, the capacitor C is not connected to the terminal 62. The analog switch circuit 63 is cut off when the test mode signal XTST is asserted during the scan test operation, and disconnects the output of the regulator 61 from the terminal 62.

  By providing the above-described configuration, the selector circuit 28 in the logic unit 21 in FIG. 2 is removed from the logic unit 21d in FIG. In other respects, the logic unit 21d and the logic unit 21 are substantially the same.

  FIG. 8 is a diagram showing an example of the configuration of the sixth embodiment of the LSI. In FIG. 8, the same components as those in FIGS. 6 and 7 are referred to by the same numerals, and a description thereof will be omitted. The LSI 20e in FIG. 8 includes a logic unit 21e, an analog circuit 22, an FeRAM 51, a regulator 61, and analog switch circuits 63 and 64. In the configuration of the fifth embodiment shown in FIG. 7, the scan mode signal SM is applied from the terminal 36 for data P00. That is, the terminal 36 is shared by the data P00 and SM. On the other hand, in the configuration of the sixth embodiment shown in FIG. 8, the scan mode signal SM is applied from the VDDF terminal 52 of the LSI 20e. That is, the terminal 52 is shared by VDDF and SM. Accordingly, as shown in FIG. 8, instead of the logic gate 27 taking the AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 36 in the logic unit 21d as shown in FIG. Is provided. As shown in FIG. 8, the logic gate 27e of the logic unit 21e takes an AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 52. Other configurations are the same as those of the LSI 20d shown in FIG.

  FIG. 9 is a diagram showing an example of the configuration of the seventh embodiment of the LSI. 9, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. The LSI 20f in FIG. 9 includes a logic unit 21f, an analog circuit 22, and a flash memory 71. The flash memory 71 is a non-volatile memory that stores information by charge injection into the floating gate, and performs operations such as programming and erasing by using the high voltage HVD from the terminal 72. In the configuration of the first embodiment shown in FIG. 2, the scan mode signal SM is applied from the terminal 36 for data P00. That is, the terminal 36 is shared by the data P00 and SM. On the other hand, in the configuration of the seventh embodiment shown in FIG. 9, the scan mode signal SM is applied from the HVD terminal 72 of the LSI 20c. That is, the terminal 72 is shared by HVD and SM. Accordingly, as shown in FIG. 9, instead of the logic gate 27 taking the AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 36 in the logic unit 21 as shown in FIG. Is provided. As shown in FIG. 9, the logic gate 27 f of the logic unit 21 f takes an AND of the negative logic of XTST and the positive logic of the scan mode signal SM from the terminal 72. Other configurations are the same as those of the LSI 20 shown in FIG.

  FIG. 10 is a flowchart of the operation control of the LSI described in the above embodiment. In step S1, it is determined whether the voltage applied to the terminal that is used for both AVCC (or AVR) and XTST is HIGH or LOW. Such a dual-purpose terminal is, for example, the terminal 31 in the case of the first embodiment shown in FIG. 2, and the terminal 32 in the case of the second embodiment shown in FIG. If the applied voltage is HIGH (VCC level), the process proceeds to step S2.

  In step S2, the LSI is normally activated. Thereafter, in step S3, the operation mode is selected. The selection of this operation mode may be determined by some external setting. When the user mode is selected, in step S4, the LSI logic unit (for example, the logic unit 21 in FIG. 2) performs a normal operation, and the analog circuit (for example, the analog circuit 22 in FIG. 2) is a peripheral device for the logic unit. Used as. When the test mode is selected, the analog circuit test is executed. In LSI chips, built-in ADCs and DACs generally contain conversion errors. Therefore, it is preferable to measure each conversion error for ADC and DAC in advance, and to perform correction processing based on the measured error when performing actual AD conversion and DA conversion. In order to determine the error between the ADC and DAC in the LSI chip, for example, a predetermined analog voltage is input via an external terminal to check a digital code after AD conversion, or an analog voltage after DA conversion for a predetermined digital code Is measured via an external terminal.

  As a result of the determination in step S1, when the applied voltage is LOW (VSS level), the process proceeds to step S6. In step S6, the LSI is activated in a scan test mode. In step S7, in the scan test mode, a scan test is performed on the logic portion and memory of the LSI. At this time, various scan-related signals such as a scan clock signal, a scan-in signal, and a scan mode signal may be applied from other shared terminals.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The disclosure of the present application includes the following contents.
(Appendix 1)
An analog circuit that receives a first positive power supply voltage via a first terminal, a reference voltage via a second terminal, and a ground voltage via a third terminal;
It operates with a second positive power supply voltage received via the fourth terminal, selectively executes a normal operation and a scan test operation, and performs the scan according to a predetermined scan test related signal related to the scan test operation A logic circuit for performing a test operation;
And a first signal path for supplying at least one of the predetermined scan test related signals to the logic circuit via at least one of the first terminal and the second terminal during the scan test operation. A semiconductor integrated circuit.
(Appendix 2)
2. The semiconductor integrated circuit according to claim 1, wherein the at least one of the predetermined scan test related signals includes a test mode signal for selecting one of a normal operation and a scan test operation.
(Appendix 3)
A second signal path;
The logic circuit performs the normal operation in response to a predetermined normal operation related signal related to the normal operation received via a fifth terminal, and the second signal path is configured to perform the fifth test operation during the scan test operation. 3. The semiconductor integrated circuit according to appendix 1 or 2, wherein at least one of the predetermined scan test related signals is supplied to the logic circuit via a terminal.
(Appendix 4)
The third signal path is provided with a circuit that cuts off a signal path according to a signal supplied from at least one of the first terminal and the second terminal. Semiconductor integrated circuit.
(Appendix 5)
Further comprising a third signal path;
The logic circuit outputs a signal generated during execution of the normal operation to the outside via a sixth terminal, and the third signal path outputs a signal generated during execution of the scan test operation. 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit outputs the signal to the outside via a terminal.
(Appendix 6)
In the third signal path, a signal line through which a signal generated during execution of the normal operation according to a signal supplied from at least one of the first terminal and the second terminal propagates and the scan test 4. The semiconductor integrated circuit according to appendix 3, wherein a circuit is provided for selecting one of a signal line through which a signal generated when the operation is performed is propagated.
(Appendix 7)
A fourth signal path;
A regulator circuit,
The output of the regulator circuit is connected to an external capacitive element via a seventh terminal during the normal operation, and the fourth signal path is configured to output a signal generated during the execution of the scan test operation to the seventh terminal. The semiconductor integrated circuit according to any one of appendices 1 to 4, wherein the semiconductor integrated circuit outputs to the outside via
(Appendix 8)
The additional signal according to claim 7, wherein the fourth signal path is provided with a circuit that blocks the signal path in accordance with a signal supplied from at least one of the first terminal and the second terminal. Semiconductor integrated circuit.
(Appendix 9)
An analog circuit that receives a first positive power supply voltage via a first terminal, a reference voltage via a second terminal, and a ground voltage via a third terminal;
It operates with a second positive power supply voltage received via the fourth terminal, selectively executes a normal operation and a scan test operation, and performs the scan according to a predetermined scan test related signal related to the scan test operation A logic circuit for performing a test operation;
And a first signal path for supplying at least one of the predetermined scan test related signals to the logic circuit via at least one of the first terminal and the second terminal during the scan test operation. A semiconductor integrated circuit.

It is a figure which shows an example of a structure of LSI which employ | adopted the scan test system. It is a figure which shows an example of a structure of the 1st Example of LSI. It is a figure which shows an example of a structure of a logic circuit. It is a figure which shows an example of a structure of the 2nd Example of LSI. It is a figure which shows an example of a structure of the 3rd Example of LSI. It is a figure which shows an example of a structure of the 4th Example of LSI. It is a figure which shows an example of a structure of the 5th Example of LSI. It is a figure which shows an example of a structure of the 6th Example of LSI. It is a figure which shows an example of a structure of the 7th Example of LSI. It is a flowchart of operation control of the LSI explained in the above embodiment.

Explanation of symbols

20 LSI
21 logic unit 22 analog circuit 23 logic circuit 24 input buffer 25 output buffer 26 logic gate 27 logic gate 28 selector circuit 41 user logic unit 42 mode control circuits 43-1 to 43-n scan flip-flop

Claims (5)

An analog circuit for receiving a first positive power supply voltage via a first terminal and a ground voltage via a third terminal;
It operates with a second positive power supply voltage received via the fourth terminal, selectively executes a normal operation and a scan test operation, and performs the scan according to a predetermined scan test related signal related to the scan test operation A logic circuit for performing a test operation;
And a first signal path for supplying at least one of the predetermined scan test related signals to the logic circuit via the first terminal during the scan test operation.   2. The semiconductor integrated circuit according to claim 1, wherein the at least one of the predetermined scan test related signals includes a test mode signal for selecting one of a normal operation and a scan test operation. A second signal path;
The logic circuit performs the normal operation in response to a predetermined normal operation related signal related to the normal operation received via a fifth terminal, and the second signal path is configured to perform the fifth test operation during the scan test operation. 3. The semiconductor integrated circuit according to claim 1, wherein at least one of the predetermined scan test related signals is supplied to the logic circuit via a terminal. Further comprising a third signal path;
The logic circuit outputs a signal generated during execution of the normal operation to the outside via a sixth terminal, and the third signal path outputs a signal generated during execution of the scan test operation. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit outputs the signal to the outside via the terminal. A fourth signal path;
A regulator circuit,
The output of the regulator circuit is connected to an external capacitive element via a seventh terminal during the normal operation, and the fourth signal path is configured to output a signal generated during the execution of the scan test operation to the seventh terminal. 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit outputs to the outside via

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