CN116224045B - Test circuit and method for reducing power consumption in capture stage in scanning test - Google Patents
Test circuit and method for reducing power consumption in capture stage in scanning test Download PDFInfo
- Publication number
- CN116224045B CN116224045B CN202310508664.8A CN202310508664A CN116224045B CN 116224045 B CN116224045 B CN 116224045B CN 202310508664 A CN202310508664 A CN 202310508664A CN 116224045 B CN116224045 B CN 116224045B
- Authority
- CN
- China
- Prior art keywords
- test
- scan
- power consumption
- internal reset
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318575—Power distribution; Power saving
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A test circuit and method for reducing power consumption in a capture phase of a scan test, wherein the test circuit is applied to a functional module, the circuit comprising: at least two internal reset modules, which are used for carrying out reset control on at least two nodes in the functional module in a one-to-one correspondence manner; at least two holding registers configured to input and latch a test vector at a scan data shift-in stage and output the latched test vector at a capture stage, which inputs a first scan test enable signal, an output signal of the functional logic module, and the test vector; a first or gate inputting a second scan test enable signal and an output signal of the control register; and the output ends of the at least two second OR gates are connected with the corresponding internal reset modules. Therefore, in the capturing stage of DFT scan, partial nodes in the functional module can be in a reset state, and the power consumption in the capturing stage is effectively reduced.
Description
Technical Field
The present application relates to the field of circuit testing technology, and in particular, to a test circuit and a method for reducing power consumption in a capture stage of a scan test.
Background
DFT scan (Design for Test scan, design for testability scan) testing is an indispensable efficient and low cost test tool in chip structuring testing. Unlike functional testing, in scan testing, a large number of registers and combinational logic are flipped such that power consumption is often greater than in functional mode. Under the condition that the back end implementation is biased to the function, the problem of overlarge power consumption easily occurs in scan test, so that test failure is caused. How to reasonably plan in the scan test process, increase the control capability of the chip, avoid overlarge transient power consumption and be vital to yield and cost.
Disclosure of Invention
In order to solve the defects existing in the prior art, the application aims to provide a test circuit and a method for reducing power consumption in a capturing stage in a scan test, which can realize that part of circuits are in a reset state in the capturing stage of DFT scan, effectively reduce the power consumption in the capturing stage, further avoid test failure caused by overlarge power consumption, and further help to reduce the influence of overlarge power consumption on the yield and cost of chips.
In order to achieve the above purpose, the test circuit provided by the application is applied to a functional module, and a plurality of functional modules are included in a chip; the test circuit includes:
at least two internal reset modules, which are used for carrying out reset control on at least two nodes in the functional module in a one-to-one correspondence manner;
a control register and a functional logic module;
the at least two holding registers are arranged corresponding to the at least two internal reset modules; configured to input and latch a test vector during a scan data in phase and output the latched test vector during a capture phase; a first input end of the holding register inputs a first scan test enabling signal; the second input end of the holding register is connected with the output end of the functional logic module; a third input end of the holding register inputs the test vector;
a first or gate, wherein a first input end of the first or gate inputs a second scan test enabling signal; the second input end of the first OR gate is connected with the output end of the control register;
the at least two second OR gates are arranged corresponding to the at least two internal reset modules; the first input end of the second OR gate is connected with the output end of the corresponding holding register; the second input end of the second OR gate is connected with the output end of the first OR gate; and the output end of the second OR gate is connected with a corresponding internal reset module so that the internal reset module determines a setting reset state based on the received test vector in the capturing stage.
Further, the holding register includes:
the first input end of the D trigger inputs the test vector; the second input end of the D trigger is connected with the output end of the multiplexer;
the first input end of the multiplexer inputs the first scanning test enabling signal; the second input end of the multiplexer is connected with the output end of the functional logic module so as to input a functional control signal; the third input end of the multiplexer is connected with the output end of the D trigger; the output end of the multiplexer is connected with a corresponding internal reset module.
To achieve the above object, the present application also provides a method for reducing power consumption in a capture stage in a scan test, the method being applied to a test circuit as described above, the method comprising:
during the scan data shift-in phase, the holding register inputs and latches the test vectors;
in the capturing stage, the holding register outputs the latched test vector; the corresponding internal reset module determines a set reset state based on the received test vector to determine whether to perform reset control on the corresponding node in the functional module.
Further, in the scan data shift-in stage, the first scan test enable signal and the second scan test enable signal received by the test circuit are at high level.
Further, in the capturing stage, the first scan test enable signal received by the test circuit is at a high level, the second scan test enable signal is at a low level, and the output end of the control register outputs a low level.
Further, the step of determining the set-reset state by the corresponding internal reset module based on the test vector includes:
responsive to generating a high level signal based on the test vector, the corresponding internal reset module is in a set state;
in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a reset state.
Further, the step of determining the set-reset state by the corresponding internal reset module based on the test vector includes:
responsive to generating a high level signal based on the test vector, the corresponding internal reset module is in a reset state;
in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a set state.
Further, before the scan data is moved into phase, the method further comprises:
acquiring the power consumption of the test circuit;
responsive to the power consumption being greater than a preset threshold, during the capture phase and the scan data shift-in phase, an output of a control register is configured as a low level signal;
in response to the power consumption being less than or equal to a preset threshold, the output of the control register is configured as a high level signal during the capture phase and the scan data shift-in phase.
Further, before the scan data is moved into phase, the method further comprises:
and carrying out combined configuration on the test modes corresponding to the internal reset modules in the test circuit so that the test modes corresponding to part of the internal reset modules do not overturn in the capturing stage.
To achieve the above object, the present application also provides a chip on which at least one functional module including the test circuit as described above is integrated.
In order to achieve the above object, the present application further provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor, where the processor is configured to execute the computer program stored in the memory, to implement the method for reducing power consumption in a capturing stage in a scan test as described above.
To achieve the above object, the present application also provides a computer-readable storage medium having at least one instruction stored therein, the instruction being loaded and executed by a processor to implement a method of reducing power consumption in a capture phase in a scan test as described above.
According to the test circuit and the method for reducing the power consumption in the capture stage in the scan test, the first scan test enabling signal, the test vector and the output signal of the functional logic module are input through the holding register, the test vector is input and latched in the scan data shifting-in stage, the latched test vector is output in the capture stage, the second scan test enabling signal and the output signal of the control register are input through the first OR gate, the output signal of the holding register and the output signal of the first OR gate are input through the second OR gate, and the output signal of the first OR gate is output to the corresponding internal reset module, so that the internal reset module determines the set reset state based on the received test vector in the capture stage, and the corresponding node in the functional module is reset controlled through the internal reset module. Therefore, the node in the functional module can be controlled to be integrated into zero in the capturing stage of DFT scan, so that part of nodes are in a reset state, the power consumption in the capturing stage is effectively reduced, the test failure caused by overlarge power consumption can be avoided, and the influence of overlarge power consumption on the chip yield and the cost is reduced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and do not limit the application. In the drawings:
FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the application;
FIG. 2 is a schematic diagram of a holding register according to an embodiment of the present application;
FIG. 3 is a waveform diagram of a signal corresponding to a reset test vector according to an embodiment of the present application;
FIG. 4 is a flowchart of a method for reducing power consumption during a capture phase in a scan test according to an embodiment of the present application;
FIG. 5 is a block diagram of a chip structure according to an embodiment of the application;
fig. 6 is a block diagram of an electronic device according to an embodiment of the application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the method embodiments of the present application may include additional steps and/or omit performing the illustrated steps. The scope of the application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
In the drawings, some structural or methodological features are shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. In some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.
It should be understood that although the terms "first," "second," etc. may be used herein to describe various modules/units or data, these modules/units or data should not be limited by these terms. These terms are used merely to distinguish between different modules/units or data and are not intended to limit the order or interdependence of functions performed by the modules/units or data. For example, a first feature may be referred to as a second feature, and similarly a second feature may be referred to as a first feature, without departing from the scope of the example embodiments.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
It should be understood that while the present application uses "high," "low," etc. to describe various level signals, these terms are used merely to logically distinguish levels and that the level heights may be altered without departing from the scope of the exemplary embodiments.
First, it should be noted that there may be a plurality of functional modules in the chip, and in a specific example, the plurality of functional modules may be independent from each other in the testing process and independent from each other in the space within the chip. The functional module includes a node located at an edge (boundary) and a node located at an interior (internal). The test circuit in the application performs reset control in the capturing stage aiming at the node positioned in the functional module so as to reduce the power consumption in the capturing stage.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a test circuit structure according to an embodiment of the application, and referring to fig. 1, a test circuit 100 is shown and applied to a functional module. The test circuit 100 includes: at least two holding registers 1, a functional logic module 2, a control register 3, a first or gate 4, at least two second or gates 5 and at least two internal reset modules 6.
And the at least two internal reset modules 6 are used for carrying out reset control on at least two nodes in the functional module in a one-to-one correspondence manner.
At least two holding registers 1 provided corresponding to at least two internal reset modules 6; configured to input and latch a test vector in a scan data shift-in (shift) stage and output the latched test vector in a capture (capture) stage; a first input terminal of the holding register 1 inputs a first Scan test enable signal (scan_mode); the second input end of the holding register 1 is connected with the output end of the functional logic module 2; the third input of the holding register 1 inputs the test vector.
A first or gate 4, a first input terminal of the first or gate 4 inputs a second Scan test enable signal (scan_enable); a second input of the first or gate 4 is connected to an output of the control register 3.
At least two second or gates 5, which are disposed corresponding to the at least two internal reset modules 6; the first input end of the second OR gate 5 is connected with the output end of the corresponding holding register 1; the second input end of the second OR gate 5 is connected with the output end of the first OR gate 4; the output end of the second or gate 5 is connected to the corresponding internal reset module 6, so that the internal reset module 6 determines the set reset state based on the received test vector in the capturing stage.
The holding register 1 is used for inputting and latching a test vector in a shift stage and outputting the latched test vector in a capture stage, so that not only can the power consumption of the capture stage be reduced, but also coverage loss can be reduced, and burrs (glitch) generated by the test vector can be avoided. And the test vector is used for controlling whether the corresponding module is reset or not in the capture stage. The functional logic module 2, in a specific example, may be a circuit topology built up by logic gates, and is configured to provide a functional control signal for DFT scan test. It will be appreciated that the functional logic module 2 may be any circuit topology having a functional control signal capable of providing signal testing, as the application is not particularly limited in this regard. A control register 3 for providing a test mode control signal to the test circuit 100 to control whether the function of reducing the power consumption of the capture stage is turned on. In a specific example, the test mode control signal output by the control register 3 may be configured to be high or low in the configuration stage, while remaining unchanged in the subsequent shift stage or capture stage. And a first or gate 4 for outputting a high level signal to the second or gate 5 in case that at least one of the second scan test enable signal and the test mode control signal is a high level signal, and outputting a low level signal to the second or gate 5 otherwise. And a second or gate 5 for outputting a high level signal to the corresponding internal reset module 6 if at least one of the output signal of the corresponding holding register 1 and the output signal of the first or gate 4 is high level, and outputting a low level signal to the corresponding internal reset module 6 otherwise. The internal reset module 6 is a reset module in the chip except for an external reset module on the partition edge. In the capturing stage, if the internal reset module 6 receives the low-level signal output by the second or gate 5, the internal reset module enters a reset state, and the corresponding test vector does not turn over, namely, the reset pattern (reset test vector); if the internal reset module 6 receives the high level signal output by the second or gate 5, it does not enter the reset state (may be referred to as being in the set state), and the corresponding test vector will be flipped based on the clock signal, i.e. the normal pattern (normal test vector). In a specific example, the internal reset module 6 may be a control circuit including a reset switch, and the specific structure of the control circuit is not particularly limited by the present application.
It should be noted that, the set state of the internal reset module in the present application is defined for convenience of description with respect to the reset state, specifically, in the capturing stage, the test vector is turned over according to the clock in the normal working state.
The principle of the test circuit of the embodiment of the application is as follows:
when the power consumption of the capture stage of the test circuit is required to be restrained, a small amount of logic is added to control a circuit corresponding to part of nodes in the functional module to adopt a reset pattern in the capture stage; and meanwhile, a circuit corresponding to another part of nodes is controlled to adopt a reset pattern. Compared with normal pattern, reset pattern has greatly reduced logic in the capturing stage, and is not easy to cause the situation of overlarge transient power consumption. That is, two types of test vectors exist simultaneously, and they do not flip at the same time in the capture phase, so that transient power consumption is reduced.
Specifically, in the case where it is necessary to reduce the power consumption of the test circuit capture stage, the control register 3 is configured to be low level in the configuration stage. Then, in the shift stage, the scan_enable received by the test circuit is at a high level, so that the reset module 6 is kept in a set state in the shift stage; at the same time, scan_mode received by the test circuit is also high, so that the test vector is input and latched to the corresponding holding register 1. Then, in the capture stage, the scan_enable received by the test circuit is at a low level, and the scan_mode is at a high level, so that the latch test vector is output by the holding register 1 in the capture stage, and the corresponding internal reset module 6 determines the set reset state based on the received test vector. Since in the early configuration, the circuits corresponding to some nodes in the test circuit 100 are configured to use normal pattern, and the circuits corresponding to other nodes are configured to use reset pattern, the test vectors corresponding to the two patterns can respectively generate high-level signals or low-level signals, so that they will not flip at the same time, and the transient power consumption in the capture stage is effectively reduced.
The control register 3 is configured to be high level in the configuration stage without reducing the power consumption of the test circuit capture stage. Thus, in the shift stage and the capture stage, the first or gate 4 and the second or gate 5 in the test circuit 100 output high levels, so that all the internal reset modules 6 maintain a set state, and transient power consumption in the capture stage is not constrained.
Fig. 2 is a schematic diagram of a holding register according to an embodiment of the application. Referring to fig. 2, the holding register 1 includes: d flip-flop 11 and multiplexer 12.
Wherein, the first input end of the D trigger 11 inputs the test vector; a second input of the D flip-flop 11 is connected to an output of the multiplexer 12.
A multiplexer 12, a first input of the multiplexer 12 inputting scan_mode; a second input terminal (0 terminal) of the multiplexer 12 is connected to the output terminal of the functional logic module 2 to input a functional control signal; the third input terminal (1 terminal) of the multiplexer 12 is connected to the output terminal of the D flip-flop 11; the output of the multiplexer 12 is connected to the corresponding internal reset module 6.
Specifically, in the shift phase and the capture phase, scan_mode is held at a high level. In the shift phase, the test vector is input along the path of Si to Q and latched into the D flip-flop 11. While in the capture phase, the D flip-flop 11 outputs the latched test vector and holds it. If the D flip-flop 11 samples the D terminal with a clock (clock) signal based on the test vector, and outputs a level signal (e.g., a low level signal) at the Q terminal, the multiplexer 12 outputs 1 so that the corresponding test mode is inverted based on the clock signal, i.e., normal pattern is adopted; if the D flip-flop 11 outputs another level signal (e.g., a high level signal) at the Q terminal based on the test vector, the multiplexer 12 outputs 0, the corresponding internal reset module is pulled to the reset state, and the Q terminal of the D flip-flop 11 is reset, so that the test mode does not flip over with the clock signal, i.e., reset pattern is adopted.
It will be appreciated that the multiplexer 12 may be a two-out multiplexer, with two select inputs corresponding to the second and third inputs of the multiplexer 12; the multiplexer 12 may be any other multiplexer, and the present application is not limited thereto.
Fig. 3 is a waveform diagram of a reset test vector corresponding to a related signal according to an embodiment of the present application, and referring to fig. 3, a clock signal CLK of a holding register, a second scan test enable signal SE of the holding register, an output signal Q1 of the holding register, and a register output signal Q2 driven by the holding register are illustrated. It can be seen that during the capture phase, Q1 of the hold register remains at 0 and Q2 of the register it drives remains at 1, i.e. its logic is in a reset state and no inversion of the corresponding circuit portion occurs. While other registers not in reset will sample normally on the clock edge (not shown in fig. 3). Therefore, from the whole test circuit, the test circuit can not only meet the test of the reset related faults, but also reduce the power consumption of the whole test circuit after the clock edge by resetting part of the functional registers.
In summary, according to the test circuit of the embodiment of the present application, the first scan test enable signal, the test vector and the output signal of the functional logic module are input through the holding register, the test vector is input and latched in the scan data shifting-in stage, the latched test vector is output in the capturing stage, the second scan test enable signal and the output signal of the control register are input through the first or gate, the output signal of the holding register and the output signal of the first or gate are input through the second or gate, and the output signal of the first or gate is output to the corresponding internal reset module, so that the internal reset module determines the set reset state based on the received test vector in the capturing stage, and the reset control is performed on the corresponding node inside the functional module through the internal reset module. Therefore, the node in the functional module can be controlled to be integrated into zero in the capturing stage of DFT scan, so that part of nodes are in a reset state, the power consumption in the capturing stage is effectively reduced, the test failure caused by overlarge power consumption can be avoided, and the influence of overlarge power consumption on the chip yield and the cost is reduced.
FIG. 4 is a flowchart of a method for reducing power consumption during a capture phase in a scan test according to an embodiment of the application, and referring to FIG. 4, the method includes the steps of:
in step 201, the holding register inputs and latches the test vectors during the scan data in phase.
In the embodiment of the application, in the stage of moving in the scan data, the first scan test enable signal and the second scan test enable signal received by the test circuit are at high level.
In step 202, during the capture phase, a holding register outputs a latched test vector; the corresponding internal reset module determines a set reset state based on the received test vector to determine whether to perform reset control on the corresponding node in the functional module.
In the embodiment of the application, in the capturing stage, the first scan test enable signal received by the test circuit is at a high level, the second scan test enable signal is at a low level, and the output end of the control register outputs a low level.
Specifically, for scan_mode, the level is always high in the DFT Scan test, so that the hold register is in operation in both the shift stage and the capture stage. For Scan_enable, the internal reset module is kept in a set state by being high in the shift stage, and the internal reset module is kept in a low level in the capture stage, so that the holding register outputs a latched test vector, and the corresponding internal reset module determines the set reset state based on the received test vector.
As one embodiment, the step of determining the set-reset state by the corresponding internal reset module based on the test vector includes: responding to the high level signal generated based on the test vector, wherein the corresponding internal reset module is in a set state; in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a reset state.
As another embodiment, the step of determining the set reset state by the corresponding internal reset module based on the test vector includes: responding to the high level signal generated based on the test vector, wherein the corresponding internal reset module is in a reset state; in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a set state.
That is, different types of signals are generated based on the test vectors, so that corresponding internal reset modules are in different states.
The high level signal or the low level signal generated based on the test vector may be a signal output from the Q terminal of the D flip-flop.
In an embodiment of the present application, before the scan data is shifted into the stage, the method further includes: acquiring power consumption of a test circuit; in response to the power consumption being greater than a preset threshold, during the capture phase and the scan data shift-in phase, the output of the control register is configured as a low level signal; in response to the power consumption being less than or equal to a preset threshold, the output of the control register is configured as a high level signal during the capture phase and the scan data shift-in phase.
Specifically, the preset threshold may be set based on a power consumption value corresponding to a test failure caused by excessive power consumption in a previous simulation stage. If the power consumption of the current test circuit is larger than a preset threshold, namely the power consumption of the capture stage is required to be restrained, the output end of the control register is configured as a low-level signal in a configuration stage; if the power consumption of the current test circuit is smaller than or equal to the preset threshold, namely the power consumption of the capture stage is not required to be restrained, the output end of the control register is configured to be a high-level signal in the configuration stage. Thereby, an optimized coverage (coverage) and test vector count (pattern count) can be achieved.
In an embodiment of the present application, before the scan data is shifted into the stage, the method further includes: and carrying out combined configuration on the test modes corresponding to the internal reset modules in the test circuit so that the test modes corresponding to part of the internal reset modules do not overturn in the capturing stage. That is, by adding a small amount of logic, the test mode of the circuit corresponding to the control part node is normal pattern, the test mode of the circuit corresponding to the control part node is reset pattern, and the circuit corresponding to the control part node and the reset pattern cannot be overturned at the same time in the capturing stage, so that the transient power consumption can be reduced.
It should be noted that, the explanation of the test circuit in the above embodiment is also applicable to the method for reducing the power consumption in the capturing stage in the scan test in this embodiment, and will not be repeated here.
According to the method for reducing the power consumption of the capturing stage in the scan test, the test vector is input and latched by the holding register during the scan data shifting-in stage, and the latched test vector is output by the holding register during the capturing stage, and the corresponding internal reset module determines the set reset state based on the received test vector. Therefore, partial nodes in the functional module can be in a reset state in the capturing stage of DFT scan, the power consumption in the capturing stage is effectively reduced, test failure caused by overlarge power consumption can be avoided, and the influence of overlarge power consumption on the chip yield and the cost is reduced.
Fig. 5 is a block diagram of a chip structure according to an embodiment of the present application, and referring to fig. 5, at least one functional module 200 is integrated on the chip 300, and the functional module 200 includes the test circuit 100 in the above embodiment.
Fig. 6 is a block diagram of an electronic device according to an embodiment of the present application, and referring to fig. 6, the electronic device 400 includes a processor 401 and a memory 402, where the memory 402 stores computer instructions, and the processor 401 is configured to execute the instructions to perform the steps of the method for reducing power consumption in the capture phase in the scan test in the above embodiment.
In an embodiment of the application, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps in a method embodiment of reducing power consumption in a capture phase in a scan test as described above when run.
Embodiments of the present application, a computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: portable computer diskette, hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present application, and the present application is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present application has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (13)
1. A test circuit is characterized in that a plurality of functional modules are included in a chip; the functional modules are mutually independent in the test process or mutually independent in the space in the chip; the functional module comprises a node positioned at an edge and a node positioned inside, the test circuit is applied to the node positioned inside, and the test circuit comprises:
at least two internal reset modules, which are used for carrying out reset control on at least two nodes in the functional module in a one-to-one correspondence manner;
a control register and a functional logic module;
the at least two holding registers are arranged corresponding to the at least two internal reset modules; configured to input and latch a test vector during a scan data in phase and output the latched test vector during a capture phase; a first input end of the holding register inputs a first scan test enabling signal; the second input end of the holding register is connected with the output end of the functional logic module; a third input end of the holding register inputs the test vector;
a first or gate, wherein a first input end of the first or gate inputs a second scan test enabling signal; the second input end of the first OR gate is connected with the output end of the control register;
the at least two second OR gates are arranged corresponding to the at least two internal reset modules; the first input end of the second OR gate is connected with the output end of the corresponding holding register; the second input end of the second OR gate is connected with the output end of the first OR gate; the output end of the second OR gate is connected with a corresponding internal reset module, so that the internal reset module determines a setting reset state based on the received test vector in the capturing stage;
a part of the internal reset modules in the at least two internal reset modules are in a reset state; the test vector output by the partial internal reset module is not turned over based on the clock signal.
2. The test circuit of claim 1, wherein the holding register comprises:
the first input end of the D trigger inputs the test vector; the second input end of the D trigger is connected with the output end of the multiplexer;
a multiplexer, a first input end of which inputs the first scan test enable signal; the second input end of the multiplexer is connected with the output end of the functional logic module so as to input a functional control signal; the third input end of the multiplexer is connected with the output end of the D trigger; the output end of the multiplexer is connected with a corresponding internal reset module.
3. A method of reducing power consumption in a capture phase of a scan test, the method being applied to the test circuit of claim 1 or 2, the method comprising:
during the scan data shift-in phase, the holding register inputs and latches the test vectors;
in the capturing stage, the holding register outputs the latched test vector; the corresponding internal reset module determines a set reset state based on the received test vector so as to determine whether to carry out reset control on the corresponding node in the functional module; a part of the internal reset modules in the at least two internal reset modules are in a reset state; the test vector output by the partial internal reset module is not turned over based on the clock signal.
4. A method of reducing power consumption in a capture phase of a scan test as defined in claim 3, wherein the first and second scan test enable signals received by the test circuit are high during the scan data shift-in phase.
5. The method of claim 3, wherein during the capture phase, the first scan test enable signal received by the test circuit is high, the second scan test enable signal is low, and the output of the control register is low.
6. A method of reducing power consumption during a capture phase in a scan test according to claim 3, wherein the step of the corresponding internal reset module determining a set reset state based on the test vector comprises:
responsive to generating a high level signal based on the test vector, the corresponding internal reset module is in a set state;
in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a reset state.
7. A method of reducing power consumption during a capture phase in a scan test according to claim 3, wherein the step of the corresponding internal reset module determining a set reset state based on the test vector comprises:
responsive to generating a high level signal based on the test vector, the corresponding internal reset module is in a reset state;
in response to generating a low level signal based on the test vector, the corresponding internal reset module is in a set state.
8. A method of reducing power consumption in a capture phase of a scan test as recited in claim 3, further comprising, prior to the scan data moving into phase:
acquiring the power consumption of the test circuit;
responsive to the power consumption being greater than a preset threshold, during the capture phase and the scan data shift-in phase, an output of a control register is configured as a low level signal;
in response to the power consumption being less than or equal to a preset threshold, the output of the control register is configured as a high level signal during the capture phase and the scan data shift-in phase.
9. A method of reducing power consumption in a capture phase of a scan test as recited in claim 3, further comprising, prior to the scan data moving into phase:
and carrying out combined configuration on the test modes corresponding to the internal reset modules in the test circuit so that the test modes corresponding to part of the internal reset modules do not overturn in the capturing stage.
10. A chip, characterized in that at least one functional module is integrated on the chip, said functional module comprising the test circuit according to claim 1 or 2.
11. A vehicle comprising the chip of claim 10.
12. An electronic device comprising a memory and a processor, wherein the memory has stored therein computer instructions, the processor being arranged to execute the instructions to perform the steps of the method of reducing power consumption in a capture phase of a scan test as claimed in any of claims 3 to 9.
13. A computer readable storage medium having stored thereon computer instructions which, when executed, perform the method of reducing power consumption in a capture phase of a scan test of any of claims 3-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310508664.8A CN116224045B (en) | 2023-05-08 | 2023-05-08 | Test circuit and method for reducing power consumption in capture stage in scanning test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310508664.8A CN116224045B (en) | 2023-05-08 | 2023-05-08 | Test circuit and method for reducing power consumption in capture stage in scanning test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116224045A CN116224045A (en) | 2023-06-06 |
| CN116224045B true CN116224045B (en) | 2023-08-15 |
Family
ID=86587648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310508664.8A Active CN116224045B (en) | 2023-05-08 | 2023-05-08 | Test circuit and method for reducing power consumption in capture stage in scanning test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116224045B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116773903B (en) * | 2023-06-14 | 2024-04-09 | 合芯科技有限公司 | Chip power consumption detection method and device, chip power consumption adjustment method and server |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101663648A (en) * | 2007-02-12 | 2010-03-03 | 明导公司 | Low power scan testing techniques and apparatus |
| CN103091620A (en) * | 2012-12-29 | 2013-05-08 | 江苏东大集成电路系统工程技术有限公司 | Optimization method of capturing power consumption in scan test |
| CN111610435A (en) * | 2020-05-22 | 2020-09-01 | Oppo广东移动通信有限公司 | Control circuit, chip and control method for controlling clock gating unit |
| CN114217211A (en) * | 2021-12-15 | 2022-03-22 | 四川创安微电子有限公司 | Circuit for reducing dynamic test power consumption of scan chain and control method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8890563B2 (en) * | 2008-05-07 | 2014-11-18 | Mentor Graphics Corporation | Scan cell use with reduced power consumption |
| US20130117618A1 (en) * | 2011-11-03 | 2013-05-09 | Freescale Semiconductor, Inc | Scan testing of integrated circuit with clock gating cells |
| US20150039956A1 (en) * | 2013-07-30 | 2015-02-05 | Stmicroelectronics Asia Pacific Pte. Ltd. | Test mux flip-flop cell for reduced scan shift and functional switching power consumption |
| US9599672B2 (en) * | 2014-12-11 | 2017-03-21 | Nxp Usa, Inc. | Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof |
| KR20160080586A (en) * | 2014-12-30 | 2016-07-08 | 삼성전자주식회사 | Method of designing an integrated circuit and computing system for designing an integrated circuit |
| WO2021134220A1 (en) * | 2019-12-30 | 2021-07-08 | 成都海光集成电路设计有限公司 | Chip, chip testing method and electronic device |
-
2023
- 2023-05-08 CN CN202310508664.8A patent/CN116224045B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101663648A (en) * | 2007-02-12 | 2010-03-03 | 明导公司 | Low power scan testing techniques and apparatus |
| CN103091620A (en) * | 2012-12-29 | 2013-05-08 | 江苏东大集成电路系统工程技术有限公司 | Optimization method of capturing power consumption in scan test |
| CN111610435A (en) * | 2020-05-22 | 2020-09-01 | Oppo广东移动通信有限公司 | Control circuit, chip and control method for controlling clock gating unit |
| CN114217211A (en) * | 2021-12-15 | 2022-03-22 | 四川创安微电子有限公司 | Circuit for reducing dynamic test power consumption of scan chain and control method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于MPU可测试性设计扫描测试方法研究;祝雪菲 等;电子器件;第38卷(第6期);1316-1320 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116224045A (en) | 2023-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6937493B2 (en) | Programming flash memory via a boundary scan register | |
| TWI460449B (en) | Method,apparatus and computer-readable medium for testing an integrated circuit | |
| US7082559B2 (en) | Semiconductor integrated circuit device and test method thereof | |
| US8332698B2 (en) | Scan latch with phase-free scan enable | |
| US9897653B2 (en) | Scan chain circuit supporting logic self test pattern injection during run time | |
| US6788105B2 (en) | Semiconductor integrated circuit | |
| US9322876B2 (en) | Control test point for timing stability during scan capture | |
| CN116224045B (en) | Test circuit and method for reducing power consumption in capture stage in scanning test | |
| KR100790428B1 (en) | Asynchronous reset circuit testing | |
| US20050235184A1 (en) | Semiconductor integrated circuit device and test method thereof | |
| US20110066906A1 (en) | Pulse Triggered Latches with Scan Functionality | |
| US20130311843A1 (en) | Scan controller configured to control signal values applied to signal lines of circuit core input interface | |
| US7484154B2 (en) | Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same | |
| US10520550B2 (en) | Reconfigurable scan network defect diagnosis | |
| US11307251B1 (en) | Circuit and testing circuit thereof | |
| US20050166109A1 (en) | Enhanced JTAG interface | |
| US7032147B2 (en) | Boundary scan circuit | |
| US20080195907A1 (en) | Circuit Arrangement and Method of Testing an Application Circuit Provided in Said Circuit Arrangement | |
| US7725792B2 (en) | Dual-path, multimode sequential storage element | |
| US20090135961A1 (en) | System and Method for Scanning Sequential Logic Elements | |
| US5515517A (en) | Data processing device with test circuit | |
| US6381720B1 (en) | Test circuit and method for system logic | |
| KR100684548B1 (en) | Self function testable system-on-chip and method for the function test | |
| CN108152719B (en) | Scan cell for dual port memory applications | |
| JP2005257366A (en) | Semiconductor circuit device and scan test method concerning semiconductor circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |