JP2004111438A - Overvoltage protection circuit of mos gate element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely protect a high voltage large current MOS gate element against an overvoltage in a small capacity ZD (Zener diode). <P>SOLUTION: In an overvoltage protection circuit of the MOS gate element for protecting the MOS gate element constituted by connecting in parallel a plurality of MOS gate element chips 1-1, 1-2, 1-3 and 1-4 in a package against the overvoltage, the Zener diode 2 is connected between a collector and a gate of the partial MOS gate element chip 1-1, and a collector and an emitter of the partial MOS gate element chip 1-1 are respectively connected to collectors and gates of the residual MOS gate elements 1-2, 1-3 and 1-4. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit for protecting a high-voltage, large-current MOS gate element such as an IGBT or an IEGT from overvoltage, and in particular, a small-capacity zener diode can reliably protect a high-voltage, large-current MOS gate element from overvoltage. The present invention relates to an overvoltage protection circuit for a MOS gate element as described above.
[0002]
[Prior art]
Recently, a high-voltage, large-current MOS gate device, for example, a high-voltage, large-current IGBT, has been implemented by connecting a plurality of MOS gate device chips in a package in parallel to realize a large-capacity IGBT. I have.
[0003]
Conventionally, such overvoltage protection of the IGBT is realized by connecting a zener diode (hereinafter referred to as ZD) between the collector and the emitter.
[0004]
FIG. 5 is a circuit diagram showing a configuration example of such a conventional MOS gate element overvoltage protection circuit.
[0005]
FIG. 5 shows an example in which there are three MOS gate element chips (here, three IGBTs 1-2, 1-3, 1-4).
[0006]
In FIG. 5, three IGBT chips 1-2, 1-3, and 1-4 are connected in parallel in the same package to form an IGBT.
[0007]
Further, as shown in FIG. 5, ZD2 is commonly connected between the collector and the emitter of each of the IGBT chips 1-2, 1-3 and 1-4 with the illustrated polarity.
[0008]
In this case, when an overvoltage occurs between the collector and the emitter of the IGBTs 1-2, 1-3 and 1-4, ZD2 turns on and its zener current becomes the gate current of the IGBTs 1-2, 1-3 and 1-4. , IGBTs 1-2, 1-3, 1-4 operate in an active region in which current flows while maintaining the voltage set by ZD2.
[0009]
That is, the IGBTs 1-2, 1-3, and 1-4 are protected from overvoltage breakdown by turning on themselves at a voltage of ZD2 setting lower than the voltage at which overvoltage breakdown occurs.
[0010]
[Problems to be solved by the invention]
However, the conventional MOS gate element overvoltage protection circuit as described above has the following problems.
[0011]
That is, as shown in FIG. 5, the IGBT is configured by connecting a plurality of IGBT chips 1-2, 1-3, and 1-4 in the same package in parallel, and when the IGBT has a high voltage and a large capacity, The gate current for driving the gates of these IGBT chips 1-2, 1-3, 1-4 increases.
[0012]
Therefore, since the ZD2 current is large and the ZD2 voltage is high, the capacity of ZD2 also becomes very large.
[0013]
However, finding such a large capacity ZD2 is extremely difficult.
[0014]
Therefore, it is conceivable to connect a plurality of ZD2s in series in order to increase the voltage. However, there is a problem that the voltage balance is not correct and the set voltage cannot be set accurately.
[0015]
The large capacity ZD2 also has problems such as poor temperature characteristics.
[0016]
An object of the present invention is to provide a MOS gate element overvoltage protection circuit that can reliably protect a high-voltage, large-current MOS gate element from overvoltage with a small capacity ZD.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, in the invention according to claim 1, a MOS gate element overvoltage protection circuit for protecting a MOS gate element formed by connecting a plurality of MOS gate element chips in a package in parallel from overvoltage. , A zener diode is connected between the collector and the gate of some of the MOS gate element chips, and the collector and the emitter of the above some MOS gate element chips are connected to the collector and the gate of the remaining MOS gate element chips, respectively. are doing.
[0018]
Accordingly, in the MOS gate element overvoltage protection circuit according to the first aspect of the present invention, a Zener diode is connected between the collector and the gate of some of the MOS gate element chips, and the collector and the collector of the remaining MOS gate element chips are connected. By connecting the collector and the emitter of some MOS gate element chips to the gates, respectively, instead of driving all the MOS gate element chips directly with zener diodes, using some MOS gate element chips Since it is only necessary to amplify the zener diode current once and then drive the remaining MOS gate element chip by a gate, a smaller current is required than in the conventional case. Can be protected reliably.
[0019]
According to a second aspect of the present invention, in the overvoltage protection circuit for a MOS gate element according to the first aspect of the present invention, the zener diode is mounted outside the package of the MOS gate element.
[0020]
According to a third aspect of the present invention, in the overvoltage protection circuit for a MOS gate element according to the second aspect of the present invention, the package includes a press-contact type MOS gate element or a module type MOS gate element package. I am trying to do it.
[0021]
Therefore, in the overvoltage protection circuit for the MOS gate element according to the second and third aspects of the present invention, the zener diode is attached to the outside of the package of the press-contact type or module type MOS gate element. The setting of the protection voltage value can be arbitrarily and easily changed.
[0022]
On the other hand, according to a fourth aspect of the present invention, in the overvoltage protection circuit for a MOS gate element according to the first aspect of the present invention, the remaining MOS gate element chips are arranged at coolable positions.
[0023]
Therefore, in the MOS gate element overvoltage protection circuit according to the fourth aspect of the present invention, the remaining MOS gate element chips to which the zener diode is not connected are arranged at coolable positions, so that the zener diode can be cooled. Since the MOS gate element chip which receives the overvoltage signal first and amplifies the signal does not need to be cooled, it can be arranged in a position where cooling is not possible. Design can be easily performed.
[0024]
According to a fifth aspect of the present invention, in the overvoltage protection circuit for a MOS gate element according to the first aspect of the present invention, an overvoltage operation detecting means for detecting that the zener diode has performed an overvoltage operation; When the overvoltage operation of the zener diode is detected by the means, a cutoff means for cutting off the supply of power to the MOS gate element is added.
[0025]
Therefore, in the overvoltage protection circuit for a MOS gate element according to the invention, since the MOS gate element is used in the active region, the load is large and the operation cannot be performed for a long time. When the Zener diode detects that the overvoltage operation has been detected, the power supply applied to the MOS gate element is cut off, thereby preventing the MOS gate element from being destroyed by heat generated by the activation region operation. The element can be reliably protected from overvoltage.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the present invention, in a MOS gate element configured by connecting a plurality of MOS gate element chips in a package in parallel, not all the MOS gate element chips are directly driven by ZD, but some of the MOS gate element chips are driven. The present invention is characterized in that the ZD current is once amplified by using the same, and then the remaining MOS gate element chips are gate-driven.
[0027]
Further, in order to easily change the setting of the voltage value of the overvoltage, a ZD serving as a setting unit is provided outside the package.
[0028]
On the other hand, the MOS gate element chip which receives the ZD overvoltage signal first and amplifies the signal does not need to be cooled, so that it can be arranged at a position where cooling is not possible.
[0029]
In addition, since this overvoltage protection uses a MOS gate element in an active region, the burden is large and the operation cannot be performed for a long time. Therefore, it is detected that this overvoltage protection has been activated, and a power supply applied to the MOS gate element is applied. I try to cut off.
[0030]
Hereinafter, embodiments of the present invention based on the above-described concept will be described in detail with reference to the drawings.
[0031]
(First Embodiment)
FIG. 1 is a circuit diagram showing a configuration example of an overvoltage protection circuit of a MOS gate element according to the present embodiment, and the same elements as those in FIG. 5 are denoted by the same reference numerals.
[0032]
FIG. 5 shows an example in which there are four MOS gate element chips.
[0033]
In FIG. 1, for example, four IGBT chips 1-1, 1-2, 1-3, and 1-4 as MOS gate elements are connected in parallel in the same package to form an IGBT.
[0034]
Further, ZD2 is connected between the collector and the emitter of some IGBT chips 1-1 with the polarity shown.
[0035]
Here, the voltage value of ZD2 is lower than the overvoltage breakdown voltage of the IGBT.
[0036]
Further, the collectors and emitters of the remaining IGBT chips 1-2, 1-3, and 1-4 are connected in parallel, so that the collectors of some of the IGBT chips 1-1 and the remaining IGBT chips 1-2,1- The collectors of the IGBT chips 3-1, 1-4 are connected, and the emitters of some IGBT chips 1-1 are connected to the gates of the remaining IGBT chips 1-2, 1-3, 1-4.
[0037]
Next, the operation of the MOS gate element overvoltage protection circuit according to the present embodiment configured as described above will be described.
[0038]
In FIG. 1, when an overvoltage is applied to the IGBT, when the voltage reaches the ZD voltage of ZD2, a ZD current flows, a current flows to the gate of the IGBT chip 1-1, and the IGBT1-1 chip is activated in the active region. Is turned on.
[0039]
Therefore, a collector current flows through the IGBT chip 1-1, and this current becomes a gate current of the IGBT chips 1-2, 1-3, 1-4, and the IGBT chips 1-2, 1-3, 1-4. Is turned on in the activation region, and the voltage between the collector and the emitter of the IGBT maintains the voltage set by ZD2 and escapes from overvoltage destruction.
[0040]
Therefore, in the configuration as in the present embodiment, the ZD2 only needs to drive the gate of the IGBT chip 1-1, so that a current as small as 1/3 of the conventional case can be used. IGBT can be reliably protected from overvoltage by ZD2.
[0041]
As described above, in the overvoltage protection circuit for the MOS gate element according to the present embodiment, it is possible to reliably protect the IGBT, which is a high-voltage, large-current MOS gate element, from overvoltage with a small capacity ZD2.
[0042]
(Second embodiment)
The MOS gate element overvoltage protection circuit according to the present embodiment is configured such that the ZD2 is attached to the outside of the MOS gate element package in the MOS gate element overvoltage protection circuit according to the above-described first embodiment.
[0043]
Further, the remaining IGBT chips 1-2, 1-3, and 1-4, to which the ZD2 is not connected, are arranged at coolable positions.
[0044]
Here, the MOS gate element is a press-contact IGBT or a module IGBT, and the package is a press-contact IGBT or a module IGBT package.
[0045]
Next, the operation of the MOS gate element overvoltage protection circuit according to the present embodiment configured as described above will be described.
[0046]
The ZD2 may be housed in the package of the IGBT at the stage of manufacturing the IGBT which is a MOS gate element. However, when an application engineer such as an inverter designer wants to set an overvoltage protection voltage, Since the setting cannot be performed if the ZD2 is sealed in the package, by setting the mounting position of the ZD2 outside the package, the application technician can set the voltage value of the overvoltage setting. Changes can be made arbitrarily and easily.
[0047]
For example, when the withstand voltage of the load is lower than the withstand voltage of the MOS gate element, the overvoltage protection can be operated according to the withstand voltage of the load.
[0048]
On the other hand, the remaining IGBT chips 1-2, 1-3 and 1-4 need to be cooled in order to generate heat because they switch on and off the current and keep flowing the current.
[0049]
However, since some IGBT chips 1-1 operate instantaneously only when overvoltage occurs, there is no need for cooling. Therefore, the cooling arrangement of the IGBT chips 1-1, 1-2, 1-3, and 1-4 is changed. When performing, the IGBT chips 1-2 to 1-4 can be arranged at a position to be cooled, and the IGBT chip 1-1 can be arranged at an arbitrary position since cooling is unnecessary.
[0050]
As a result, the arrangement of the IGBT chips 1-1, 1-2, 1-3, and 1-4 is arbitrary, and the package can be easily designed.
[0051]
FIG. 2 is a circuit diagram showing a specific configuration example of the MOS gate element overvoltage protection circuit according to the present embodiment. The same parts as those in FIG. Now, only the different parts will be described.
[0052]
FIG. 2 shows an example in which the MOS gate element is a press-contact type IGBT.
[0053]
In FIG. 2, reference numeral 8 denotes a package for a press-contact IGBT.
[0054]
Reference numeral 5 denotes a heat sink for cooling the IGBT chip which also serves as a collector electrode.
[0055]
Reference numeral 6 denotes a heat sink also serving as an emitter electrode.
[0056]
The ZD 2 is arranged outside the press-contact type IGBT package 8 so that an application engineer can arbitrarily select a voltage value of overvoltage protection in accordance with protection coordination regarding overvoltage of the system.
[0057]
Reference numeral 7 denotes an insulator made of a material having poor heat conductivity.
[0058]
The insulator 7 connects the emitter of the IGBT 1-1 to the gates of the IGBTs 1-2, 1-3, 1-4, but does not connect the collector.
[0059]
On the other hand, since the IGBT 1-1 operates only at the time of overvoltage, there is no need for cooling, and there is no problem even if the insulator 7 has poor heat conduction.
[0060]
Although the insulator 7 usually has poor heat conduction, it is not necessary to cool the IGBT 1-1. Therefore, the insulator of the IGBT 1-1 and the IGBTs 1-2, 1-3 and 1-4 are formed by using a normal insulator. It becomes easy to connect to the gate.
[0061]
Of course, there is no problem even if the insulator 7 is electrically insulated and has good heat conduction.
[0062]
FIG. 3 is a circuit diagram showing another specific configuration example of the MOS gate element overvoltage protection circuit according to the present embodiment. The same parts as those in FIG. Here, only the different parts will be described.
[0063]
FIG. 3 shows an example in which the MOS gate element is a module type IGBT.
[0064]
In FIG. 3, reference numeral 9 denotes a package for a module type IGBT.
[0065]
Reference numeral 10 denotes a heat sink for cooling the IGBT chip, which also serves as an emitter electrode.
[0066]
Reference numeral 11 denotes a heat sink also serving as a collector electrode.
[0067]
12 is a wire bonding.
[0068]
The ZD 2 is disposed outside the module type IGBT package 9 so that an application engineer can arbitrarily select a voltage value of overvoltage protection in accordance with protection coordination regarding overvoltage of the system.
[0069]
The heat sink 10 for cooling the IGBT chip also serving as the emitter electrode is a heat sink for cooling, but the IGBTs 1-2, 1-3, and 1-4 that generate heat need to be cooled. Since there is no need for cooling, it can be placed at any location irrespective of cooling, so that the package can be easily designed.
[0070]
As described above, in the overvoltage protection circuit of the MOS gate element according to the present embodiment, the setting of the voltage value for overvoltage protection can be arbitrarily and easily changed.
[0071]
Further, the arrangement of the IGBT chip is arbitrary, and the package can be easily designed.
[0072]
(Third embodiment)
FIG. 4 is a circuit diagram showing a configuration example of the overvoltage protection circuit of the MOS gate element according to the present embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. Only mention.
[0073]
That is, as shown in FIG. 4, the MOS gate element overvoltage protection circuit according to the present embodiment includes a current detector (CT) 13 and a level detector 14 as overvoltage operation detection means, and a switch 15 as interruption means. Is added to the configuration of FIG.
[0074]
The current detector 13 detects the current of ZD2.
[0075]
When detecting that the ZD2 current detected by the current detector 13 has reached a set value or more, the level detector 14 detects that the ZD2 has performed an overvoltage operation.
[0076]
When an overvoltage operation of ZD2 is detected by the current detector 13 and the level detector 14, the switch 15 is opened to cut off the supply of the power supply 16 to the IGBT.
[0077]
Next, the operation of the MOS gate element overvoltage protection circuit according to the present embodiment configured as described above will be described.
[0078]
In order to protect the IGBT, which is a MOS gate element, from overvoltage, the IGBT is operated in the activation region. The operation of the activation region is performed because a high voltage and a large current are simultaneously applied to the IGBT. Since the generated loss has an abnormally large value, it must be stopped in a short time.
[0079]
For that purpose, it is necessary to detect that the IGBT is operating at an overvoltage and to cut off the power supply to the IGBT.
[0080]
That is, in order to detect that the IGBT is performing an overvoltage operation, it is sufficient to detect that a current has flowed through ZD2.
[0081]
In this regard, in the present embodiment, when the ZD2 current is detected by the current detector 13 and the level detector 14 detects that the current has reached the set value or more to prevent malfunction, it is determined that the overvoltage prevention operation has been activated and the IGBT By opening the switch 15 between the power supply 16 and the power supply 16, the application of the voltage to the IGBT is cut off.
[0082]
As a result, the IGBT, which is a MOS gate element, can be prevented from being destroyed by heat due to the activation region operation, and the IGBT can be reliably protected from overvoltage.
[0083]
As described above, in the overvoltage protection circuit for the MOS gate element according to the present embodiment, the IGBT that is the MOS gate element can be prevented from being destroyed by heat generated by the activation region operation, and the IGBT can be reliably protected from overvoltage. It becomes possible.
[0084]
(Other embodiments)
It should be noted that the present invention is not limited to the above embodiments, and can be variously modified and implemented in an implementation stage without departing from the scope of the invention.
In each of the above-described embodiments, the case where the present invention is applied to the MOS gate element having one MOS gate element chip and three remaining MOS gate element chips has been described. However, the present invention is not limited to this. For example, the present invention is similarly applied to a MOS gate element in which a part of the MOS gate element chips is two or three and the remaining MOS gate element chips are twenty or thirty, and the same as in the case described above. It is possible to achieve the function and effect.
[0085]
In addition, the embodiments may be combined as appropriate as much as possible, and in that case, the combined effects can be obtained.
Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features.
For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and the effects of the invention can be solved. In the case where (at least one of) the effects described in the section is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
[0086]
【The invention's effect】
As described above, according to the MOS gate element overvoltage protection circuit of the present invention, a small-capacity ZD can reliably protect a high-voltage, large-current MOS gate element from overvoltage.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of an overvoltage protection circuit for a MOS gate element according to the present invention.
FIG. 2 is a circuit diagram showing an example of a second embodiment of an overvoltage protection circuit for a MOS gate element according to the present invention.
FIG. 3 is a circuit diagram showing another example of the second embodiment of the MOS gate element overvoltage protection circuit according to the present invention.
FIG. 4 is a circuit diagram showing a third embodiment of an overvoltage protection circuit for a MOS gate element according to the present invention.
FIG. 5 is a circuit diagram showing a configuration example of a conventional MOS gate element overvoltage protection circuit.
[Explanation of symbols]
1-1, 1-2, 1-3, 1-4 IGBT chip 2 ZD for determining overvoltage set value
Reference Signs List 5: Heat sink also serving as collector electrode 6: Heat sink also serving as emitter electrode 7: Insulator 8 ... Package for press-contact type IGBT 9 Detector (CT)
14 level detector 15 switch 16 power supply

Claims (5)

In a MOS gate element overvoltage protection circuit for protecting a MOS gate element formed by connecting a plurality of MOS gate element chips in parallel in a package from overvoltage,
A zener diode is connected between the collector and the gate of some of the MOS gate element chips,
An overvoltage protection circuit for a MOS gate element, wherein a collector and an emitter of the partial MOS gate element chip are connected to a collector and a gate of the remaining MOS gate element chip, respectively. 2. The MOS gate element overvoltage protection circuit according to claim 1,
An overvoltage protection circuit for a MOS gate element, wherein the zener diode is mounted outside a package of the MOS gate element. 3. The MOS gate element overvoltage protection circuit according to claim 2,
An overvoltage protection circuit for a MOS gate element, wherein the package is a press-contact type MOS gate element or a module type MOS gate element. 2. The MOS gate element overvoltage protection circuit according to claim 1,
An overvoltage protection circuit for a MOS gate element, wherein the remaining MOS gate element chips are arranged at coolable positions. 2. The MOS gate element overvoltage protection circuit according to claim 1,
Overvoltage operation detecting means for detecting that the Zener diode has performed an overvoltage operation,
When an overvoltage operation of the zener diode is detected by the overvoltage operation detection unit, a shutoff unit that shuts off power supply to the MOS gate element;
And an overvoltage protection circuit for a MOS gate element.

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