JP2004094261A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption while securing display of minimum allowable quality at the time of standby in a liquid crystal display. <P>SOLUTION: A voltage control part 6 generate a plurality of kinds of voltage for gradation display. A signal driving circuit 1 generates signal voltage with amplitude according to gradation specified by image data to be inputted via an interface circuit 7 by using the voltage for gradation display generated by the voltage control part and applies the signal voltage to a liquid crystal matrix panel 2. When the standby is instructed via the interface circuit 7, the voltage control part 6 makes a value of the voltage for gradation display to be generated small. In this display device, the amplitude of the signal voltage to be applied to the liquid crystal matrix panel 2 is made small, the power consumption is reduced and display of minimum allowable quality is secured at the time of standby. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a liquid crystal display device, and particularly to a technique for reducing power consumption in a standby state.

(4) Liquid crystal display devices are thinner and lighter than CRTs and the like, and have low power consumption, so that they are widely used in portable information devices and the like that operate on the power supplied by a battery.

However, it is desired that such portable information devices have a longer operable time by a battery. On the other hand, there is a demand for further downsizing of portable information devices, and for this purpose, batteries also need to be downsized.

In order to realize such a proposition, it is desirable to reduce the power consumption of a liquid crystal display device used for information equipment.

Here, as a conventional technique for reducing the power consumption of a liquid crystal display device, for example, when the keyboard or the like is not operated for a long time by a personal computer, that is, when the device is in a standby state, A technique for shutting off a power supply is known.

Although not related to a liquid crystal display device, as described in NIKKEI ELECTRONICS NO590 (issued on September 13, 1993), in a display device using a CRT, a deflection circuit or 2. Description of the Related Art There is known a technique for cutting off power supply to a high-voltage circuit to reduce power consumption of a device.

According to the techniques for reducing the power consumption during the standby, the display of the display device is not performed in the standby state, so that the state of the information device at that time cannot be visually recognized.

Therefore, an object of the present invention is to provide a liquid crystal display device that can perform display with low power consumption in a standby state.

In order to achieve the above object, according to the present invention, during a period in which a standby is instructed, the signal driving unit includes, for each of a plurality of scanning periods, each of the liquid crystal cells among the liquid crystal cells of a column to which the liquid crystal cell belongs. A method of applying and holding a signal voltage corresponding to the content to be commonly displayed on a plurality of liquid crystal cells on a plurality of lines to which the scanning voltage is applied during the scanning period. provide.

In order to achieve the above object, according to the present invention, during a period in which the standby is instructed, the signal driver has a signal voltage having an amplitude smaller than that in the non-standby state and is determined according to a gray scale to be displayed. Provided is a method for reducing power consumption of a liquid crystal display device, wherein an oscillation voltage having an amplitude is applied and held.

According to the power consumption reduction method of the present invention, the current flowing into and out of the liquid crystal matrix panel is reduced by lengthening the change period of the signal voltage applied to the liquid crystal matrix panel or reducing the voltage level of the signal voltage. As a result, power consumption is reduced. Further, even if the change period of the signal voltage is lengthened or the voltage level of the signal voltage is reduced, a display that can be visually recognized by the user is secured. You can see the status of the device. In this case, the quality of display deteriorates during the standby state period, but since the standby state is a period during which the user does not use, there is no problem in use.

As described above, according to the present invention, the present invention can provide a liquid crystal display device capable of performing display with low power consumption in a standby state.

Hereinafter, embodiments of the information equipment according to the present invention will be described.

First, the configuration and operation of an information device and a liquid crystal display device that are common to the embodiments presented below will be described.

FIG. 1 shows the appearance of the information device according to the present embodiment.

In the figure, 1000 is an information device, 2 is a display unit of a liquid crystal display device, 3000 is a floppy disk insertion slot of a floppy disk driver, 4000 is an input pen, 5000 is a key switch group, 6000 is a power save switch, and 7000. Is a power switch. As illustrated, the liquid crystal display device is incorporated in the information device 1000.

FIG. 2 shows the internal configuration of the information device 1.

In the figure, 1001 is a CPU, 1002 is a ROM storing a program to be executed by the CPU 1, 1003 is a RAM used for executing the program, 1004 is a battery, 10 is a liquid crystal display device, 1005 is a liquid crystal for controlling the display of the liquid crystal display device. A display device, 1006 is a V-RAM for storing data defining display contents to be displayed on the display device, 1007 is an interface circuit between the power save switch 6000 and key switch group 5000, etc., and 1008 is a floppy disk. An interface circuit with the disk drive; 1009, an interface circuit for the control signal 2003 with the display controller 10; 1010, an interface circuit with the input pen 4000;

The liquid crystal display device 10 includes the display unit 2, the light source 4, and the drive control circuit 2005.

Now, in such a configuration, when the input pen 4000 is placed on the display unit 2, the input pen 4000 detects coordinates on the display unit 2, for example, by detecting a voltage applied to the display unit 2. .

Further, the CPU 1001 executes a program in accordance with the coordinates detected by the input pen 4000 and an input of a key of the key switch group 5000, and displays the contents displayed on the display unit 2 of the liquid crystal display device 10 in accordance with the execution result. Then, the image data defining the display contents is written to the V-RAM 1006. The display control device 1005 sends the image data 2002 stored in the V-RAM 1006 to the liquid crystal display device 10 together with a synchronization signal group 2001 necessary for display on the liquid crystal display device 10.

Further, the CPU 1001 detects that the power save switch 6 is turned on via the interface circuit 1007, or detects the coordinates of the input pen 4 or the key switch group 5000 for a certain period or more. Is detected, the power save control signal 2003 for instructing the shift to the power save mode is sent to the liquid crystal display device 10 via the interface circuit 1009. .

When the power switch is turned on, the battery 1004 supplies power of a predetermined voltage to each part of the information device 1000 including the liquid crystal display device 10.

Next, FIG. 3 shows an internal configuration of the liquid crystal display device 10.

As shown in the figure, it is composed of a signal drive circuit 1, a scan drive circuit 3, a display control circuit 5, a voltage control circuit 6, a light source 4, an interface circuit 7, and a display unit 2. The signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, and the interface circuit 7 correspond to the drive control circuit 2005 shown in FIG.

In this embodiment, a liquid crystal matrix panel is assumed as the display unit 2. As shown in FIG. 4, one pixel of the liquid crystal matrix panel 2 includes a TFT (thin film transistor) 13 and a liquid crystal 14. The scanning lines 12a to 12d are connected to the gate electrode of the TFT 13, and the signal lines 11a to 11c are connected to the drain electrode.

The image data 2002 to be displayed on the display unit 2 is input from the display control device 1005 to the interface circuit 7. A vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal synchronized with the image data 2002 are input as the synchronizing signals included in the synchronizing signal group 2001, and a power-save control signal 2003 is transmitted through an interface circuit 1009. It is input from the CPU 1001. Here, the image data 2002 is input in an order according to the raster scan method. The vertical synchronizing signal is a pulse signal output every one frame period of an image to be displayed, and the horizontal synchronizing signal is a pulse signal output every one line scanning period.

(4) The interface circuit 7 passes these signals to the display control circuit 5.

From the image data 2002, the synchronization signal 2001, and the power save control signal 2003, the display control circuit 5 converts the image data DATA, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the power -Generate a save control signal PS, send the generated vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, clock signal DCLK, and image data DATA to the signal drive circuit 1, and send the horizontal synchronization signal HSYNC, A vertical synchronization signal VSYNC is sent, a synchronization signal (one or both of VSYNC and HSYNC) necessary for realizing a polarity inversion driving method described later and a clock signal DCLK are sent to the voltage control circuit 6, and the voltage control circuit 6 A power control signal PS is sent to the circuit 1, the scanning drive circuit 3, and the light source 4.

However, in some embodiments described below, it may not be necessary to send some signals.

FIG. 5 shows the timings of the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the clock signal DCLK, and the image data DATA in the normal mode (in the non-power save operation mode) (FIG. 5A). The correspondence of the display screen (FIG. 5B) defined by this is shown below. The timing shown in FIG. 5A coincides with the timing of the vertical synchronizing signal, the horizontal synchronizing signal, the clock signal, and the image data input to the interface circuit 7.

Now, the voltage control circuit 6 generates a scan drive voltage using the power supplied from the battery 1004 and sends it to the scan drive circuit 3. Further, a signal driving voltage is generated and sent to the signal driving circuit 1.

As shown in FIG. 6, the scan drive circuit 3 synchronizes with the horizontal synchronization signal HSYNC and sequentially applies different scan lines 12 a to 12 d in the order of the arrangement in accordance with the scan drive voltage sent from the voltage control circuit 6. Applied scanning voltages Vg1 to Vgn. Further, every time the vertical synchronization signal VSYNC is input, the above operation from the first scanning line 12a is repeated. That is, the scanning voltage sequentially becomes the value Vgh for each line, and the TFT is turned on for each line.

On the other hand, the signal drive circuit 1 includes two groups of latches that can store one line of image data. In addition, the same number of output circuits as the number of image data for one line connected to the signal lines 11a to 11c are provided. The first latch group sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and synchronizes the latched one line of image data DATA with the second latch group in synchronization with the horizontal synchronization signal HSYNC. The image data for one line is transferred in parallel, the transferred image data for one line is held until the transfer of the image data for the next line is received, and output to different output circuits in parallel. During this time, the first latch group sequentially takes in the image data of the next line in the same manner as the previous line. As a result, signal voltages Vd1 to Vdm are applied as shown in FIG.

(4) Each output circuit applies the signal voltages Vd1 to Vdm to the connected signal lines according to the value of the received image data and the signal driving voltage sent from the voltage control circuit 6.

The configuration and operation of the information device and the liquid crystal display device common to the embodiments presented in this embodiment have been described above. Hereinafter, embodiments of the liquid crystal display device 10 having such a configuration for reducing power consumption while ensuring display will be described.

First, the first embodiment will be described.

In the first embodiment, when the display control device 5 receives the power save signal from the interface circuit 7, the display control device 5 sets the cycle of the output horizontal synchronization signal HSYNC to twice that in the normal mode, and A power save operation mode is instructed to the scanning drive circuit 3 and the signal drive circuit 1 by the power save signal PS. Note that such a change in the cycle of the horizontal synchronization signal HSYNC is performed by changing the frequency of the horizontal synchronization signal HSYNC to be output to the display control circuit 8 when the power save signal PS indicates ON, as described later. The frequency dividing circuit can be realized by providing a frequency dividing circuit for dividing the frequency of the horizontal synchronizing signal inputted from the source circuit 7 into half. Alternatively, when the power save signal PS indicates ON, the signal is phase-synchronized with the horizontal synchronizing signal input from the interface circuit 7 and a signal having a half frequency thereof is output as the horizontal synchronizing signal HSYNC. An oscillator may be provided.

As shown in FIG. 7, the scan drive circuit 3 sequentially applies two scan signals, such as Vg1 and Vg2, and Vg3 and Vg4, for each cycle of the horizontal synchronization signal HSYNC output from the display control circuit 3. Apply the value Vgh. The application of the scanning voltage for each of the two scanning signals is performed by, for example, counting the number of the output circuits corresponding to the number of the scanning signals connected to the different scanning signal lines and the number of the HSYNCs to the scanning drive circuit 3, and resetting by the VSYNC. And a decoder for decoding the count value of the counter in accordance with the value of the power save signal PS, and the output circuits are sequentially activated in accordance with the decoder value of the decoder. It can be realized by making it. Here, the output circuit is a circuit that outputs a scan voltage supplied from the voltage control circuit 6 to a corresponding scan signal line when the output circuit is activated.

On the other hand, in the signal drive circuit 1, when the first latch group becomes full by taking in the image data of the odd-numbered line, the operation of discarding the input image data of the even-numbered line is repeated. The image data of the odd-numbered line captured by the first latch group is captured by the second latch group by the horizontal synchronization signal HSYNC input at the end of the input of the image data of the next even-numbered line. The signal is held up to the input of the horizontal synchronization signal HSYNC and output to the output circuit. As a result, the voltage applied to each signal line is updated at twice the period of the normal mode.

に す る Thus, the period during which the TFT of the liquid crystal matrix 2 is turned on is doubled. In addition, the period at which the levels of the signal voltages Vd1 to Vdm change also doubles accordingly. Accordingly, power consumption of the liquid crystal matrix 2, the signal drive circuit, the voltage control circuit 6, and the like can be reduced.

On the other hand, the resolution of the image displayed on the liquid crystal matrix 2 is １ ／ of that in the normal mode in the vertical direction, but in the power save mode, the period during which the user is not working. Therefore, there is no practical problem.

The display control circuit 8 outputs the input signals from the interface circuit 7 as they are for the vertical synchronization signal VSYNC, the operation clock DCLK, and the image data DATA.

As shown in FIG. 8, even during the power save mode, the scanning voltages Vg1, Vg2. . Is applied in the same manner as in the normal mode, and only the signal voltage is changed every two lines by the display control circuit 5 doubling only the period of the horizontal synchronizing signal HSYNC given to the signal drive circuit 1. You may do so. Also in this case, the cycle in which the level of the signal voltage changes can be doubled, and substantially the same effect as in the first embodiment can be achieved.

Further, the cycle of the clock signal DCLK is doubled, and in the signal drive circuit 1, the image data is fetched into the first latch group every other pixel data, and the image data is transferred from the n-th latch of the first latch group to the second latch group. Data may be transferred in parallel to the (2n-1) -th and 2n-th latches of the latch group in synchronization with the horizontal synchronization signal HSYNC. Such a change of the cycle of the clock signal DCLK is performed by inputting the frequency of the clock signal DCLK to be output from the interface circuit 7 to the display control circuit 8 when the power save signal PS indicates ON. This can be realized by providing a frequency dividing circuit for dividing the frequency of the operation clock signal to. Of course, an oscillator may be provided which generates a clock having a frequency which is half the frequency of the operation clock signal input from the interface circuit 7 in phase with the operation clock signal input from the interface circuit 7. Good.

In this case, the resolution in the horizontal direction of the display is also reduced to 、. However, as described above, in the power save mode, there is a practical problem since the user is not working. It will not be. Further, since the operating frequency of the first latch group of the signal drive circuit 1 is の of that in the normal mode, power consumption can be reduced.

In the present embodiment, the driving / operating frequency of the scanning drive circuit 3 and the signal drive circuit 1 is changed to 1/2 in the power save mode. The ratio may be used.

Hereinafter, a second embodiment will be described.

In the first embodiment, the driving / operating frequency of the scanning drive circuit 3 and the signal drive circuit 1 is reduced, and the resolution of the image displayed by the image data input to the interface circuit 7 is reduced to display the image. Reduced power. In this embodiment, in the power save mode, a predetermined image is generated by a built-in pattern generator without using the image data input to the interface circuit 7, and is displayed.

FIG. 9 shows the configuration of the display control circuit 5 according to the second embodiment.

As shown in the figure, in the second embodiment, the display control circuit 5 includes a selection circuit group 19 including selection circuits 19a to 19d, an oscillation circuit 22, a pattern generator 20, and a control circuit 21.

The control circuit 21 uses the basic clock output from the oscillation circuit 22 to generate three signals VSYNC (equal in frequency ratio between the direct synchronizing signal, the horizontal synchronizing signal, and the operating clock input from the interface circuit). IN), HSYNC (IN), and DCLK (IN). The pattern generator 20 is actually a memory storing image data, and outputs, for example, image data indicating a predetermined image pattern as shown in FIG. 10 in synchronization with DCLK (IN). I do.

In the normal mode, the selection circuits 19a to 19d output the vertical synchronizing signal, the horizontal synchronizing signal, the operation clock and the image data input from the interface circuit 7 as VSYNC, HSYNC, DCLK and DATA as they are, and In the save mode, the timing signals VSYNC (IN), HSYNC (IN), and DCLK (IN) input from the control circuit 21 are output as VSYNC, HSYNC, and DCLK, and the pattern generator 20 Is output as DATA.

Here, the frequency of VSYNC (IN), HSYNC (IN), and DCLK (IN) output from the control circuit 21 is based on the frequency of the direct synchronization signal, horizontal synchronization signal, and operation clock input from the interface circuit. It is possible to use a frequency as small as not to significantly impair the visibility of the display of the liquid crystal matrix 2. Accordingly, since the driving / operating frequency of each unit can be made smaller than that in the normal mode, power consumption can be reduced.

It should be noted that among VSYNC (IN), HSYNC (IN) and DCLK (IN) output from the control circuit 21, a horizontal synchronizing signal input from the interface circuit 7 for HSYNC (IN) and DCLK (IN), operation The frequency ratio with respect to the clock is set to, for example, 1/2 of the frequency ratio with respect to the vertical synchronizing signal input from the VSYNC (IN) interface circuit 7, and the scanning drive circuit 3 performs the same operation as in the first embodiment (see FIG. 7). If two scanning signal lines are driven at a time, the resolution in the vertical direction will be １ ／ of that in the normal mode, but the scanning driving circuit 3 and the signal driving circuit 1 are similar to those shown in FIG. Can further reduce the driving / operating frequency and can further reduce power consumption. In this case, the pattern generator 20 stores image data in which the image to be displayed is reduced in half in the vertical direction in advance.

Alternatively, at the time of the power save mode, the frequency ratio between the horizontal synchronizing signal input from the interface circuit 7 of HSYNC (IN) and DCLK (IN) to the signal driving circuit 1 and the frequency of the operation clock is VSYNC (IN If the frequency ratio with respect to the vertical synchronizing signal input from the interface circuit 7) is, for example, 1/2, the driving / operation of the signal driving circuit 1 is the same as that shown in FIG. 8 in the first embodiment. The frequency can be reduced, and the power consumption can be further reduced. Also in this case, the pattern generator 20 stores in advance image data obtained by reducing the image to be displayed by half in the vertical direction.

Further, the frequency ratio of the DCLK (IN) to the operation clock input from the interface circuit 7 is set to, for example, 1/2 of the frequency ratio to the horizontal synchronization signal input from the interface circuit 7 of the HSYNC (IN). As described above, in the signal driving circuit 1, the image data is fetched into the first latch group every other pixel data, and the nth latch of the first latch group to the (2n-1) th latch of the second latch group. If the data is transferred in parallel to the 2n-th latch in synchronization with the horizontal synchronization signal HSYNC (IN), the horizontal direction and the resolution are reduced to half those in the normal mode. The driving / operating frequency of the circuit 1 can be further reduced, and the power consumption can be further reduced. In this case, the pattern generator 20 stores in advance image data in which the image to be displayed is reduced by half in the vertical and horizontal directions.

As described above, in the second embodiment, in the power save operation mode, a predetermined image pattern as shown in FIG. 10 is displayed. By sequentially shifting the generation timings of the timing signals HSYNC (IN), VSYNC (IN), and DCLK (IN) with respect to the read timing of the image pattern, the image pattern moves on the display screen. By doing so, the user can easily recognize the power save state. In addition, it is possible to reduce deterioration in image quality such as a change in brightness and an afterimage caused by a change in characteristics of a film constituting a TFT or a change in characteristics of a liquid crystal material caused by displaying at the same position for a long time.

In the second embodiment, in the display control circuit shown in FIG. 9, switching between VSYNC, HSYNC, and DCLK in the normal mode and the power save operation mode is controlled by the oscillator and the control. This is realized by providing the circuit 21 and the selection circuit group 19, but this is not performed in the normal mode as shown in FIG. 11, but the interface circuit is used in the power save mode. 7 may be realized by providing a frequency-dividing circuit group 23 composed of frequency-dividing circuits 23a, 23b, and 23c that divide the horizontal synchronizing signal and the operation clock inputted from 7 at a predetermined frequency dividing ratio. .

Hereinafter, a third embodiment of the liquid crystal display device will be described.

In the third embodiment, the liquid crystal matrix panel 2 is driven by the line-by-line polarity inversion driving method. That is, as shown in FIG. 12, the polarity of the signal voltage is inverted for each horizontal line and applied to the pixels of the liquid crystal matrix panel. The application of such a signal voltage is realized by the voltage control circuit 6 inverting the polarity of the voltage supplied to the signal drive circuit for each horizontal line using the input HSYNC and DCLK.

In the third embodiment, a liquid crystal matrix panel 2 capable of displaying gradations is used. The display gradation of each pixel is controlled by the value of the signal voltage provided from the signal drive circuit 1. The configuration of the liquid crystal matrix panel 2 is the same as that shown in FIG.

FIG. 13 shows waveforms of the signal voltage Vd corresponding to each gradation applied to the signal line by the line-by-line polarity inversion driving method and the voltage Vcom applied to the common electrode. As shown in the figure, the polarity of the voltage Vcom applied to the common electrode is inverted for each line, and the polarity of the signal voltage Vd is also inverted so as to maintain the absolute value of the voltage difference from the voltage Vcom. The OFF voltage of the scan voltage has the same phase and the same amplitude value as the common voltage Vcom. In addition, the polarity of the signal voltage corresponding to the five gradations from black to white is inverted at the halftone 2.

Now, in the liquid crystal matrix panel 2 shown in FIG. 4, the potential difference between the signal electrode (drain electrode) and the common electrode is the smallest, the potential difference between the signal electrode and the scanning electrode (gate electrode) is the smallest, and the common electrode The power consumption is lowest when three conditions that minimize the potential difference between the signal electrode and the signal electrode are satisfied. This is because a transient current flows through the parasitic capacitance due to a parasitic capacitance between the electrodes.

Here, as understood from FIG. 13, such a transient current is minimized in the case of white display. Accordingly, it is desirable to display the entire screen in white in the power save operation mode. However, this makes it impossible to visually recognize the operation state of the device. Therefore, in the present embodiment, a predetermined pattern is displayed in the power save operation mode as shown in FIG. Then, the brightness of the background is set to white or a halftone display close to white, and the pattern portion is set to a halftone display with a gradation darker than the background portion. Such a pattern can be displayed in the same manner as in the second embodiment.

In this case, since the background looks bright, the voltage applied to the light source 4 may be reduced, or the current flowing through the light source may be limited to lower the luminance. Thus, the power consumption of the display device can be further reduced. Further, in particular, when the liquid crystal matrix panel 2 is of both the reflection type and the transmission type, the power source of the light source 4 may be cut off.

The third embodiment relates to the normally white mode liquid crystal matrix panel 2 which is brightest when no voltage is applied to the liquid crystal. On the other hand, when the liquid crystal matrix panel 2 of the normally black mode, which becomes dark, is used, the brightness of the background is changed to black or a halftone display close to black, and the pattern portion is changed to a halftone display of a gradation brighter than the background portion. What should I do?

When the liquid crystal matrix panel 2 capable of color display is used, the pattern may be a halftone display brighter than the background portion for one of the three colors RGB.

In the third embodiment, not only the polarity inversion driving method for each line, but also a driving method for inverting the polarity for each pixel as shown in FIG. 15, a polarity inversion as shown in FIG. A driving method in which the polarity is inverted for each frame, a driving method in which the polarity is inverted for each frame, or a driving method in which these are combined can be similarly applied. (4) Even when the number of gradations of the liquid crystal matrix panel 2 is not 5 gradations, the same can be applied.

Hereinafter, a fourth embodiment of the present invention will be described.

In the fourth embodiment, as in the third embodiment, a liquid crystal matrix panel 2 capable of displaying gradation is used.

FIG. 17 shows a configuration of the voltage control circuit 6 according to the present embodiment.
As illustrated, the voltage control circuit 6 includes selection circuits 24 and 25 and a gradation circuit 26.

In the power save mode operation, when the power save control signal PS is input from the display control circuit 5, the selection circuit 24 changes the power supply voltage of the power supply VDR supplied to the gradation circuit 26 from VN1. Switch to VS1. Similarly, the selection circuit 25 switches the power supplied to the signal drive circuit 1 from VN2 to VS2. The magnitude relationship between the power supply voltages is VN1> VS1, VN2> VS2. That is, during the power save mode operation, the voltage applied to the gradation circuit 26 and the signal drive circuit 1 is reduced. It should be noted that only one of the power supplies of the gradation circuit 26 and the signal circuit 1 may be lowered without lowering them at the same time.

The gradation circuit 26 divides the power supply voltage provided from the selection circuit at a predetermined ratio and outputs voltages V1 to Vk. Since VN1> VS1, the voltages V1 to Vk decrease in the ratio of VS1 / VN1 during the power save mode operation. It should be noted that the gradation voltages V1 to Vk are set at regular intervals in accordance with the driving method of the liquid crystal matrix panel 2 described above (the polarity inversion driving method for each line, the polarity inversion driving method for each pixel, and the polarity inversion driving method for each frame). Alternatively, the polarity may be reversed.

FIG. 18 shows the configuration of the signal circuit 1 according to the fourth embodiment.

As shown in the figure, the signal circuit 1 includes, as described above, a latch group for sequentially latching one line of image data DATA in synchronization with the clock signal DCLK, and a latch group for transferring one line of image data to the next line. It has a logic circuit section 27 including a second latch group for holding the image data until it is transferred and outputting it in parallel to the output circuit 28, and an output circuit 28.

Further, as shown in FIG. 19A, each output circuit 28 includes a decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27, and a decoder 2810 according to the decoded value. A selector unit 2800 having an analog selector for selecting any of the voltages V1 to Vk sent from the adjustment circuit 26, and the voltage selected by the analog selector 2800 is connected to the power supply voltage VDR (VN2 Or VS2), and has a driver circuit 2801 for amplifying and applying the amplified signal to a corresponding signal electrode.

The selector of the output circuit 28 of the signal circuit 1 includes a decoder 2810 for decoding the value of the image data sent from the logic circuit 27, and a decoder 2810, as shown in FIG. A configuration may be provided that includes a voltage dividing circuit 2890 that divides the voltages V1 to Vk sent from the gradation circuit 26 and an analog selector 2800 that selects one of the divided voltages according to the value.

The output circuit 28 can be configured in various ways. As shown in FIG. 19C, a decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27, and a decoder 2810 A sample hold circuit 2820 that holds the power supply voltage VDR at the timing of each clock signal DCLK in accordance with the hold value, and a hold power supply voltage VDR as a control input (for example, a gate voltage). It is also possible to use a transistor (for example, FET) 2830 for selectively outputting any one of the voltages V1 to Vk sent from the adjustment circuit 26.

In any case, if the image data values are the same, the output voltage of the output circuit 28 is determined by the voltages V1 to Vk sent from the gradation circuit 26 and the power supply voltage VDR.

With the above configuration, the waveforms of the signal voltage Vd applied to the signal electrode and the power supply voltage VDR applied to the signal circuit 1 are different from those in the non-power-save operation mode and in the power-save mode. It changes as shown in FIG. 20 in the operation mode.

中 In the figure, (a) shows a non-power-save operation mode, and (b) shows a power-save operation mode.

As shown in the figure, in the power save operation mode, a low signal due to the effects of the gradation voltages V1 to Vk and the power supply voltage VDR, which is lower than in the non-power save operation mode. Voltage is applied to the signal electrode. Accordingly, the power consumption is lower than in the non-power-save operation mode.

In this case, in the power save operation mode, a display with lower or higher brightness is performed than in the non-power save operation mode. In the operation mode, there is no problem since the user is not working.

Normally, the scanning drive circuit 3 is provided with a driver circuit for sequentially driving the scanning lines by using the supplied power. Therefore, during the power save mode operation, the power supply supplied to this driver circuit is provided. Even when the voltage is reduced, power consumption can be reduced as in the fourth embodiment.

Hereinafter, a fifth embodiment of the liquid crystal display device according to the present invention will be described.

FIG. 17 shows a configuration of the voltage control circuit 6 according to the fifth embodiment.
As shown in the figure, the voltage control circuit 6 includes a gradation circuit 26, and includes gradation circuit 26 gradation voltage generation circuits 26a to 26e.

{Circle around (5)} In the non-power-save operation mode, each of the gradation voltage generation circuits 26a to 26e generates gradation voltages V1 to Vk shown in FIG. Further, in the power save operation mode, the gray scale voltages V1 to Vk shown in FIG.

That is, only V1 and V2 are changed, and the other output voltages are set to a constant voltage (Vc) so as not to change.

The figure shows a case where the polarity of the voltage is changed every horizontal scanning time ta by the line-by-line polarity inversion driving method.

In the fifth embodiment, a predetermined pattern is displayed on the liquid crystal matrix panel by the display control circuit 5 having the pattern generator 20 shown in FIG.

For example, in the output circuit 28 shown in FIG. 19A, a voltage V1 or V2 is selected for a portion for displaying a pattern, and any voltage of V3 to Vk is selected for other portions. Thus, the value of the image data output from the pattern generator 20 is given in advance.

As a result, when the pattern shown in FIG. 23 is displayed, as shown in FIG. 24, the background portion 2300 is driven at a constant voltage level, and the pattern display portion 2301 is driven by the voltages V1 and V2. Driven.

The voltage control circuit 6 according to the fifth embodiment may be configured as shown in FIG.

電 圧 As shown, the voltage control circuit 6 includes a gradation circuit 26, a gradation circuit 41, a gradation control circuit 42, and a switch circuit 35.

The gradation circuit 26 generates V1 to Vk gradation voltages whose polarity is inverted every horizontal scanning period shown in FIG. 22A from the supplied power supply voltage and the horizontal synchronization signal HSYNC. , And generates a gray scale voltage V1 to Vk whose polarity is inverted every horizontal scanning period shown in FIG. 22B from the supplied power supply voltage and the horizontal synchronization signal HSYNC.

The gradation control circuit 42 controls the switch circuit 35 to select the output voltage of the gradation circuit 26 and apply it to the signal drive circuit 1 during the non-power-save mode operation. In the negative operation, the output voltage of the gradation circuit 41 is selected and applied to the signal drive circuit 1.

Further, the gradation control circuit 42 stops the operation of the gradation circuit 41 during the non-power-save mode operation, and stops the operation of the gradation circuit 26 during the power-save mode operation. I do. The operation can be stopped by, for example, stopping the supply of power or stopping the supply of the horizontal synchronization signal HSYNC or the clock signal DCLK used for inverting the polarity of the generated voltage.

In the fifth embodiment, only V1 and V2 may be changed, and the other output voltages may be voltages having amplitudes smaller than V1 and V2.

Alternatively, only V1 may be changed, and the other output voltage may be constant or a voltage having an amplitude smaller than V1, so that characters and the like are simply driven by V1 and the background is driven by other voltages.

(4) By doing so, the power consumption of a gray scale circuit generally composed of a differential amplifier, a resistor and a capacitor can be reduced. Further, by making the voltage input to the signal drive circuit 1 constant or reducing the amplitude, the current due to the stray capacitance in the signal drive circuit 1 and the liquid crystal matrix panel 2 can be reduced, and the power consumption can be reduced.

As described above, according to each of the embodiments of the liquid crystal display device according to the present invention, it is possible to reduce the power consumption in the power save operation mode while performing a constant display.

In the above embodiment, the liquid crystal display device in which the signal driving circuit 1 drives the liquid crystal matrix panel according to image data which is digital data is described. However, the signal driving circuit 1 directly switches the liquid crystal matrix according to an analog image signal. In an apparatus for driving a panel, the signal drive circuit 1 in the fourth embodiment may be configured as shown in FIG.

That is, the input analog image signal 2850 is sequentially circulated based on the sample clock signals and the sample hold circuits 2803 corresponding to the number of signal electrodes that sample-hold in synchronization with the sample clock signal 2804 corresponding to the data clock. A logic circuit unit 2805 for providing a sampling operation permission signal for each sample hold circuit 2803, and a power supply voltage supplied from the selection circuit 24 provided for each sample hold circuit. (VN2 or VS2), and may be configured by a driver circuit 2801 for amplifying and amplifying the amplified signal to a corresponding signal electrode. In the case where the signal driving circuit 1 drives the liquid crystal matrix panel in accordance with the analog image signal directly and drives the liquid crystal matrix panel by inverting the polarity for each line or each frame, the polarity inversion is performed. A circuit that inverts the polarity of the analog image signal applied to the driving method signal drive circuit 1 and shifts the analog image signal voltage by an amount equivalent to the common voltage in synchronization with the timing may be provided.

In the sixth embodiment, when the signal driving circuit 1 directly drives the liquid crystal matrix panel according to the analog image signal using the signal driving circuit 1 shown in FIG. 26, the signal voltage shown in FIG. The pattern generator 20 may be configured to generate an analog image signal output by the signal drive circuit 1.

In the above embodiment, when the liquid crystal display device 10 receives the power save control signal 2003 from the CPU 1001, it shifts to the power save operation mode. The usage state of the device 1000 may be determined, and the mode may be automatically shifted to the power save operation mode. This is achieved by, for example, providing a frame buffer for storing one frame of image data in the liquid crystal display device 10 and judging the coincidence between the image data in the frame buffer and the input image data. -The change between frames is sequentially obtained, and if there is no predetermined change in the number of frames, it is determined that the frame is not currently used by the user, and the power save mode is automatically set. This can be realized by making the transition. Alternatively, the state of the power switch may be directly read and the mode may be shifted to the power save operation mode.

It is a figure showing appearance of an information device concerning an example of the present invention. FIG. 1 is a block diagram illustrating a configuration of an information device according to an embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a liquid crystal matrix panel. FIG. 4 is a diagram illustrating an operation in a normal mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 4 is a timing chart showing a driving voltage waveform in a normal mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 4 is a timing chart showing a first drive voltage waveform in a power save mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 5 is a timing chart showing a second drive voltage waveform in a power save mode of the liquid crystal display device according to the first embodiment of the present invention. FIG. 9 is a block diagram illustrating a configuration of a first display control circuit according to a second example of the present invention. FIG. 11 is a diagram showing a pattern display in a power save mode according to a second embodiment of the present invention. FIG. 9 is a block diagram illustrating a configuration of a second display control circuit according to a second example of the present invention. FIG. 4 is a diagram illustrating the polarity of a voltage applied to a pixel by a line-by-line polarity inversion driving method. FIG. 9 is a timing chart showing signal voltages corresponding to each gradation applied to a signal line by a line-by-line polarity inversion driving method. FIG. 14 is a diagram showing a pattern display in a power save mode according to a third embodiment of the present invention. FIG. 3 is a diagram illustrating the polarity of a voltage applied to a pixel by a pixel-by-pixel polarity inversion driving method. FIG. 4 is a diagram illustrating the polarity of a voltage applied to a pixel by a driving method that combines a pixel-by-pixel polarity inversion driving method and a line-by-line polarity inversion driving method. FIG. 13 is a block diagram illustrating a configuration of a voltage control circuit according to a fourth embodiment of the present invention. FIG. 11 is a block diagram illustrating a configuration of a signal drive circuit according to a fourth example of the present invention. FIG. 14 is a block diagram illustrating a configuration of an output circuit according to a fourth embodiment of the present invention. FIG. 11 is a timing chart showing a signal driving voltage waveform according to a fourth example of the present invention. FIG. 11 is a block diagram illustrating a first configuration of a voltage control circuit according to a fifth embodiment of the present invention. FIG. 14 is a timing chart showing an output voltage waveform of a voltage control circuit according to a fifth example of the present invention. FIG. 14 is a diagram showing a pattern display in a power save mode according to a fifth embodiment of the present invention. FIG. 14 is a timing chart showing a driving voltage waveform in a power save mode of the liquid crystal display device according to the fifth embodiment of the present invention. FIG. 13 is a block diagram illustrating a second configuration of the voltage control circuit according to the fifth embodiment of the present invention. FIG. 9 is a block diagram illustrating another configuration of the output circuit according to the embodiment of the present invention.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Signal drive circuit 2 Liquid crystal matrix panel 3 Scan drive circuit 4 Light source 5 Display control circuit 6 Voltage control circuit 7 Interface circuit

Claims (10)

When a scanning voltage is applied, a liquid crystal cell which performs display according to the amplitude of the applied signal voltage is arranged in a matrix, and the liquid crystal cell belongs to each line on the matrix every predetermined scanning period. A scan driver for sequentially applying and holding a scan voltage line by line to the liquid crystal cells; and, in each scanning period, the liquid crystal cells in each of the columns of the liquid crystal cells to which the liquid crystal cells belong. A method for reducing power consumption during a standby state in a liquid crystal display device having a signal driver that applies and holds a signal voltage corresponding to the content to be displayed on a liquid crystal cell of a line to which a voltage is applied,
During a period instructed to wait, the signal driving unit applies the scanning voltage to each liquid crystal cell in each of the plurality of scanning periods of the column to which the liquid crystal cell belongs in the plurality of scanning periods. A method of applying and holding a signal voltage corresponding to a content to be displayed commonly on a plurality of liquid crystal cells of a plurality of lines, the power consumption of the liquid crystal display device being reduced. A liquid crystal cell which performs display according to the amplitude of the applied signal voltage when a scanning voltage is applied, and a liquid crystal matrix panel arranged in a matrix, and belonging to each line on the matrix every predetermined scanning period A scan driver for sequentially applying and holding a scan voltage line by line to the liquid crystal cells; and, in each scanning period, the liquid crystal cells in each of the columns of the liquid crystal cells to which the liquid crystal cells belong. A signal drive unit that applies and holds a signal voltage having an amplitude corresponding to a gray scale to be displayed on a liquid crystal cell of a line to which a voltage is applied, and a method of reducing power consumption during standby in a liquid crystal display device,
During the period in which the standby is instructed, the signal driver applies and holds a signal voltage having an amplitude smaller than the amplitude corresponding to the gray scale to be displayed and having an amplitude determined according to the gray scale to be displayed. A method for reducing power consumption of a liquid crystal display device. When a scanning voltage is applied, a liquid crystal cell which performs display according to the amplitude of the applied signal voltage is provided in a liquid crystal matrix panel arranged in a matrix. A scan driver that sequentially applies and holds a scan voltage line by line to liquid crystal cells belonging to each line, and a liquid crystal cell in each column during a scanning period. A signal drive unit that applies and holds a signal voltage having an amplitude corresponding to the content displayed on the liquid crystal cell of the line to which the scanning voltage is applied during a scanning period,
The signal driver is configured to apply the scan voltage to each liquid crystal cell in a plurality of scan periods during a plurality of scan periods of a column to which the liquid crystal cell belongs during a period instructed to wait. A liquid crystal display device having means for applying and holding a signal voltage having an amplitude corresponding to the content to be commonly displayed on a plurality of liquid crystal cells of a plurality of lines. A method for reducing power consumption of a liquid crystal display device according to claim 3,
The scan driving unit simultaneously applies a scan voltage to the liquid crystal cells belonging to the plurality of lines sequentially during a plurality of scanning periods corresponding to the plurality of lines during a period in which the standby is instructed. A liquid crystal display device comprising: means for holding and holding. A liquid crystal cell which performs display according to the amplitude of the applied signal voltage when a scanning voltage is applied, and a liquid crystal matrix panel arranged in a matrix, and belonging to each line on the matrix every predetermined scanning period A scan driver for sequentially applying and holding a scan voltage line by line to a liquid crystal cell, a voltage controller for generating a plurality of gradation display voltages, and a liquid crystal cell for each liquid crystal cell in each scanning period. Among the liquid crystal cells belonging to the column to which the scanning voltage is applied in the scanning period, a signal voltage having an amplitude corresponding to the gradation displayed on the liquid crystal cell on the line to which the scanning voltage is applied is generated by a plurality of gradations generated by the voltage control unit. A method for reducing power consumption during standby in a liquid crystal display device having a signal driving unit that generates, applies, and holds using a display voltage,
The voltage control unit, during a period instructed to wait, the signal drive unit generates a signal voltage having an amplitude smaller than the amplitude corresponding to the gray scale to be displayed according to the gray scale to be displayed, and applies the signal voltage. A liquid crystal display device comprising: means for changing a value of a generated gradation display voltage so as to hold the voltage. A liquid crystal cell which performs display according to the amplitude of the applied signal voltage when a scanning voltage is applied, and a liquid crystal matrix panel arranged in a matrix, and belonging to each line on the matrix every predetermined scanning period A scan driver that applies and holds a scan voltage generated by using a supplied power supply voltage to a liquid crystal cell in a line-by-line manner, and a liquid crystal of a column to which the liquid crystal cell belongs in each liquid crystal cell in each scan period A signal drive for generating, applying, and holding a signal voltage having an amplitude corresponding to the content to be displayed on the liquid crystal cell of the line to which the scanning voltage is applied in the scanning period using the supplied power supply voltage in the scanning period. A liquid crystal display device comprising:
During a period in which the standby is instructed, at least one of a power supply voltage supplied to the scan driving circuit and a power supply voltage supplied to the signal driving circuit is changed to a value smaller than a value before the standby is instructed. A liquid crystal display device comprising: 7. A liquid crystal display device according to claim 3, wherein the data is processed, and image data specifying contents to be displayed in each liquid crystal cell of the liquid crystal matrix panel is generated in accordance with the processing result and sent to the liquid crystal display. Together with a data processing unit that instructs the liquid crystal display device to wait according to the use state of the user,
The signal drive circuit of the liquid crystal display device, wherein the image data sent from the data processing unit is input, and the content specified by the input image data is the content to be displayed on the liquid crystal cell. machine. 6. A liquid crystal display device according to claim 5, wherein the data is processed, and image data for specifying a gradation to be displayed in each liquid crystal cell of the liquid crystal matrix panel is generated and sent to the liquid crystal display according to the processing result. A data processing unit that instructs the liquid crystal display device to wait according to a user's use state,
The signal drive circuit of the liquid crystal display device inputs image data sent from a data processing unit, and sets a gradation designated by the input image data as a gradation to be displayed on the liquid crystal cell. Information equipment. The information device according to claim 7, wherein:
The liquid crystal display device has a pattern generation unit that generates image data representing a predetermined image at least during a period when a standby is instructed,
The liquid crystal display device has means for inputting the image data generated by the pattern generation unit to the signal drive circuit in place of the image data sent from the data processing unit during the period when the standby is instructed. A liquid crystal display device characterized by the above-mentioned. The information device according to claim 7, 8, 9,
The information processing apparatus according to claim 1, wherein the data processing unit includes a pen-type input device, and coordinate detection means for detecting a placement position of the pen-type input device on the liquid crystal matrix panel as the data.