JP4254963B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique for reducing power consumption in a standby state.

  Liquid crystal display devices are widely used in portable information devices that operate with battery power because they are thinner and lighter than CRTs and consume less power.

  However, it is desired to extend the operation time of such portable information equipment using a battery. On the other hand, further downsizing of portable information devices is desired. For this purpose, the battery needs to be downsized.

  In order to realize such a proposition, it is desirable to reduce the power consumption of a liquid crystal display device used in information equipment.

  Here, as a conventional technique for reducing the power consumption of a liquid crystal display device, for example, a technology for shutting off the power of the device when a keyboard or the like is not operated for a long time on a personal computer, that is, when it is in a standby state is known. It has been.

  In addition, although not related to liquid crystal display devices, as described in NIKKEI ELECTRONICS NO590 (issued on September 13, 1993), when a display device using a CRT is in a standby state, There is known a technique for reducing the power consumption of an apparatus by interrupting the supply of power to a high-voltage circuit.

  According to the respective technologies for reducing the standby power consumption, display on the display device is not performed in the standby state, so that the state of the information device at that time cannot be visually recognized.

  Accordingly, an object of the present invention is to provide a liquid crystal display device that can perform display with low power consumption when in a standby state.

  In order to achieve the above object, according to the present invention, during a period in which standby is instructed, the signal driving unit includes, for each of a plurality of scanning periods, a plurality of liquid crystal cells in a column to which the liquid crystal cell belongs. A method for reducing the power consumption of a liquid crystal display device, wherein a signal voltage corresponding to the content to be displayed in common is applied to and held in a plurality of liquid crystal cells of a plurality of lines to which the scanning voltage is applied during the scanning period provide.

  In order to achieve the above object, according to the present invention, the signal driver has a signal voltage having an amplitude smaller than that in the non-standby state during a period in which standby is instructed, and is determined according to a gradation to be displayed. A method for reducing power consumption of a liquid crystal display device, characterized by applying and holding an oscillation voltage having an amplitude.

  According to the power consumption reduction method of the present invention, the current flowing into and out of the liquid crystal matrix panel can be reduced by lengthening the change period of the signal voltage applied to the liquid crystal matrix panel or reducing the voltage level of the signal voltage. As a result, power consumption is reduced. In addition, even if the change period of the signal voltage is increased or the voltage level of the signal voltage is decreased, a display that can be visually recognized by the user is ensured. You can see the state of the equipment. In this case, the display quality is deteriorated in the standby state period, but the standby state is a period in which the user does not use, so that no problem in use occurs.

  As described above, according to the present invention, the present invention can provide a liquid crystal display device capable of performing display with low power consumption when in a standby state.

  Examples of information equipment according to the present invention will be described below.

  First, the configuration and operation of an information device and a liquid crystal display device common to each embodiment presented below will be described.

  FIG. 1 shows the appearance of the information device according to the present embodiment.

  In the figure, 1000 is an information device, 2 is a display unit of a liquid crystal display device, 3000 is a floppy disk insertion slot of a floppy (registered trademark) disk driver, 4000 is an input pen, 5000 is a key switch group, 6000 is a power save switch, 7000 Is a power switch. As shown in the figure, the liquid crystal display device is incorporated in the information device 1000.

  FIG. 2 shows the internal configuration of the information device 1.

  In the figure, 1001 is a CPU, 1002 is a ROM storing a program executed by the CPU 1, 1003 is a RAM used for executing the program, 1004 is a battery, 10 is a liquid crystal display device, and 1005 is a liquid crystal display for controlling the display of the liquid crystal display device. 1006 is a V-RAM that stores data defining display contents to be displayed on the display device, 1007 is an interface circuit between the power save switch 6000 and the key switch group 5000, etc., and 1008 is a floppy disk drive. The interface circuit 1009 is an interface circuit for a control signal 2003 with the display control apparatus 10, and 1010 is an interface circuit with the input pen 4000.

  The liquid crystal display device 10 includes a display unit 2, a light source 4, and a drive control circuit 2005.

  In such a configuration, when the input pen 4000 is placed on the display unit 2, the input pen 4000 detects the coordinates on the display unit 2, for example, by detecting the voltage applied to the display unit 2. .

  Further, the CPU 1001 executes a program in accordance with the coordinates detected by the input pen 4000 and the key input of the key switch group 5000, and determines the content to be displayed on the display unit 2 of the liquid crystal display device 10 according to the execution result. Then, the image data defining the display contents is written into the V-RAM 1006. The display control device 1005 sends the image data 2002 stored in the V-RAM 1006 to the liquid crystal display device 10 together with a synchronization signal group 2001 necessary for display on the liquid crystal display device 10.

  Further, the CPU 1001 detects that the power save switch 6 is turned on via the interface circuit 1007, or has detected no coordinates of the input pen 4 or key input of the key switch group 5000 for a certain period or more. Is detected, a power save control signal 2003 for instructing the shift to the power save mode is sent to the liquid crystal display device 10 via the interface circuit 1009.

  Now, when the power switch is turned on, the battery 1004 supplies power of a predetermined voltage to each part of the information device 1000 including the liquid crystal display device 10.

  Next, FIG. 3 shows an internal configuration of the liquid crystal display device 10.

  As shown in the figure, the signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, the light source 4, the interface circuit 7, and the display unit 2 are configured. The signal drive circuit 1, the scan drive circuit 3, the display control circuit 5, the voltage control circuit 6, and the interface circuit 7 correspond to the drive control circuit 2005 shown in FIG.

  In this embodiment, a liquid crystal matrix panel is assumed as the display unit 2. As shown in FIG. 4, the liquid crystal matrix panel 2 includes one pixel including a TFT (thin film transistor) 13 and a liquid crystal 14. Further, the scanning lines 12 a to 12 d are connected to the gate electrode of the TFT 13, and the signal lines 11 a to 11 c are connected to the drain electrode.

  The interface circuit 7 receives image data 2002 to be displayed on the display unit 2 from the display control device 1005. As a synchronization signal included in the synchronization signal group 2001, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal synchronized with the image data 2002 are input, and a power save control signal 2003 is input from the CPU 1001 via the interface circuit 1009. . Here, the image data 2002 is input in the order according to the raster scan method. The vertical synchronization signal is a pulse signal output every frame period of an image to be displayed, and the horizontal synchronization signal is a pulse signal output every line scanning period.

  The interface circuit 7 passes these signals to the display control circuit 5.

  The display control circuit 5 receives image data DATA, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, power save control signal, which are signals corresponding to the inside of the apparatus, from image data 2002, synchronization signal 2001, and power save control signal 2003. PS is generated, the generated vertical synchronizing signal VSYNC, horizontal synchronizing signal HSYNC, clock signal DCLK, and image data DATA are sent to the signal driving circuit 1, and the horizontal synchronizing signal HSYNC and vertical synchronizing signal VSYNC are sent to the scanning driving circuit 3. The voltage control circuit 6 is supplied with a synchronizing signal (one or both of VSYNC and HSYNC) and a clock signal DCLK necessary for realizing a polarity inversion driving method, which will be described later, and the voltage control circuit 6, the signal driving circuit 1, and the scanning driving circuit. 3. A power control signal PS is sent to the light source 4.

  However, depending on the embodiment described below, it may not be necessary to send some signals.

  Here, FIG. 5 shows the timing (FIG. 5a) of the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the clock signal DCLK, and the image data DATA in the normal mode (non-power saving operation mode) and the display defined thereby. The correspondence of the screen (FIG. 5b) is shown. The timing shown in FIG. 5a coincides with the timing of the vertical synchronization signal, horizontal synchronization signal, clock signal, and image data input to the interface circuit 7.

  The voltage control circuit 6 uses the power supplied from the battery 1004 to generate a scan drive voltage and send it to the scan drive circuit 3. Further, a signal driving voltage is generated and sent to the signal driving circuit 1.

  As shown in FIG. 6, the scanning drive circuit 3 sequentially responds to the scanning drive voltage sent from the voltage control circuit 6 to the different scanning lines 12 a to 12 d in the order of the arrangement in synchronization with the horizontal synchronization signal HSYNC. The scanning voltages Vg1 to Vgn are applied. Each time the vertical synchronization signal VSYNC is input, the above operation is repeated from the first scanning line 12a. That is, the scanning voltage sequentially becomes the value Vgh for each line, and the TFT is turned on for each line.

  On the other hand, the signal driving circuit 1 includes two groups of latch groups that can store image data for one line. The signal lines 11a to 11c are provided with the same number of output circuits as the number of image data for one line respectively connected. The first latch group sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and the latched image data DATA for one line in the second latch group in synchronization with the horizontal synchronization signal HSYNC. The data for one line is transferred in parallel, and the transferred image data for one line is held until the image data for the next line is received, and is output in parallel to different output circuits. During this time, the first latch group sequentially captures the image data of the next line in the same manner as the previous line. As a result, as shown in FIG. 6, signal voltages Vd1 to Vdm are applied.

  Each output circuit applies the signal voltages Vd1 to Vdm to the connected signal lines according to the value of the received image data and the signal driving voltage sent from the voltage control circuit 6.

  The configuration and operation of the information equipment and the liquid crystal display device common to the embodiments presented in this embodiment have been described above. Hereinafter, in the liquid crystal display device 10 having such a configuration, each embodiment for reducing power consumption while ensuring display will be described.

  First, the first embodiment will be described.

  In the first embodiment, when the display control device 5 receives the power save signal from the interface circuit 7, the cycle of the horizontal synchronizing signal HSYNC to be output is doubled in the normal mode and the power save signal PS is used to save the power. The operation mode is instructed to the scanning drive circuit 3 and the signal drive circuit 1. Note that such a change in the cycle of the horizontal synchronization signal HSYNC causes the display circuit 8 to change the frequency of the horizontal synchronization signal HSYNC to be output from the interface circuit 7 when the power save signal PS indicates ON, as will be described later. This can be realized by providing a frequency dividing circuit that divides the frequency by half of the frequency of the input horizontal synchronizing signal. Alternatively, when the power save signal PS indicates ON, an oscillator is provided that outputs a signal having a frequency ½ of this as a horizontal synchronization signal HSYNC in phase with the horizontal synchronization signal input from the interface circuit 7. May be.

  As shown in FIG. 7, the scanning drive circuit 3 sequentially scans two scanning signals at two scanning signals, such as Vg1 and Vg2, and Vg3 and Vg4, for each period of the horizontal synchronization signal HSYNC output from the display control circuit 3. Apply the value Vgh. For example, the scanning voltage is applied for each of the two scanning signals. For example, the scanning driving circuit 3 counts the number of scanning signals connected to different scanning signal lines and the number of scanning signals, and the HSYNC is reset by the VSYNC. And a decoder that decodes the count value of the counter in accordance with the value of the power save signal PS, and can be realized by sequentially enabling the output circuit in accordance with the decode value of the decoder. Here, the output circuit is a circuit that outputs the scanning voltage supplied from the voltage control circuit 6 to the corresponding scanning signal line when it is validated.

  On the other hand, in the signal driving circuit 1, when the first latch group becomes full by taking in the image data of the odd-numbered lines, the operation of discarding the input image data of the even-numbered lines is repeated. The odd-numbered line image data captured by the first latch group is captured by the second latch group by the horizontal synchronization signal HSYNC input at the end of the input of the next even-numbered line image data. Up to the horizontal synchronization signal HSYNC input is held and output to the output circuit. As a result, the voltage applied to each signal line is updated at a cycle twice that of the normal mode.

  By doing so, the period in which the TFT of the liquid crystal matrix 2 is turned on is doubled. In accordance with this, the cycle in which the levels of the signal voltages Vd1 to Vdm change is also doubled. Accordingly, power consumption of the liquid crystal matrix 2, the signal driving circuit, the voltage control circuit 6 and the like can be reduced.

  On the other hand, the resolution of the image displayed on the liquid crystal matrix 2 is ½ of that in the normal mode in the vertical direction. However, in the power save mode, it is a practical problem because it is a period during which the user is not working. Never become.

  The display control circuit 8 outputs the input signal from the interface circuit 7 as it is for the vertical synchronization signal VSYNC, the operation clock DCLK, and the image data DATA.

  By the way, as shown in FIG. 8, the scanning voltages Vg1, Vg2,. . Is applied in the same manner as in the normal mode, and the display control circuit 5 doubles only the period of the horizontal synchronizing signal HSYNC given to the signal driving circuit 1 so that the level of only the signal voltage is changed every two lines. May be. Even in this case, the cycle in which the level of the signal voltage changes can be doubled, and the same effect as in the first embodiment can be achieved.

  Further, the cycle of the clock signal DCLK is doubled, and in the signal driving circuit 1, the image data is taken into the first latch group every other pixel data, and the second latch from the n-th latch in the first latch group. Data may be transferred in parallel to the 2n-1st and 2nth latches of the latch group in synchronization with the horizontal synchronization signal HSYNC. Such a change in the cycle of the clock signal DCLK is caused by changing the frequency of the clock signal DCLK to be output from the interface circuit 7 to the display control circuit 8 when the power save signal PS is turned on. This can be realized by providing a frequency dividing circuit that divides the frequency by half. Of course, an oscillator that generates a clock having a frequency half that of the operation clock signal input from the interface circuit 7 in phase synchronization with the operation clock signal input from the interface circuit 7 may be provided.

  In this way, the horizontal resolution of the display is also halved. However, as described above, in the power save mode, there is no practical problem since the user is not working. Further, since the operating frequency of the first latch group of the signal driving circuit 1 is ½ that in the normal mode, power consumption can be reduced.

  In this embodiment, in the power save mode, the driving / operating frequency of the scanning driving circuit 3 and the signal driving circuit 1 is changed to 1/2, but this is set to other ratios such as 1/4. May be.

  The second embodiment will be described below.

  In the first embodiment, the drive / operation frequency of the scanning drive circuit 3 and the signal drive circuit 1 is lowered, and the resolution of the image displayed by the image data input to the interface circuit 7 is lowered to display the power consumption. Reduced. In this embodiment, in the power save mode, a predetermined image is generated by the built-in pattern generator and displayed without using the image data input to the interface circuit 7.

  FIG. 9 shows the configuration of the display control circuit 5 according to the second embodiment.

  As shown in the figure, in the second embodiment, the display control circuit 5 includes a selection circuit group 19 including selection circuits 19a to 19d, an oscillation circuit 22, a pattern generator 20, and a control circuit 21.

  The control circuit 21 uses the basic clock output from the oscillation circuit 22 and three signals VSYNC (IN), HSYNC having the same frequency ratio as the frequency ratio of the direct synchronization signal, horizontal synchronization signal, and operation clock input from the interface circuit. (IN) and DCLK (IN) are generated. The pattern generator 20 is actually a memory storing image data, and outputs image data indicating a predetermined image pattern as shown in FIG. 10, for example, in synchronization with DCLK (IN).

  The selection circuits 19a to 19d output the vertical synchronization signal, horizontal synchronization signal, operation clock, and image data input from the interface circuit 7 as they are in the normal mode as VSYNC, HSYNC, DCLK, and DATA, and in the power save mode, Timing signals VSYNC (IN), HSYNC (IN), and DCLK (IN) input from the control circuit 21 are output as VSYNC, HSYNC, and DCLK, and DATA (IN) input from the pattern generator 20 is output as DATA.

  Here, the frequency of VSYNC (IN), HSYNC (IN), and DCLK (IN) output from the control circuit 21 depends on the frequency of the direct sync signal, horizontal sync signal, and operation clock input from the interface circuit. A small frequency can be used to such an extent that the visibility of the display is not significantly impaired. Accordingly, the driving / operating frequency of each part can be reduced as compared with the normal mode, so that power consumption can be reduced.

  Of the VSYNC (IN), HSYNC (IN), and DCLK (IN) output from the control circuit 21, the frequency ratio of the HSYNC (IN) and DCLK (IN) to the horizontal synchronization signal input from the interface circuit 7 and the operation clock. Is set to, for example, 1/2 of the frequency ratio to the vertical synchronization signal input from the interface circuit 7 of VSYNC (IN). Similarly to the first embodiment (see FIG. 7), the scanning drive circuit 3 applies two scanning signal lines. If driven, the resolution in the vertical direction is halved compared to that in the normal mode, but the driving / operating frequencies of the scanning drive circuit 3 and the signal drive circuit 1 are further slowed as in the case shown in FIG. Power consumption can be further reduced. In this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance by ½ in the vertical direction.

  Alternatively, in the power save mode, the horizontal synchronization signal input from the interface circuit 7 of HSYNC (IN) and DCLK (IN) given to the signal drive circuit 1 and the frequency ratio to the operation clock are input from the interface circuit 7 of VSYNC (IN). If the frequency ratio with respect to the vertical synchronizing signal is, for example, ½, the driving / operating frequency of the signal driving circuit 1 can be delayed as in the first embodiment shown in FIG. Power consumption can be reduced. Also in this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance by ½ in the vertical direction.

  Further, the frequency ratio of DCLK (IN) to the operation clock input from the interface circuit 7 is set to, for example, 1/2 of the frequency ratio of the horizontal synchronization signal input from the interface circuit 7 of HSYNC (IN). As described above, in the signal driving circuit 1, image data is taken into the first latch group every other pixel data, and the nth latch of the first latch group to the 2n−1th and 2nth of the second latch group. If the data is transferred in parallel to the latches in synchronization with the horizontal synchronization signal HSYNC (IN), the horizontal direction and the resolution are halved in the normal mode, but the driving / operation of the signal driving circuit 1 is performed. The frequency can be further reduced, and the power consumption can be further reduced. In this case, the pattern generator 20 stores image data obtained by reducing an image to be displayed in advance to ½ in the vertical direction.

  As described above, in the second embodiment, in the power save operation mode, the predetermined image pattern as shown in FIG. 10 is displayed, but the timing signal for the timing of reading the image pattern from the pattern generator 20 is displayed. The image pattern may move on the display screen by sequentially shifting the generation timing of HSYNC (IN), VSYNC (IN), and DCLK (IN). , Power save status can be easily recognized. In addition, it is possible to reduce deterioration in image quality such as a change in brightness and an afterimage caused by a change in characteristics of a film constituting a TFT, a change in characteristics of a liquid crystal material, and the like caused by displaying the same position for a long time.

  In the second embodiment, the display control circuit shown in FIG. 9 is provided with an oscillator, a control circuit 21 and a selection circuit group 19 for switching between VSYNC, HSYNC and DCLK in the normal mode and the power saving operation mode. As shown in FIG. 11, this is achieved by dividing the horizontal synchronization signal and the operation clock input from the interface circuit 7 in a predetermined amount in the power save mode without performing frequency division in the normal mode. It may be realized by providing a frequency dividing circuit group 23 including frequency dividing circuits 23a, 23b, and 23c that divide by a frequency ratio.

  A third embodiment of the liquid crystal display device will be described below.

  In the third embodiment, the liquid crystal matrix panel 2 is driven by a line-by-line polarity inversion driving method. That is, as shown in FIG. 12, for each horizontal line, the polarity of the signal voltage is inverted and applied to the pixels of the liquid crystal matrix panel. Such application of the signal voltage is realized by inverting the polarity of the voltage supplied to the signal driving circuit for each horizontal line using the input HSYNC and DCLK in the voltage control circuit 6.

  In the third embodiment, a liquid crystal matrix panel 2 that can display gradations is used. The display gradation of each pixel is controlled by the value of the signal voltage supplied from the signal driving circuit 1. The configuration of the liquid crystal matrix panel 2 is the same as that shown in FIG.

  FIG. 13 shows waveforms of the signal voltage Vd corresponding to each gradation applied to the signal line and the voltage Vcom applied to the common electrode by the line-by-line polarity inversion driving method. As shown in the figure, the polarity of the voltage Vcom applied to the common electrode is inverted for each line, and the polarity of the signal voltage Vd is also inverted so as to maintain the absolute value of the voltage difference from the voltage Vcom. Note that the OFF voltage of the scanning voltage is in phase with the common voltage Vcom and has the same amplitude value. Further, the polarity of the signal voltage corresponding to the five gradations from black to white is inverted at the halftone 2.

  In the liquid crystal matrix panel 2 shown in FIG. 4, the potential difference between the signal electrode (drain electrode) and the common electrode is the smallest, the potential difference between the signal electrode and the scanning electrode (gate electrode) is the smallest, and further, the common electrode and the signal The power consumption is lowest when the three conditions that minimize the potential difference between the electrodes are satisfied. This is because a transient current flows through the parasitic capacitance due to the parasitic capacitance between the electrodes.

  Here, as understood from FIG. 13, the transient current is minimized in the case of white display. Therefore, it is desirable to display the entire screen in white during the power save operation mode. However, this makes it impossible to visually recognize the operation state of the apparatus. Therefore, in this embodiment, a predetermined pattern is displayed as shown in FIG. 14 in the power saving operation mode. Then, the background brightness is set to white or a halftone display close to white, and the pattern portion is set to a halftone display having a darker gradation than the background portion. Such a pattern display can be performed in the same manner as in the second embodiment.

  In this case, since the background looks bright, the voltage applied to the light source 4 may be reduced, or the current flowing through the light source may be limited to lower the luminance. As a result, the power consumption of the display device can be further reduced. In particular, when the liquid crystal matrix panel 2 is used for both reflection type and transmission type, the power source of the light source 4 may be shut off.

  The third embodiment is for the normally white mode liquid crystal matrix panel 2 that is brightest when no voltage is applied to the liquid crystal, but it is the darkest when the voltage is not applied to the liquid crystal. In the case of using the liquid crystal matrix panel 2 in the mari black mode, on the contrary, the brightness of the background may be black or a halftone display close to black, and the pattern portion may be a halftone display with a gradation that is lighter than the background portion.

  When the liquid crystal matrix panel 2 capable of color display is used, the pattern may be displayed in a halftone display brighter than the background portion for one of the three RGB colors.

  In the third embodiment, not only the polarity inversion driving method for each line but also the driving method for inverting the polarity for each pixel as shown in FIG. 15, the polarity as shown in FIG. The same applies to a driving method in which the polarity is inverted every time, a driving method in which the polarity is inverted every frame, or a driving method in which these are combined. Further, the liquid crystal matrix panel 2 can be similarly applied even if the number of gradations is not five.

  The fourth embodiment of the present invention will be described below.

  In the fourth embodiment, as in the third embodiment, a liquid crystal matrix panel 2 that can display gray scales is used.

FIG. 17 shows the configuration of the voltage control circuit 6 according to this embodiment.
As illustrated, the voltage control circuit 6 includes selection circuits 24 and 25 and a gradation circuit 26.

  During the power save mode operation, when the power save control signal PS is input from the display control circuit 5, the selection circuit 24 switches the power supply voltage of the power supply VDR supplied to the gradation circuit 26 from VN1 to VS1. Similarly, the selection circuit 25 switches the power supplied to the signal driving circuit 1 from VN2 to VS2. The relationship between the power supply voltages is VN1> VS1, VN2> VS2. That is, during the power save mode operation, the voltage applied to the gradation circuit 26 and the signal driving circuit 1 is reduced. Note that only one of the grayscale circuit 26 and the signal circuit 1 may be reduced without simultaneously reducing the power supply.

  The gradation circuit 26 divides the power supply voltage supplied from the selection circuit at a predetermined ratio and outputs voltages V1 to Vk. Since VN1> VS1, the voltages V1 to Vk are reduced at a ratio of VS1 / VN1 during the power save mode operation. Note that the gradation voltages V1 to Vk are polar at regular intervals according to the driving method (polarity inversion driving method for each line, polarity inversion driving method for each pixel, and polarity inversion driving method for each frame) described above. May be reversed.

  Next, FIG. 18 shows the configuration of the signal circuit 1 according to the fourth embodiment.

  As shown in the figure, as described above, the signal circuit 1 includes a latch group that sequentially latches the image data DATA for one line in synchronization with the clock signal DCLK, and the transferred image data for one line in the next line. The output circuit 28 includes a logic circuit unit 27 including a second latch group that holds the image data until it is transferred and outputs the image data in parallel to the output circuit 28.

  Further, as shown in FIG. 19A, each output circuit 28 is sent from the gradation circuit 26 in accordance with the decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27 and the decoded value. A selector unit 2800 having an analog selector for selecting any one of the voltages V1 to Vk and the voltage selected by the analog selector 2800 are amplified using the power supply voltage VDR (VN2 or VS2) supplied from the selection circuit 24. The driver circuit 2801 is provided to the corresponding signal electrode.

  As shown in FIG. 19B, the selector section of the output circuit 28 of the signal circuit 1 includes a decoder 2810 for decoding the value of the image data sent from the logic circuit section 27, and a level according to the decoded value. A voltage dividing circuit 2890 that divides the voltages V1 to Vk sent from the adjusting circuit 26 and an analog selector 2800 that selects one of the divided voltages may be provided.

  The output circuit 28 can be configured in various ways. As shown in FIG. 19C, a decoder 2810 for decoding the value of the image data sent from the logic circuit unit 27, and a decoded value, A sample hold circuit 2820 for holding the power supply voltage VDR at the timing of each clock signal DCLK, and any of the voltages V1 to Vk sent from the gradation circuit 26 using the held power supply voltage VDR as a control input (for example, a gate voltage). A transistor (for example, FET) 2830 for selectively outputting the above can also be used.

  In any case, if the image data values are the same, the output voltage of the output circuit 28 is determined by the voltages V1 to Vk sent from the gradation circuit 26 and the power supply voltage VDR.

  With the above configuration, the waveforms of the signal voltage Vd applied to the signal electrode and the power supply voltage VDR applied to the signal circuit 1 are shown in FIG. 20 in the non-power saving operation mode and in the power saving operation mode. It changes as shown.

  In the figure, (a) represents the non-power save operation mode, and (b) represents the power save operation mode.

  As shown in the figure, in the power saving operation mode, a low signal voltage is applied to the signal electrode due to the influence of the gradation voltages V1 to Vk and the power supply voltage VDR, which are reduced compared to the non-power saving operation mode. Accordingly, the power consumption is also reduced compared to the non-power saving operation mode.

  In this case, in the power saving operation mode, the display is lower or higher in luminance than in the non-power saving operation mode, but the user is not working in the power saving operation mode. There is no problem because it is a period.

  In general, the scanning drive circuit 3 includes a driver circuit that sequentially drives the scanning lines using the supplied power, so that the power supply voltage supplied to the driver circuit is lowered during the power save mode operation. However, the power consumption can be reduced as in the fourth embodiment.

  The fifth embodiment of the liquid crystal display device according to the present invention will be described below.

FIG. 17 shows the configuration of the voltage control circuit 6 according to the fifth embodiment.
As shown in the figure, the voltage control circuit 6 includes a gradation circuit 26, and includes gradation circuits 26 and gradation voltage generation circuits 26a to 26e.

  Each gradation voltage generation circuit 26a to 26e generates gradation voltages V1 to Vk shown in FIG. 22A in the non-power-saving operation mode. In the power saving operation mode, gradation voltages V1 to Vk shown in FIG. 22B are generated.

  That is, only V1 and V2 are changed, and other output voltages are set to a constant voltage (Vc) so as not to change.

  In the figure, the voltage polarity is changed every horizontal scanning time ta by the line-by-line polarity inversion driving method.

  In the fifth embodiment, a predetermined pattern is displayed on the liquid crystal matrix panel by the display control circuit 5 having the pattern generator 20 shown in FIG.

  For example, in the output circuit 28 shown in FIG. 19 (a), the voltages V1 and V2 are selected for the part displaying the pattern, and any one of the voltages V3 to Vk is selected for the other parts. The value of the image data output from the pattern generator 20 is given in advance.

  Accordingly, when the pattern shown in FIG. 23 is displayed, as shown in FIG. 24, the background portion 2300 is driven at a constant voltage level, and the portion 2301 displaying the pattern is driven at voltages V1 and V2.

  The voltage control circuit 6 according to the fifth embodiment may be configured as shown in FIG.

  As shown in the figure, the voltage control circuit 6 includes a gradation circuit 26, a gradation circuit 41, a gradation control circuit 42, and a switch circuit 35.

  The gradation circuit 26 generates gradation voltages V1 to Vk whose polarities are inverted every horizontal scanning period shown in FIG. 22A from the supplied power supply voltage and the horizontal synchronization signal HSYNC. The grayscale voltages V1 to Vk whose polarities are inverted every horizontal scanning period shown in FIG. 22B are generated from the supplied power supply voltage and the horizontal synchronization signal HSYNC.

  The gradation control circuit 42 controls the switch circuit 35, selects the output voltage of the gradation circuit 26 and supplies it to the signal drive circuit 1 during the non-power save mode operation, and the gradation circuit 41 operates during the power save mode operation. An output voltage is selected and applied to the signal drive circuit 1.

  The gradation control circuit 42 stops the operation of the gradation circuit 41 during the non-power save mode operation, and stops the operation of the gradation circuit 26 during the power save mode operation. The operation can be stopped by, for example, stopping the supply of power, or stopping the supply of the horizontal synchronization signal HSYNC and the clock signal DCLK used to invert the polarity of the generated voltage.

  In the fifth embodiment, only V1 and V2 may be changed, and the other output voltages may be voltages having amplitudes smaller than those of V1 and V2.

  Alternatively, only V1 may be changed, the other output voltage may be constant or a voltage having an amplitude smaller than V1, and the character or the like may be simply driven by V1, and the background may be driven by another voltage.

  By doing so, it is possible to reduce the power consumption of a gradation circuit that is generally composed of a differential amplifier, a resistor, a capacitor, and the like. Furthermore, by making the voltage input to the signal driving circuit 1 constant or reducing the amplitude, current due to stray capacitance in the signal driving circuit 1 and the liquid crystal matrix panel 2 can be reduced, and power consumption can be reduced.

  As described above, according to the embodiments of the liquid crystal display device of the present invention, it is possible to reduce the power consumption in the power saving operation mode while performing a constant display.

  In the above embodiment, the liquid crystal display device in which the signal driving circuit 1 drives the liquid crystal matrix panel according to the image data which is digital data has been described. However, the signal driving circuit 1 directly corresponds to the analog image signal. In an apparatus for driving a panel, the signal driving circuit 1 in the fourth embodiment may be configured as shown in FIG.

  That is, the input analog image signal 2850 is sampled and held in synchronization with the sample clock signal 2804 corresponding to the data clock, and the sample and hold circuits 2803 for the number of signal electrodes, and each sample is sequentially and cyclically based on the sample clock signal. A logic circuit unit 2805 for giving a sampling operation permission signal of the hold circuit 2803, provided for each sample and hold circuit, amplifies the sampled and held voltage using the power supply voltage (VN2 or VS2) supplied from the selection circuit 24, You may make it comprise from the driver circuit 2801 given to a corresponding signal electrode. When the signal driving circuit 1 directly drives the liquid crystal matrix panel in accordance with the analog image signal as described above, when the polarity is inverted for each line or frame, the timing of the polarity inversion is used. In synchronism, a circuit for inverting the polarity of the analog image signal applied to the driving method signal driving circuit 1 and shifting the analog image signal voltage by the amount corresponding to the common voltage may be provided.

  In the sixth embodiment, when the signal driving circuit 1 directly drives the liquid crystal matrix panel according to the analog image signal using the signal driving circuit 1 shown in FIG. 26, the signal voltage shown in FIG. The pattern generator 20 may be configured to generate an analog image signal that is output from the signal driving circuit 1.

  In the above embodiment, when the liquid crystal display device 10 receives the power save control signal 2003 from the CPU 1001, the liquid crystal display device 10 shifts to the power save operation mode, but the liquid crystal display device itself determines the usage status of the information device 1000. Thus, the mode may be automatically shifted to the power saving operation mode. For example, a frame buffer for storing one frame of image data is provided in the liquid crystal display device 10, and a change between two consecutive frames is determined by determining whether the image data in the frame buffer matches the input image data. If the predetermined number of frames does not change, it can be realized by determining that the frame is not currently used by the user and automatically shifting to the power saving operation mode. Alternatively, the state of the power switch may be directly read to shift to the power saving operation mode.

It is a figure which shows the external appearance of the information equipment which concerns on the Example of this invention. It is a block diagram which shows the structure of the information equipment which concerns on the Example of this invention. It is a block diagram which shows the structure of the liquid crystal display device based on the Example of this invention. It is a block diagram which shows the structure of a liquid crystal matrix panel. It is a figure which shows the operation | movement at the time of the normal mode of the liquid crystal display device based on the Example of this invention. FIG. 6 is a timing diagram illustrating a driving voltage waveform in a normal mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 6 is a timing diagram illustrating a first drive voltage waveform in a power save mode of the liquid crystal display device according to the embodiment of the present invention. FIG. 6 is a timing diagram illustrating a second driving voltage waveform in the power save mode of the liquid crystal display device according to the first embodiment of the present invention. It is a block diagram which shows the structure of the 1st display control circuit based on 2nd Example of this invention. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 2nd Example of this invention. It is a block diagram which shows the structure of the 2nd display control circuit based on 2nd Example of this invention. It is a figure which shows the polarity of the voltage applied to a pixel by the polarity reversal drive method for every line. FIG. 5 is a timing diagram showing signal voltages corresponding to respective gradations applied to signal lines by a line-by-line polarity inversion driving method. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 3rd Example of this invention. It is a figure which shows the polarity of the voltage applied to a pixel by the polarity inversion drive method for every pixel. It is a figure which shows the polarity of the voltage applied to a pixel by the drive method which combined the polarity inversion drive method for every pixel and the polarity inversion drive method for every line. It is a block diagram which shows the structure of the voltage control circuit which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the signal drive circuit which concerns on 4th Example of this invention. It is a block diagram which shows the structure of the output circuit which concerns on 4th Example of this invention. It is a timing diagram which shows the signal drive voltage waveform which concerns on 4th Example of this invention. It is a block diagram which shows the 1st structure of the voltage control circuit which concerns on 5th Example of this invention. It is a timing diagram which shows the output voltage waveform of the voltage control circuit which concerns on 5th Example of this invention. It is the figure which showed the appearance of the pattern display at the time of the power save mode which concerns on 5th Example of this invention. FIG. 10 is a timing diagram illustrating drive voltage waveforms in a power save mode of a liquid crystal display device according to a fifth embodiment of the present invention. It is a block diagram which shows the 2nd structure of the voltage control circuit which concerns on 5th Example of this invention. It is a block diagram which shows the other structure of the output circuit based on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal drive circuit 2 Liquid crystal matrix panel 3 Scan drive circuit 4 Light source 5 Display control circuit 6 Voltage control circuit 7 Interface circuit

Claims (4)

Is configured to have a plurality of signal lines arranged to intersect the plurality of scanning lines and the plurality of scanning lines supply, a matrix panel for polarity inversion driving, a signal voltage to each of said plurality of signal lines a signal driver for, in a display device having a scan driver for supplying a scan voltage to each of the plurality of scanning lines,
It applies a voltage at a cycle in each of the previous SL plurality of scanning lines, a first mode of updating the voltage applied to the plurality of signal lines from the signal driver in the first cycle,
Applies a voltage at a cycle in the each of the previous SL plurality of scanning lines, said signal driving unit holds the image data contained in a certain order line to the particular order of the line, from the following the certain order A second mode in which the voltage applied from the signal driver to the plurality of signal lines is updated in a longer cycle than the first cycle by repeating the process of discarding the image data up to the specific order line. and, to have a display device.   2. The display device according to claim 1, wherein the period of the second mode is a period that is n (n is a natural number of 2 or more) times the period of the first mode.   The display device according to claim 1, wherein the certain period and the first period are the same period.   The display device according to claim 1, wherein the display device is a liquid crystal display device.