JP2004087744A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- JP2004087744A JP2004087744A JP2002246093A JP2002246093A JP2004087744A JP 2004087744 A JP2004087744 A JP 2004087744A JP 2002246093 A JP2002246093 A JP 2002246093A JP 2002246093 A JP2002246093 A JP 2002246093A JP 2004087744 A JP2004087744 A JP 2004087744A
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Abstract
Description
【0001】
【発明の属する技術分野】
本発明は半導体装置の製造技術に係わり、特にレジスト膜を除去する工程に関する。
【0002】
【従来の技術】
半導体製造分野において、レジスト膜は下層の導体膜或いは絶縁膜のパターン形成のためのマスクとして半導体基板主面に形成される。
このレジスト膜の除去方法としては、酸素のプラズマを用いる方法が非常に一般的である。また、異方性を得るために試料にバイアスを印加して、酸素に窒素を混ぜたガスのプラズマで処理する方法、窒素と水素を混合したガスのプラズマで処理する方法、アンモニアガスのプラズマで処理する方法、水素のみのプラズマで処理する方法などが検討されている。
【0003】
【発明が解決しようとする課題】
半導体装置の製造工程では、数年以内に配線間の絶縁材料としてカーボン元素を含む低誘電率膜が用いられる見通しである。
このような工程では、エッチング後の低誘電率膜に寸法変動や変質なくマスク材料のレジストを除去する技術が必要になる。
また、通常レジスト除去後には再びリソグラフィでマスクを形成する。リソグラフィは微量な酸による触媒反応を使う技術のため、これを阻害するNH4+などのアルカリ性塩基が低誘電率膜中に生成されないレジスト除去方法が必要である。
また、低誘電率膜除去後には150nm〜300nm程度のレジストが残っているため、スループットの観点から最低でも100nm/分以上のレジスト除去速度が必要である。これらのレジスト除去の要求に対して、従来の酸素ガスのプラズマや酸素と窒素の混合ガスのプラズマによる処理では、カーボン元素を含む低誘電率膜にサイドエッチや変質を生じる問題がある。
また、水素と窒素の混合ガスやアンモニアのプラズマによる処理では、低誘電率膜中にNH4+のアルカリ性塩基を生成するため、露光不良を引き起こす問題がる。また、水素のみのプラズマ処理では十分なエッチング速度がえられない問題がある。
本発明は、カーボン元素を含む低誘電率膜を用いた半導体の製造工程において、量産適用可能なレジストマスクの除去方法を提供する。
【0004】
【課題を解決するための手段】
水素に希ガスを添加した混合ガスのプラズマを用い、かつ、試料に高周波バイアスを印加する。
【0005】
【発明の実施の形態】
(実施例1)
(1)水素とネオン、(2)水素とアルゴン、(3)水素とクリプトンの各混合ガスのプラズマを用いて、0.5W/cm2の高周波バイアスを印加した試料上のレジストの除去を検討した。試料(半導体基板)は、カーボン元素を含む低誘電率膜のMSQ(methylsilsequioxane)にホールパターンのレジストマスクを形成し、前記ホールパターンに合わせてMSQをエッチングしたものを用いた。
各混合ガスのプラズマのレジスト除去速度と希ガスの添加率の関係を図1に示す。質量数の小さいネオンの添加ではガスを添加しても高いエッチング速度が得られない。質量数の大きいアルゴンやクリプトンの添加によって高い除去速度が得られることがわかった。
アルゴンやクリプトン添加で高い除去速度が得られる理由は、高周波バイアスによって加速された質量数の大きい希ガスのイオンが試料に照射されることによって、水素ラジカルによるレジスト除去反応が促進されるためであることがわかった。
また、この機構のため、水素ラジカルや希ガスのイオンが多く作られる高密度プラズマ程、高いレジスト除去速度が得られることがわかった。
また、レジスト除去後の形状は、いずれの方法でも、垂直形状が得られることが確認された。
(実施例2)
図2は本発明のレジスト除去方法を半導体装置の多層配線工程に適用した例である。本配線工程では(1)ケミカルベーパーデポジション法(CVD法)によるSiC膜の形成(2)回転塗布法(SOD法)によるMSQの堆積(3)MSQ上へのにSiONの作成(4)リソグラフィー法によるレジストマスク作成(5)レジストマスクに沿ってCHF系ガスのプラズマによるSiONおよびMSQをエッチングするよって、MSQにViaホールを作成する。この時のプロセス断面図を図3に示す。1は半導体基板、2はSiC膜、3はMSQ膜、4はSiONそして5はレジストマスクである。次に、(6)実施例1に記載の水素とクリプトンの混合ガスプラズマによるレジスト除去を行い(7)再びリソグラフィーによってトレンチパターンを形成する(8)レジストマスクに沿ってCHF系ガスのプラズマによるSiONおよびMSQのエッチングすることによってホールおよびトレンチ構造が形成される。この時のプロセス断面図を図4に示す。
さらに(9)SiCの除去した後、(10)残ったレジストマスクを除去し、(11)ホールおよびトレンチ構造にスパッタ法によってCuの拡散防止膜Ta,TaN層とメッキのシード層Cuを順に形成する。(12)この後メッキ法によってCuを埋め込む。次に埋め込み工程でMSQ上に表面上に堆積した余剰なCuおよび拡散防止膜をSiONの上層部とともに(13)ケミカルメカニカルポリッシング法(CMP法)で除去し、(14)薬液による洗浄を行う。
洗浄した試料を、再び工程(1)のCVDから順に繰り返し処理することによって多層配線が形成される。(6)のレジスト除去工程に水素とクリプトンの混合ガスの添加を用いた本製造方法で作られた半導体装置の歩留まりは90%であった。一方、(6)の工程で窒素と水素の混合ガスのプラズマを用いたものは、(7)のリソグラフィー工程の露光不良によって歩留まりが50%に低下した。また、(6)や(10)のレジスト除去工程に酸素を含むガスプラズマを用いた場合は、MSQが変質し、高周波特性が大幅に劣化した。
以上のように、カーボン元素を含む絶縁膜を用いた半導体の製造工程では、レジストマスクの除去の際に水素と希ガスの混合ガスのプラズマを用いることで信頼性の高い半導体装置を作ることができる。
【0006】
【発明の効果】
本発明の半導体装置の製造工程を用いることで、高い信頼性の半導体装置を作ることができる。
【図面の簡単な説明】
【図1】水素と希ガスの混合ガスのプラズマを用いた場合のレジスト除去速度を示す特性図。
【図2】本発明のエッチング方法を適用した半導体装置の多層配線工程を示すフローチャート図。
【図3】本発明の半導体装置の製造過程を示す断面図。
【図4】本発明の半導体装置の製造過程を示す断面図。
【符号の説明】
1…半導体基板、2…SiC膜、3…MSQ膜、4…SiON、5…レジストマスク。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly to a step of removing a resist film.
[0002]
[Prior art]
In the field of semiconductor manufacturing, a resist film is formed on a main surface of a semiconductor substrate as a mask for forming a pattern of a lower conductive film or an insulating film.
As a method for removing the resist film, a method using oxygen plasma is very common. In addition, a method of applying a bias to a sample to obtain anisotropy and treating with a plasma of a gas in which nitrogen is mixed with oxygen, a method of treating with a plasma of a gas in which nitrogen and hydrogen are mixed, and a method of treating with a plasma of ammonia gas A method of processing, a method of processing with plasma of only hydrogen, and the like are being studied.
[0003]
[Problems to be solved by the invention]
In the process of manufacturing a semiconductor device, it is expected that a low dielectric constant film containing a carbon element will be used as an insulating material between wirings within several years.
In such a process, a technique for removing the resist of the mask material from the low-dielectric-constant film after etching without dimensional change or deterioration is required.
After the removal of the resist, a mask is formed again by lithography. Since lithography is a technique using a catalytic reaction with a trace amount of acid, a resist removing method is required in which an alkaline base such as NH4 + that inhibits this is not generated in the low dielectric constant film.
Further, since the resist of about 150 nm to 300 nm remains after the removal of the low dielectric constant film, a resist removal rate of at least 100 nm / min or more is required from the viewpoint of throughput. In response to these requirements for resist removal, conventional processing using plasma of oxygen gas or plasma of mixed gas of oxygen and nitrogen has a problem of causing side etching and alteration in a low dielectric constant film containing a carbon element.
In addition, in the case of processing using a mixed gas of hydrogen and nitrogen or plasma of ammonia, an alkaline base of NH4 + is generated in the low dielectric constant film, which causes a problem of causing exposure failure. Further, there is a problem that a sufficient etching rate cannot be obtained by the plasma treatment using only hydrogen.
The present invention provides a method of removing a resist mask applicable to mass production in a semiconductor manufacturing process using a low dielectric constant film containing a carbon element.
[0004]
[Means for Solving the Problems]
A plasma of a mixed gas obtained by adding a rare gas to hydrogen is used, and a high-frequency bias is applied to the sample.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
Using a plasma of a mixed gas of (1) hydrogen and neon, (2) hydrogen and argon, and (3) hydrogen and krypton, removal of the resist from the sample to which a high-frequency bias of 0.5 W /
FIG. 1 shows the relationship between the plasma resist removal rate of each mixed gas and the rare gas addition rate. With the addition of neon having a small mass number, a high etching rate cannot be obtained even if a gas is added. It was found that a high removal rate can be obtained by adding argon or krypton having a large mass number.
The reason why a high removal rate can be obtained by adding argon or krypton is that a resist removal reaction by hydrogen radicals is promoted by irradiating a sample with ions of a rare gas having a large mass number accelerated by a high frequency bias. I understand.
In addition, it was found that, due to this mechanism, a higher resist removal rate can be obtained with a higher density plasma in which more hydrogen radicals and rare gas ions are produced.
In addition, it was confirmed that a vertical shape can be obtained by any method after removing the resist.
(Example 2)
FIG. 2 shows an example in which the resist removing method of the present invention is applied to a multilayer wiring process of a semiconductor device. In this wiring process, (1) formation of SiC film by chemical vapor deposition method (CVD method) (2) deposition of MSQ by spin coating method (SOD method) (3) formation of SiON on MSQ (4) lithography (5) Via holes are formed in the MSQ by etching SiON and MSQ by plasma of a CHF-based gas along the resist mask. FIG. 3 shows a cross-sectional view of the process at this time. 1 is a semiconductor substrate, 2 is a SiC film, 3 is an MSQ film, 4 is SiON, and 5 is a resist mask. Next, (6) the resist is removed by the mixed gas plasma of hydrogen and krypton described in Example 1, and (7) a trench pattern is formed again by lithography. (8) SiON by plasma of CHF-based gas along the resist mask. And etching of the MSQ forms a hole and trench structure. FIG. 4 shows a process sectional view at this time.
(9) After the removal of SiC, (10) the remaining resist mask is removed, and (11) a Cu diffusion prevention film Ta, a TaN layer and a plating seed layer Cu are sequentially formed on the hole and trench structures by sputtering. I do. (12) Thereafter, Cu is embedded by plating. Next, the excess Cu and the diffusion preventing film deposited on the surface of the MSQ in the embedding process are removed together with the upper layer of SiON by (13) chemical mechanical polishing (CMP), and (14) cleaning with a chemical solution is performed.
The washed sample is repeatedly processed in order from the CVD in the step (1) again to form a multilayer wiring. The yield of the semiconductor device manufactured by this manufacturing method using the addition of the mixed gas of hydrogen and krypton in the resist removing step (6) was 90%. On the other hand, in the case of using the plasma of the mixed gas of nitrogen and hydrogen in the step (6), the yield was reduced to 50% due to exposure failure in the lithography step of (7). Further, when gas plasma containing oxygen was used in the resist removal step (6) or (10), the MSQ was altered and the high frequency characteristics were significantly deteriorated.
As described above, in a semiconductor manufacturing process using an insulating film containing a carbon element, a highly reliable semiconductor device can be manufactured by using plasma of a mixed gas of hydrogen and a rare gas when removing a resist mask. it can.
[0006]
【The invention's effect】
By using the manufacturing process of the semiconductor device of the present invention, a highly reliable semiconductor device can be manufactured.
[Brief description of the drawings]
FIG. 1 is a characteristic diagram showing a resist removal rate when plasma of a mixed gas of hydrogen and a rare gas is used.
FIG. 2 is a flowchart showing a multilayer wiring step of a semiconductor device to which the etching method of the present invention is applied.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.
FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.
[Explanation of symbols]
DESCRIPTION OF
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JP2002246093A JP2004087744A (en) | 2002-08-27 | 2002-08-27 | Method of manufacturing semiconductor device |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006025123A1 (en) * | 2004-09-01 | 2006-03-09 | Shibaura Mechatronics Corporation | Ashing method and ashing apparatus |
US7169708B2 (en) | 2004-06-28 | 2007-01-30 | Rohm Co., Ltd. | Semiconductor device fabrication method |
JP2008072101A (en) * | 2006-09-12 | 2008-03-27 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
JP2014513868A (en) * | 2011-03-14 | 2014-06-05 | プラズマ − サーム、エルエルシー | Method and apparatus for plasma dicing semiconductor wafer |
-
2002
- 2002-08-27 JP JP2002246093A patent/JP2004087744A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7169708B2 (en) | 2004-06-28 | 2007-01-30 | Rohm Co., Ltd. | Semiconductor device fabrication method |
WO2006025123A1 (en) * | 2004-09-01 | 2006-03-09 | Shibaura Mechatronics Corporation | Ashing method and ashing apparatus |
US8524102B2 (en) | 2004-09-01 | 2013-09-03 | Shibaura Mechatronics Corporation | Ashing method and ashing device |
JP2008072101A (en) * | 2006-09-12 | 2008-03-27 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
JP2014513868A (en) * | 2011-03-14 | 2014-06-05 | プラズマ − サーム、エルエルシー | Method and apparatus for plasma dicing semiconductor wafer |
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