JP2004072635A - Gate drive circuit of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate driving device of a semiconductor device capable of suppressing surge voltage even when characteristics of the semiconductor device are dispersed. <P>SOLUTION: Resistors R1, R2 discharge gate electric charge in parallel by a fact that output of a control circuit 104 is switched from H to L and transistors Q2 and Q3 is turned on when an IGBT (insulated gate bipolar transistor) device Q1 is turned off. A MOSFET (metal oxide semiconductor field effect transistor) Q4 is turned off by output of a delay circuit after elapse of prescribed time from turn off. At the point of time, an operation amplifier 105 detects gate voltage divided by resistors R3, R4 and outputs the gate voltage to a CR integration circuit 103. A MOSFET Q5 is turned off and discharge of gate electric charge by the resistor R1 is stopped when the output voltage reaches a gate threshold of the MOSFET 5 based on a time coefficient of the CR integration circuit. Consequently, discharge speed is changed at the set optimal timing even when gate voltage of the IGBT device is dispersed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a gate drive circuit for a semiconductor element that turns on and off a semiconductor element according to an input drive signal.
[0002]
[Prior art]
In a gate drive circuit of a semiconductor device, a voltage detecting means for detecting a collector voltage of the semiconductor device is provided in order to suppress a surge voltage generated when the semiconductor device is turned off, and when a voltage between the collector and the emitter reaches a predetermined value. Therefore, after a predetermined time from the operation of the delay circuit, the resistance value of the discharge resistor connected to the gate terminal and the ground and discharging the gate charge is changed, and the discharge speed is reduced by increasing the resistance value. If the resistance value is changed early, there is a problem that the switching loss increases, so that it is set immediately before the start of the cutoff of the collector current.
[0003]
In order to prevent the change timing of the resistance value from being shifted due to the variation in component characteristics, Japanese Patent Application Laid-Open No. 2001-314075 discloses a detection circuit for detecting that the voltage between the gate and the emitter has reached a predetermined value. The logical product of the output of the detection circuit and the output of the delay circuit is calculated, and the resistance value is changed according to the result of the logical product calculation.
[0004]
That is, when the delay time of the delay circuit is equal to the set value, the resistance of the discharge resistor is changed at the set timing as in the related art, and control is performed to slow the discharge speed just before the collector current starts to be cut off. If the delay time of the delay circuit is shorter than the set value, the resistance value of the discharge resistor is changed when the voltage between the gate and the emitter reaches a predetermined value according to the result of the logical product operation. Is prevented from being advanced, and an increase in switching loss is prevented.
[0005]
[Problems to be solved by the invention]
However, the above-described countermeasures against variations in component characteristics have the following problems. That is, regardless of the characteristics of the semiconductor device, when the voltage between the gate and the emitter reaches a predetermined value, an AND operation is performed. If the characteristics of the semiconductor element are different, such as a variation in threshold value, the resistance value of the discharge resistor cannot be changed at an optimal timing, and there is a possibility that the surge voltage cannot be reliably suppressed.
The present invention has been made in view of the above-mentioned conventional problems, and even when the characteristics of semiconductor elements are different, it is possible to change the resistance value of the discharge resistor at a desired timing and prevent the occurrence of surge voltage while preventing an increase in switching loss. It is an object of the present invention to provide a gate drive circuit for a semiconductor element that can be reliably suppressed.
[0006]
[Means for Solving the Problems]
For this reason, the present invention provides a gate voltage detecting means that is connected to a gate terminal of a semiconductor element and that can change a resistance value of a discharge resistor that discharges a gate charge when the semiconductor element is turned off, and that detects a gate voltage of the semiconductor element. The timing for performing control to change the resistance value of the discharge resistor is set based on the voltage detected by the gate voltage detection means after a predetermined time has elapsed from the start of turn-off of the semiconductor element. At the start of the turn-off of the semiconductor element, the discharge resistor discharges the gate charge of the semiconductor element at a predetermined resistance value, and at a set timing, the resistance value of the discharge resistor is increased by the control of the resistance control means. The discharging speed for discharging the electric charges is reduced.
[0007]
【The invention's effect】
The gate voltage at a predetermined time after the start of turn-off is detected, and the timing for changing the resistance value of the discharge resistor is set based on the detected voltage. Even if the threshold value of the voltage fluctuates, it is possible to change the resistance value of the discharge resistor at an optimum time immediately before the start of the cutoff of the collector current. For this reason, even if the semiconductor element characteristics are different, the surge voltage can be controlled, and the destruction of components due to the surge voltage can be prevented, and the effect of preventing an increase in switching loss can be obtained.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the invention will be described with reference to examples.
FIG. 1 is a diagram showing a gate drive circuit of a semiconductor device.
The collector terminal C of the IGBT element Q1 used as a semiconductor element is connected to the power supply VB via the load 101, and the emitter terminal E of the IGBT element Q1 is connected to ground (GND). The gate terminal G of the IGBT element Q1 is connected to the gate power supply VCC via the resistor R8 and the NPN transistor Q6, so that the transistor Q6 can charge the IGBT element Q1 with a gate charge.
[0009]
The gate terminal G of the IGBT element Q1 is connected to GND via a resistor R1, a PNP transistor Q2 and a Pch-MOSFET Q5, and is also connected to GND via a resistor R2 and a PNP transistor Q3. The resistor R1 can discharge a gate charge to the IGDT element Q1 by controlling the PNP transistor Q2 and the Pch-MOSFET Q5 as a first discharging resistor. The resistor R2 serves as a second discharging resistor so that the gate charge can be discharged by controlling the PNP transistor Q3.
The resistance value of the resistor R1 is smaller than the resistance value of the resistor R2.
[0010]
The base terminals of transistors Q2 and Q3 are connected to the output of control circuit 104 via resistors R7 and R6, respectively, and transistors Q2 and Q3 are turned on when drive signal Vin output from control circuit 104 is at L level. ing. The base terminal of the transistor Q6 is connected to the output of the control circuit 104 via the resistor R9, and the transistor Q6 is turned on when the drive signal Vin output from the control circuit 104 is at the H level. Therefore, the IGBT element Q1 is turned on / off by the drive signal Vin of the control circuit 104, and the load 101 can be driven.
[0011]
Between the gate terminal of the IGBT element Q1 and GND, a voltage dividing circuit including a resistor R3 and a resistor R4 connected in series is connected, and a positive input terminal of the operational amplifier 105 is connected to a connection terminal of the two resistors. The negative input terminal of the operational amplifier 105 is directly connected to the output terminal, and is configured to divide the gate voltage Vge of the IGBT element Q1, convert the impedance, and detect the impedance. Here, the resistors R3 and R4 have sufficiently large resistance values as compared with the resistors R1, R2 and R8, and the current flowing from the gate terminal of the IGBT element Q1 to the resistors R3 and R4 is sufficiently small. It is configured.
[0012]
An output terminal of the operational amplifier 105 is connected to an input terminal of a CR integration circuit 103 including a resistor and a capacitor. The output terminal of the CR integration circuit 103 is connected to the gate of the Pch-MOSFET Q5. The output terminal of the operational amplifier 105 is connected to GND via a resistor R5 and an Nch-MOSFET Q4. The gate terminal of the MOSFET Q4 is connected to the output of the delay circuit 102 connected to the output terminal of the control circuit 104.
[0013]
Next, the operation of the above circuit will be described.
FIG. 2 is a time chart showing an operation when the IGBT element Q1 is turned off from a completely on state.
Vin is the output of the control circuit 104, Vge is the gate voltage of the IGBT element Q1, Vdly is the output of the delay circuit 102, VG is the output of the operational amplifier 105, VGt is the output of the CR integration circuit 103, and Ic is the collector current flowing through the IGBT element Q1. , Vce indicate a collector voltage generated in the IGBT element Q1, Ig1 indicates a gate current flowing through the resistor R1, and Ig2 indicates a gate current flowing through the resistor R2.
In the figure, each waveform (a) or (b) shows a waveform when a characteristic difference occurs due to manufacturing variations or temperature characteristics of the IGBT element Q1.
[0014]
At time t1 when the output Vin of the control circuit 104 switches from the H level to the L level, the transistors Q2 and Q3 are turned on. At this time, the Pch-MOSFET Q5 is turned on, so that the gate current from the gate of the IGBT element Q1 toward GND is turned on. Ig1 and Ig2 are generated. Thereby, the gate charge of the IGBT element Q1 is discharged, and the gate voltage Vge of the IGBT element Q1 decreases. At this time, Ig1≫Ig2 due to the relationship of the resistances R1≪R2. At time t1, the delay circuit 102 to which the output signal Vin of the control circuit 104 is input is activated, and outputs the delay signal Vdly at time t2 after a lapse of a predetermined time.
[0015]
At time t2 when the MOSFET Q4 is turned off due to the delay signal Vdly, the output voltage VG of the operational amplifier 105 becomes a voltage level obtained by dividing the gate voltage of the IGBT element Q1 by the resistors R3 and R4, and the output voltage VG of the operational amplifier 105 is input. The CR integration circuit 103 outputs a signal whose voltage changes in proportion to the level of the input voltage VG according to a predetermined CR time constant. The time required for this signal to reach the operation threshold value of MOSFET Q5 from time t2 varies depending on the level (a) or (b) of voltage VG input according to the characteristics of IGBT element Q1. Become.
[0016]
At time t3 when the output voltage VGt of the CR integration circuit 103 reaches the threshold value of the MOSFET Q5 and the MOSFET Q5 shifts from on to off, the transistor Q2 is turned off, the path through which the gate current Ig1 flows is cut off, and the IGBT element Q1 Discharge current of the gate charge is only Ig2. As a result, the discharge speed becomes slower, so that di / dt when the collector current Ic of the IGBT element Q1 is cut off can be reduced, and the collector voltage Vce of the IGBT element Q1 is not affected by the difference in characteristics of the IGBT element Q1. Surge voltage Vs (a) and Vs (b) can be suppressed.
[0017]
As described above, even when the characteristic difference of the IGBT element Q1 occurs, in (a) or (b), the time until the gate current Ig1 path is cut off can be varied according to the Vge voltage level at the predetermined time t2. By doing so, the collector current Ic of the IGBT element Q1 is always adjusted to be small immediately before the interruption, and the timing for switching the discharge resistor can be optimized. Di / dt can be alleviated without being greatly affected by characteristic variations, and an effect of suppressing a surge voltage Vs generated in the IGBT element Q1 collector voltage Vce can be stably obtained. Further, by optimizing the timing of switching the discharge resistor, the switching loss can be minimized.
[0018]
FIG. 3 is a diagram showing a waveform when a Vge voltage detected by the operational amplifier 105 is directly applied to the MOSFET Q5 without providing a CR integration circuit for comparison.
In (a) ′, constants are adjusted for the discharge resistors R1 and R2 according to the characteristic (a) ′ of the semiconductor element, and the Ic and Vce waveforms when the surge voltage is suppressed to Vs (a) ′. Is shown.
As described above, the timings tg (a) ′ and tg (b) ′ at which the discharge resistance is switched from low to high are determined at the predetermined determination level of the gate voltage. , The collector current is cut off at time tg (b) ′. However, at Vge (b) ′ where the IGBT elements vary, the collector current is already being cut off at time tg (b) ′, and di / dt is determined only by a substantially small discharge resistance. Therefore, after that, di / dt is not reduced, and the surge voltage Vs (b) ′ becomes larger than Vs (a) ′.
[0019]
In the embodiment, the timing of changing the resistance value of the discharge resistor is adjusted according to the gate-emitter voltage of the IGBT element Q1, so that even if the characteristics of the IGBT element Q1 vary, Immediately before the current starts to be cut off, the discharge current of the gate charge can be adjusted to be small, the surge voltage can be effectively suppressed, and the switching loss can be prevented from increasing.
In this embodiment, the resistors R1 and R2 constitute a discharge resistor.
The operational amplifier 105 and the resistors R3 and R4 constitute an operational amplifier circuit and a gate voltage detecting unit.
The CR integration circuit 103 constitutes a change timing setting means.
MOSFET Q5 constitutes resistance control means.
The delay circuit 102 constitutes a delay unit.
In this embodiment, an IGBT element is used as a semiconductor element, but another semiconductor element can be used.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of the present invention.
FIG. 2 is a time chart showing the operation of the embodiment of the present invention.
FIG. 3 is a time chart for comparison.
[Explanation of symbols]
101 Load 102 Delay circuit 103 CR integration circuit 104 Control circuit 105 Operational amplifier Q1 IGBT element Q4 MOSFET (second transistor)
Q5 MOSFET (first transistor)
R1 resistance (first discharge resistance)
R2 resistance (second discharge resistance)
R8 resistance

Claims (4)

In a gate drive circuit of a semiconductor element for turning on and off a semiconductor element based on an input drive signal,
A discharge resistor connected to a gate terminal of the semiconductor element and discharging a gate charge when the semiconductor element is turned off;
Gate voltage detecting means for detecting a gate voltage of the semiconductor element,
Change timing setting means for setting a timing for performing control for changing a resistance value of the discharge resistor based on a gate voltage detected by the voltage detection means after a predetermined time has elapsed from the start of turn-off of the semiconductor element;
At the start of turn-off of the semiconductor element, the discharge resistor discharges the gate charge of the semiconductor element at a predetermined resistance value, and increases the resistance value of the discharge resistance at the timing set by the change timing setting means. And a resistance control means for changing a resistance value so as to cause the resistance to change. 2. The semiconductor device according to claim 1, further comprising: delay means for delaying an input drive signal by a predetermined time, wherein the output of the delay means causes the semiconductor element to have passed a predetermined time from the start of turn-off. Gate drive circuit for semiconductor devices. The change timing setting means is a CR integration circuit that receives the output of the gate voltage detection means as an input. When the output voltage of the CR integration circuit reaches a predetermined value, the change timing setting means changes the resistance value of the discharge resistor. 3. The gate drive circuit for a semiconductor device according to claim 1, wherein: In a gate drive circuit of a semiconductor element for turning on and off a semiconductor element based on an input drive signal,
A first discharge resistor and a second discharge resistor are connected to a gate terminal of the semiconductor element, and a voltage applied to a gate of the first discharge resistor reaches a gate threshold. A first transistor to be turned off is connected, and the first discharge resistor and the second discharge resistor are connected to ground when the semiconductor element is turned off, so as to discharge a gate charge.
An operational amplifier circuit for dividing and detecting a gate voltage is provided at a gate terminal of the semiconductor element,
An output of the operational amplifier circuit is connected to a gate terminal of the first transistor via a CR integration circuit, and a resistor and a second transistor are connected to an output of the operational amplifier circuit and ground,
A drive signal for driving the semiconductor element is output to a gate terminal of the second transistor via a delay circuit,
The second transistor is turned off after a predetermined time set by the delay circuit from the first time the level of the drive signal changes and the semiconductor element is turned off, and in response thereto, the operational amplifier circuit changes the gate voltage. The first transistor is detected and output to the CR integration circuit. When the output voltage of the CR integration circuit reaches the gate threshold value of the first transistor based on the time constant of the CR integration circuit, the first transistor is activated. A gate drive circuit for a semiconductor element, wherein the gate discharge is stopped by turning off the first discharge resistor.

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