JP2004070656A - Data transfer unit, data transfer method and program including the same method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To validly and efficiently use the storage area of a storage device incorporated in a data transfer unit. <P>SOLUTION: In this data transfer unit for temporarily storing data for transmission or reception in a storage device such as a single port memory 27, and for transferring the data, the storage device is divided into a plurality of blocks of predetermined same units. In response to transmission data writing request signal ITXFWREQB or ATXFWREQB at transferring and transmitting data, one unused block is selected from the plurality of blocks, and the selected block is turned into a use state, and the data for transmission are written in the selected block, and then read out and transferred. In response to a reception data writing request signal RXFRREQB at transferring and receiving the data, one unused block is selected from the plurality of blocks, and the selected block is turned into a use state, and the data for reception are written in the selected block, and read out and transferred. <P>COPYRIGHT: (C)2004,JPO

Description

【００６２】
【数２】

【００６３】
【数３】

【００６４】
ここで、“ＩＮＶ”は否定演算又は反転演算を意味し、“ＯＲ”は論理和演算を意味し、“ＡＮＤ”は論理積演算を意味する。
【００６５】
図１０は、図８の受信用タイミングコントローラ３１に内蔵される回路の一部であるカウンターの構成例を示すブロック図である。図１０のレジスタＲＷＲＮＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックの次に書き込みできるブロックを示す値が格納される。そして、そのレジスタＲＷＲＮＢＰＴＲの入力端子にはＢＥＭＰ［４：０］信号が入力される。また、レジスタＲＷＲＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックを示す値が格納され、その出力信号はＲＷＢ［４：０］信号として出力される。そして、レジスタＲＷＲＢＰＴＲの入力端子には、レジスタＲＷＲＮＢＰＴＲからの出力信号が入力される。また、６ビットアップカウンタ５１には、現在書き込んでいるブロックのどのアドレスを書き込むかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の書き込んでいるアドレスを示すＲＷＲＣＮＴ［１０：０］信号のうちの上位５ビットの信号は、レジスタＲＷＲＢＰＴＲからのＲＷＲＣＮＴ［１０：６］信号であり、その下位６ビットの信号は６ビットアップカウンタ５１のＤＯ［５：０］端子からのＲＷＲＣＮＴ［５：０］信号である。
【００６６】
また、ＲＢＡＬＡＣＫＢ信号は、オアゲートＯＲ１の第１の入力端子に入力され、オアゲートＯＲ１からの出力信号はナンドゲートＮＡＮＤ２の第１の入力端子に入力され、オアゲートＯＲ１からの出力信号はレジスタＲＷＲＮＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力されるとともに、２ビット同期アップダウンカウンタ５２のＤＢ入力端子及びナンドゲートＮＡＮＤ２の第１の入力端子に入力される。ナンドゲートＮＡＮＤ２からの出力信号はＤタイプのフリップフロップＦ１のＤ入力端子に出力され、フリップフロップＦ１からのＱ出力信号は、ＲＢＡＬＲＥＱＢ信号としてブロックコントローラ３５に出力されるとともに、オアゲートＯＲ１の第２の入力端子及びナンドゲートＮＡＮＤ１の第２の入力端子とに入力され、ナンドゲートＮＡＮＤ１からの出力信号はレジスタＲＷＲＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。フリップフロップＦ１からの反転ＱＢ出力信号はオアゲートＯＲ２の第２の入力端子に入力され、オアゲートＯＲ２からの出力信号はナンドゲートＮＡＮＤ２の第２の入力端子に出力される。６ビットアップカウンタ５１からのキャリーアウト信号（ＣＯ）はナンドゲートＮＡＮＤ３の第１の入力端子に入力され、ナンドゲートＮＡＮＤ３の第２の入力端子にはＲＸＷＲＢ信号がインバータＮ１を介して入力される。ナンドゲートＮＡＮＤ３からの出力信号は２ビット同期アップダウンカウンタ５２のＵＢ入力端子に出力されるとともに、インバータＮ２を介してアンドゲートＡＮＤ２の第１の入力端子に入力され、アンドゲートＡＮＤ２からの出力信号はＲＦＴ信号としてデータ選択コントローラ３４に出力される。２ビット同期アップダウンカウンタ５２からＤ０出力信号はアンドゲートＡＮＤ２の第２の入力端子とオアゲートＯＲ３の第１の入力端子とに入力され、２ビット同期アップダウンカウンタ５２のＤ１出力信号はオアゲートＯＲ３の第２の入力端子に入力されるとともに、ＲＸＦＵＬＬ信号としてＬＩＮＫ回路６に出力される。オアゲートＯＲ３からの出力信号はナンドゲートＮＡＮＤ１の第１の入力端子とオアゲートＯＲ２の第１の入力端子とに入力される。
【００６７】
また、レジスタＲＲＤＢＰＴＲは５ビットのレジスタであって、現在読み出しているブロックを示すＲＮＲＢ［４：０］信号の値が格納され、その出力信号はＲＲＢ［４：０］信号として出力される。また、６ビットアップカウンタ５３は、現在読み出しているブロックのどのアドレスを読み出すかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の読み出しているアドレスを示すＲＲＤＣＮＴ［１０：０］信号は、その上位５ビットの信号がレジスタＲＲＤＢＰＴＲからのＲＲＤＣＮＴ［１０：６］信号となり、その下位６ビットの信号が６ビットアップカウンタ５３から出力ＤＯ［５：０］信号であるＲＲＤＣＮＴ［５：０］信号となる。また、ＲＮＲＢＯＫ信号はナンドゲートＮＡＮＤ４の第１の入力端子に入力され、ナンドゲートＮＡＮＤ４の出力信号は、レジスタＲＲＤＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力されるとともに、ＤタイプのフリップフロップＦ２のＤ入力端子に入力される。フリップフロップＦ２のＱ出力信号はＤタイプのフリップフロップＦ３のＲＢ入力端子に出力される。６ビットアップカウンタ５３のキャリーアウト信号（ＣＯ）はナンドゲートＮＡＮＤ４の第１の入力端子に入力され、ナンドゲートＮＡＮＤ４の第２の入力端子にはＲＦＷＲＢ信号がインバータＮ３を介して入力される。ナンドゲートＮＡＮＤ４からの出力信号はＲＲＢＦＲＥＥ信号としてブロックコントローラ３５に入力されるとともに、クロック信号としてフリップフロップＦ３に入力される。フリップフロップＦ３のＤ入力端子はハイレベルを示す電圧源Ｖｃｃに接続され、フリップフロップＦ３からのＱ出力信号はナンドゲートＮＡＮＤ４の第２の入力端子に入力される。
【００６８】
図１１は、図８の同期送信用タイミングコントローラ３２に内蔵される回路の一部であるカウンターの構成例を示すブロック図である。図１１のレジスタＩＷＲＮＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックの次に書き込みできるブロックを示す値が格納される。そして、そのレジスタＩＷＲＮＢＰＴＲの入力端子にはＢＥＭＰ［４：０］信号が入力される。また、レジスタＩＷＲＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックを示す値が格納され、その出力信号はＩＷＢ［４：０］信号として出力される。そして、レジスタＩＷＲＢＰＴＲの入力端子にはレジスタＩＷＲＮＢＰＴＲからの出力信号が入力される。また、６ビットアップカウンタ５４は現在書き込んでいるブロックのどのアドレスを書き込むかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の書き込んでいるアドレスを示すＩＩＷＲＣＮＴ［１０：０］信号は、その上位５ビットがレジスタＩＷＲＢＰＴＲからの出力信号であるＩＷＲＣＮＴ［１０：６］信号となり、その下位６ビットが６ビットアップカウンタ５４からの出力ＤＯ［５：０］信号であるＩＷＲＣＮＴ［５：０］信号となる。
【００６９】
また、ＩＢＡＬＡＣＫＢ信号はオアゲートＯＲ４の第１の入力端子に入力され、オアゲートＯＲ４からの出力信号は、ナンドゲートＮＡＮＤ６の第１の入力端子に入力されるとともに、レジスタＩＷＲＮＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。ナンドゲートＮＡＮＤ６からの出力信号はＤタイプのフリップフロップＦ４のＤ入力端子に入力され、フリップフロップＦ４からのＱ出力信号は、ＩＢＡＬＲＥＱＢ信号としてブロックコントローラ３５に出力されるとともに、オアゲートＯＲ４の第２の入力端子とナンドゲートＮＡＮＤ５の第２の入力端子とに入力される。ナンドゲートＮＡＮＤ５からの出力信号はレジスタＩＷＲＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。６ビットアップカウンタ５４のキャリーアウト信号（ＣＯ）はアンドゲートＡＮＤ４の第１の入力端子に入力され、アンドゲートＡＮＤ４の第２の入力端子にはＩＦＲＤＢ信号がインバータＮ４を介して入力される。アンドゲートＡＮＤ４からの出力信号は、ナンドゲートＮＡＮＤ５の第１の入力端子とオアゲートＯＲ５の第１の入力端子とに入力され、フリップフロップＦ４からの反転ＱＢ出力信号はオアゲートＯＲ５の第２の入力端子に入力される。オアゲートＯＲ５からの出力信号はナンドゲートＮＡＮＤ６の第２の入力端子に入力される。
【００７０】
また、レジスタＩＲＤＢＰＴＲは５ビットのレジスタであって、現在読み出しているブロックを示すＩＮＲＢ［４：０］信号の値が格納され、その出力信号はＩＲＢ［４：０］信号として出力される。また、６ビットアップカウンタ５５は現在読み出しているブロックのどのアドレスを読み出すかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の読み出しているアドレスを示すＩＲＤＣＮＴ［１０：０］信号は、その上位５ビットがレジスタＩＲＤＢＰＴＲからの出力信号であるＩＲＤＣＮＴ［１０：６］信号となり、その下位６ビットが６ビットアップカウンタ５５からの出力ＤＯ［５：０］信号であるＩＲＤＣＮＴ［５：０］信号となる。また、６ビットアップカウンタ５５からのキャリーアウト信号（ＣＯ）はナンドゲートＮＡＮＤ７の第１の入力端子に入力され、ナンドゲートＮＡＮＤ７の第２の入力端子にはＩＴＸＲＤＢ信号がインバータＮ５を介して入力される。ナンドゲートＮＡＮＤ７からの出力信号は、ＩＲＢＦＲＥＥ信号としてブロックコントローラ３５に出力されるとともに、レジスタＩＲＤＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。
【００７１】
図１２は、図８の非同期送信用タイミングコントローラ３３に内蔵される回路の一部であるカウンターの構成例を示すブロック図である。図１２のレジスタＡＷＲＮＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックの次に書き込みできるブロックを示す値が格納される。そして、そのレジスタＡＷＲＮＢＰＴＲの入力端子にはＢＥＭＰ［４：０］信号が入力される。また、レジスタＡＷＲＢＰＴＲは５ビットのレジスタであって、現在書き込んでいるブロックを示す値が格納され、その出力信号はＡＷＢ［４：０］信号として出力される。そして、レジスタＡＷＲＢＰＴＲの入力端子にはレジスタＡＷＲＮＢＰＴＲからの出力信号が入力される。また、６ビットアップカウンタ５６は現在書き込んでいるブロックのどのアドレスを書き込むかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の書き込んでいるアドレスを示すＡＷＲＣＮＴ［１０：０］信号は、その上位５ビット信号がレジスタＡＷＲＢＰＴＲからの出力信号であるＡＷＲＣＮＴ［１０：６］となり、その下位６ビット信号が６ビットアップカウンタ５６からの出力ＤＯ［５：０］信号であるＡＷＲＣＮＴ［５：０］信号となる。
【００７２】
また、ＡＢＡＬＡＣＫＢ信号はオアゲートＯＲ６の第１の入力端子に入力され、オアゲートＯＲ６からの出力信号は、ナンドゲートＮＡＮＤ９の第１の入力端子に入力され、レジスタＡＷＲＮＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。ナンドゲートＮＡＮＤ９からの出力信号はＤタイプのフリップフロップＦ５のＤ入力端子に入力され、フリップフロップＦ５からのＱ出力信号は、ＡＢＡＬＲＥＱＢ信号としてブロックコントローラ３５に出力されるとともに、オアゲートＯＲ６の第２の入力端子とナンドゲートＮＡＮＤ８の第１の入力端子とに入力される。ナンドゲートＮＡＮＤ８からの出力信号はレジスタＡＷＲＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。６ビットアップカウンタ５６のキャリーアウト信号（ＣＯ）はアンドゲートＡＮＤ５の第１の入力端子に入力され、アンドゲートＡＮＤ５の第２の入力端子にはＡＦＲＤＢ信号がインバータＮ６を介して入力される。アンドゲートＡＮＤ５からの出力信号は、ナンドゲートＮＡＮＤ８の第１の入力端子とオアゲートＯＲ７の第１の入力端子とに入力され、フリップフロップＦ５からの反転ＱＢ出力信号はオアゲートＯＲ７の第２の入力端子に入力される。オアゲートＯＲ７からの出力信号はナンドゲートＮＡＮＤ９の第２の入力端子に入力される。
【００７３】
また、レジスタＡＲＤＢＰＴＲは５ビットのレジスタであって、現在読み出しているブロックを示すＡＮＲＢ［４：０］信号の値が格納され、その出力信号はＡＲＢ［４：０］信号として出力される。また、６ビットアップカウンタ５７は現在読み出しているブロックのどのアドレスを読み出すかを示す値が格納される。そして、現在の外部のシングルポートメモリ２７の読み出しているアドレスを示すＡＲＤＣＮＴ［１０：０］信号は、その上位５ビットがレジスタＡＲＤＢＰＴＲからの出力信号であるＡＲＤＣＮＴ［１０：６］信号となり、その下位６ビットが６ビットアップカウンタ５７からの出力ＤＯ［５：０］信号であるＡＲＤＣＮＴ［５：０］信号となる。また、６ビットアップカウンタ５７のキャリーアウト信号（ＣＯ）はナンドゲートＮＡＮＤ１０の第１の入力端子に入力され、ナンドゲートＮＡＮＤ１０の第２の入力端子にはＡＴＸＲＤＢ信号がインバータＮ７を介して入力される。ナンドゲートＮＡＮＤ１０からの出力信号は、ＡＲＢＦＲＥＥ信号としてブロックコントローラ３５に出力されるとともに、レジスタＡＲＤＢＰＴＲのＬＢ入力端子に同期ロードイネーブル信号として入力される。
【００７４】
次に、上述されたＩＥＥＥ１３９４インターフェース装置１０の動作について図１３乃至図２４を参照して、各信号のタイミングチャートを参照して説明をする。
【００７５】
図１３は本実施形態のブロックコントローラ３５における各信号の初期タイミングチャートを示す。「ＬＣＬＫ」は、ＩＥＥＥ１９４バスＢ１側のクロック信号を示す。図１３に示すように受信用、同期送信用及び非同期送信用としてそれぞれブロックＢ００、Ｂ０１及びＢ０２が割り当てられている。また、上記のブロックはいずれも、次の書き込みブロックを割り当てられていないため、ブロックＢ００、Ｂ０１及びＢ０２の次のブロックとしてそれぞれタイミングｔ４、タイミングｔ６及びタイミングｔ８でそれぞれブロックＢ０３、Ｂ０４及びＢ０５が割り当てられ、各レジスタＢ００ＮＸＰＴ、Ｂ０１ＮＸＰＴ及びＢ０２ＮＸＰＴにそれぞれの値が設定される。
【００７６】
図１４は、書き込みブロックの切替えがない場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における受信時の各信号のタイミングチャートを示す。「ＤＣＬＫ」は、ＰＣＩバスＢ２側のクロック信号を示す。このタイミングチャートは、受信用の読み出し／書き込みブロックがブロックＢ００のアドレス“００ｈ”から指定されて動作が開始された場合の実施例である。そして、タイミングＴ２、Ｔ４、Ｔ６、Ｔ８及びＴ１０においてそれぞれ、ＬＩＮＫ回路６から３ポートＦＩＦＯ記憶装置５にそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、そのため各タイミングでＲＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。また、それらのデータは、タイミングＴ３、Ｔ５、Ｔ７、Ｔ９及びＴ１１において、ＲＲＤＣＮＴ信号をインクリメントしてシングルポートメモリ２７から順次読み出され、受信用ＦＩＦＯメモリ２１に書き込まれる。そして、タイミングｔ１３、ｔ１６、ｔ２１、ｔ２２及びｔ２３で、順次、３ポートＦＩＦＯ記憶装置５から読み出されたデータは、受信用ＤＭＡコントローラ２に出力される。
【００７７】
図１５は、書き込みブロックの切替えがない場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における同期送信時の各信号のタイミングチャートを示す。このタイミングチャートは、同期送信用の読み出し／書き込みブロックがブロックＢ０１のアドレス“００ｈ”から指定された動作が開始された場合の実施例である。同期送信用ＤＭＡコントローラ３から同期送信用ＦＩＦＯメモリ２２にタイミングｔ２、ｔ３、ｔ４、ｔ６及びｔ７でそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、タイミングＴ３、Ｔ４、Ｔ５、Ｔ６及びＴ７で同期送信用ＦＩＦＯメモリ２２から読み出され、各タイミングでＩＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。そして、タイミングＴ１１、Ｔ１２、Ｔ１３、Ｔ１４及びＴ１５で、ＬＩＮＫ回路６は、ＩＲＤＣＮＴ信号をインクリメントしながら、シングルポートメモリ２７からデータを順次読み出す。
【００７８】
図１６は、書き込みブロックの切替えがない場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における非同期送信時の各信号タイミングチャートを示す。このタイミングチャートは、非同期送信用の読み出し／書き込みブロックがブロックＢ０２のアドレス“００ｈ”から指定されて動作が開始された場合の実施例である。非同期送信用ＤＭＡコントローラ４から非同期送信用ＦＩＦＯメモリ２３にタイミングｔ２、ｔ３、ｔ４、ｔ６及びｔ７でそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、タイミングＴ３、Ｔ４、Ｔ５、Ｔ６及びＴ７で非同期送信用ＦＩＦＯメモリ２３から読み出され、各タイミングでＡＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。そして、タイミングＴ１１、Ｔ１２、Ｔ１３、Ｔ１４及びＴ１５で、ＬＩＮＫ回路６は、ＡＲＤＣＮＴ信号をインクリメントしながらシングルポートメモリ２７からデータを順次読み出す。
【００７９】
図１７は、書き込みブロックの切替えがある場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における受信時の各信号のタイミングチャートを示す。このタイミングチャートは、受信用の読み出し／書き込みブロックがブロックＢ００のアドレス“３Ｅｈ”から指定されて動作が開始された場合の実施例である。そして、タイミングＴ２、Ｔ４、Ｔ６、Ｔ８及びＴ１０においてＬＩＮＫ回路６から３ポートＦＩＦＯ記憶装置５にそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、そのため各タイミングでＲＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。また、タイミングＴ３、Ｔ５、Ｔ７、Ｔ９及びＴ１１において、それらのデータは、ＲＲＤＣＮＴ信号をインクリメントしながら、シングルポートメモリ２７から順次読み出され、受信用ＦＩＦＯメモリ２１に書き込まれる。そして、タイミングｔ１３、ｔ１６、ｔ２１、ｔ２２及びｔ２３で順次３ポートＦＩＦＯ記憶装置５から読み出されたデータは受信用ＤＭＡコントローラ２に出力される。そして、タイミングＴ４の書き込み時、ブロックＢ００の最終データであるため次のタイミングＴ６でＲＢＡＬＲＥＱＢ信号がローレベルとなり次の書き込みブロックの割り当て処理が実行され、タイミングＴ８でブロックＢ０６が次の書き込みブロックであるブロックＢ０３の次のブロックとして割り当てられる。また、タイミングＴ５ではブロックＢ００の最終データを読み出したため、タイミングＴ６でブロックＢ００の割り当てが開放され、レジスタＢ００ＵＳＥがローレベルにされる。
【００８０】
図１８は、書き込みブロックの切替えがある場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における同期送信時の各信号のタイミングチャートを示す。このタイミングチャートは、同期送信用の読み出し／書き込みブロックがブロックＢ０１のアドレス“３Ｅｈ”から指定されて動作が開始された場合の実施例である。同期送信用ＤＭＡコントローラ３から同期送信用ＦＩＦＯメモリ２２にタイミングｔ２、ｔ３、ｔ４、ｔ６及びｔ７でそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、上記データはタイミングＴ３、Ｔ４、Ｔ７、Ｔ８及びＴ９で同期送信用ＦＩＦＯメモリ２２から読み出され、各タイミングでＩＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。そして、タイミングＴ１１、Ｔ１２、Ｔ１３、Ｔ１４及びＴ１５において、ＬＩＮＫ回路６は、ＩＲＤＣＮＴ信号をインクリメントしながらシングルポートメモリ２７からデータを順次読み出す。そして、タイミングＴ４の書き込み時、ブロックＢ０１の最終データであるため、次のタイミングＴ５でＩＢＡＬＲＥＱＢ信号がローレベルとなり、次の書き込みブロックの割り当て処理が実行される。また、タイミングＴ５、Ｔ６の間は次の書き込みブロックの割り当てが完了していないため、同期送信用ＦＩＦＯメモリ２２への書き込みもストップされている。そして、タイミングＴ７において、ブロックＢ０６が、次の書き込みブロックであるブロックＢ０４の次のブロックとして割り当てられる。また、タイミングＴ１２ではブロックＢ０１の最終データを読み出したため、タイミングＴ１３でブロックＢ０１の割り当てが開放され、レジスタＢ０１ＵＳＥがローレベルにされる。
【００８１】
図１９は、書き込みブロックの切替えがある場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における非同期送信時の各信号のタイミングチャートを示す。このタイミングチャートは、非同期送信用の読み出し／書き込みブロックがブロックＢ０２のアドレス“３Ｅｈ”から指定されて動作が開始された場合の実施例である。非同期送信用ＤＭＡコントローラ４から非同期送信用ＦＩＦＯメモリ２３にタイミングｔ２、ｔ３、ｔ４、ｔ６及びｔ７でそれぞれデータＤ０、Ｄ１、Ｄ２、Ｄ３及びＤ４が書き込まれ、上記データはタイミングＴ３、Ｔ４、Ｔ７、Ｔ８及びＴ９で非同期送信用ＦＩＦＯメモリ２３から読み出され、各タイミングでＡＷＲＣＮＴ信号がインクリメントされ、順次にデータはシングルポートメモリ２７に蓄えられる。そして、タイミングＴ１１、Ｔ１２、Ｔ１３、Ｔ１４及びＴ１５で、ＬＩＮＫ回路６は、ＡＲＤＣＮＴ信号をインクリメントしながら、シングルポートメモリ２７からデータを順次読み出す。そして、タイミングＴ４の書き込み時、ブロックＢ０２の最終データであるため次のタイミングＴ５でＡＢＡＬＲＥＱＢ信号がローレベルとなり、次の書き込みブロックの割り当て処理が実行される。また、タイミングＴ５、Ｔ６の間は次の書き込みブロックの割り当てが完了していないため、非同期送信用ＦＩＦＯメモリ２３への書き込みもストップされている。そして、タイミングＴ７でブロックＢ０６が次の書き込みブロックであるブロックＢ０５の次のブロックとして割り当てられる。また、タイミングＴ１２ではブロックＢ０２の最終データを読み出したため、タイミングＴ１３でブロックＢ０２の割り当てが開放され、レジスタＢ０２ＵＳＥがローレベルにされる。
【００８２】
図２０は、書き込みブロックの切替えがある場合でかつ空きブロックが存在せずにＦＩＦＯ記憶装置がフル状態になってしまう場合の、本実施形態の３ポートＦＩＦＯ記憶装置５における受信時の各信号のタイミングチャートを示す。このタイミングチャートは、受信用の読み出し／書き込みブロックにおいて、ブロックＢ００が使用されていて何らかの理由で受信用ＦＩＦＯメモリ２１の読み出しがストップしてしまい、そのため読み出しアドレスであるＲＲＤＣＮＴ信号が“０１０ｈ”でストップしているときの実施例である。タイミングＴ０、Ｔ２及びＴ４においてＬＩＮＫ回路６からデータがシングルポートメモリ２７に書き込まれるがタイミングＴ２でブロックＢ００の最終データが書き込まれるため、タイミングＴ４でＲＢＡＬＲＥＱＢ信号がローレベルになる。しかしながら、空きブロックが存在しない（ＢＦＵＬＬ信号がハイレベル）ので、ＲＢＡＬＡＣＫＢ信号はローレベルにならない。そして、更にＬＩＮＫ回路６からのデータ書き込みが順次なされ、タイミングＴ８においてブロックＢ０３も最終データの書き込みを実行してしまう。そのためタイミングＴ８ではＤＩＳＥＬ［１：０］信号が“３”となりシングルポートメモリ２７がフル状態になって、強制的にそれを示すデータである「３３’ｈ１００００００１４」がシングルポートメモリ２７に書き込まれる。そして、タイミングＴ９からＲＸＦＵＬＬ信号がハイレベルとなり、ＬＩＮＫ回路６に３ポートＦＩＦＯ記憶装置５への書き込みをストップするように要求する。そして、しばらくして受信用ＤＭＡコントローラ２が受信用ＦＩＦＯメモリ２１からデータの読み出しを開始し、データは順次タイミングＴ１０、Ｔ１１、Ｔ１２及びＴ１３で読み出されていく。そして、タイミングＴ１０においてブロックＢ００の最終データを読み出したため、タイミングＴ１１でブロックＢ００の割り当てが開放されレジスタＢ００ＵＳＥがローレベルになる。しかし、タイミングＴ１１で空きブロックとなったブロックＢ００が現在の書き込みブロックであるブロックＢ０３の次の書き込みブロックとして割り当てられるため、タイミングＴ１２でレジスタＢ００ＵＳＥはハイレベルとなる。また、ブロックＢ０３に次の書き込みブロックが割り当てられたためＲＸＦＵＬＬ信号はタイミングＴ１２でローレベルになり、それによってＬＩＮＫ回路６からの次の受信パケットの書き込みが許可される。しかし、ブロックＢ００の次の書き込みブロックが割り当てられていないことから、ＲＢＡＬＲＥＱＢ信号はタイミングＴ１３で再びローレベルになる。そして、順次受信用ＤＭＡコントローラ２は受信用ＦＩＦＯメモリ２１からデータを読み出し、タイミングＴ１４でブロックＢ０３の最終データを読み出したことから、タイミングＴ１５でブロックＢ０３が開放され、レジスタＢ０３ＵＳＥがローレベルとなる。しかし、ブロックＢ００の次の書き込みブロックが割り当てられていないことから、タイミングＴ１５から空きブロックとなったブロックＢ０３を、タイミングＴ１６でブロックＢ００の次の書き込みブロックとして割り当てる。そのためタイミングＴ１６でレジスタＢ０３ＵＳＥはハイレベルとなる。
【００８３】
図２１は、本実施形態の３ポートＦＩＦＯ記憶装置５における、受信及び同期送信混在時のタイミングチャートを示す。このタイミングチャートは、受信用の読み出し／書き込みブロックがブロックＢ００のアドレス“００ｈ”から指定されて動作が開始され、同期送信用の読み出し／書き込みブロックがブロックＢ０１のアドレス“００ｈ”から指定されて動作が開始された場合の実施例である。タイミングＴ２、Ｔ４、Ｔ６及びＴ８において、データＲ０、Ｒ１、Ｒ２及びＲ３が、ＬＩＮＫ回路６からシングルポートメモリ２７に順次書き込まれる。また、タイミングｔ２、ｔ３、ｔ４及びｔ６において、データＩ０、Ｉ１、Ｉ２及びＩ３が、同期送信用ＤＭＡコントローラ３から同期送信用ＦＩＦＯメモリ２２に順次書き込まれる。そして、タイミングＴ５、Ｔ９、Ｔ１１及びＴ１３において、データＲ０、Ｒ１、Ｒ２及びＲ３が、シングルポートメモリ２７から受信用ＦＩＦＯメモリ２１に順次書き込まれる。また、タイミングＴ３、Ｔ７、Ｔ１０及びＴ１２において、データＩ０、Ｉ１、Ｉ２及びＩ３が、同期送信用ＦＩＦＯメモリ２２からシングルポートメモリ２７に順次書き込まれる。そして、タイミングｔ２０、ｔ２３、ｔ２４及びｔ２６において、データＲ０、Ｒ１、Ｒ２及びＲ３が、受信用ＦＩＦＯメモリ２１から受信用ＤＭＡコントローラ２に順次読み出される。そして、タイミングＴ１４、Ｔ１５、Ｔ１６及びＴ１７において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＩ０、Ｉ１、Ｉ２及びＩ３を順次読み出す。
【００８４】
図２２は、本実施形態の３ポートＦＩＦＯ記憶装置５における、受信及び非同期送信混在時のタイミングチャートを示す。このタイミングチャートは、受信用の読み出し／書き込みブロックがブロックＢ００のアドレス“００ｈ”から指定されて動作が開始され、非同期送信用の読み出し／書き込みブロックがブロックＢ０２のアドレス“００ｈ”から指定されて動作が開始される場合の実施例である。タイミングＴ２、Ｔ４、Ｔ６及びＴ８において、データＲ０、Ｒ１、Ｒ２及びＲ３が、ＬＩＮＫ回路６からシングルポートメモリ２７に順次書き込まれる。また、タイミングｔ２、ｔ３、ｔ４及びｔ６において、データＡ０、Ａ１、Ａ２及びＡ３が、非同期送信用ＤＭＡコントローラ４から非同期送信用ＦＩＦＯメモリ２３に順次書き込まれる。そして、タイミングＴ５、Ｔ９、Ｔ１１及びＴ１３において、データＲ０、Ｒ１、Ｒ２及びＲ３が、シングルポートメモリ２７から受信用ＦＩＦＯメモリ２１に順次書き込まれる。また、タイミングＴ３、Ｔ７、Ｔ１０及びＴ１２において、データＡ０、Ａ１、Ａ２及びＡ３が、非同期送信用ＦＩＦＯメモリ２３からシングルポートメモリ２７に順次書き込まれる。そして、タイミングｔ２０、ｔ２３、ｔ２４及びｔ２６において、データＲ０、Ｒ１、Ｒ２及びＲ３が、受信用ＦＩＦＯメモリ２１から受信用ＤＭＡコントローラ２に順次読み出される。そして、タイミングＴ１４、Ｔ１５、Ｔ１６及びＴ１７において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＡ０、Ａ１、Ａ２及びＡ３を順次読み出す。
【００８５】
図２３は、本実施形態の３ポートＦＩＦＯ記憶装置５における、同期送信及び非同期送信混在時のタイミングチャートを示す。このタイミングチャートは、非同期送信用の読み出し／書き込みブロックがブロックＢ０１のアドレス“００ｈ”から指定されて動作が開始され、非同期送信用の読み出し／書き込みブロックがブロックＢ０２のアドレス“００ｈ”から指定されて動作が開始された場合の実施例である。タイミングｔ２、ｔ３及びｔ５において、データＩ０、Ｉ１及びＩ２が、同期送信用ＤＭＡコントローラ３から同期送信用ＦＩＦＯメモリ２２に順次書き込まれる。また、タイミングｔ４、ｔ５、ｔ６及びｔ８において、データＡ０、Ａ１、Ａ２及びＡ３が、非同期送信用ＤＭＡコントローラ４から非同期送信用ＦＩＦＯメモリ２３に順次書き込まれる。また、タイミングＴ３、Ｔ５及びＴ７において、データＩ０、Ｉ１及びＩ２が、同期送信用ＦＩＦＯメモリ２２からシングルポートメモリ２７に順次書き込まれる。また、タイミングＴ４、Ｔ６、Ｔ８及びＴ１２において、データＡ０、Ａ１、Ａ２及びＡ３が、非同期送信用ＦＩＦＯメモリ２３からシングルポートメモリ２７に順次書き込まれる。そして、タイミングＴ９、Ｔ１０及びＴ１１において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＩ０、Ｉ１及びＩ２を順次読み出す。そして、タイミングＴ１４、Ｔ１５、Ｔ１６及びＴ１７において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＡ０、Ａ１、Ａ２及びＡ３を順次読み出す。
【００８６】
図２４は、本実施形態の３ポートＦＩＦＯ記憶装置５における、受信及び同期送信及び非同期送信混在時のタイミングチャートを示す。このタイミングチャートは、受信用の読み出し／書き込みブロックがブロックＢ００のアドレス“００ｈ”から指定されて動作が開始され、非同期送信用の読み出し／書き込みブロックがブロックＢ０１のアドレス“００ｈ”から指定されて動作が開始され、非同期送信用の読み出し／書き込みブロックがブロックＢ０２のアドレス“００ｈ”から指定されて動作が開始された場合の実施例である。タイミングＴ２、Ｔ４及びＴ６において、データＲ０、Ｒ１及びＲ２が、ＬＩＮＫ回路から順次シングルポートメモリ２７に書き込まれる。タイミングｔ２、ｔ３及びｔ４において、データＩ０、Ｉ１及びＩ２が、同期送信用ＤＭＡコントローラ３から同期送信用ＦＩＦＯメモリ２２に順次書き込まれる。また、タイミングｔ４、ｔ５及びｔ６において、データＡ０、Ａ１及びＡ２が、非同期送信用ＤＭＡコントローラ４から非同期送信用ＦＩＦＯメモリ２３に順次書き込まれる。そして、タイミングＴ５、Ｔ９及びＴ１２において、データＲ０、Ｒ１及びＲ２が、シングルポートメモリ２７から受信用ＦＩＦＯメモリ２１に順次書き込まれる。また、タイミングＴ３、Ｔ８及びＴ１１において、データＩ０、Ｉ１及びＩ２が、同期送信用ＦＩＦＯメモリ２２からシングルポートメモリ２７に順次書き込まれる。また、タイミングＴ７、Ｔ１０及びＴ１６において、データＡ０、Ａ１及びＡ２が、非同期送信用ＦＩＦＯメモリ２３からシングルポートメモリ２７に順次書き込まれる。そして、タイミングｔ２０、ｔ２１及びｔ２２において、データＲ０、Ｒ１及びＲ２が、受信用ＦＩＦＯメモリ２１から受信用ＤＭＡコントローラ２に順次読み出される。そして、タイミングＴ１３、Ｔ１４及びＴ１５において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＩ０、Ｉ１及びＩ２を順次読み出す。そして、図示しないタイミングＴ１８以降において、ＬＩＮＫ回路６はシングルポートメモリ２７からデータＡ０、Ａ１、Ａ２及びＡ３を順次読み出す。
【００８７】
以上説明したように、本実施形態によれば、送信又は受信のためのデータを、例えばシングルポートメモリ２７である記憶装置に一時的に格納した後転送するデータ転送装置において、上記記憶装置を所定の同一の単位の複数のブロックに分割し、データを転送して送信するときの送信用データ書込要求信号ＩＴＸＦＷＲＥＱＢ又はＡＴＸＦＷＲＥＱＢに応答して、上記複数のブロックのうち未使用の１つのブロックを選択して当該選択したブロックを使用状態とし、送信用データを当該選択したブロックに書き込んだ後読み出して転送するとともに、データを転送して受信するときの受信用データ書込要求信号ＲＸＦＲＲＥＱＢに応答して、上記複数のブロックのうち未使用の１つのブロックを選択して当該選択したブロックを使用状態とし、受信用データを当該選択したブロックに書き込んだ後読み出して転送するように制御する。従って、１つの記憶装置を、例えば受信パケットが多い状態では記憶領域のほとんどを受信用に、また、送信用のパケットが多いい状態では記憶領域のほとんどを送信用に使用できるため、それぞれの送信用及び受信用として記憶装置として使用できる容量が見かけ上増加したように処理でき、すなわち、当該記憶装置を有効的にかつ効率的に使用することができ、当該記憶装置としての処理能力が向上する。
【００８８】
また、従来技術のように複数のＦＩＦＯ記憶装置を持った場合と同じ処理能力で良ければ、本実施形態に係る１つのＦＩＦＯ記憶装置５のメモリ容量を、従来の複数のＦＩＦＯ記憶装置の最大容量サイズにすることが可能となる。つまり、転送装置として大きなゲートを占めるＦＩＦＯ記憶装置５のメモリ容量を大きく減らすことができる。言い換えれば、ＦＩＦＯ記憶装置５のメモリ容量を少なくして従来技術と同様の動作を得ることができる。
【００８９】
また、本実施形態に係るデータ転送装置を実現するための従来技術からの付加回路の規模は、図９のブロックコントローラ３５全体の約３０００ゲートと図１０乃至図１２に示すタイミングコントローラ３１，３２，３３のカウンター構成例の約９００ゲートから、図２６に示す従来技術のタイミングコントローラ１２４，１３３，１４３のカウンター構成例の約６００ゲートを減算した分である。つまり約３３００ゲートのわずかな増加だけである。つまり、処理能力を向上するためには約３３００ゲートの回路増加のみを必要とし、また、処理能力は同等で良いのであれば、約３３００ゲートの回路増加を必要とするものの、ゲート規模の多くを占めるＦＩＦＯ記憶装置を大きく減少できるので、全体としては大きな回路規模の減少をはかれる。
【００９０】
上記データ転送装置において、上記制御手段は、好ましくは、上記複数のブロックのうち未使用の１つのブロックを選択するときに、選択したブロックに続いてデータを書き込むための次のブロックを選択して当該選択した次のブロックを使用状態として確保する。従って、選択したブロックに続いてデータを書き込むための次のブロックを確実に確保して次のブロックのデータ書き込み動作に移行することができる。
【００９１】
この場合において、現在書き込んでいるブロックの書き込み領域が存在しない場合には、次の書き込みブロックに処理が移るが、次の書き込みブロックのその次の書き込みブロックが割り当てられないと書き込み処理が出来ない。例えば、本実施例の送信用としてのＦＩＦＯ記憶装置５の図２０のタイミングＴ５〜Ｔ６において書き込み処理がストップされている。しかし、本実施例の受信用としてのＦＩＦＯ記憶装置５は上述のように構成されているので、図１９のタイミングＴ５のように現在の書き込みブロック領域がなくなっても書き込み処理が連続的に実行でき、処理の連続化をはかることができる。
【００９２】
以上の実施形態においては、シングルポートメモリ２７の動作を制御するＦＩＦＯタイミングコントローラ２８はハードウエア回路で構成しているが、本発明はこれに限らず、デジタルシグナルプロセッサ（ＤＳＰ）により実行されるコンピュータで読取可能なプログラムで構成してもよい。すなわち、ＦＩＦＯタイミングコントローラ２８のシングルポートメモリ２７を制御するステップは、コンピュータで読取可能なプログラムで表現することができ、当該プログラムをＣＤ−ＲＯＭ、ＣＤ−Ｒ、ＣＤ−ＲＷ、ＤＶＤ，ＤＶＤ−Ｒ、ＤＶＤ−ＲＷ、ＤＶＤ−ＲＡＭなどの光ディスク等のコンピュータで読取可能な記録媒体に記録することができる。これにより、ソフトウェアで動作するデータ転送装置におけるメモリー領域の使用量の削減又は処理能力の向上がはかれる。
【００９３】
【発明の効果】
以上詳述したように本発明に係るデータ転送装置又はデータ転送方法によれば、送信又は受信のためのデータを記憶装置に一時的に格納した後転送するデータ転送装置において、上記記憶装置を所定の同一の単位の複数のブロックに分割し、データを転送して送信するときの送信用データ書込要求信号に応答して、上記複数のブロックのうち未使用の１つのブロックを選択して当該選択したブロックを使用状態とし、送信用データを当該選択したブロックに書き込んだ後読み出して転送するとともに、データを転送して受信するときの受信用データ書込要求信号に応答して、上記複数のブロックのうち未使用の１つのブロックを選択して当該選択したブロックを使用状態とし、受信用データを当該選択したブロックに書き込んだ後読み出して転送するように制御する。従って、１つの記憶装置を、例えば受信パケットが多い状態では記憶領域のほとんどを受信用に、また、送信用のパケットが多いい状態では記憶領域のほとんどを送信用に使用できるため、それぞれの送信用及び受信用として記憶装置として使用できる容量が見かけ上増加したように処理でき、すなわち、当該記憶装置を有効的にかつ効率的に使用することができ、当該記憶装置としての処理能力が向上する。
【００９４】
上記データ転送装置又はデータ転送方法において、上記制御手段は、好ましくは、上記複数のブロックのうち未使用の１つのブロックを選択するときに、選択したブロックに続いてデータを書き込むための次のブロックを選択して当該選択した次のブロックを使用状態として確保する。従って、選択したブロックに続いてデータを書き込むための次のブロックを確実に確保して次のブロックのデータ書き込み動作に移行することができる。
【００９５】
また、上記データ転送装置又はデータ転送方法において、好ましくは、上記各ブロックに対応して設けられ、次のブロックのアドレスを記憶する第１のレジスタ手段をさらに備える。従って、選択したブロックに続いてデータを書き込むための次のブロックを確実に示して次のブロックのデータ書き込み動作に移行することができる。
【００９６】
さらに、上記データ転送装置又はデータ転送方法において、好ましくは、上記各ブロックに対応して設けられ、次のブロックのアドレスが選択されて確保されているか否かを示すデータを記憶する第２のレジスタ手段をさらに備える。従って、選択したブロックに続いてデータを書き込むための次のブロックが確保されているか否かの情報を得ることができ、次のブロックのデータ書き込み動作に移行することができる。
【００９７】
また、上記データ転送装置又はデータ転送方法において、上記制御手段は、好ましくは、上記ブロックからデータを読み出したとき、当該ブロックを未使用状態として解放する。従って、使用しなくなったブロックを確実に解放することにより、当該記憶装置を有効的にかつ効率的に使用することができる。
【００９８】
さらに、上記データ転送装置又はデータ転送方法において、好ましくは、上記各ブロックに対応して設けられ、上記各ブロックが使用状態であるか否かを示すデータを記憶する第３のレジスタ手段をさらに備えたことを特徴とする。従って、上記記憶装置の書くブロックが使用中であるか否かの情報を得ることができ、次のブロックの検索を容易にかつ高速で実行できる。
【図面の簡単な説明】
【図１】本発明の実施形態に係るＩＥＥＥ１３９４インターフェース装置の構成を示すブロック図である。
【図２】図１の３ポートＦＩＦＯ記憶装置の詳細な構成を示すブロック図である。
【図３】図２のシングルポートメモリ２７を用いたデータの記憶方法を説明するための図である。
【図４】図３のシングルポートメモリ２７に受信ＦＩＦＯデータ、同期送信ＦＩＦＯデータ及び非同期送信ＦＩＦＯデータを記憶するときの初期状態を示す図である。
【図５】図４のシングルポートメモリ２７においてパケットを受信するときの状態を示す図である。
【図６】図５のシングルポートメモリ２７において受信されたパケットを処理する方法を説明するための図である。
【図７】図５のシングルポートメモリ２７においてパケットを同期送信する準備をする方法を説明するための図である。
【図８】図２のＦＩＦＯタイミングコントローラ２８の詳細な構成を示すブロック図である。
【図９】図８のブロックコントローラ３５の詳細な構成を示すブロック図である。
【図１０】図８の受信用タイミングコントローラ３１の詳細な構成を示すブロック図である。
【図１１】図８の同期送信用タイミングコントローラ３２の詳細な構成を示すブロック図である。
【図１２】図８の非同期送信用タイミングコントローラ３３の詳細な構成を示すブロック図である。
【図１３】図８のブロックコントローラ３５における各信号の初期状態を示すタイミングチャートである。
【図１４】図１の３ポートＦＩＦＯ記憶装置５における受信時の各信号を示すタイミングチャートである。
【図１５】図１の３ポートＦＩＦＯ記憶装置５における同期送信時の各信号を示すタイミングチャートである。
【図１６】図１の３ポートＦＩＦＯ記憶装置５における非同期送信時の各信号を示すタイミングチャートである。
【図１７】図１の３ポートＦＩＦＯ記憶装置５における受信時の各信号を示すタイミングチャートである。
【図１８】図１の３ポートＦＩＦＯ記憶装置５における同期送信時の各信号を示すタイミングチャートである。
【図１９】図１の３ポートＦＩＦＯ記憶装置５における非同期送信時の各信号を示すタイミングチャートである。
【図２０】図１の３ポートＦＩＦＯ記憶装置５における受信時の各信号を示すタイミングチャートである。
【図２１】図１の３ポートＦＩＦＯ記憶装置５における受信及び同期送信時の各信号を示すタイミングチャートである。
【図２２】図１の３ポートＦＩＦＯ記憶装置５における受信及び非同期送信時の各信号を示すタイミングチャートである。
【図２３】図１の３ポートＦＩＦＯ記憶装置５における同期送信及び非同期送信時の各信号を示すタイミングチャートである。
【図２４】図１の３ポートＦＩＦＯ記憶装置５における受信及び同期送信及び非同期送信時の各信号を示すタイミングチャートである。
【図２５】従来技術のＩＥＥＥ１３９４インターフェース装置の構成を示すブロック図である。
【図２６】図２５の受信用ＦＩＦＯ記憶装置１０５、同期送信用ＦＩＦＯ記憶装置１０６及び非同期送信用ＦＩＦＯ記憶装置１０７の詳細な構成を示すブロック図である。
【図２７】（ａ）、（ｂ）及び（ｃ）はそれぞれ、図２６のタイミングコントローラ１２４、１３３及び１４４の詳細な構成を示すブロック図である。
【符号の説明】
１…ＰＣＩインターフェースコントローラ、
２…受信用ＤＭＡコントローラ、
３…同期送信用ＤＭＡコントローラ、
４…非同期送信用ＤＭＡコントローラ、
５…３ポートＦＩＦＯ記憶装置、
６…ＬＩＮＫ回路、
７…ＰＨＹ回路、
１０…ＩＥＥＥ１３９４インターフェース装置、
１１…ＲＡＭ、
１２…ＣＰＵ、
１３…パーソナルコンピュータ、
２１…受信用ＦＩＦＯメモリ、
２２…同期送信用ＦＩＦＯメモリ、
２３…非同期送信用ＦＩＦＯメモリ、
２４，２５，２６，４３乃至４６…マルチプレクサ、
２７…シングルポートメモリ、
２８…タイミングコントローラ、
３１…受信用タイミングコントローラ、
３２…同期送信用タイミングコントローラ、
３３…非同期送信用タイミングコントローラ、
３４…データ選択コントローラ、
３５…ブロックコントローラ、
４１…ブロックアクセスコントローラ、
４２…３２ビットプライオリティエンコーダ、
５１，５３，５４，５５，５６，５７…６ビットアップカウンタ、
５２…２ビット同期アップダウンカウンタ、
Ｂ１…ＩＥＥＥ１３９４バス、
Ｂ２…ＰＣＩバス、
Ｂ００ＮＸＰＴ乃至Ｂ３１ＮＸＰＴ，Ｂ００ＮＯＫ乃至Ｂ３１ＮＯＫ，Ｂ００ＵＳＥ乃至Ｂ３１ＵＳＥ，ＲＲＤＢＰＴＲ，ＲＷＲＢＰＴＲ，ＩＲＤＢＰＴＲ，ＩＷＲＢＰＴＲ，ＡＲＤＢＰＴＲ，ＡＷＲＢＰＴＲ，ＲＷＲＮＢＰＴＲ，ＩＷＲＮＢＰＴＲ，ＡＷＲＮＢＰＴＲ…レジスタ、
Ｂ００乃至Ｂ３１…ブロック、
ＡＮＤ１乃至ＡＮＤ５…アンドゲート、
ＯＲ１乃至ＯＲ７…オアゲート、
ＮＡＮＤ１乃至ＮＡＮＤ１０…ナンドゲート、
Ｎ１乃至Ｎ７…インバータ、
Ｆ１乃至Ｆ５…フリップフロップ。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer device, a data transfer method, and a program recording the data transfer method, and more particularly, to a data transfer device and a data transfer method for transferring data between an IEEE1394-compliant device and a PCI bus such as a computer. And a program recording a data transfer method.
[0002]
[Prior art]
FIG. 25 is a block diagram showing a configuration of an IEEE 1394 interface device 110 according to the prior art, which uses a storage device such as a FIFO memory for data transmission and reception in accordance with IEEE 1394, which is generally used. As shown in FIG. 25, the IEEE 1394 interface device 110 provides an interface between the IEEE 1394 bus B1 and the PCI bus B2 of the personal computer 113. Since the IEEE 1394 bus B1 and the PCI bus B2 have different clock frequencies, the IEEE 1394 interface device 110 performs reception operation, synchronous transmission operation, and asynchronous operation in order to perform a transfer operation after buffering the FIFO storage device or the like in the IEEE 1394 interface device 110. Separate FIFO storage devices 105, 106, and 107 are provided for transmission.
[0003]
The packet input via the IEEE 1394 bus B1 is subjected to interface processing such as signal conversion of the link layer via the PHY circuit 9 which performs interface processing such as signal conversion of the physical layer in the IEEE 1394 interface device 10 of the personal computer 113. The link is transmitted to the LINK circuit 108 and stored in the FIFO memory 105 for reception. Next, the packet stored in the receiving FIFO storage device 105 is read out by the receiving DMA controller 102 and is sent to the PCI bus B2 via the PCI interface controller 1 which performs interface processing such as signal conversion with the PCI bus. And stored in the RAM 11. Then, the CPU 12 can use the data stored in the RAM 11 as received packet data. Further, the CPU 12 prepares the data of the packet for synchronous transmission in the RAM 11, and then the DMA controller 103 for synchronous transmission reads out the data in the RAM 11 via the PCI interface controller and stores it in the FIFO memory 106 for synchronous transmission. Then, the LINK circuit 108 reads out the stored data and transmits the data via the PHY circuit 9 onto the IEEE1394 bus B1. The asynchronous transmission packet in the RAM 11 is also transmitted to the IEEE 1394 bus B1 with the same data flow using the asynchronous transmission DMA controller 104 and the asynchronous transmission FIFO storage device 107.
[0004]
In the IEEE 1394 interface device 110, the transmission and reception FIFO storage devices used therein require a large gate scale. For example, as described in JP-A-2001-134421, a small-sized asynchronous two-port memory is used. Efforts have been made to reduce the ratio of occupying the FIFO storage device in the IEEE 1394 interface device 110 by using a one-port memory having a large size.
[0005]
The detailed configuration of the receiving FIFO storage device 105, the synchronous transmission FIFO storage device 106, and the asynchronous transmission FIFO storage device 107 when the technology disclosed in the publication is used for the IEEE 1394 interface device 110 of FIG. 25 is shown. 26. Thereafter, when the signal name is XXXXB (that is, the signal name ends with "B"), the signal is a low level active low enable signal; otherwise, it is a high level active high signal. This is an enable signal.
[0006]
In FIG. 26, a reception data bus RXDO [31: 0] for transmitting data sent from the LINK circuit 108 (where [31: 0] is bit 31) is provided between the LINK circuit 108 and the reception FIFO storage device 105. , And signal bits from 0 to 0, and are similarly displayed in the following.) And a bus RXDO [32] that transmits a signal indicating the final data of the received packet. Further, an RXWRB signal indicating permission to write received data from the LINK circuit 108 to the receiving FIFO storage device 105 and an area that can be written to the receiving FIFO storage device 105 have disappeared from the receiving FIFO storage device 105 (memory). (Full state) using the RXFULL signal shown in the LINK circuit 108. Further, between the receiving DMA controller 102 and the receiving FIFO storage device 105, a receiving data bus RXDI [31: 0] through which the receiving DMA controller 102 reads out received data from the receiving FIFO storage device 105 is provided. It is connected by a bus RXDI [32] that transmits a signal indicating that it is the last data of the received packet, and further between the receiving DMA controller 102 and the receiving FIFO storage device 105, An RXFRREQB signal, which is a request to read data in the reception FIFO storage device 105; an RXFRACKB signal, which indicates that the reception FIFO storage device 105 permits reading in response to a read request from the reception DMA controller 102; Controller 102 Credit from the FIFO storage device 105 a when the data is read out is connected with the RXFRWAIT signal for instructing the stop of the temporary reading.
[0007]
As shown in FIG. 26, a transmission data bus ITXDO [31: 0] for transmitting data transmitted from the synchronous transmission DMA controller 103 is provided between the synchronous transmission DMA controller 103 and the synchronous transmission FIFO storage device 106. And a bus ITXDO [32] for transmitting a signal indicating that the data is the final data of the transmission packet. The synchronous transmission DMA controller 103 and the synchronous transmission FIFO storage device 106 further have a synchronous transmission The ITXFWREQB signal, which is a request to write the transmission data sent from the synchronous transmission DMA controller 103, to the FIFO storage device 106, and the synchronous transmission FIFO storage device 106 writes the transmission data write request from the synchronous transmission DMA controller 103. ITX which is permission And WACKB signal, is connected with the ITXFWDTVL signal indicating that it and its data synchronization transmission DMA controller 103 is transmitting the data write request is valid. Further, between the synchronous transmission FIFO storage device 106 and the LINK circuit 108, a transmission data bus ITXDI [31: 0] for the LINK circuit 108 to read synchronous transmission data from the synchronous transmission FIFO storage device 106, and the transmission thereof. It is connected by a bus ITXDI [32] for transmitting a signal indicating that it is the last data of the data, and between the synchronous transmission FIFO storage device 106 and the LINK circuit 108, the LINK circuit 108 further stores the synchronous transmission FIFO storage. The connection is made using an ITXRDB signal that is a request to read transmission data from the device 106.
[0008]
Further, as shown in FIG. 26, a transmission data bus ATXDO [31: 0] for transmitting data transmitted from the asynchronous transmission DMA controller 104 is provided between the asynchronous transmission DMA controller 104 and the asynchronous transmission FIFO storage device 107. And a bus ATXDO [32] for transmitting a signal indicating that the data is the last data of the transmission packet. The asynchronous transmission DMA controller 104 and the asynchronous transmission FIFO storage device 107 further have an asynchronous transmission The ATXFWREQB signal, which is a request to write transmission data sent from the asynchronous transmission DMA controller 104, to the FIFO storage device 107, and the writing of the asynchronous transmission FIFO storage device 107 in response to the transmission data writing request from the asynchronous transmission DMA controller 104. And ATXFWACKB signal is allowed only, is connected with the ATXFWDTVL signal indicating that asynchronous transmission DMA controller 104 is a possible and the data is valid is transmitting data to the write request. A transmission data bus ATXDI [31: 0] for the LINK circuit 108 to read out asynchronous transmission data from the asynchronous transmission FIFO storage device 107 is provided between the asynchronous transmission FIFO storage device 107 and the LINK circuit 108. The ATXDI [32] that transmits a signal indicating that the data is the last data, is connected between the asynchronous transmission FIFO storage device 107 and the LINK circuit 108, and is further connected to the asynchronous transmission FIFO storage device by the LINK circuit 108. The connection is made using an ATXRDB signal, which is a request to read out transmission data from 107.
[0009]
The receiving FIFO storage device 105 includes, for example, a single-port memory 122 of 33 bits × 1024 words, a FIFO memory 121 of 33 bits × 32 words, and is formed of, for example, an SRAM, for sequentially storing received data. A two-to-one 33 for changing the last data of the packet to a fixed value in order to notify the receiving DMA controller 102 when the receiving FIFO storage device 105 becomes full during the writing of the received packet. A bit multiplexer 123, a LINK circuit 108 connected to the reception FIFO storage device 105, a reception DMA controller 102, and a timing controller 124 for controlling the single-port memory 122, the FIFO memory 121, and the multiplexer 123. Have You.
[0010]
The configuration and operation of those components will be described. The data input from the LINK circuit 108 via the reception data bus RXDO [32: 0] is input to the first input terminal of the multiplexer 123, while the reception FIFO is input to the second input terminal of the multiplexer 123. A fixed data value 33'h1000000014 used when the storage device 105 is full is input. In the above data values, “33 ′” means that the data size is 33 bits, and “h” means that the data value is displayed in hexadecimal, but this value is an example. The output signal from the multiplexer 123 is input to the single port memory 122 via the bus MDI [32: 0], and the output data bus MDO [32: 0] of the single port memory 122 is connected to the input bus of the FIFO memory 121. Connected to. An output bus of the FIFO memory 121 is a reception data bus RXDI [32: 0] connected to the reception DMA controller 102, and a signal output from the FIFO memory 121 is a reception data bus RXDI [32: 0]. Is input to the receiving DMA controller 102 via the. Then, the RXWRB signal from the LINK circuit 108 is input to the timing controller 124 of the receiving FIFO storage device 105, and the timing controller 124 outputs an RXFULL signal indicating a memory full state to the LINK circuit 108. Further, the timing controller 124 outputs data representing the address of the single-port memory 122 to the single-port memory 122 via the address bus MAD [9: 0], and a signal for permitting the single-port memory 122 to write data. Is output to the single-port memory 122. Further, the timing controller 124 outputs to the FIFO memory 121 a FWRB signal indicating permission to write data to the FIFO memory 121 and an FRDB signal indicating permission to read data from the FIFO memory 121. The timing controller 124 receives the RXFRREQB signal and the RXFRWAIT signal from the receiving DMA controller 102, and outputs the RXFRACKB signal to the receiving DMA controller 102.
[0011]
The synchronous transmission FIFO storage device 106 is, for example, an SRAM, and includes a 33-bit × 512-word single-port memory 132 for sequentially storing synchronous transmission data, and a 33-bit × 32-word FIFO memory 131. Further, it includes a LINK circuit 108 connected to the synchronous transmission FIFO storage device 106, a synchronous transmission DMA controller 103, and a timing controller 133 for controlling the above-described single port memory 132 and FIFO memory 131.
[0012]
The configuration and operation of those components will be described. The data arriving from the synchronous transmission DMA controller 103 via the synchronous transmission data bus ITXDO [32: 0] is input to the input bus of the FIFO memory 131. The output bus MDI [32: 0] of the FIFO memory 131 is connected to the input bus of the single port memory 132, and the output bus MDO [32: 0] of the single port memory 132 is ITXDI [32: 0]. To the LINK circuit 108. The ITXRDB signal is input from the LINK circuit 108 to the timing controller 133 of the synchronous transmission FIFO storage device 106. Further, the timing controller 133 outputs data representing the address of the single port memory 132 to the single port memory 132 via the address bus MAD [9: 0], and a signal for permitting the data writing of the single port memory 132. Is output to the single-port memory 132. Further, the timing controller 133 outputs to the FIFO memory 131 a FWRB signal indicating permission to write data to the FIFO memory 131 and an FRDB signal indicating permission to read data from the FIFO memory 131. Further, the ITXFWREQB signal and the ITXFWDTVL signal are input from the synchronous transmission DMA controller 103 to the timing controller 133, and the timing controller 133 outputs the ITXFWACKB signal to the synchronous transmission DMA controller 103.
[0013]
The asynchronous transmission FIFO storage device 107 is, for example, an SRAM, and includes a 33-bit × 512-word single-port memory 142 for sequentially storing asynchronous transmission data, and a 33-bit × 32-word FIFO memory 141. A link circuit 108 connected to the FIFO memory 107 for asynchronous transmission, a DMA controller 104 for asynchronous transmission, and a timing controller 143 for controlling the single-port memory 142 and the FIFO memory 141 are provided.
[0014]
The configuration and operation of those components will be described. Data is input from the asynchronous transmission DMA controller 104 to the input bus of the FIFO memory 141 via the asynchronous transmission data bus ATXDO [32: 0]. The output bus MDI [32: 0] of the FIFO memory 141 is connected to the input bus of the single port memory 142, and the output bus MDO [32: 0] becomes ATXDI [32: 0] and becomes the LINK circuit 108. Connected to. Then, the ATXRDB signal is input from the LINK circuit 108 to the timing controller 143 of the FIFO memory device 107 for asynchronous transmission. In addition, the timing controller 143 outputs data representing the address of the single port memory 142 to the single port memory 142 via the address bus MAD [9: 0], and a signal for permitting the single port memory 142 to write data. Is output to the single-port memory 142. Further, the timing controller 143 outputs to the FIFO memory a FWRB signal indicating permission to write data to the FIFO memory and a FRDB signal indicating permission to read data from the FIFO memory. The ATXFWREQB signal and the ATXFWDTVL signal are input from the asynchronous transmission DMA controller 104 to the timing controller 143, and the timing controller 143 outputs the ATXFWACKB signal to the asynchronous transmission DMA controller 104.
[0015]
[Problems to be solved by the invention]
When a DVCR (Digital Video Cassette Recorder), which is an IEEE 1394 device, is connected to a data transfer device as shown in FIG. 25 to store data of the DVCR in the personal computer 113, the IEEE 1394 bus B1 has almost no connection. Only the packet of the synchronous reception data exists. For this reason, the reception FIFO storage device 105 is used, but the synchronous transmission FIFO storage device 106 and the asynchronous transmission FIFO storage device 107 are hardly used. On the other hand, when data stored in the personal computer 113 is to be stored in the DVCR, only packets of synchronous transmission data exist on the IEEE1394 bus B1. Therefore, the synchronous transmission FIFO storage device 106 is used, but the other reception FIFO storage device 105 and asynchronous transmission FIFO storage device 107 are not used.
[0016]
Also, a device using the SBP2 protocol such as a hard disk drive, which is an IEEE 1394 device, is connected to a data transfer device as shown in FIG. 25, and data is stored in the personal computer 113 from the device connected to the end of the IEEE 1394 bus B1. In this case, most of the IEEE 1394 bus B1 is mostly occupied by asynchronously received data packets. Therefore, the reception FIFO storage device 105 is used, but the synchronous transmission FIFO storage device 106 and the asynchronous transmission FIFO storage device 107 are hardly used. Conversely, when data stored in the personal computer 113 is to be stored in a device connected to the end of the IEEE 1394 bus B1, asynchronous transmission packets occupy most of the IEEE 1394 bus B1. Therefore, the asynchronous transmission FIFO storage device 107 is used, but the other reception FIFO storage device 105 and the asynchronous transmission FIFO storage device 106 are not used.
[0017]
From the above, the FIFO storage device occupying a large gate scale in the IEEE 1394 interface device 110 is not effectively used. The same applies to a configuration in which each of the FIFO storage devices 105, 106, and 107 is small as shown in FIG.
[0018]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and in a data transfer device such as an IEEE1394 interface device, a data transfer device and a data transfer method capable of effectively and efficiently using a storage area of a built-in storage device. And a program including the method.
[0019]
[Means for Solving the Problems]
A data transfer device according to a first invention is a data transfer device that temporarily stores data for transmission or reception in a storage device and then transfers the data, wherein the storage device is divided into a plurality of blocks of a predetermined same unit. Then, in response to a transmission data write request signal when transferring and transmitting data, one of the plurality of blocks is selected and an unused block is used, and the selected block is used. The data is written to the selected block and then read and transferred. In response to a data write request signal for reception when transferring and receiving the data, an unused one of the plurality of blocks is written. A control unit for selecting and setting the selected block in a use state, and controlling to write and read reception data to the selected block, and to transfer the received data. And wherein the door.
[0020]
In the data transfer device, the control unit preferably selects a next block for writing data following the selected block when selecting one unused block among the plurality of blocks. The next block selected is secured as a use state.
[0021]
Preferably, the data transfer device further comprises a first register means provided corresponding to each of the blocks and storing an address of a next block.
[0022]
Further, the data transfer device preferably further comprises a second register means provided corresponding to each of the blocks and storing data indicating whether or not the address of the next block is selected and secured. It is characterized by having.
[0023]
Further, in the data transfer device, preferably, when the data is read from the block, the control unit releases the block as an unused state.
[0024]
Further, the data transfer device preferably further comprises a third register means provided corresponding to each of the blocks and storing data indicating whether or not each of the blocks is in use. And
[0025]
A data transfer method according to a second invention is a data transfer method for temporarily storing data for transmission or reception in a storage device and then transferring the data, wherein the storage device is divided into a plurality of blocks of a predetermined same unit. Then, in response to a transmission data write request signal when transferring and transmitting data, one of the plurality of blocks is selected and an unused block is used, and the selected block is used. The data is written to the selected block and then read and transferred. In response to a data write request signal for reception when transferring and receiving the data, an unused one of the plurality of blocks is written. And selecting the selected block to be in a use state, and writing the data for reception to the selected block, and then reading and transferring the data. The features.
[0026]
In the data transfer method, preferably, the controlling step includes, when selecting one unused block from among the plurality of blocks, selecting a next block for writing data following the selected block. In this case, the selected next block is secured as a use state.
[0027]
Preferably, the data transfer method further includes a step of storing an address of a next block in first register means provided corresponding to each of the blocks.
[0028]
Further, in the data transfer method, preferably, a step of storing data indicating whether or not an address of a next block is selected and secured in a second register means provided corresponding to each of the blocks. Is further included.
[0029]
In the data transfer method, the control step preferably releases the block as an unused state when data is read from the block.
[0030]
Further, the data transfer method preferably further includes a step of storing data indicating whether or not each of the blocks is in use, in a third register means provided corresponding to each of the blocks. It is characterized.
[0031]
A program including the data transfer method according to the third invention is characterized in that it includes a data transfer method including the above steps.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0033]
FIG. 1 is a block diagram showing a configuration of an IEEE 1394 interface device 10 according to an embodiment of the present invention. In the prior art shown in FIG. 25, the reception FIFO storage device 105, the synchronous transmission FIFO storage device 106, and the asynchronous transmission FIFO storage device 107 are divided into three, but in the present embodiment, these three storage devices 105 are used. , 106, and 107 are integrated into a single three-port FIFO storage device 5.
[0034]
The data transfer device according to the embodiment of FIG. 1 is a data transfer device that temporarily stores data for transmission or reception in a storage device such as a single-port memory 27 and then transfers the data. In response to a transmission data write request signal ITXFWREQB or ATXFWREQB when data is transferred and transmitted, and selects one unused block from the plurality of blocks. Then, the selected block is put into a use state, and the transmission data is written to the selected block, read and transferred, and in response to the reception data write request signal RXFRREQB when the data is transferred and received. Selecting one unused block from among the plurality of blocks and setting the selected block to a use state; Credit data is characterized by controlling to transfer by reading after writing to the selected block. In the data transfer device, preferably, when selecting one unused block from among the plurality of blocks, the control unit selects a next block for writing data following the selected block. Then, the selected next block is secured as a use state.
[0035]
In FIG. 1, received data arriving at the personal computer 13 from the IEEE 1394 bus B1 is received by a PHY circuit 7 of the IEEE 1394 interface device 10, and the PHY circuit 7 converts the input received data into an interface such as a signal conversion in a physical layer. After the processing is executed, it is output to the LINK circuit 6. The LINK circuit 6 performs interface processing such as signal conversion in the link layer on the input received data, and then writes the data in the 3-port FIFO storage device 5. Next, the receiving DMA controller 2 reads the received data in the 3-port FIFO storage device 5 and outputs it to the PCI interface controller 1, and in response, the PCI interface controller 1 sends a signal to the read received data. After executing interface processing such as conversion, the data is output to the RAM 11 via the PCI bus B2 and stored.
[0036]
When transmitting data from the personal computer 13 to the IEEE 1394 bus B1, the CPU 12 sends the transmission data in the RAM 11 to the PCI interface controller 1, and the PCI interface controller 1 performs interface processing such as signal conversion on the transmission data. If the synchronous transmission is performed after the execution, the synchronous transmission DMA controller 3 outputs the transmitted data to the 3-port FIFO storage device 5 in response to the output. If the transmission data is transmitted asynchronously, the transmission data is output from the PCI interface controller 1 to the asynchronous transmission DMA controller 4, and the asynchronous transmission DMA controller 4 stores the transmitted transmission data in the 3-port FIFO storage device 5. Write. Next, the LINK circuit 6 reads out the data in the three-port FIFO storage device 5 and executes interface processing such as signal conversion of the link layer, and then via the PHY circuit 7 which executes interface processing such as signal conversion of the physical layer. To the IEEE 1394 bus B1.
[0037]
FIG. 2 is a block diagram showing a detailed configuration of the 3-port FIFO storage device 5. The differences from the prior art of FIGS. 25 to 27 will be described below.
[0038]
The reception FIFO storage device 105, the synchronous transmission FIFO storage device 106, and the asynchronous transmission FIFO storage device 107 in FIG. 26 correspond to the three-port FIFO storage device 5 in FIG. The FIFO memory 121 of the reception FIFO storage device 105, the FIFO memory 131 of the synchronous transmission FIFO storage device 106, and the FIFO memory 141 of the asynchronous transmission FIFO storage device 107 of FIG. 26 are respectively the reception FIFO memory 21 of FIG. They correspond to the transmission FIFO memory 22 and the asynchronous transmission FIFO memory 23, and have the same data capacity. The single port memory 122 of the reception FIFO storage device 105, the single port memory 132 of the synchronous transmission FIFO storage device 106, and the single port memory 142 of the asynchronous transmission FIFO storage device 107 of FIG. Correspondingly, the total capacity of the three single-port memories of FIG. 26 is the same as the capacity of FIG. The single port memory 27 is constituted by, for example, an SRAM.
[0039]
The data from the 4-to-1 33-bit multiplexer 24 is input to the first input terminal of the single port memory 27 in FIG. 2 via the input data bus MDI [32: 0]. The output data of the FIFO memory 23 for asynchronous transmission is input to the first input terminal (0) via the data bus ATDO [32: 0], and the second input terminal (1) of the multiplexer 24 is connected to the data bus ATDO [32: 0]. The output data of the synchronous transmission FIFO memory 22 is input via ITDO [32: 0], and the third input terminal (2) of the multiplexer 24 is supplied from the LINK circuit 6 via the data bus RXDO [32: 0]. 26 is input to the fourth input terminal (3) of the multiplexer 24 in the receiving FIFO storage device 105 shown in FIG. Fixed value of the same data 33'h10000014 shall be used to input of the multiplexer 123 when 憶 device 105 becomes full state (this value is an example.) Is input. A second input terminal of the single port memory 27 shown in FIG. 2 is connected to an output terminal of a 4-to-1 11-bit multiplexer 25 via an address bus MAD [10: 0]. The input terminal (0) receives address data for asynchronous transmission from the FIFO timing controller 28 via the address bus AAD [10: 0], and the second input terminal (1) of the multiplexer 25 connects the address bus IAD [10 : 0], the address data for synchronous transmission is input from the FIFO timing controller 28, and the third input terminal (2) and the fourth input terminal (3) of the multiplexer 25 are connected to the address bus RAD [10: 0]. , Receiving address data from the FIFO timing controller 28 is input. The read / write control signal MWRB output from the 4-to-1 1-bit multiplexer 26 is input to the third input terminal of the single-port memory 27 in FIG. 2, and the first input terminal (0 ) Is supplied with a read request signal AFRDB of the asynchronous transmission FIFO memory 23 from the FIFO timing controller 28, and the second input terminal (1) of the multiplexer 26 receives the synchronous transmission FIFO memory 22 from the FIFO timing controller 28. The read request signal IFRDB is input, and the write request signal RFWRB of the receiving FIFO memory 21 from the FIFO timing controller 28 is input to the third input terminal (2) and the fourth input terminal (3) of the multiplexer 26. You. A bus DISEL [1: 0] is connected between the FIFO timing controller 28 and each of the multiplexers 24, 25, 26 in order to transmit a data select signal to the three multiplexers 24, 25, 26 described above. You.
[0040]
The output data bus MDO [32: 0] of the single port memory 27 becomes the data bus ITXDI [32: 0] and ATXDI [32: 0] to the LINK circuit 6, and the input data of the reception FIFO memory 21. Become a bus. The output data bus of the receiving FIFO memory 21 is the data bus RXDI [32: 0] to the receiving DMA controller 2, and the data bus ITXDO [32: 0] from the synchronous transmitting DMA controller 3 is the synchronous transmitting FIFO. The data bus ATXDO [32: 0] from the asynchronous transmission DMA controller 4 serves as an input data bus for the asynchronous transmission FIFO memory 23.
[0041]
Further, an RFRDB signal is input from the FIFO timing controller 28 to the reception FIFO memory 21 as a read request signal of the reception FIFO memory 21, and an RFWRB signal is received from the FIFO timing controller 28 as a write request signal of the reception FIFO memory 21. Input to the FIFO memory 21 for use. Also, an IFRDB signal is input from the FIFO timing controller 28 to the synchronous transmission FIFO memory 22 as a read request signal for the synchronous transmission FIFO memory 22, and the IFRDB signal is output from the FIFO timing controller 28 as a write request signal for the synchronous transmission FIFO memory 22. The signal is input to the FIFO memory 22 for synchronous transmission. Further, the AFRDB signal is input from the FIFO timing controller 28 to the asynchronous transmission FIFO memory 23 as a read request signal of the asynchronous transmission FIFO memory 23, and the FIFO timing controller 28 outputs the AFWRB signal as a write request signal of the asynchronous transmission FIFO memory 23. The signal is input to the FIFO memory 23 for asynchronous transmission.
[0042]
In the above embodiment, the FIFO memories 21, 22, and 23 are used as storage devices between the single port memory 27 and each of the DMA controllers 2, 3, and 4. However, the present invention is not limited to this. The device may be a memory such as an asynchronous dual port memory.
[0043]
Next, a storage method of the IEEE 1394 interface device 10 of FIGS. 1 and 2 will be described with reference to FIGS.
[0044]
In the present embodiment, as shown in FIG. 3, the data storage area of the single port memory 27 in the 3-port FIFO storage device 5 is divided into predetermined small blocks, and each block is used for reception, synchronous transmission, and asynchronous transmission. It is characterized in that it can be used for any transmission. The single-port memory 27 shown in FIG. 3 has a memory capacity of 33 bits × 2048 words, and divides the memory area into 32 blocks B00 to B31 every 64 words. Further, as shown in FIG. 3, the following registers are provided for each of the blocks B00 to B31.
(A) Registers B00NXPT [4: 0] to B31NXPT [4: 0] for storing an address pointer for indicating which block the data in each block follows next, or 5-bit data of the block pointer.
(B) Registers B00USE to B31USE each storing 1-bit data indicating whether each block is allocated and used as a memory of a FIFO storage device for reception, synchronous transmission, or asynchronous transmission.
(C) Registers B00NOK to B31NOK for storing 1-bit data indicating whether a block next to each block is allocated.
The detailed configuration of these registers will be described later.
[0045]
4 to 7 are schematic explanatory diagrams relating to the operation of the single-port memory 27 in FIG. As shown in FIG. 4 to FIG. 7, data is written to or read from any block in the single port memory 27 corresponding to the reception FIFO data, the synchronous transmission FIFO data, and the asynchronous transmission FIFO data, respectively. Is provided. Further, as a basic condition of the present embodiment, as for all the blocks in the single port memory 27, one block to which data can be written next is assigned to the block to which data is currently written. Next, an example of the operation will be described below with reference to FIGS.
[0046]
In the initial state of FIG. 4, the reception FIFO data read block pointer “RRDBPTR” and the write block pointer “RWRBPTR” are both “00h” (“h” indicates a hexadecimal number), and indicates the block B00. . The synchronous transmission FIFO data read block pointer “IRDBTPR” and the write block pointer “IWRBTPR” both become “01h”, indicating the block B01. The asynchronous transmission FIFO data read block pointer “ARDBPTR” and the write block pointer “AWRBPTR” are both “02h”, indicating the block B02. The detailed configuration of each of the above-described block pointers will be described later. Further, the register B00NXPT of the address pointer indicating the block following the block B00 becomes "03h", indicating the block B03. Also, the register B01NXPT becomes “04h” and indicates the block B04. Further, the register B02NXPT becomes “05h” and indicates the block B05. Further, since the next block is allocated to the blocks B00 to B02, the registers B00NOK, B01NOK and B02NOK become high level. Further, since the blocks B00 to B05 are allocated to the respective FIFO data of reception, synchronous transmission, and asynchronous transmission, the registers B00USE, B01USE, B02USE, B03USE, B04USE, and B05USE become high level.
[0047]
5 shows a state after the received packet is transferred from the LINK circuit 6 and written into the single port memory 27 from the initial state of FIG. When the received data sent from the LINK circuit 6 has been written into all the blocks B00, the data value of the register B00NXPT is "03h", so that the writing of the continuation of the received data to the block B03 is started. At the same time, since the block next to the block B03 is not allocated, the block B06, which is an unused block, is allocated for the reception FIFO data. Therefore, the register B03NXPT becomes "06h" (that is, indicates the address of the block B06), the register B03NOK becomes high level, and the register B06USE becomes high level. When the received data has been written to all of the blocks B03, the data value of the register B03NXPT is "06h", so that the continuation of the received data is started to be written to the block B06. At the same time, since the block next to the block B06 is not allocated, the block B07, which is an unused block, is allocated for the reception FIFO data. Therefore, the register B06NXPT becomes "07h" (that is, the address of the block B07 is indicated), the register B06NOK goes high, and the register B07USE goes high.
[0048]
In the reception packet processing of FIG. 6, the reception DMA controller 2 reads out the reception packet stored in the single port memory 27 from the packet reception state of FIG. The receiving DMA controller 2 reads out all the data of the block B00 and ends the reading, and starts reading out the data in the block B03 indicated by the data value "03h" of the register B00NXPT. At the same time, since all the data of the block B00 has been read and no longer required, the registers B00NOK and B00USE are set to low level. This inevitably makes the data in the register B00NXPT meaningless. When reading of all data of the block B03 is completed, reading of data of the block B06 indicated by the data value “06h” of the register B03NXPT is started. At the same time, all the data in the block B03 has been read out, and the data is no longer needed. Therefore, the registers B03NOK and B03USE are set to low level. As a result, the data of the register B03NXPT necessarily becomes meaningless data.
[0049]
7 shows a state after the synchronous transmission DMA controller prepares synchronous transmission data in the synchronous transmission FIFO memory 22 after the reception packet processing state in FIG. When the synchronous transmission data sent from the synchronous transmission DMA controller has been written to all of the blocks B01, the data value of the register B01NXPT is "04h", so that the continuation of the synchronous transmission data is written to the block B04. To start. Since the block next to the block B04 is not allocated at the same time, the block B08, which is an unused block, is allocated for synchronous transmission data. Therefore, the register B04NXPT becomes “08h”, the register B04NOK goes high, and the register B08USE goes high. When the synchronous transmission data has been written to all blocks B04, the data value of the register B04NXPT is "08h", so that writing to the block B08 is started. At the same time, since the block next to the block B08 is not allocated, the block B09, which is an unused block, is allocated for synchronous transmission data. Therefore, the register B08NXPT becomes "09h", the register B08NOK goes high, and the register B09USE goes high.
[0050]
As described above, two or more blocks are always allocated to one FIFO data, and the used blocks are released from the allocation, so that an effective and efficient FIFO storage device can be used according to the situation. Can perform usage. Although not described above, the same processing can be performed when writing and / or reading asynchronous transmission data in the single port memory 27. In addition, the examples of FIGS. 4 to 7 are examples of a method of always allocating the first empty block, and allocating from the block B00 when the block B31 is allocated. However, a method of always allocating an empty block closest to the block B00 may be used, and this method is used in the description of the detailed configurations in FIGS.
[0051]
Hereinafter, a more detailed configuration of the IEEE 1394 interface device 10 described with reference to FIGS. 1 and 2 will be described.
[0052]
FIG. 8 shows a configuration example of the FIFO timing controller 28 of FIG. The reception timing controller 31, the synchronous transmission timing controller 32, and the asynchronous transmission timing controller 33 in FIG. 8 are basically the timing controller 124 and the synchronous transmission FIFO storage device 106 of the reception FIFO storage device 105 in FIG. The timing controller 133 and the timing controller 143 of the asynchronous transmission FIFO storage device 107 perform the timing control of the reception FIFO memory 21, the synchronous transmission FIFO memory 22, and the asynchronous transmission FIFO memory 23. In FIG. 8, a block controller 35 is provided as a controller for controlling each block obtained by dividing the single port memory 27 of the present embodiment into a certain size. The block controller 35 includes the registers B00NXPT to B31NXPT [4: 0], the registers B00NOK to B31NOK, and the registers B00USE to B31USE described with reference to FIG.
[0053]
The block controller 35 receives a signal RWB [4: 0] indicating the value of the current write block from the reception timing controller 31 and a signal of the block when a block that can be used next to the block currently being written is not allocated. An RBALREQB signal for making an allocation request, an RRB [4: 0] signal indicating the value of the block currently being read, and an RRBFREE signal indicating that all the data of the block currently being read have been read and thus the block can be deallocated. Input as a signal for reception. In addition, the block controller 35 transmits to the reception timing controller 31 a BEMP [4: 0] signal indicating the currently selected empty block value and an RBALACKB signal for permitting block allocation in response to a new block allocation request. Then, an RNRB [4: 0] signal indicating a block to be read next to the block currently being read and an RNRBOK signal indicating that the block to be read next has already been allocated are output as signals for reception.
[0054]
Also, when the block controller 35 is not assigned from the synchronous transmission timing controller 32 an IWB [4: 0] signal indicating the value of the current write block and a block that can be used next to the block currently being written. , An IBALREQB signal for requesting block allocation, an IRB [4: 0] signal indicating the value of the block currently being read, and indicating that all the data of the block currently being read have been read, so that the block can be deallocated. The IRBFREE signal is input as a signal for synchronous transmission. In addition, the block controller 35 supplies the synchronous transmission timing controller 32 with a BEMP [4: 0] signal indicating the currently selected empty block value and an IBALACKKB signal for permitting block allocation in response to a new block allocation request. And an INRB [4: 0] signal indicating the block to be read next to the block currently being read, as a signal for synchronous transmission.
[0055]
Also, when the AWB [4: 0] signal indicating the value of the current write block and the block that can be used next to the block currently being written are not allocated to the block controller 35 from the timing controller 33 for asynchronous transmission. , An ARBREQB signal for requesting block allocation, an ARB [4: 0] signal indicating the value of the block currently being read, and that all blocks of the block currently being read have been read, so that the block can be deallocated. The ARBFREE signal is input as a signal for asynchronous transmission. Further, the block controller 35 supplies the asynchronous transmission timing controller 33 with a BEMP [4: 0] signal indicating the currently selected empty block value and an ABALACKB signal for permitting block allocation in response to a new block allocation request. And an ANRB [4: 0] signal indicating the block to be read next to the block currently being read are output as signals for asynchronous transmission.
[0056]
The reception timing controller 31 receives an RXFRREQB signal and an RXFRWAIT signal from the reception DMA controller 2, and the reception timing controller 31 outputs an RXFRACKB signal to the reception DMA controller 2. Further, the RX timing signal from the LINK circuit 6 is input to the reception timing controller 31, and the reception timing controller 31 outputs an RXFULL signal to the LINK circuit 6. The address bus RAD [10: 0] shown in FIG. 2 is connected to the reception timing controller 31, and the reception timing controller 31 outputs an RFRDB signal and an RFWRB signal. The ITXFWREQB signal and the ITXFWDTVL signal are input from the synchronous transmission DMA controller 3 to the synchronous transmission timing controller 32, and the synchronous transmission timing controller 32 outputs an ITXFWACKB signal to the synchronous transmission DMA controller 3. The synchronous transmission timing controller 32 receives an ITXRDB signal from the LINK circuit 6. The address bus IAD [10: 0] shown in FIG. 2 is connected to the synchronous transmission timing controller 32, and the synchronous transmission timing controller 32 outputs an IFRDB signal and an IFWRB signal. The ATXFWREQB signal and the ATXFWDTVL signal are input from the asynchronous transmission DMA controller 4 to the asynchronous transmission timing controller 33, and the asynchronous transmission timing controller 33 outputs the ATXFWACKB signal to the asynchronous transmission DMA controller 4. The ATXRDB signal is input from the LINK circuit 6 to the asynchronous transmission timing controller 33. The address bus AAD [10: 0] shown in FIG. 2 is connected to the asynchronous transmission timing controller 33, and the asynchronous transmission timing controller 33 outputs an AFRDB signal and an AFWRB signal. Then, the RXWRB signal, the ITXRDB signal, the ATXRDB signal, the RFWRB signal, the IFRDB signal, and the AFRDB signal are input to the data selection controller 34. Further, when the 3-port FIFO storage device 5 is in the full state, the write data from the LINK circuit 6 is received. An RFT signal that goes high when the last data is input is input, and a data select signal is output from the data selection controller 34 via the bus DISEL [1: 0]. The data select signal output via the bus DISEL [1: 0] is "10b" during the data reception processing, "01b" during the data synchronous transmission processing, and the asynchronous data transmission. The processing period is “00b”, and the period in which the RFT signal is at the high level during the data receiving process, that is, when the 3-port FIFO memory device 5 is in the full state and the writing from the LINK circuit 6 is performed. The period in which the data is the last data is “11b”. As a condition for the operation of the LINK circuit 6, the RXWRB signal, the ITXRDB signal, and the ATXRDB signal are not activated at the same time, and which of these signals is activated is given the highest priority in the operation of the LINK circuit 6. Selected. When the RFWRB signal, the IFRDB signal, and the AFRDB signal become active when those signals are not active, the single port memory 27, the reception FIFO memory 21, the synchronous transmission FIFO memory 22, or the asynchronous transmission FIFO The read / write of the packet to / from the memory 23 is selected by changing the priority in order.
[0057]
FIG. 9 shows an embodiment of the block controller 35 of FIG. As described above, the registers B00NXPT [4: 0] to B31NXPT [4: 0], the registers B00NOK to B31NOK, and the registers B00USE to B31USE used in the schematic explanatory diagrams of FIGS. 4 to 7 are provided in the block controller 35. In the following description, “##” indicates 00 to 31.
[0058]
The block access controller 41 of the block controller 35 controls these registers to control access to each of the blocks B00 to B31 created by dividing the memory area of the single port memory 27 (FIGS. 4 to 4). (See FIG. 7). Each register B ## NXPT [4: 0] is a 5-bit register with a synchronous data load enable (EB), and each register B ## NXPT [4: 0] has a B # output from the block access controller 41. The #NXB signal is input. The BEMP [4: 0] signal output from the 32-bit priority encoder 42 is input to the input terminal of each register B ## NXPT [4: 0]. The output terminal of each register B ## NXPT [4: 0] is connected to the input terminals of three 32-to-1 5-bit multiplexers 44, 45 and 46. The RRB [4: 0] signal is input to the select signal terminal of the multiplexer 44, and the RNRB [4: 0] signal is output from the output terminal of the multiplexer 44. Further, the IRB [4: 0] signal is input to the select signal terminal of the multiplexer 45, and the INRB [4: 0] signal is output from the output terminal of the multiplexer 45. Further, the ARB [4: 0] signal is input to the select signal terminal of the multiplexer 46, and the ANRB [4: 0] signal is output from the output terminal of the multiplexer 46.
[0059]
Each register B ## NOK which is a D-type flip-flop is a 1-bit register with a synchronous data load enable (EB), and each register B ## NOK has a B # output from the block access controller 41. The #NXB signal is input. Each register B # NOK has a synchronous reset (RB) terminal, and a B ## FLB signal output from the block access controller 41 is input to the terminal. The D input terminal of each register B ## NOK is connected to a voltage source Vcc indicating a high level. The output signal from each register B ## NOK becomes an input signal of a 32-to-1 1-bit multiplexer 43, and an RRB [4: 0] signal is input to a select signal terminal of the multiplexer 43. An RNRBOK signal is output from the output terminal. Each register B ## USE, which is a D-type flip-flop, is a 1-bit register with a synchronous data load enable (EB), and each register B ## USE has a B ## output from the block access controller 41. The ALB signal is input. Further, each register B ## USE has a synchronous reset (RB) terminal, and a B ## FLB signal output from the block access controller 41 is input to each register B ## USE. The D input terminal of each register B ## USE is connected to a voltage source Vcc indicating a high level. The output signal from each of these registers B ## USE becomes an input signal to the 32-bit priority encoder 42, and the output signal from the 32-bit priority encoder 42 is output to the outside of the block controller 35 as a BEMP [4: 0] signal. And input to the block access controller 41.
[0060]
An output signal from each register B ## USE is input to an OR gate AND1 having 32 input terminals, and an output signal from the OR gate AND1 is input to the block access controller 41 as a BFULL signal. In addition, the block access controller 41 includes an RWB [4: 0] signal, an RBALREQB signal, an RRBFREE signal, an IWB [4: 0] signal, an IBALREQB signal, an IRBFREE signal, an AWB [4: 0] signal, an ABALREQB signal, and an ARBFREE signal. Are input, and the block access controller 41 outputs an RBALACKB signal, an IBALACKKB signal, and an ABALACKKB signal. Here, based on the input RBALREQB signal, IBALREQB signal, ABALREQB signal, and BFULL signal, the block access controller 41 generates an RBALACKB signal, an IBALACKKB signal, which is a permission signal for a new block allocation request for reception, synchronous transmission, and asynchronous transmission. Generate and output an ABALACKB signal. In the signal generation method, priorities may be equally assigned to the three types of request signals including the RBALREQB signal, the IBALREQB signal, and the ABALREQB signal, or priorities such as reception> synchronous transmission> asynchronous transmission may be given. The B ## ALB signal, B ## FRB signal, and B ## NXB signal are generated by the following equations.
[0061]
(Equation 1)

[0062]
(Equation 2)

[0063]
[Equation 3]

[0064]
Here, “INV” means a negation operation or an inversion operation, “OR” means a logical sum operation, and “AND” means a logical product operation.
[0065]
FIG. 10 is a block diagram showing a configuration example of a counter which is a part of a circuit built in the reception timing controller 31 of FIG. The register RWRNBPTR in FIG. 10 is a 5-bit register, and stores a value indicating a block which can be written next to the block currently being written. Then, a BEMP [4: 0] signal is input to an input terminal of the register RWRNBPTR. The register RWRBPTR is a 5-bit register that stores a value indicating the block currently being written, and outputs an output signal thereof as an RWB [4: 0] signal. Then, an output signal from the register RWRBPTR is input to an input terminal of the register RWRBPTR. The 6-bit up counter 51 stores a value indicating which address of the block currently being written is to be written. The upper 5 bits of the RWRCNT [10: 0] signal indicating the address currently being written to the external single port memory 27 are the RWRCNT [10: 6] signals from the register RWRBPTR, and the lower 5 bits. The 6-bit signal is the RWRCNT [5: 0] signal from the DO [5: 0] terminal of the 6-bit up counter 51.
[0066]
The RBALACKB signal is input to the first input terminal of the OR gate OR1, the output signal from the OR gate OR1 is input to the first input terminal of the NAND gate NAND2, and the output signal from the OR gate OR1 is input to the LB input terminal of the register RWRNBPTR. At the same time as the synchronous load enable signal, and is also inputted to the DB input terminal of the 2-bit synchronous up / down counter 52 and the first input terminal of the NAND gate NAND2. The output signal from the NAND gate NAND2 is output to the D input terminal of the D-type flip-flop F1, the Q output signal from the flip-flop F1 is output to the block controller 35 as the RBALREQB signal, and the second input of the OR gate OR1. The input signal is input to the terminal and the second input terminal of the NAND gate NAND1, and the output signal from the NAND gate NAND1 is input to the LB input terminal of the register RWRBPTR as a synchronous load enable signal. The inverted QB output signal from the flip-flop F1 is input to a second input terminal of the OR gate OR2, and the output signal from the OR gate OR2 is output to a second input terminal of the NAND gate NAND2. The carry-out signal (CO) from the 6-bit up counter 51 is input to the first input terminal of the NAND gate NAND3, and the RXWRB signal is input to the second input terminal of the NAND gate NAND3 via the inverter N1. The output signal from the NAND gate NAND3 is output to the UB input terminal of the 2-bit synchronous up / down counter 52, and is also input to the first input terminal of the AND gate AND2 via the inverter N2, and the output signal from the AND gate AND2 is It is output to the data selection controller 34 as an RFT signal. The D0 output signal from the 2-bit synchronous up / down counter 52 is input to the second input terminal of the AND gate AND2 and the first input terminal of the OR gate OR3, and the D1 output signal of the 2-bit synchronous up / down counter 52 is output to the OR gate OR3. The signal is input to the second input terminal and is output to the LINK circuit 6 as an RXFULL signal. An output signal from the OR gate OR3 is input to a first input terminal of the NAND gate NAND1 and a first input terminal of the OR gate OR2.
[0067]
The register RRDBPTR is a 5-bit register that stores the value of the RNRB [4: 0] signal indicating the block currently being read, and outputs its output signal as the RRB [4: 0] signal. The 6-bit up counter 53 stores a value indicating which address of the block currently being read is to be read. The upper 5 bits of the RRDCNT [10: 0] signal indicating the address currently being read from the external single port memory 27 are the RRDCNT [10: 6] signals from the register RRDBPTR, and the lower 6 bits Becomes the RRDCNT [5: 0] signal which is the DO [5: 0] signal output from the 6-bit up counter 53. The RNRBOK signal is input to the first input terminal of the NAND gate NAND4, and the output signal of the NAND gate NAND4 is input to the LB input terminal of the register RRDBPTR as a synchronous load enable signal, and the D input of the D-type flip-flop F2. Input to the terminal. The Q output signal of the flip-flop F2 is output to the RB input terminal of the D-type flip-flop F3. The carry-out signal (CO) of the 6-bit up counter 53 is input to the first input terminal of the NAND gate NAND4, and the RFWRB signal is input to the second input terminal of the NAND gate NAND4 via the inverter N3. The output signal from the NAND gate NAND4 is input to the block controller 35 as an RRB FREE signal, and is also input to the flip-flop F3 as a clock signal. The D input terminal of the flip-flop F3 is connected to the voltage source Vcc indicating a high level, and the Q output signal from the flip-flop F3 is input to the second input terminal of the NAND gate NAND4.
[0068]
FIG. 11 is a block diagram showing a configuration example of a counter which is a part of a circuit built in the synchronous transmission timing controller 32 of FIG. The register IWRNBPTR in FIG. 11 is a 5-bit register, and stores a value indicating a block to which data can be written next to a block to which data is currently written. Then, a BEMP [4: 0] signal is input to an input terminal of the register IWRNBPTR. The register IWRBPTR is a 5-bit register that stores a value indicating the block currently being written, and outputs an output signal thereof as an IWB [4: 0] signal. Then, an output signal from the register IWRBPTR is input to an input terminal of the register IWRBPTR. The 6-bit up counter 54 stores a value indicating which address of the block currently being written is to be written. The upper five bits of the IIWRCNT [10: 0] signal indicating the address currently being written to the external single-port memory 27 become the IWRCNT [10: 6] signal which is the output signal from the register IWRBPTR, and the lower five bits. Six bits become an IWRCNT [5: 0] signal which is an output DO [5: 0] signal from the 6-bit up counter 54.
[0069]
The IBALACKB signal is input to the first input terminal of the OR gate OR4, and the output signal from the OR gate OR4 is input to the first input terminal of the NAND gate NAND6, and the synchronous load enable signal is input to the LB input terminal of the register IWRNBPTR. Is entered as The output signal from the NAND gate NAND6 is input to the D input terminal of the D-type flip-flop F4, the Q output signal from the flip-flop F4 is output to the block controller 35 as an IBALREQB signal, and the second input of the OR gate OR4. And the second input terminal of the NAND gate NAND5. The output signal from the NAND gate NAND5 is input to the LB input terminal of the register IWRBPTR as a synchronous load enable signal. The carry-out signal (CO) of the 6-bit up counter 54 is input to a first input terminal of the AND gate AND4, and an IFRDB signal is input to a second input terminal of the AND gate AND4 via the inverter N4. The output signal from the AND gate AND4 is input to the first input terminal of the NAND gate NAND5 and the first input terminal of the OR gate OR5, and the inverted QB output signal from the flip-flop F4 is input to the second input terminal of the OR gate OR5. Is entered. An output signal from the OR gate OR5 is input to a second input terminal of the NAND gate NAND6.
[0070]
The register IRDBPTR is a 5-bit register that stores the value of the INRB [4: 0] signal indicating the block currently being read, and outputs its signal as the IRB [4: 0] signal. The 6-bit up counter 55 stores a value indicating which address of the block currently being read is to be read. The upper five bits of the IRDCNT [10: 0] signal indicating the address currently being read from the external single-port memory 27 are the IRDCNT [10: 6] signals output from the register IRDBPTR, and the lower five bits. Six bits become an IRDCNT [5: 0] signal which is an output DO [5: 0] signal from the 6-bit up counter 55. The carry-out signal (CO) from the 6-bit up counter 55 is input to the first input terminal of the NAND gate NAND7, and the ITXRDB signal is input to the second input terminal of the NAND gate NAND7 via the inverter N5. The output signal from the NAND gate NAND7 is output to the block controller 35 as an IRBF FREE signal, and is input to the LB input terminal of the register IRDBPTR as a synchronous load enable signal.
[0071]
FIG. 12 is a block diagram showing a configuration example of a counter which is a part of a circuit built in the asynchronous transmission timing controller 33 of FIG. The register AWRNBPTR in FIG. 12 is a 5-bit register and stores a value indicating a block to which data can be written next to a block to which data is currently written. Then, a BEMP [4: 0] signal is input to an input terminal of the register AWRNBPTR. The register AWRBPTR is a 5-bit register that stores a value indicating the block currently being written, and outputs an output signal thereof as an AWB [4: 0] signal. Then, an output signal from the register AWRNBPTR is input to an input terminal of the register AWRBPTR. The 6-bit up counter 56 stores a value indicating which address of the block currently being written is to be written. The AWRCNT [10: 0] signal indicating the current address of the external single-port memory 27 to which data is being written has its upper 5-bit signal as AWRCNT [10: 6], which is the output signal from the register AWRBPTR, and its lower 5 bits. The 6-bit signal becomes the AWRCNT [5: 0] signal which is the DO [5: 0] signal output from the 6-bit up counter 56.
[0072]
The ABALACKB signal is input to the first input terminal of the OR gate OR6, and the output signal from the OR gate OR6 is input to the first input terminal of the NAND gate NAND9, and is input to the LB input terminal of the register AWRNBPTR as a synchronous load enable signal. Is done. The output signal from the NAND gate NAND9 is input to the D input terminal of the D-type flip-flop F5, the Q output signal from the flip-flop F5 is output to the block controller 35 as an ABALREQB signal, and the second input of the OR gate OR6. And the first input terminal of the NAND gate NAND8. The output signal from the NAND gate NAND8 is input to the LB input terminal of the register AWRBPTR as a synchronous load enable signal. The carry-out signal (CO) of the 6-bit up counter 56 is input to a first input terminal of the AND gate AND5, and an AFRDB signal is input to a second input terminal of the AND gate AND5 via the inverter N6. An output signal from the AND gate AND5 is input to a first input terminal of the NAND gate NAND8 and a first input terminal of the OR gate OR7, and an inverted QB output signal from the flip-flop F5 is input to a second input terminal of the OR gate OR7. Is entered. An output signal from the OR gate OR7 is input to a second input terminal of the NAND gate NAND9.
[0073]
The register ARDBPTR is a 5-bit register that stores the value of the ANRB [4: 0] signal indicating the block currently being read, and outputs its output signal as the ARB [4: 0] signal. The 6-bit up counter 57 stores a value indicating which address of the block currently being read is to be read. The upper five bits of the ARDCNT [10: 0] signal indicating the address currently being read from the external single-port memory 27 are the ARDCNT [10: 6] signals output from the register ARDBPTR, and the lower five bits thereof. Six bits become an ARDCNT [5: 0] signal which is an output DO [5: 0] signal from the 6-bit up counter 57. The carry-out signal (CO) of the 6-bit up counter 57 is input to the first input terminal of the NAND gate NAND10, and the ATXRDB signal is input to the second input terminal of the NAND gate NAND10 via the inverter N7. The output signal from the NAND gate NAND10 is output to the block controller 35 as an ARBF FREE signal, and is input to the LB input terminal of the register ARDBPTR as a synchronous load enable signal.
[0074]
Next, the operation of the above-described IEEE 1394 interface device 10 will be described with reference to FIGS. 13 to 24 and a timing chart of each signal.
[0075]
FIG. 13 shows an initial timing chart of each signal in the block controller 35 of the present embodiment. “LCLK” indicates a clock signal on the IEEE 194 bus B1 side. As shown in FIG. 13, blocks B00, B01, and B02 are allocated for reception, for synchronous transmission, and for asynchronous transmission, respectively. In addition, since none of the above blocks has been assigned a next write block, blocks B03, B04 and B05 are respectively assigned at timings t4, t6 and t8 as blocks following blocks B00, B01 and B02, respectively. Then, respective values are set in the registers B00NXPT, B01NXPT, and B02NXPT.
[0076]
FIG. 14 is a timing chart of each signal at the time of reception in the 3-port FIFO storage device 5 of the present embodiment when there is no switching of the write block. “DCLK” indicates a clock signal on the PCI bus B2 side. This timing chart is an embodiment in the case where the read / write block for reception is specified from the address “00h” of the block B00 and the operation is started. Then, at timings T2, T4, T6, T8, and T10, data D0, D1, D2, D3, and D4 are written from the LINK circuit 6 to the three-port FIFO storage device 5, respectively, so that the RWRCNT signal is incremented at each timing. , Data is sequentially stored in the single port memory 27. The data is sequentially read from the single-port memory 27 by incrementing the RRDCNT signal at timings T3, T5, T7, T9, and T11, and written to the reception FIFO memory 21. Then, at timings t13, t16, t21, t22 and t23, the data read from the three-port FIFO storage device 5 is sequentially output to the receiving DMA controller 2.
[0077]
FIG. 15 shows a timing chart of each signal at the time of synchronous transmission in the 3-port FIFO storage device 5 of the present embodiment when there is no switching of the write block. This timing chart is an embodiment in the case where the read / write block for synchronous transmission starts the operation specified by the address “00h” of the block B01. The data D0, D1, D2, D3, and D4 are written from the synchronous transmission DMA controller 3 to the synchronous transmission FIFO memory 22 at timings t2, t3, t4, t6, and t7, respectively, and timings T3, T4, T5, T6, and T7. Is read from the synchronous transmission FIFO memory 22, the IWRCNT signal is incremented at each timing, and the data is sequentially stored in the single port memory 27. Then, at timings T11, T12, T13, T14 and T15, the LINK circuit 6 sequentially reads data from the single port memory 27 while incrementing the IRDCNT signal.
[0078]
FIG. 16 is a timing chart of each signal at the time of asynchronous transmission in the 3-port FIFO storage device 5 according to the present embodiment when there is no switching of the write block. This timing chart is an embodiment in the case where the read / write block for asynchronous transmission is specified from the address “00h” of the block B02 and the operation is started. Data D0, D1, D2, D3 and D4 are written from the asynchronous transmission DMA controller 4 to the asynchronous transmission FIFO memory 23 at timings t2, t3, t4, t6 and t7, respectively, and the timings T3, T4, T5, T6 and T7. Is read from the asynchronous transmission FIFO memory 23, the AWRCNT signal is incremented at each timing, and data is sequentially stored in the single port memory 27. Then, at timings T11, T12, T13, T14, and T15, the LINK circuit 6 sequentially reads data from the single port memory 27 while incrementing the ARDCNT signal.
[0079]
FIG. 17 shows a timing chart of each signal at the time of reception in the three-port FIFO storage device 5 of the present embodiment when the write block is switched. This timing chart is an embodiment when the read / write block for reception is specified from the address “3Eh” of the block B00 and the operation is started. Then, at timings T2, T4, T6, T8, and T10, the data D0, D1, D2, D3, and D4 are written from the LINK circuit 6 to the three-port FIFO storage device 5, respectively. Therefore, the RWRCNT signal is incremented at each timing, and sequentially. Is stored in the single port memory 27. At timings T3, T5, T7, T9, and T11, the data is sequentially read from the single-port memory 27 and written to the reception FIFO memory 21 while incrementing the RRDCNT signal. The data sequentially read from the 3-port FIFO storage device 5 at timings t13, t16, t21, t22 and t23 is output to the receiving DMA controller 2. Then, at the time of writing at the timing T4, the RBALREQB signal goes low at the next timing T6 because the last data of the block B00, and the allocation processing of the next writing block is executed. At the timing T8, the block B06 is the next writing block. The block is allocated as a block next to the block B03. At timing T5, the last data of block B00 has been read, so at timing T6 the allocation of block B00 is released, and register B00USE is set to low level.
[0080]
FIG. 18 shows a timing chart of each signal at the time of synchronous transmission in the 3-port FIFO storage device 5 of the present embodiment when the write block is switched. This timing chart is an embodiment in the case where the read / write block for synchronous transmission is specified from the address “3Eh” of the block B01 and the operation is started. Data D0, D1, D2, D3, and D4 are written from the synchronous transmission DMA controller 3 to the synchronous transmission FIFO memory 22 at timings t2, t3, t4, t6, and t7, respectively, and the data is written at timings T3, T4, T7, and T7. At T8 and T9, the data is read from the synchronous transmission FIFO memory 22, the IWRCNT signal is incremented at each timing, and the data is sequentially stored in the single port memory 27. Then, at timings T11, T12, T13, T14 and T15, the LINK circuit 6 sequentially reads data from the single port memory 27 while incrementing the IRDCNT signal. Then, at the time of writing at the timing T4, since it is the last data of the block B01, the IBALREQB signal becomes low level at the next timing T5, and the allocation processing of the next write block is executed. Further, since the allocation of the next write block is not completed between the timings T5 and T6, the writing to the synchronous transmission FIFO memory 22 is also stopped. Then, at a timing T7, the block B06 is allocated as a block next to the block B04 which is the next write block. At timing T12, the last data of the block B01 is read, so at timing T13, the allocation of the block B01 is released, and the register B01USE is set to low level.
[0081]
FIG. 19 shows a timing chart of each signal at the time of asynchronous transmission in the three-port FIFO storage device 5 of the present embodiment when the write block is switched. This timing chart is an embodiment in the case where the read / write block for asynchronous transmission is specified from the address “3Eh” of the block B02 and the operation is started. Data D0, D1, D2, D3, and D4 are written from the asynchronous transmission DMA controller 4 to the asynchronous transmission FIFO memory 23 at timings t2, t3, t4, t6, and t7, respectively, and the data is written at timings T3, T4, T7, At T8 and T9, the data is read from the asynchronous transmission FIFO memory 23, the AWRCNT signal is incremented at each timing, and the data is sequentially stored in the single port memory 27. Then, at timings T11, T12, T13, T14, and T15, the LINK circuit 6 sequentially reads data from the single port memory 27 while incrementing the ARDCNT signal. Then, at the time of writing at the timing T4, the ABALREQB signal becomes low level at the next timing T5 because it is the last data of the block B02, and the next write block allocation processing is executed. Further, since the allocation of the next write block has not been completed between the timings T5 and T6, the writing to the asynchronous transmission FIFO memory 23 is also stopped. Then, at a timing T7, the block B06 is allocated as a block next to the block B05 which is the next write block. At timing T12, the last data of the block B02 is read, so at timing T13, the allocation of the block B02 is released, and the register B02USE is set to low level.
[0082]
FIG. 20 shows the state of each signal at the time of reception in the three-port FIFO storage device 5 according to the present embodiment when the write block is switched and the FIFO storage device becomes full without an empty block. 4 shows a timing chart. This timing chart shows that in the read / write block for reception, the block B00 is used and reading of the reception FIFO memory 21 is stopped for some reason, so that the RRDCNT signal which is the read address is stopped at "010h". This is an example when the operation is performed. At timings T0, T2, and T4, data is written from the LINK circuit 6 to the single-port memory 27. Since the last data of the block B00 is written at timing T2, the RBALREQB signal goes low at timing T4. However, since there is no empty block (the BFULL signal is at a high level), the RBALACKB signal does not go to a low level. Then, data writing from the LINK circuit 6 is sequentially performed, and the block B03 also executes writing of the final data at the timing T8. Therefore, at timing T8, the DISEL [1: 0] signal becomes "3" and the single port memory 27 becomes full, and the data "33'h1000000014" indicating this is forcibly written to the single port memory 27. Then, from timing T9, the RXFULL signal becomes high level, requesting the LINK circuit 6 to stop writing to the 3-port FIFO storage device 5. Then, after a while, the receiving DMA controller 2 starts reading data from the receiving FIFO memory 21, and the data is sequentially read at timings T10, T11, T12, and T13. Then, since the last data of the block B00 is read at the timing T10, the allocation of the block B00 is released at the timing T11, and the register B00USE becomes the low level. However, since the block B00 that has become an empty block at the timing T11 is allocated as the next write block after the block B03 that is the current write block, the register B00USE goes high at the timing T12. Further, since the next write block is allocated to the block B03, the RXFULL signal goes low at the timing T12, whereby the writing of the next received packet from the LINK circuit 6 is permitted. However, since the write block next to the block B00 is not allocated, the RBALREQB signal goes low again at the timing T13. Then, the receiving DMA controller 2 sequentially reads data from the receiving FIFO memory 21 and reads the last data of the block B03 at the timing T14, so that the block B03 is released at the timing T15 and the register B03USE goes to a low level. However, since the write block next to the block B00 has not been allocated, the block B03 that has become an empty block from timing T15 is allocated as the write block next to the block B00 at timing T16. Therefore, the register B03USE goes high at the timing T16.
[0083]
FIG. 21 is a timing chart when the reception and the synchronous transmission are mixed in the three-port FIFO storage device 5 of the present embodiment. In this timing chart, the operation starts when the read / write block for reception is specified from the address “00h” of the block B00, and the operation starts when the read / write block for synchronous transmission is specified from the address “00h” of the block B01. Is an example in the case where is started. At timings T2, T4, T6 and T8, data R0, R1, R2 and R3 are sequentially written from the LINK circuit 6 to the single port memory 27. At timings t2, t3, t4 and t6, data I0, I1, I2 and I3 are sequentially written from the synchronous transmission DMA controller 3 to the synchronous transmission FIFO memory 22. Then, at timings T5, T9, T11 and T13, the data R0, R1, R2 and R3 are sequentially written from the single port memory 27 to the reception FIFO memory 21. At timings T3, T7, T10 and T12, data I0, I1, I2 and I3 are sequentially written from the synchronous transmission FIFO memory 22 to the single port memory 27. Then, at timings t20, t23, t24, and t26, the data R0, R1, R2, and R3 are sequentially read from the receiving FIFO memory 21 to the receiving DMA controller 2. Then, at timings T14, T15, T16, and T17, the LINK circuit 6 sequentially reads the data I0, I1, I2, and I3 from the single port memory 27.
[0084]
FIG. 22 is a timing chart when reception and asynchronous transmission are mixed in the 3-port FIFO storage device 5 of the present embodiment. In this timing chart, the operation starts when the read / write block for reception is specified from the address “00h” of the block B00, and the operation starts when the read / write block for asynchronous transmission is specified from the address “00h” of the block B02. Is an example in which is started. At timings T2, T4, T6 and T8, data R0, R1, R2 and R3 are sequentially written from the LINK circuit 6 to the single port memory 27. At timings t2, t3, t4 and t6, data A0, A1, A2 and A3 are sequentially written from the asynchronous transmission DMA controller 4 to the asynchronous transmission FIFO memory 23. Then, at timings T5, T9, T11 and T13, the data R0, R1, R2 and R3 are sequentially written from the single port memory 27 to the reception FIFO memory 21. At timings T3, T7, T10, and T12, data A0, A1, A2, and A3 are sequentially written from the asynchronous transmission FIFO memory 23 to the single port memory 27. Then, at timings t20, t23, t24, and t26, the data R0, R1, R2, and R3 are sequentially read from the receiving FIFO memory 21 to the receiving DMA controller 2. Then, at timings T14, T15, T16 and T17, the LINK circuit 6 sequentially reads the data A0, A1, A2 and A3 from the single port memory 27.
[0085]
FIG. 23 shows a timing chart when the synchronous transmission and the asynchronous transmission are mixed in the 3-port FIFO storage device 5 of the present embodiment. In this timing chart, the operation starts when the read / write block for asynchronous transmission is specified from the address “00h” of the block B01, and the read / write block for asynchronous transmission is specified from the address “00h” of the block B02. It is an embodiment when the operation is started. At timings t2, t3 and t5, the data I0, I1 and I2 are sequentially written from the synchronous transmission DMA controller 3 to the synchronous transmission FIFO memory 22. At timings t4, t5, t6 and t8, data A0, A1, A2 and A3 are sequentially written from the asynchronous transmission DMA controller 4 to the asynchronous transmission FIFO memory 23. At timings T3, T5 and T7, the data I0, I1 and I2 are sequentially written from the synchronous transmission FIFO memory 22 to the single port memory 27. At timings T4, T6, T8 and T12, data A0, A1, A2 and A3 are sequentially written from the asynchronous transmission FIFO memory 23 to the single port memory 27. Then, at timings T9, T10, and T11, the LINK circuit 6 sequentially reads the data I0, I1, and I2 from the single port memory 27. Then, at timings T14, T15, T16 and T17, the LINK circuit 6 sequentially reads the data A0, A1, A2 and A3 from the single port memory 27.
[0086]
FIG. 24 is a timing chart when reception, synchronous transmission, and asynchronous transmission are mixed in the 3-port FIFO storage device 5 of the present embodiment. In this timing chart, the operation starts when the read / write block for reception is specified from the address “00h” of the block B00, and the operation starts when the read / write block for asynchronous transmission is specified from the address “00h” of the block B01. Is started, and the operation is started when the read / write block for asynchronous transmission is designated from the address “00h” of the block B02. At timings T2, T4, and T6, data R0, R1, and R2 are sequentially written to the single-port memory 27 from the LINK circuit. At timings t2, t3 and t4, data I0, I1 and I2 are sequentially written from the synchronous transmission DMA controller 3 to the synchronous transmission FIFO memory 22. At timings t4, t5, and t6, the data A0, A1, and A2 are sequentially written from the asynchronous transmission DMA controller 4 to the asynchronous transmission FIFO memory 23. Then, at timings T5, T9, and T12, the data R0, R1, and R2 are sequentially written from the single port memory 27 to the reception FIFO memory 21. At timings T3, T8 and T11, the data I0, I1 and I2 are sequentially written from the synchronous transmission FIFO memory 22 to the single port memory 27. At timings T7, T10, and T16, data A0, A1, and A2 are sequentially written from the asynchronous transmission FIFO memory 23 to the single port memory 27. Then, at timings t20, t21, and t22, the data R0, R1, and R2 are sequentially read from the reception FIFO memory 21 to the reception DMA controller 2. Then, at timings T13, T14, and T15, the LINK circuit 6 sequentially reads the data I0, I1, and I2 from the single port memory 27. After timing T18 (not shown), the LINK circuit 6 sequentially reads the data A0, A1, A2, and A3 from the single port memory 27.
[0087]
As described above, according to the present embodiment, in a data transfer device that temporarily stores data for transmission or reception in a storage device such as the single port memory 27 and then transfers the data, In response to a transmission data write request signal ITXFWREQB or ATXFWREQB when data is transferred and transmitted, and selects one unused block from the plurality of blocks. Then, the selected block is put into a use state, and the transmission data is written to the selected block, read and transferred, and in response to the reception data write request signal RXFRREQB when the data is transferred and received. Selecting one unused block from the plurality of blocks and setting the selected block as a use state. , Controls the reception data to forward reading after writing to the selected block. Accordingly, one storage device can be used for receiving most of the storage area when there are many received packets, and most of the storage area can be used for transmitting when there are many packets for transmission. It can be processed as if the capacity that can be used as a storage device for trust and reception is apparently increased, that is, the storage device can be used effectively and efficiently, and the processing capability as the storage device is improved. .
[0088]
Further, if the same processing capacity as in the case of having a plurality of FIFO storage devices as in the prior art is sufficient, the memory capacity of one FIFO storage device 5 according to the present embodiment is changed to the maximum capacity of the conventional plurality of FIFO storage devices. It is possible to reduce the size. That is, the memory capacity of the FIFO memory device 5 occupying a large gate as a transfer device can be greatly reduced. In other words, the same operation as the related art can be obtained by reducing the memory capacity of the FIFO storage device 5.
[0089]
Further, the scale of the additional circuit from the prior art for realizing the data transfer device according to the present embodiment is approximately 3000 gates of the entire block controller 35 of FIG. 9 and the timing controllers 31, 32, and 30 shown in FIGS. 26 is obtained by subtracting about 600 gates of the counter configuration example of the conventional timing controllers 124, 133 and 143 shown in FIG. 26 from about 900 gates of the 33 counter configuration example. That is, only a slight increase of about 3300 gates. That is, in order to improve the processing capacity, only a circuit increase of about 3300 gates is required, and if the processing capacity is the same, a circuit increase of about 3300 gates is required. Since the occupied FIFO memory device can be greatly reduced, the overall circuit size can be largely reduced.
[0090]
In the data transfer device, the control unit preferably selects a next block for writing data following the selected block when selecting one unused block among the plurality of blocks. The selected next block is reserved for use. Therefore, it is possible to reliably secure the next block for writing data following the selected block and shift to the data writing operation of the next block.
[0091]
In this case, if there is no write area of the block currently being written, the process proceeds to the next write block, but the write process cannot be performed unless the next write block of the next write block is allocated. For example, the writing process is stopped at timings T5 to T6 in FIG. 20 of the FIFO storage device 5 for transmission according to the present embodiment. However, since the FIFO memory device 5 for reception of the present embodiment is configured as described above, the write process can be continuously executed even when the current write block area runs out as shown at the timing T5 in FIG. In addition, the process can be continuous.
[0092]
In the above embodiment, the FIFO timing controller 28 for controlling the operation of the single port memory 27 is constituted by a hardware circuit. However, the present invention is not limited to this, and a computer executed by a digital signal processor (DSP) It may be constituted by a program which can be read by. That is, the step of controlling the single port memory 27 of the FIFO timing controller 28 can be represented by a computer-readable program, and the program is stored in a CD-ROM, a CD-R, a CD-RW, a DVD, a DVD-R. , A DVD-RW, a DVD-RAM, or other optical disk, or other computer-readable recording medium. As a result, it is possible to reduce the use amount of the memory area or to improve the processing capacity in the data transfer device operated by software.
[0093]
【The invention's effect】
As described above in detail, according to the data transfer device or the data transfer method of the present invention, in a data transfer device that temporarily stores data for transmission or reception in a storage device and then transfers the data, In response to a transmission data write request signal when data is transferred and transmitted, one unused block is selected from the plurality of blocks and the block is selected. The selected block is put into a use state, the transmission data is written to the selected block, read and transferred, and in response to a reception data write request signal when the data is transferred and received, the plurality of transmission data are written. One unused block is selected from the blocks, the selected block is used, the reception data is written to the selected block, and then read. Controls so as to feed. Accordingly, one storage device can be used for receiving most of the storage area when there are many received packets, and most of the storage area can be used for transmitting when there are many packets for transmission. It can be processed as if the capacity that can be used as a storage device for trust and reception is apparently increased, that is, the storage device can be used effectively and efficiently, and the processing capability as the storage device is improved. .
[0094]
In the data transfer device or the data transfer method, preferably, when selecting one unused block among the plurality of blocks, a next block for writing data following the selected block is preferably used. Is selected to secure the selected next block as a use state. Therefore, it is possible to reliably secure the next block for writing data following the selected block and shift to the data writing operation of the next block.
[0095]
Further, in the data transfer device or the data transfer method, preferably, the data transfer device or the data transfer method further includes first register means provided corresponding to each of the blocks and storing an address of a next block. Therefore, it is possible to reliably indicate the next block for writing data following the selected block and shift to the data writing operation of the next block.
[0096]
Further, in the data transfer device or the data transfer method, preferably, a second register is provided corresponding to each of the blocks and stores data indicating whether an address of a next block is selected and secured. Means are further provided. Therefore, information as to whether or not the next block for writing data following the selected block is secured can be obtained, and the process can proceed to the data writing operation of the next block.
[0097]
In the data transfer device or the data transfer method, preferably, when reading out data from the block, the control unit releases the block as an unused state. Therefore, by reliably releasing the blocks that are no longer used, the storage device can be used effectively and efficiently.
[0098]
Further, in the data transfer device or the data transfer method, preferably, the data transfer apparatus or the data transfer method further includes a third register unit that is provided corresponding to each of the blocks and stores data indicating whether each of the blocks is in use. It is characterized by having. Therefore, it is possible to obtain information as to whether or not a block to be written in the storage device is in use, and search for the next block can be executed easily and at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an IEEE 1394 interface device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of the 3-port FIFO storage device of FIG.
FIG. 3 is a diagram for explaining a data storage method using the single port memory 27 of FIG. 2;
FIG. 4 is a diagram showing an initial state when receiving FIFO data, synchronous transmission FIFO data, and asynchronous transmission FIFO data are stored in the single port memory 27 of FIG. 3;
FIG. 5 is a diagram showing a state when a packet is received in the single port memory 27 of FIG. 4;
6 is a diagram for explaining a method of processing a packet received in the single port memory 27 of FIG.
FIG. 7 is a diagram for explaining a method of preparing for synchronous transmission of a packet in the single port memory 27 of FIG. 5;
FIG. 8 is a block diagram showing a detailed configuration of a FIFO timing controller 28 of FIG. 2;
FIG. 9 is a block diagram showing a detailed configuration of a block controller 35 of FIG. 8;
FIG. 10 is a block diagram showing a detailed configuration of a reception timing controller 31 of FIG. 8;
11 is a block diagram showing a detailed configuration of the synchronous transmission timing controller 32 of FIG. 8;
FIG. 12 is a block diagram showing a detailed configuration of an asynchronous transmission timing controller 33 of FIG. 8;
FIG. 13 is a timing chart showing an initial state of each signal in the block controller 35 of FIG. 8;
FIG. 14 is a timing chart showing signals at the time of reception in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 15 is a timing chart showing signals at the time of synchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 16 is a timing chart showing signals at the time of asynchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 17 is a timing chart showing signals at the time of reception in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 18 is a timing chart showing signals at the time of synchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 19 is a timing chart showing signals at the time of asynchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
20 is a timing chart showing signals at the time of reception in the three-port FIFO storage device 5 of FIG. 1;
21 is a timing chart showing signals at the time of reception and synchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 22 is a timing chart showing signals at the time of reception and asynchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
FIG. 23 is a timing chart showing signals at the time of synchronous transmission and asynchronous transmission in the 3-port FIFO storage device 5 of FIG. 1;
24 is a timing chart showing signals at the time of reception, synchronous transmission, and asynchronous transmission in the three-port FIFO storage device 5 of FIG. 1;
FIG. 25 is a block diagram showing the configuration of a conventional IEEE 1394 interface device.
26 is a block diagram showing a detailed configuration of the receiving FIFO storage device 105, the synchronous transmission FIFO storage device 106, and the asynchronous transmission FIFO storage device 107 of FIG.
27 (a), (b) and (c) are block diagrams showing a detailed configuration of the timing controllers 124, 133 and 144 of FIG. 26, respectively.
[Explanation of symbols]
1: PCI interface controller,
2 ... DMA controller for reception,
3 ... DMA controller for synchronous transmission,
4: DMA controller for asynchronous transmission
5 ... 3-port FIFO storage device,
6 ... LINK circuit,
7 ... PHY circuit,
10 ... IEEE1394 interface device,
11 ... RAM,
12 ... CPU,
13. Personal computer,
21: FIFO memory for reception,
22: FIFO memory for synchronous transmission,
23: FIFO memory for asynchronous transmission,
24, 25, 26, 43 to 46 ... multiplexer,
27 ... Single port memory,
28 ... Timing controller,
31 ... Reception timing controller
32 ... Synchronous transmission timing controller,
33 ... Asynchronous transmission timing controller
34 ... data selection controller
35 ... Block controller,
41 ... Block access controller,
42 ... 32-bit priority encoder,
51, 53, 54, 55, 56, 57 ... 6-bit up counter,
52 2-bit synchronous up / down counter,
B1 ... IEEE 1394 bus,
B2: PCI bus,
B00NXPT to B31NXPT, B00NOK to B31NOK, B00USE to B31USE, RRDBPTR, RWRBPTR, IRDBPTR, IWRBPTR, ARDBPTR, AWRBPTR, RWRNBPTR, IWRNBBPTR, AWRNBPTR ... registers,
B00 to B31 ... block,
AND1 to AND5 ... AND gate,
OR1 to OR7 ... OR gate,
NAND1 to NAND10: NAND gate,
N1 to N7 ... inverters
F1 to F5: flip-flops.

Claims (13)

In a data transfer device that temporarily stores data for transmission or reception in a storage device and then transfers the data, the storage device is divided into a plurality of blocks of a predetermined same unit, and data is transferred and transmitted. In response to the transmission data write request signal, one unused block is selected from the plurality of blocks, the selected block is used, and the transmission data is written to the selected block and then read. In response to a data write request signal for reception when data is transferred and received, one of the plurality of blocks is selected and the selected block is set to a use state. A data transfer device comprising: a control unit that controls reception data to be written to the selected block, read out, and transferred. When selecting one unused block from among the plurality of blocks, the control means selects a next block for writing data following the selected block, and sets the selected next block in a use state. The data transfer device according to claim 1, wherein the data transfer device is secured. 3. The data transfer device according to claim 2, further comprising first register means provided corresponding to each of said blocks and storing an address of a next block. 4. The apparatus according to claim 2, further comprising second register means provided for each of said blocks and storing data indicating whether an address of a next block is selected and secured. A data transfer device according to claim 1. 5. The data transfer device according to claim 1, wherein the control unit releases the block as an unused state when reading data from the block. 6. The apparatus according to claim 1, further comprising a third register provided in correspondence with each of said blocks and storing data indicating whether each of said blocks is in use. The data transfer device according to one. In a data transfer method in which data for transmission or reception is temporarily stored in a storage device and then transferred, the storage device is divided into a plurality of blocks of a predetermined same unit, and data is transferred and transmitted. In response to the transmission data write request signal, one unused block among the plurality of blocks is selected, the selected block is used, and the transmission data is written to the selected block and then read. In response to a reception data write request signal when data is transferred and received, one of the plurality of blocks is selected and an unused block is set to a use state. Controlling the writing of the receiving data into the selected block, and then reading and transferring the data. The step of controlling includes, when selecting an unused block among the plurality of blocks, selecting a next block for writing data following the selected block and using the selected next block 8. The data transfer method according to claim 7, wherein the state is secured. 9. The data transfer method according to claim 8, further comprising the step of storing an address of a next block in first register means provided for each of said blocks. 9. The method according to claim 8, further comprising the step of storing data indicating whether or not the address of the next block is selected and secured in the second register means provided for each of the blocks. Or the data transfer method according to 9. 11. The data transfer method according to claim 7, wherein in the controlling step, when data is read from the block, the block is released as an unused state. 12. The method according to claim 7, further comprising the step of storing data indicating whether or not each of the blocks is in use in a third register provided for each of the blocks. The data transfer method according to any one of the above. A program including a computer-readable data transfer method, comprising the data transfer method according to any one of claims 7 to 12.

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