JP2004045879A - Display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus which imports an image with high resolution and high accuracy. <P>SOLUTION: The display apparatus is equipped with a pixel array part 1 where signal lines and scanning lines are laid, a signal line driving circuit 2 to drive the signal lines, a scanning line driving circuit 3 to drive the scanning lines, a detection circuit 41 and an output circuit 4 to import and output an image, and a sensor controlling circuit 5 to control the sensor for importing an image. As each pixel is provided with a plurality of sensors 12a, 12b to import an image, the image are imported with high resolution. Because the image data imported by the sensors 12a, 12b is stored in a buffer 13, the quantity of light accepted by photodiodes D1, D2 is accurately detected. Further, as an array substrate 21, a counter substrate 24 and a backlight 23 are arranged in this order, the intensity of the reflected light from a paper surface 22 is accurately detected by the photodiodes D1, D2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device having an image capturing function.
[0002]
[Prior art]
The liquid crystal display device includes an array substrate on which signal lines, scanning lines, and pixel TFTs are arranged in rows, and a driving circuit that drives the signal lines and scanning lines. With the recent advancement and development of integrated circuit technology, a process technology for forming a part of a drive circuit on an array substrate has been put to practical use. As a result, the entire liquid crystal display device can be made lighter, thinner and smaller, and is widely used as a display device for various portable devices such as a mobile phone and a notebook computer.
[0003]
By the way, there has been proposed a display device in which a close contact type area sensor for capturing an image is arranged on an array substrate (see JP-A-2001-292276 and JP-A-2001-339640).
[0004]
[Problems to be solved by the invention]
However, in this type of conventional display device, one photodiode is provided for each pixel, and the resolution of the scanner is low, so that the image is coarse and the utility is poor.
[0005]
In addition, polysilicon TFTs widely used as driving TFTs for liquid crystal display devices are technically difficult to make electrical characteristics uniform, and it is difficult to A / D convert sensor outputs with high accuracy. .
[0006]
In addition, since the distance between the sensor and the paper surface to be captured is 1.1 mm, which is the sum of the glass thickness of 0.7 mm and the optical film thickness of 0.4 mm, diffused light on the paper surface enters the adjacent sensor. It causes noise.
[0007]
The present invention has been made in view of such a point, and an object of the present invention is to provide a display device capable of capturing images with high resolution and high accuracy.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a display element formed near each intersection of a signal line and a scanning line arranged in rows and columns, and a plurality of display elements corresponding to each of the display elements. A sensor that receives incident light in different ranges and accumulates charges according to the amount of light received, the sensor includes: a photoelectric conversion unit that outputs an electric signal according to the amount of received light; A charge accumulating unit that accumulates the corresponding charge, an initialization control unit that switches whether or not to accumulate the initial charge in the charge accumulating unit, and whether to output a signal corresponding to the accumulated charge of the charge accumulating unit. And an output control unit for switching.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings.
[0010]
(1st Embodiment)
FIG. 1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention, showing a configuration on an array substrate. The display device shown in FIG. 1 includes a pixel array section 1 in which signal lines and scanning lines are arranged in a row, a signal line driving circuit 2 for driving signal lines, a scanning line driving circuit 3 for driving scanning lines, and an image capturing device. And a sensor control circuit 5 for controlling an image capturing sensor.
[0011]
FIG. 2 is a block diagram showing a part of the pixel array unit 1 in detail. The pixel array unit 1 in FIG. 2 includes a pixel TFT 11 formed near each intersection of a signal line and a scanning line arranged vertically and horizontally, a liquid crystal capacitor C1 connected between one end of the pixel TFT 11 and a Cs line, and It has an auxiliary capacitor C2 and two image capture sensors 12a and 12b provided for each pixel TFT 11. The sensors 12a and 12b are connected to a power line and a control line (not shown).
[0012]
FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail. As shown in FIG. 3, the sensors 12a and 12b have photodiodes D1 and D2 and sensor switching transistors Q1 and Q2, respectively. The photodiodes D1 and D2 output an electric signal according to the amount of received light. The sensor switching transistors Q1 and Q2 alternately select one of the plurality of photodiodes D1 and D2 in one pixel.
[0013]
Each pixel includes two sensors 12a and 12b, a capacitor C3 shared by the two sensors 12a and 12b in the same pixel, a buffer 13 for storing binary data corresponding to the charge stored in the capacitor C3, and a buffer 13 And a reset transistor Q4 for initializing the buffer 13 and the capacitor C3.
[0014]
The buffer 13 is composed of a static RAM (SRAM), for example, as shown in FIG. 4, two inverters IV1 and IV2 connected in series, an output terminal of the succeeding inverter IV2, and an input terminal of the preceding inverter IV1. And an output transistor Q6 connected to the output terminal of the subsequent inverter.
[0015]
When the signal SPOLB is at a high level, the transistor Q5 is turned on, and the two inverters IV1 and IV2 perform a holding operation. When the signal OUTi is at a high level, the held data is output to the detection line.
[0016]
The display device of the present embodiment can perform a normal display operation, and can also perform image capture similar to a scanner. When a normal display operation is performed, the transistor Q3 is turned off, and no valid data is stored in the buffer 13. In this case, a signal line voltage is supplied from the signal line driving circuit 2 to the signal line, and display according to the signal line voltage is performed.
[0017]
On the other hand, when performing image capture, an image capture target (for example, a paper surface) 22 is disposed on the upper surface side of the array substrate 21 as shown in FIG. 5, and light from the backlight 23 is transmitted to the opposing substrate 24 and the array substrate 21. And irradiate the paper surface 22 via. The light reflected on the paper surface 22 is received by the sensors 12a and 12b on the array substrate 21, and an image is captured. The captured image data is stored in the buffer 13 and then sent to a CPU (not shown) via a detection line. The CPU receives digital signals output from the display device of the present embodiment and performs arithmetic processing such as rearranging data and removing noise in data. Note that the CPU may be constituted by one semiconductor chip or a plurality of semiconductor chips.
[0018]
FIG. 6 is an operation timing chart at the time of image capture. First, since the signals PAR of the sensors 12a and 12b are at a high level, the left transistor in one pixel is selected.
[0019]
Next, from time t1 to t2 in FIG. 6, the pixel array unit 1 is sequentially driven row by row, and all pixels are set to the same color (for example, white).
[0020]
Next, at time t3, the signals RST, SPOLA, and SPOLB are all set to the high level, and all the transistors Q3, Q4, and Q5 are turned on. As a result, initial values are set in the buffer 13 and the capacitor C3.
[0021]
When the signal RST goes low (time t4), the sensors 12a and 12b start capturing images. When the light reflected from the paper surface 22 is received by the photodiodes D1 and D2 in the sensors 12a and 12b, the charge stored in the capacitor C3 flows to the ground terminal GND through the photodiodes D1 and D2. That is, a leak current flows. As a result, the charge stored in the capacitor C3 decreases.
[0022]
At time t5, the signal SPOLA goes high, and the binary data corresponding to the charge stored in the capacitor C3 is stored in the buffer 13.
[0023]
Thereafter, at time t6, the signal SPOLB goes high, and the buffer 13 starts the holding operation. Thereafter, at time t7, the data stored in the buffer 13 is sequentially supplied to the detection line for each pixel and sent to a CPU (not shown).
[0024]
In FIG. 6, the reason why the buffer 13 is provided for each pixel is as follows. The accumulated charge of the capacitor C3 leaks not only by the current flowing through the photodiodes D1 and D2 in the sensors 12a and 12b, but also by the current flowing through the TFT in the pixel. Therefore, the accumulated charge of the capacitor C3 decreases with time, and the voltage across the capacitor C3 also decreases. Therefore, if the buffer 13 is provided for each pixel and the charge stored in the capacitor C3 is transferred to the buffer 13 before it leaks, the image can be captured without being affected by the leak of the capacitor C3.
[0025]
The reason why the SRAM is used as the buffer 13 is that the SRAM does not cause a malfunction such as logical inversion even when irradiated with light of several hundred thousand lux.
[0026]
After time t8, the sensor switching signal PAR becomes low level, and switches between the sensors 12a and 12b to capture an image.
[0027]
Each component formed on the array substrate 21 of the present embodiment is formed using an n-channel TFT and a p-channel TFT.
[0028]
FIG. 7 is a manufacturing process diagram of an n-channel TFT, and FIG. 8 is a manufacturing process diagram of a p-channel TFT. First, an undercoat layer made of SiNx, SiOx, or the like is formed on a glass substrate 31 by a CVD method. The reason for forming the undercoat layer is to prevent impurities from diffusing into elements formed on the glass substrate 31.
[0029]
Next, after an amorphous silicon film is formed on the glass substrate 31 by a PECVD method, a sputtering method, or the like, the amorphous silicon film is irradiated with a laser to be crystallized, thereby forming a polycrystalline silicon film 32.
[0030]
Next, after patterning the polycrystalline silicon film 32, a first insulating layer 33 made of a SiOx film formed by a PECVD method or an ECR-CVD method is formed. Then, low-concentration boron is implanted into predetermined portions of the polycrystalline silicon film 32 (FIGS. 7A and 8A).
[0031]
Next, phosphorus is ion-implanted into a predetermined portion using the resist 34 as a mask (FIGS. 7B and 8B). Next, using the resist or the like 34 as a mask, boron is ion-implanted into a portion where the n-channel TFT is to be formed (FIG. 7C).
[0032]
Next, a first metal such as Mo-Ta or Mo-W is deposited and patterned to form a gate electrode 35. Next, using the resist or the like 34 as a mask, phosphorus ions are implanted into the formation location of the n-channel TFT by ion implantation (FIG. 7D), and boron ions are implanted into the formation location of the p-channel TFT (FIG. 8 (c)).
[0033]
Next, low-concentration phosphorus is ion-implanted into a portion where the p-channel TFT is to be formed using the resist 34 as a mask (FIG. 8D).
[0034]
Next, after a second insulating layer 36 of SiOx is formed, a contact hole for forming an electrode is opened, a second metal 37 is formed, and the source / drain electrodes are patterned (FIG. 7 ( e), FIG. 8 (e)). Finally, a SiN film is formed as a passivation film to complete an n-channel TFT and a p-channel TFT.
[0035]
The photodiodes D1 and D2 in the sensors 12a and 12b shown in FIG. 2 preferably have a PIN structure including a p ⁺ layer, a p ⁻ layer, an n ⁻ layer, and an n ⁺ layer. This is because the PIN structure has a wide depletion layer and good light-current conversion efficiency.
[0036]
FIG. 9 is a manufacturing process diagram of the photodiodes D1 and D2 having the PIN structure. First, after the first insulating layer 33 is formed on the glass substrate 31, low-concentration boron is ion-implanted on the upper surface thereof to form ap ⁻ layer (FIG. 9A).
[0037]
Next, phosphorus is ion-implanted using the resist 34 as a mask to form an n ⁺ layer in a part of the first insulating layer 33 (FIG. 9B). Next, boron ions are implanted using the resist 34 as a mask to form ap ⁺ layer in a part of the first insulating layer 33 (FIG. 9C).
[0038]
Next, after the first metal to be the gate electrode 35 is formed, low-concentration phosphorus is ion-implanted using the resist 34 as a mask (FIG. 9D). Next, a contact hole is formed by forming a second insulating layer 36, and a second metal 37 is formed in a predetermined shape (FIG. 9E).
[0039]
In the display device of the present embodiment, as shown in FIG. 5, an opposing substrate 24 is arranged between an array substrate 21 and a backlight 23. The reason is that if the array substrate 21 is arranged between the counter substrate 24 and the backlight 23 as shown in FIG. 10, all the elements formed on the array substrate 21 directly receive the light from the backlight 23. At the same time, the intensity of the reflected light from the paper surface 22 is weakened, and the intensity of the reflected light cannot be accurately detected. On the other hand, in the case of the present embodiment, as shown in FIG. 11, the direct light from the backlight 23 can be blocked by the first and second metals 37 on the array substrate 21 and the reflected light from the paper surface 22 can be blocked. Only the light can enter the polysilicon layer.
[0040]
The internal configuration of the sensors 12a and 12b is not limited to the circuit shown in FIG. FIG. 12 is a diagram showing a modification of the internal configuration of the sensors 12a and 12b. Type-A has a circuit configuration similar to that of FIG. 3, and leaks the charge accumulated in the capacitor C3 to the ground terminal VSS1 via the photodiode D1 that has received light.
[0041]
Type-B is a type that, contrary to Type-A, causes a current to flow from the photodiode D1 that has received light to the capacitor C3 to accumulate charges.
[0042]
Type-C is a device that causes a current to flow from the photodiode D1 that has received light to the capacitor C3 to accumulate charges, and when no light is received, charges are slowly leaked from the capacitor C3 via the biasing transistor Q7. .
[0043]
Type-E is for extracting a voltage corresponding to the intensity of light.
[0044]
As described above, in the present embodiment, since a plurality of sensors 12a and 12b are provided for each pixel to capture an image, it is possible to capture an image at a high resolution. In addition, since the image data captured by the sensors 12a and 12b is stored in the buffer 13, the amount of light received by the photodiodes D1 and D2 can be accurately detected.
[0045]
Further, since the array substrate 21, the counter substrate 24 and the backlight 23 are arranged in this order, the direct light from the backlight 23 is not incident on the photodiodes D1 and D2, and the intensity of the reflected light from the paper surface 22 is reduced by the photodiodes D1 and D1. D2 enables accurate detection.
[0046]
FIG. 2 illustrates an example in which two sensors 12a and 12b are provided for one pixel. However, the number of sensors 12a and 12b is not limited to two, and may be three or more. As the number of sensors 12a and 12b increases, the resolution at the time of image capture can be increased.
[0047]
(Second embodiment)
In the second embodiment, a detection circuit for performing A / D conversion is provided instead of the buffer.
[0048]
FIG. 13 is a block diagram showing a schematic configuration of the second embodiment of the display device. The display device of FIG. 13 includes a detection circuit 41 for performing A / D conversion instead of the buffer, as can be seen from the comparison with FIG. 3, and the accumulated charge of the capacitor C3 is transmitted through the transistor Q3 and the detection line. It is supplied to the detection circuit 41. The detection circuit 41 is provided on a frame portion of the array substrate.
[0049]
With the configuration as shown in FIG. 13, the number of elements in a pixel is reduced. In a display device, such as a transmissive liquid crystal display device, which has a light source on the back surface and controls the display element in each pixel to control the brightness of each pixel to perform display, the ratio of the area of the pixel opening (aperture ratio) Can be increased and the luminance of the light source can be made relatively low, so that the power consumption of the light source can be reduced.
[0050]
Also, when considering the operation as a contact sensor, the light from the light source is effectively not reflected by the elements in the pixels but reaches and reflects on the imaging target effectively. Power consumption of the light source can be reduced.
[0051]
If no buffer is provided in the pixel, the signal of the sensor must be transmitted to the A / D conversion circuit provided in the frame portion via the detection line. The capacitance of the sensor output holding capacitor C3 provided in the pixel is at most about 1 pF due to restrictions on securing an aperture ratio, and the capacitance Cout of the detection line is, for a display device, a pixel electrode or other element / wiring electrode. It is about 20 pF due to capacitive coupling (in the case of 4 "QVGA).
[0052]
If 5 V is temporarily stored in the capacitance of 1 pF in the pixel, the amplitude becomes extremely weak as soon as the voltage is guided to the capacitance Cout of the detection line of 20 pF. The magnitude is about C3 / (C3 + Cout) of the original signal amplitude so that it can be easily estimated by the law of conservation of charge. In this case, it is estimated that the amplitude becomes 1 [pF] / (1 [pF] +20 [pF]), which is less than 5% of the original signal amplitude. Therefore, it is necessary that the A / D conversion circuit in the frame part can amplify a minute potential difference to a clear potential difference.
[0053]
However, unlike a transistor circuit formed on a silicon substrate, an LTPS element (Low Temperature Poly-Si element) formed on an insulating substrate by using a low-temperature polysilicon process has the same element characteristics even on the same chip. Vth variation may be about 1V. For this reason, a differential circuit (operational amplifier) often used in an A / D conversion circuit on a silicon substrate cannot be used as it is, and an A / D conversion circuit having means for compensating for Vth variation is required. This is because if an operational amplifier is used normally, a certain sensor output potential is converted to a high level by a certain detection circuit and is converted to a low level by another detection circuit due to a variation in Vth of the element, which is not practical. .
[0054]
Hereinafter, a detection circuit including an A / D conversion circuit having Vth variation compensation means particularly effective when integrally formed on an array substrate of a display device using an LTPS element will be described.
[0055]
FIG. 14 is a circuit diagram showing a detailed configuration of the detection circuit 41. The detection circuit 41 of FIG. 14 includes, for each detection line, the transistors Q7 and Q8, the amplifier 42 including the capacitor C4 and the inverter IV1, the inverter IV2, the latch 43, the transistor Q9, the transistor Q10, and the register circuit 44. And a shift register 45.
[0056]
The signal / PRC is input to all the gates of the transistor Q7, and the signal PRC is input to all the gates of the transistor Q8. First, the signal PRC is set to a high level for a predetermined period. As a result, the transistor Q8 turns on, and the input terminal of the amplifier 42 is initialized to the voltage VPRC. The voltage VPRC is set to a voltage between a detection line voltage when a high-level output of the sensor is led to the detection line and a detection line voltage when a low-level output of the sensor is led to the detection line. You. The switch SW1 is connected between the input and output terminals of the inverter IV1 in the amplifier 42, and when the voltage PRC is at a high level, the switch SW1 is turned on. Therefore, the input terminal of the inverter IV1 (= below the capacitor element C4) End) holds the operation threshold value of the inverter. At this time, the amplifier 42 does not perform the amplification operation. This operation cancels Vth. Even if Vth varies, the operation threshold of the inverter IV1 is held at the input terminal of the inverter IV1.
[0057]
Next, when the signal / PRC is set to the high level (the signal PRC is set to the low level), whether or not the voltage of the detection line is higher than the voltage VPRC is directly applied to the input terminal of the inverter IV1 via the capacitor element C4. And an inverted amplified output is reliably output to the output terminal of the inverter IV1. In this way, A / D conversion is performed reliably even when the Vth variation is about 1 V.
[0058]
Thereafter, the latch 43 performs a latch operation at a predetermined timing. Thereafter, when the signal A goes high, the output of the latch 43 is written to each register circuit 44 of the shift register 45. Thereafter, when the signal A goes low, the transistor Q10 is turned on, the register circuits 44 are cascade-connected, and the data is shifted right by one step by one step in synchronization with the clock CLK, and transmitted from the rightmost register circuit 44 to the CPU. Supplied.
[0059]
In some cases, the latch 43 can be omitted. What is necessary is just to guide | induce the output of a detection line to the shift register 45 directly. However, it is necessary to supply the output of the detection line to the shift register 45 at the right timing when the shift register 45 has finished outputting data to the CPU. This is to prevent the output of the detection circuit 41 from changing until the data is completely stored in the shift register 45.
[0060]
On the other hand, when the latch 43 is provided as shown in FIG. 14, the output of the A / D conversion can be kept in the latch 43 regardless of the operation of the shift register 45, and the next detection operation can be started immediately. There is an advantage that can be.
[0061]
In FIG. 14, the amplifier 42 is composed of one capacitor C4 and one inverter IV1. However, as shown in FIG. 15, a plurality of capacitors C4 and inverters IV1 may be cascaded. Thereby, the accuracy of the gain control of the amplifier 42 can be improved. The larger the number of cascade connections, the smaller the minimum amplitude of the A / D-convertible detection line can be, and the higher the sensitivity of the A / D converter can be.
[0062]
As described above, in the second embodiment, since the detection circuit 41 provided in the frame portion of the array substrate performs A / D conversion of the accumulated charge of the capacitor C2, it is not necessary to provide a buffer in the pixel, and the pixel is not required. The structure can be simplified, and the resolution of the sensor can be improved accordingly.
[0063]
FIG. 13 illustrates an example in which the buffer is not provided in the pixel array unit and the detection circuit 41 is provided in the frame portion of the array substrate. However, a buffer similar to that in FIG. 3 may be provided in the pixel array unit. As a result, A / D conversion is performed twice, but the output amplitude of the buffer can be reduced, so that power consumption can be reduced.
[0064]
That is, in the case of the display device, the detection line is capacitively coupled to the display pixel electrode and the like as described above, and thus becomes a large driving load for the buffer. The power consumption for driving the detection line can be expressed as Cout × fout × Va × Va, where Cout is the capacitance of the detection line, fout is the frequency at which the detection line is driven, and Va is the amplitude of the detection line. Therefore, reducing Va to such a degree that the detection circuit can determine it is effective for reducing power consumption. For example, when the detection line is driven with a 5 V amplitude, when the detection line is driven with a 1 V amplitude, the power consumption for driving the detection line of the buffer unit is reduced by a factor of 25.
[0065]
In FIG. 13 described above, an example in which the detection circuit 41 is provided for each detection line has been described, but the same detection circuit 41 may be shared by a plurality of sensors.
[0066]
FIG. 16 is a circuit diagram of a detection circuit 41a when the same detection circuit 41 is shared by a plurality of detection lines. Compared with the detection circuit 41 of FIG. 14, a detection line selection circuit having transistors Q11 and Q12 connected to different detection lines is newly provided.
[0067]
One of the transistors Q11 and Q12 in the detection line selection circuit is turned on by the logic of the signal KIR, and supplies one of the signals on the two detection lines to the transistor Q7.
[0068]
As described above, by sharing the same detection circuit 41a with a plurality of detection lines, the number of the detection circuits 41a can be reduced, and the occupied area of the frame portion and the power consumption can be reduced.
[0069]
Note that the same detection circuit may be shared by three or more detection lines. As the number of detection lines sharing the same detection circuit increases, the area occupied by the detection circuit and the power consumption can be reduced.
[0070]
In the above-described embodiment, the detection circuit of the contact sensor integrated display device that photoelectrically converts the reflected light of the imaging target into a leak current of an element on an array substrate such as a photodiode has been described. The present invention can be similarly applied even if it does not use. For example, the present invention is also effective as a detection circuit of a sensor that sets the potential between the drain and source electrodes of a TFT element to an appropriate potential and converts whether or not a finger or the like approaches the gate electrode into a drain-source current.
[0071]
【The invention's effect】
As described above in detail, according to the present invention, the amount of charge stored in the charge storage unit is variably controlled according to the electric signal output from the photoelectric conversion unit, so that the amount of light received by the sensor can be accurately detected.
[0072]
Further, according to the present invention, since the A / D converter for A / D converting the amount of light received by the sensor is provided in the frame portion of the insulating substrate, the amount of light received by the sensor can be reduced while simplifying the structure of the pixel display area. Accurate detection is possible.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of a display device according to the present invention.
FIG. 2 is a block diagram showing a part of a pixel array unit in detail.
FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail;
FIG. 4 is a circuit diagram showing an internal configuration of a buffer.
FIG. 5 is a simplified cross-sectional view illustrating a structure of a display device.
FIG. 6 is an operation timing chart at the time of image capture.
FIG. 7 is a manufacturing process diagram of an n-channel TFT.
FIG. 8 is a manufacturing process diagram of a p-channel TFT.
FIG. 9 is a manufacturing process diagram of a photodiode having a PIN structure.
FIG. 10 is a sectional view when the positional relationship between an array substrate and a counter substrate is changed.
FIG. 11 is a sectional view of the embodiment.
FIG. 12 is a diagram showing a modification of the internal configuration of the sensor.
FIG. 13 is a block diagram illustrating a schematic configuration of a second embodiment of the display device.
FIG. 14 is a circuit diagram showing a detailed configuration of a detection circuit 41.
FIG. 15 is a circuit diagram showing a modification of the amplifier.
FIG. 16 is a circuit diagram of a detection circuit when the same detection circuit is shared by a plurality of detection lines.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Signal line drive circuit 3 Scan line drive circuit 4 Detection circuit 41 & output circuit 5 Sensor control circuit 11 Pixel TFT
12a, 12b Sensor 13 Buffer 21 Array substrate 22 Paper surface 23 Backlight 24 Counter substrate 41 Detection circuit 42 Amplifier 43 Latch 45 Shift register

Claims (11)

A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A plurality of sensors provided for each of the display elements, each of which receives a different range of incident light and accumulates a charge corresponding to a received light amount,
The sensor is
A photoelectric conversion unit that outputs an electric signal according to the amount of received light,
A charge accumulation unit that accumulates charge according to the electric signal;
An initialization control unit that switches whether to store the initial charge in the charge storage unit, and an output control unit that switches whether to output a signal corresponding to the charge stored in the charge storage unit. Display device. The initialization control unit, before the operation of the sensor, previously store the initial charge in the charge storage unit,
2. The display device according to claim 1, wherein the photoelectric conversion unit discharges the charge storage unit from the initial charge by an amount corresponding to an amount of light received by the photoelectric conversion unit. 3. The initialization control unit, before the operation of the sensor, previously store the initial charge in the charge storage unit,
2. The display device according to claim 1, wherein the photoelectric conversion unit charges the charge accumulation unit from the initial charge by an amount corresponding to an amount of light received by the photoelectric conversion unit. 3. A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A plurality of sensors provided for each of the display elements, each of which receives a different range of incident light and accumulates a charge corresponding to a received light amount,
The sensor is
A photoelectric conversion unit that outputs an electric signal according to the amount of received light,
A charge accumulation unit that accumulates charge according to the electric signal;
A discharge control unit that continuously discharges the stored charge of the charge storage unit by a predetermined amount,
An output control unit that switches whether to output a signal according to the accumulated charge of the charge accumulation unit,
The display device according to claim 1, wherein the photoelectric conversion unit charges or discharges the charge storage unit only from a charge portion corresponding to an amount of light received by the photoelectric conversion unit from the initial charge. A display element formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A plurality of sensors provided for each of the display elements, each of which receives a different range of incident light and accumulates a charge corresponding to a received light amount,
The sensor is
A plurality of serially connected photoelectric conversion units that output an electric signal according to the amount of received light,
A charge accumulation unit that accumulates charge according to the electric signal;
An initialization control unit that switches whether to store the initial charge in the charge storage unit, and an output control unit that switches whether to output a signal corresponding to the charge stored in the charge storage unit. Display device. A display element constituting a display screen formed near each intersection of signal lines and scanning lines arranged in rows and columns;
A sensor provided in the display screen,
An A / D converter for A / D converting an output signal of the sensor,
The display device, wherein the A / D converter is formed in a frame portion of an insulating substrate on which the signal line and the scanning line, the display element, and the sensor are formed. The A / D converter comprises:
A first transistor, a capacitor, an amplifier, a second transistor, and a shift register connected in series on a detection line for supplying a signal corresponding to the charge stored in the charge storage unit;
The display device according to claim 6, further comprising a third transistor that switches whether to set a voltage of a connection path between the first transistor and the capacitor to a predetermined voltage. The A / D converter turns on the third transistor, stores initial charge in the capacitor, turns on the first transistor, and checks whether an input voltage of the amplifier is higher than an operation threshold value of the amplifier. The display device according to claim 7, wherein A / D conversion is performed depending on whether or not the display is determined. 9. The display device according to claim 7, wherein the amplifier is configured by cascade-connecting a plurality of inverting units each including a capacitor and an inverter connected in series. An output selector that is provided for each of the plurality of display elements and that can select any one of output signals of the sensors corresponding to the plurality of display elements,
The display according to any one of claims 6 to 9, wherein the A / D converter is provided for each of the output selection units, and A / D converts an output of the corresponding output selection unit. apparatus. 7. The display device according to claim 6, wherein the A / D converter includes a sensitivity improving unit configured by cascading a plurality of amplifiers each having an element characteristic compensating unit in a plurality of stages.

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