JP4188987B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to an active matrix type display device in which a display drive circuit is formed on a substrate surface thereof.

  For example, an active matrix type liquid crystal display device includes a gate signal line extending in the x direction and arranged in parallel in the y direction on the liquid crystal side surface of one of the substrates opposed to each other through the liquid crystal. A region surrounded by drain signal lines extending in the y direction and arranged in parallel in the x direction is defined as a pixel region.

  The pixel region includes a thin film transistor that operates when a scanning signal is supplied from one gate signal line, and a pixel electrode that receives a video signal from one drain signal line via the thin film transistor.

  For example, an electric field is generated between the pixel electrode and the counter electrode formed on the other substrate side, and the light transmittance of the liquid crystal between these electrodes is controlled by this electric field.

  Such a liquid crystal display device includes a scanning signal driving circuit that supplies a scanning signal to each of the gate signal lines and a video signal driving circuit that supplies a video signal to each of the drain signal lines.

  In view of the fact that such a scanning signal driving circuit and video signal line driving circuit are composed of a large number of MIS transistors having the same configuration as the thin film transistor formed in the pixel region, the semiconductor layer of each of these transistors is formed of polycrystalline silicon. It is known that the scanning signal driving circuit and the video signal line driving circuit are formed on the one substrate surface in parallel with the formation of the pixels, while being formed of (p-Si).

  The scanning signal driving circuit is a circuit mainly including a shift register, and the video signal line driving circuit also uses a shift register as a part thereof.

As prior art documents related to the invention of the present application, there are the following.
Japanese Examined Patent Publication No. 62-45638

  However, in recent years, there has been a demand for a shift register that can operate at a higher speed with lower voltage and lower power and that does not have a through current. For example, a shift register called a dynamic ratio shift register is used. It was considered.

  This dynamic ratio shift register has a configuration as shown in FIG. 9A as disclosed in, for example, Patent Document 1 described above.

  FIG. 9B is a timing chart of the circuit shown in FIG. 9A, and shows respective outputs VN1 to VN6 at nodes N1 to N6 with respect to the input pulse φIN and the synchronization pulses φ1 and φ2. .

  First, at time t1, when φ1 changes from a low level (hereinafter referred to as “L”) to a high level (hereinafter referred to as “H”), φIN is set to “H”. The potential VN1 changes from “L” to “H”.

  When the input pulse φIN and the synchronization pulses φ1 and φ2 having opposite phases are set to the ground level (GND) and 'H' is set to the threshold VTH <NMT1, the potential of VN1 at this time is approximately As shown in (1).

[Equation 1]
VN1 = Vφ−Vth (1)
Even when φ1 falls from 'H' to 'L' at time t2, since φIN remains H, VN1 holds the voltage of the above equation (1) (strictly speaking, when φ1 falls, NMT1 The potential becomes lower than the voltage of the above formula (1) due to the capacitive coupling between the gate and the node N1, but is ignored because it is not essential for the explanation of the operation. And since NMT1 becomes OFF level, N1 becomes a floating node.

Next, when φ2 changes from 'L' to 'H' at time t2, if the following equation (2) is satisfied,
[Equation 2]
Vφ−Vth ≧ Vφ (2)
NMT2 is turned on, and pulse φ2 enters node N2.

  At this time, due to the coupling capacitor Cb1 called a bootstrap capacitor provided between N1 and N2, the increase of the point pressure of N2 is transmitted to the floating N1, and the potential of N2 also rises.

Assuming that the rising potential of N2 is ΔVN2, VN1 is given by the following equation (3).
[Equation 3]
VN1 = (Vφ−Vth) + ΔVN2 (Cb / Cb (Cb + Cs))
(3)

  Here, in addition to the capacitance shown in the circuit diagram as in the previous Cb1, Cb is a capacitance formed by the gate and drain of NMT2, or an inversion layer (channel) formed under the gate, and the φ2 wiring and N1 Including all the coupling capacitances of φ2 and N1, including the direct connection capacitance. Cs is obtained by subtracting the bootstrap capacitor Cb from all the capacitors of N1, and is called a so-called parasitic capacitor.

Here, if ΔVN2⇒Vφ, the following equation (4) is satisfied:
[Equation 4]
(Vφ−Vth) + Vφ (Cb / Cb (Cb + Cs))> Vφ + Vth
(4)

  This means that the gate voltage of NMT2, that is, VN1, becomes higher than Vφ + Vth, and therefore VN2 becomes the potential of Vφ.

  By appropriately selecting the design element Cb1, it is easy to satisfy the above formula (4), and VN2 can be set to the potential of Vφ.

At the same time, the potential of the node N3 becomes a value represented by the following equation (5) through the diode-connected NMT3.
[Equation 5]
VN3 = Vφ−Vth (5)
Since NMT3 is diode-connected, even if φ2 changes from H to L at time t3, the state of the above equation (5) is maintained.

  When φ1 changes from L to H at time t3, an operation similar to the above equation (3) occurs in N3 and NMT5, and VN3 and VN4 cause a potential change schematically shown in FIG.

  Here, when N2, N4, and N6 are used as output nodes, a shift pulse (VN2, VN4, VN6) having the same potential as that of the synchronization pulse 'H' is obtained, and a through current is applied as apparent from the above operation. Dynamic operation is not accompanied.

  However, when a dynamic ratio register having such a configuration is formed as it is by a MIS transistor having a semiconductor layer made of polycrystalline silicon (p-Si) on the surface of a substrate (glass substrate) opposed to the liquid crystal, it is extremely difficult. It was confirmed that it was operating unstablely, and countermeasures were required.

  That is, the capacitance when the floating nodes such as N1 and N3 are “L” is extremely small, and the synchronous pulse and the drain-gate coupling capacitance of N1 and N3 shown in Cdg1 and Cdg2 of FIG. , Cdg1, Cdg2, etc., and other capacitances of N1, N2 are very small, and there is a high possibility that an unselected transistor will be in the ON state. Will be quite constrained.

  The main causes for the capacitance becoming very small when the floating node is 'L' in a dynamic ratioless shift register comprising a thin film transistor formed on a glass substrate with respect to a single crystal semiconductor are as follows.

  FIG. 10A is a schematic cross-sectional view of an n-type MOS transistor formed on a single crystal semiconductor. A semiconductor integrated circuit having a substrate as a semiconductor is generally used after being biased (including ground) for element isolation or the like.

  For this reason, as shown in FIG. 10A, the depletion layer capacitance Csw, the drain-well depletion layer capacitance Cdw, and the gate-well capacitance due to the reverse bias between the source (diffusion layer) and the well (or substrate). It is capacitively coupled to the well with a capacity of Cgw. The wiring is also capacitively coupled to the substrate or well immediately below by a CLw though a thick insulating film. These are usually called parasitic capacitances.

  Therefore, for example, in the portion of the node N3 shown in FIG. 9A, Csw (Csw3) of NMT3, Cgw (Cgw6), Cdw (Cdw6) of NMT6, Csw (Csw7) of NMT7, and Clw of the wiring forming this node (Clw3) has a large coupling capacity with the well.

  Further, if the bootstrap capacitor has an enhanced MOS capacitor configuration as shown in FIGS. 10B and 10C, an inversion layer extending from a depletion layer serving as another node at the time of ON shown in FIG. Capacitive coupling and an efficient bootstrap effect (boost effect) are obtained. On the other hand, when OFF, the coupling capacitance Cb1 (w) with the well is obtained as shown in FIG.

Therefore, when N3 is “L”, even when the circuit is floating on the circuit of FIG. 9A, a large capacitance is provided between the well and the well via the coupling capacitance. Since the sum of the Cdw (CdW1) of NMT3 and the space capacitance Clφ1 between the wiring of φ1 and N3 is sufficiently small with respect to these capacitances, the potential of N3 when φ1 changes from “L” to “H” The change ΔVN3 is roughly expressed by the following equation (6),
[Equation 6]
ΔVN3 = Vφ × (Cdw + Clφ1) / (Cdw1 + Clφ2 + Csw3 + Cgw6 + Cdw6 + Csw7 + Cb1 (w))
(6)

And as described above, since there is a relationship of the following equation (7),
[Equation 7]
Cdw1 + Clφ2 << Csw3 + Cgw6 + Cdw6 + Csw7 + Cb1 (w)
(7)

It is easy to satisfy the following formula (8).
[Equation 8]
ΔVN3 <Vth (8)
However, when a similar circuit composed of a polycrystalline thin film transistor is formed on a glass substrate, it does not operate as described above.

  10D is a schematic cross-sectional view of a polycrystalline thin film transistor formed on a glass substrate. If the substrate is an insulator, the p layer under the source, drain, or gate is once floating. Capacitances that can be coupled are only depletion layer capacitances Cdp, Csp between the source or drain and the p-layer below the gate, or small space capacitances Csl, Cpl, Cdl with far wires.

  As in the case described above, taking the part of the node N3 of the circuit shown in FIG. 9A as an example, it is capacitively coupled to N2 via the source Csp3 of NMT3. However, since N2 is also floating, N1 is connected via Cb1. And a path for capacitive coupling to φ2 through SP2 of NMT2. Since N1 is also floating, it is divided into a path that is capacitively coupled to φIN via Csp1 of NMT1, and a path that is capacitively coupled to Vss via Csp4 of NMT4 and Csp4 of NMT1.

  That is, both capacities become very small, and the coupling with φ1 works to increase VN3 when φ1 is “L” → “H”.

  The source of NMT7 is capacitively coupled to VSS via Csp7, but this is not significant. N3 is capacitively coupled to N4 via Cb2, but N4 is also floating. The wiring forming the node of N3 does not have a capacitance immediately below, and has only a weak capacitive coupling with any wiring through the space capacitance.

  N3 is φ1 capacitively coupled through Cdg5 of NMT5. This is a direct capacitive coupling with the outside and is relatively large. This capacity causes instability.

  If the total of the other secondary coupling capacities of N3 excluding Cdg5 is CN3, the potential change ΔVN3 of N3 when φ1 changes from “L” to “H” is approximately given by the following equation (9). As described above, since CN3 is not so large, depending on the values of Vφ and Cdg5 (W dimension design of NMT5 and φ1 wiring layout), the condition shown in the following equation (10) easily occurs.

[Equation 9]
ΔVN3 = Vφ × (Cdg5 / (Cdg5 + CN3)) (9)
[Equation 10]
ΔVN3 ≧ Vth (10)

  Once the condition shown in the above equation (10) is satisfied, the Cgp (capacitance with the inversion layer) and the bootstrap capacitance Cb2 of NMT5 are changed to the coupling capacitance between N3 and φ1, conversely, The possibility that the NMT 3 is completely turned on becomes extremely large.

  That is, a node that is not related to the controlling node becomes “H”, and an unstable operation occurs such that an output is generated or scanning starts from that portion.

The present invention has been made based on such circumstances, and an object of the present invention is to provide a display device including a dynamic ratioless shift register that can operate stably and can increase design flexibility.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
Means 1.
The display device according to the present invention includes, for example, a drive circuit including a shift register on a substrate surface thereof, and the shift register includes a MISFT having polycrystalline silicon as a semiconductor layer, and a first terminal of the first MISFT is an input. Connected to the pulse, the gate terminal of the first MISTFT is connected to the first synchronization pulse to form an input, and the second terminal of the first MISTFT is connected to the gate terminal of the second MISTFT and the fourth terminal The first terminal of the first capacitor and the second terminal of the first capacitor are connected to a fixed voltage, and the second terminal of the second MISFT is connected to the first terminal of the first capacitor. The first terminal is connected to a second synchronizing pulse having a phase opposite to that of the first synchronizing pulse, and the second terminal of the second MISTFT is connected to the first terminal and the gate terminal of the third MISTFT. And The second terminal of the second capacitor is connected to the first terminal of the second capacitor, the second terminal of the first MISFT, the gate terminal of the second MISFET, and the first terminal of the fourth MISFT. The second terminal of the third MISTFT is connected to the gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT, and the first terminal of the third capacitor element. And a first output terminal, the second terminal of the third capacitor is connected to a fixed voltage, and the first terminal of the fifth MISTFT is connected to the first synchronization pulse. The second terminal of the fifth MISFT is connected to the first terminal and gate terminal of the sixth MISFT and the gate terminal of the fourth MISFT, and is connected to the first terminal of the fourth capacitor. And forming a second output terminal and a fourth capacitor The second terminal is connected to the second terminal of the third MISTFT, the gate terminal of the fifth MISTFT, and the first terminal of the seventh MISTFT, and the second terminal of the fourth MISTFT and the seventh terminal. The second terminal of the MISFT is equal to the voltage that becomes the source voltage of the MISFT among the voltages of the first and second synchronization pulses, or at least equal to or higher than the threshold value of the fourth MISFT. It is connected to a fixed power source or ground potential that is not different from the voltage that becomes the source voltage of the pulse, and the gate terminal of the seventh MOSTFT is a pulse corresponding to the pulse input to the gate terminal of the fourth MISTFT. A pulse shifted by one clock is input.

  The display device configured as described above has a configuration in which one end side of a load capacitor is connected to a node that can be in a floating state, and the other end side is connected to a fixed potential or the like, thereby avoiding the unstable elements described above. The design margin in the field of view increases, and a stable dynamic ratioless shift register made of a thin film transistor made of polycrystalline silicon can be realized.

Mean 2.
In the display device according to the present invention, for example, on the premise of the configuration of the means 1, n basic circuits composed of second to seventh MISTFTs and first to fourth capacitors are connected in multiple stages, i. The gate terminal of the MISFT corresponding to the second MISTFT of the th basic circuit is connected to the second terminal of the MISFT corresponding to the sixth MISTFT of the (i−1) th basic circuit, and the i th The gate terminal of the MISTFT corresponding to the seventh MISTFT of the basic circuit is connected to the second terminal of the MISTFT corresponding to the (i + 1) th second MISTFT, and the seventh terminal of the nth basic circuit. The gate terminal of the MISFT corresponding to this MISFT is shifted by one clock with a pulse corresponding to the pulse inputted to the gate terminal of the fourth MISFT of the next basic circuit. It is characterized in that the pulse is inputted.

Means 3.
In the display device according to the present invention, for example, on the premise of the configuration of the means 2, the second MISTFT is incorporated in the first basic circuit, and the first MISTFT and the second MISTFT are incorporated in the second and subsequent basic circuits. The first MISFT has its gate terminal connected to the input terminal of the input pulse, the first terminal connected to the gate terminal of the MISFT corresponding to the second MISFT, and the second terminal connected to the first and first terminals. Of the two sync pulse voltages, it is equal to the voltage that becomes the source voltage of the MISFT, or is at least equal to or higher than the threshold voltage of the fourth MISFT and the voltage that becomes the source voltage of the first and second sync pulses. Not connected to a fixed power supply or ground potential, the second MISTFT has its gate terminal connected to the input terminal of the input pulse, and the first terminal connected to the fifth MISTF Alternatively, the second terminal is connected to the gate terminal of the MISFT corresponding to the fifth MISTFT, and the second terminal is equal to the voltage that becomes the source voltage of the MISTFT among the voltages of the first and second synchronization pulses, or at least the fourth It is characterized in that it is connected to a fixed power supply or ground potential that is not different from the voltage that becomes the source voltage of the first and second synchronizing pulses above the threshold voltage of the MISFT.

Means 4.
The display device according to the present invention includes, for example, a drive circuit including a shift register on a substrate surface, and the shift register includes a MISFT having polycrystalline silicon as a semiconductor layer, and the first terminal and the gate terminal of the first MISFT. Is connected to the input pulse to form an input portion, the second terminal of the first MISTFT is connected to the gate terminal of the second MISTFT and the first terminal of the fourth MISTFT, and the first The first terminal of the capacitive element is connected, the second terminal of the first capacitor is connected to a fixed voltage, and the first terminal of the second MISTFT is in a phase opposite to that of the first synchronization pulse. The second terminal of the second MISFT is connected to the first terminal and the gate terminal of the third MISFT, and is connected to the first terminal of the second capacitor. , Second capacity second Are connected to the second terminal of the first MISFT, the gate terminal of the second MISFET, and the first terminal of the fourth MISFT, and the second terminal of the third MISFT is connected to the fifth terminal. Connected to the gate terminal of the first MISFT and the first terminal of the seventh MISFT, connected to the first terminal of the third capacitor element, and formed the first output terminal, and the second capacitor Are connected to a fixed voltage, the first terminal of the fifth MISFT is connected to the first synchronization pulse, and the second terminal of the fifth MISFT is the first terminal of the sixth MISFT. And the gate terminal and the gate terminal of the fourth MISFT, and is connected to the first terminal of the fourth capacitor and forms a second output terminal, and the second terminal of the fourth capacitor is Second terminal of third MISFT, fifth The gate terminal of the MISFT and the first terminal of the seventh MISFT are connected, and the second terminal of the fourth MISFT and the second terminal of the seventh MISFT are voltages of the first and second synchronization pulses. Of the fixed power source or the ground potential equal to the voltage that becomes the source voltage of the MISFT, or at least equal to the voltage that becomes the source voltage of the first and second synchronization pulses at least the threshold value of the fourth MISFT. The gate terminal of the seventh MISTFT is connected with a pulse shifted by one clock with a pulse corresponding to the pulse input to the gate terminal of the fourth MISTFT. is there.

Means 5.
In the display device according to the present invention, for example, on the premise of the configuration of the means 4, n basic circuits composed of second to seventh MISTFTs and first to fourth capacitors are connected in multiple stages, i. The gate terminal of the MISFT corresponding to the second MISTFT of the th basic circuit is connected to the second terminal of the MISFT corresponding to the sixth MISTFT of the (i−1) th basic circuit, and the i th The gate terminal of the MISTFT corresponding to the seventh MISTFT of the basic circuit is connected to the second terminal of the MISTFT corresponding to the (i + 1) th second MISTFT, and the seventh terminal of the nth basic circuit. The gate terminal of the MISFT corresponding to this MISFT is shifted by one clock with a pulse corresponding to the pulse inputted to the gate terminal of the fourth MISFT of the next basic circuit. It is characterized in that the pulse is inputted.

Means 6.
In the display device according to the present invention, for example, on the premise of the configuration of the means 5, the second MISTFT is incorporated in the first basic circuit, and the first MISTFT and the second MISTFT are incorporated in the second and subsequent basic circuits. The first MISFT has its gate terminal connected to the input terminal of the input pulse, the first terminal connected to the gate terminal of the MISFT corresponding to the second MISFT, and the second terminal connected to the first and first terminals. Of the two sync pulse voltages, it is equal to the voltage that becomes the source voltage of the MISFT, or is at least equal to or higher than the threshold voltage of the fourth MISFT and the voltage that becomes the source voltage of the first and second sync pulses. Not connected to a fixed power supply or ground potential, the second MISTFT has its gate terminal connected to the input terminal of the input pulse, and the first terminal connected to the fifth MISTF Alternatively, the second terminal is connected to the gate terminal of the MISFT corresponding to the fifth MISTFT, and the second terminal is equal to the voltage that becomes the source voltage of the MISTFT among the voltages of the first and second synchronization pulses, or at least the fourth It is characterized in that it is connected to a fixed power supply or ground potential that is not different from the voltage that becomes the source voltage of the first and second synchronizing pulses above the threshold voltage of the MISFT.

Mean 7
The display device according to the present invention includes, for example, a drive circuit including a shift register on a substrate surface, and the shift register includes a MISFT having polycrystalline silicon as a semiconductor layer, and the first terminal and the gate terminal of the first MISFT. Is connected to the input pulse to form an input portion, the second terminal of the first MISTFT is connected to the gate terminal of the second MISTFT and the first terminal of the fourth MISTFT, and the first The capacitor is connected to a fixed voltage, and the first terminal of the second MISFT is connected to a second synchronization pulse having a phase opposite to that of the first synchronization pulse. Are connected to the first terminal and the gate terminal of the third MISTFT, and the second terminal of the first MISTFT, the gate terminal of the second MISTFT and the gate terminal of the second MISTFT through the second capacitor. The third terminal of the third MISTFT is connected to the first terminal of the fourth MISTFT, the second terminal of the third MISTFT is connected to the gate terminal of the fifth MISTFT, the first terminal of the seventh MISTFT, and the third terminal. Are connected to a fixed voltage, the first terminal of the fifth MISTFT is connected to the first synchronization pulse, and the first terminal of the fifth MISTFT is connected to the sixth MISTFT. The second terminal of the third MISFT, the gate terminal of the fifth MISFT, and the seventh terminal are connected to the first terminal, the gate terminal, and the gate terminal of the fourth MISFT, and through the fourth capacitor. The second terminal of the fourth MISFT is equal to or equal to at least the voltage that becomes the source voltage of the MISFT among the voltages of the first and second synchronization pulses. M It is connected to a fixed power source or a ground potential that is not different from the source voltage of the first and second synchronization pulses above the STFT threshold, and the gate terminal of the seventh MISFT is connected to the 14th A pulse shifted by one clock with a pulse corresponding to the pulse input to the gate terminal of the MISFT is input.

Means 8.
In the display device according to the present invention, for example, on the premise of the configuration of the means 7, n basic circuits composed of second to eleventh MISTFTs and first and second capacitors are connected in multiple stages, and the ith The gate terminal of the MISFT corresponding to the second MISTFT of the basic circuit is connected to the second terminal of the MISFT corresponding to the tenth MISTFT of the (i-1) th basic circuit, and the i-th basic The second terminal of the MISFT corresponding to the sixth MISFT of the (i + 1) th basic circuit is connected to the gate terminal of the MISFT corresponding to the eighth MISFT of the circuit and the first terminal of the MISFT corresponding to the seventh MISFT. Connected to the terminal, the gate terminal of the MISFT corresponding to the eighth MISFT of the nth basic circuit and the first of the MISFT corresponding to the seventh MISFT. The terminal is characterized in that the pulses are the first 14 one clock shift corresponding pulse to the pulse inputted to the gate terminal of MISTFT of is inputted.

Means 9.
The display device according to the present invention includes, for example, a drive circuit including a shift register on a substrate surface, and the shift register includes a MISFT having polycrystalline silicon as a semiconductor layer, and a first terminal of the first MISFT is an input pulse. And the gate terminal of the first MISFT is connected to the first synchronization pulse to form an input section, and the second terminal of the first MISFT is the gate terminal of the fourth MISFT and the third Connected to the first terminal of the first capacitor and to the first terminal of the first capacitor, the second terminal of the first capacitor is the second terminal of the fourth MISFT, the second terminal of the fifth MISFT The first terminal, the gate terminal, the first terminal and the gate terminal of the sixth MISFT, and the gate terminal of the second MISFT connected to the gate terminal of the seventh MISFT. The child is connected to the input pulse, the first terminal of the second MISFT is connected to the second terminal of the eleventh MISFT and the gate terminal of the third MISFT, the second terminal of the second MISFT, and The second terminal of the seventh MISFT is equal to the voltage that becomes the source voltage of the MISFT among the voltages of the first and second synchronization pulses, or at least equal to or higher than the threshold voltage of the fourth MISFT. It is connected to a fixed power supply or ground potential that is not different from the voltage that becomes the source voltage of the second synchronization pulse, and the second terminal of the third MISFT is the voltage of the first and second synchronization pulses. It is equal to the voltage that becomes the source voltage of the MISFT, or at least different from the voltage that becomes the source voltage of the first and second synchronization pulses at least the threshold voltage of the fourth MISFT. The first terminal of the fourth MISFT is connected to the second synchronization pulse, the second terminal of the fifth MISFT is connected to the gate terminal of the ninth MISFT and The second terminal of the second capacitor is connected to the first terminal of the eighth MISFT, the second terminal of the ninth MISFT, the first terminal and the gate terminal of the tenth MISFT, and the eleventh terminal. The first terminal and the gate terminal of the MISFT and the first terminal of the second capacitor element are connected to the first terminal and the gate terminal of the MISFT, and the first output terminal is formed. The second terminal of the eighth MISTFT is connected to the gate terminal, and the second terminal of the eighth MISTFT is equal to or at least equal to the voltage that becomes the source voltage of the MISTFT among the voltages of the first and second synchronization pulses. Is connected to a fixed power source or a ground potential that is not different from the voltage that becomes the source voltage of the first and second synchronization pulses above the threshold voltage, and the first terminal of the ninth MISTFT is connected to the first terminal A pulse that is connected to the synchronization pulse and shifted by one clock with a pulse corresponding to the pulse input to the gate terminal of the fourth MISFT is applied to the gate terminal of the eighth MISFT and the first terminal of the seventh MISFT. It is characterized by being input.

Means 10.
The display device according to the present invention, for example, is based on the configuration of the means 9 and is basically composed of second, third, fourth, fifth, seventh, eighth, ninth and tenth MISTFTs and first and second capacitors. N circuits are connected in multiple stages, and the second terminal of the MISFT corresponding to the tenth MISTF of the i-th basic circuit is the second terminal of the MISFT corresponding to the fourth MISFT of the (i−1) -th basic circuit. The second terminal of the MISTFT corresponding to the seventh MISTFT of the i-th basic circuit connected to the gate terminal and the gate terminal of the MISTFT corresponding to the third MISTFT are the first of the (i + 1) th basic circuit. The second terminal of the sixth MISTFT is connected to the capacitor corresponding to the second capacitor, the second terminal of the MISFT, and the MISFT gate corresponding to the third MISFT. Is connected to the bets terminal, the first terminal and the gate terminal is characterized in that it is connected to the capacitor.

Means 11.
In the display device according to the present invention, for example, in each of the second basic circuits, the second terminal of the first MISTFT in which the first terminal and the gate terminal are connected to the input pulse corresponds to the eleventh MISTFT. The second terminal of the second MISTFT whose first terminal and gate terminal are connected to the input pulse in each of the third basic circuits connected to the second terminal of the MISTFT Connected to the gate terminal of the MISFT corresponding to the eighth MISFT of the basic circuit, and to the second terminal of the capacitor corresponding to the first capacitor via the MISFT, and the second terminal of the MISFT is The second MISFT is connected to the second terminal, and the first terminal and the gate terminal are connected to the capacitor.

Means 12.
The display device according to the present invention includes, for example, a drive circuit including a shift register on a substrate surface, and the shift register includes a MISFT having polycrystalline silicon as a semiconductor layer, and the first terminal and the gate terminal of the first MISFT. Is connected to the input pulse to form an input portion, the second terminal of the first MISTFT is connected to the gate terminal of the fourth MISTFT and the first terminal of the third MISTFT, and the first The second terminal of the first capacitor is connected to the second terminal of the fourth MISTFT, the first terminal and the gate terminal of the fifth MISTFT, and the first terminal of the sixth MISTFT. And the gate terminal of the seventh MISFT, the gate terminal of the second MISFT is connected to the input pulse, and the second MISFT is connected to the gate terminal of the seventh MISFT. The first terminal is connected to the second terminal of the eleventh MISTFT and the gate terminal of the third MISTFT. The second terminal of the second MISTFT and the second terminal of the seventh MISTFT are the first, The voltage of the second sync pulse is equal to the voltage that becomes the source voltage of the MISFT, or is different from the voltage that becomes the source voltage of the first and second sync pulses at least above the threshold voltage of the fourth MISFT. The second terminal of the third MISTFT is equal to or at least equal to the voltage that becomes the source voltage of the MISFT among the voltages of the first and second synchronization pulses. 4 is connected to a fixed power source or a ground potential that is not different from a voltage that becomes a source voltage of the first and second synchronization pulses above the threshold voltage of the fourth MISFT. The first terminal of the MISFT is connected to the second synchronization pulse, the second terminal of the fifth MISFT is connected to the gate terminal of the ninth MISFT and the first terminal of the eighth MISFT, and the second The second terminal of the capacitor is connected to the second terminal of the ninth MISFT, the first terminal and gate terminal of the tenth MISFT, the first terminal and gate terminal of the eleventh MISFT, and the second terminal. The first terminal of the seventh MISTFT is connected to the gate terminal of the eighth MISTFT, and the second terminal of the eighth MISTFT is connected to the first terminal of the capacitor and forms the first output terminal. Is equal to the voltage that becomes the source voltage of the MISFT among the voltages of the first and second synchronization pulses, or is at least equal to or higher than the threshold voltage of the fourth MISFT. The first terminal of the ninth MISTFT is connected to the first synchronization pulse, the gate terminal of the eighth MISTFT and the seventh A pulse shifted by one clock with a pulse corresponding to a pulse input to the gate terminal of the fourth MISFT is input to the first terminal of the MISFT.

Means 13.
The display device according to the present invention, for example, on the premise of the configuration of the means 12, is basically composed of second, third, fourth, fifth, seventh, eighth, ninth and tenth MISTFTs and first and second capacitors. N circuits are connected in multiple stages, and the second terminal of the MISFT corresponding to the tenth MISTF of the ith basic circuit is the second terminal of the MISFT corresponding to the fourth MISTF of the (i−1) th basic circuit. The second terminal of the MISTFT corresponding to the seventh MISTFT of the i-th basic circuit connected to the gate terminal and the gate terminal of the MISTFT corresponding to the third MISTFT are the first of the (i + 1) th basic circuit. The second terminal of the sixth MISTFT is connected to the capacitor corresponding to the second capacitor, the second terminal of the MISFT, and the MISFT gate corresponding to the third MISFT. Is connected to the bets terminal, the first terminal and the gate terminal is characterized in that it is connected to the capacitor.

Means 14.
In the display device according to the present invention, on the premise of the configuration of the means 13, in each of the second basic circuits, the second terminal of the first MISTFT in which the first terminal and the gate terminal are connected to the input pulse is the second. The second terminal of the second MISFT whose first terminal and gate terminal are connected to the input pulse in each of the third basic circuits is connected to the second terminal of the MISFT corresponding to the eleven MISFT. , Connected to the gate terminal of the MISFT corresponding to the eighth MISFT of the basic circuit in the previous stage of the basic circuit, and connected to the second terminal of the capacitor corresponding to the first capacitor via the MISFT. The second terminal is connected to the second terminal of the second MISTFT, and the first terminal and the gate terminal are connected to the capacitor.

Means 15.
The display device according to the present invention includes, for example, a display driving circuit including a ratioless type dynamic shift register including a multistage inverter on a substrate surface, and the ratioless type dynamic shift register is formed from a MISFT having polycrystalline silicon as a semiconductor layer. A separate MISTFT is connected in parallel to the MISTFT connected to the ground level of each output of each stage, and the separate MISTFT is the input of the inverter in the previous stage of the stage constituted by the MISFT. In the signal, each output is dropped to the ground level during a period other than when a high level signal is transmitted.

Means 16.
In the display device according to the present invention, on the premise of the configuration of the means 15, the separate MISTF is operated by using the output of the next stage as an input, and the input signal of the inverter at the front stage of the stage constituted by the MISFT is at a high level. Each output is dropped to the ground level during a period other than when the above signal is transmitted.

Means 17.
In the display device according to the present invention, for example, on the premise of the configuration of the means 15, the separate MISTF is operated by inputting a clock pulse, and a high level is applied to the input signal of the inverter in the preceding stage constituted by the MISFT. Each output is dropped to the ground level during a period other than when the above signal is transmitted.

Means 18.
The display device according to the present invention includes, for example, a display driving circuit including a ratioless type dynamic shift register including a multistage inverter on a substrate surface, and the ratioless type dynamic shift register is formed from a MISFT having polycrystalline silicon as a semiconductor layer. A first MISTFT and a second MISTFT connected in parallel to each other as MISTFTs connected to the ground level of each output of each stage, of the first MISTFT and the second MISTFT Is configured to drop each output to the ground level during a period other than when a high level signal is transmitted in the input signal of the inverter in the previous stage of the stage constituted by the MISFT. MISTFT and second MI The charge charged to the gate between the one gate of the TFT and the node to which the clock is supplied via the diode causes the potential of the node to fall below the ground level, thereby causing the reverse current of the diode as the reverse current. A diode including a third MISTFT that prevents leakage to the node is provided.

Means 19.
The display device according to the present invention includes, for example, a display driving circuit including a ratioless type dynamic shift register including a multistage inverter on a substrate surface, and the ratioless type dynamic shift register is formed from a MISFT having polycrystalline silicon as a semiconductor layer. The first MISTFT and the second MISTFT, which are each configured to drop to the ground level when the first clock and the second clock are turned on, and turned on when the output is at the high level. And a third MISTFT and a fourth MISTFT for turning off the first MISTFT and the second MISTFT.

Means 20.
In the display device according to the present invention, for example, on the premise of the configuration of the means 19, the first clock is input to the gate of the first MISFT via the first capacitive element, and the second clock is input to the gate of the second MISFT. A fifth MISTFT that is input via a two-capacitance element and is diode-connected between the gate of the first MISTFT and the ground level, and between the gate of the second MISTFT and the ground level, and A sixth MISTFT is provided.

Means 21.
The display device according to the present invention includes, for example, a display driving circuit including a ratioless type dynamic shift register including a multistage inverter on a substrate surface, and the ratioless type dynamic shift register is formed from a MISFT having polycrystalline silicon as a semiconductor layer. The first MISTFT connected to the ground level of each output of each stage and the output of the previous stage, one end being connected to the ground level and the other end being connected to the clock via the first capacitive element. The second end is connected to the gate of the first MISTFT, and a second capacitive element is provided between the other end of the second MISTFT and the ground level. is there.

Means 22.
The display device according to the present invention is characterized in that, for example, on the premise of the configuration of the means 21, the second capacitor element has a capacitance larger than the gate-drain capacitance of the second MISTFT.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the display device of the present invention, it is possible to obtain a display device including a dynamic ratioless shift register that operates stably and can increase design flexibility.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example 1]
"overall structure"
FIG. 2 is a schematic configuration diagram showing the entire liquid crystal display device according to the present invention. This figure is a plan view corresponding to the actual geometric arrangement.
In the figure, there is a transparent substrate SUB1 made of, for example, a glass substrate among a pair of transparent substrates disposed to face each other via a liquid crystal.

  In the central portion (display portion AR) excluding the periphery of the liquid crystal side surface of the transparent substrate SUB1, gate signal lines GL extending in the x direction and juxtaposed in the y direction are extended in the y direction. Then, drain signal lines DL arranged in parallel in the x direction are formed.

  Each region surrounded by the adjacent gate signal line GL and the adjacent drain signal line DL constitutes a pixel region, and this pixel region is operated by supplying a scanning signal from the gate signal line GL on one side. A thin film transistor TFT and a pixel electrode PX to which a video signal is supplied from the drain signal line DL on one side through the thin film transistor TFT are provided.

  That is, for example, a scanning signal (voltage) is sequentially supplied to each gate signal line GL from the top to the bottom in the figure, and the thin film transistor TFT is turned on by this scanning signal. In accordance with this timing, a video signal (voltage) is supplied from each drain signal line DL and applied to the pixel electrode PX via the thin film transistor TFT in the ON state.

  Each of the pixel electrodes PX generates an electric field between, for example, a counter electrode (not shown) formed in common in each pixel region on the liquid crystal side surface of another transparent substrate disposed opposite to the transparent substrate SUB1. This electric field controls the light transmittance of the liquid crystal.

  Each gate signal line GL is connected to the pixel driving shift register 1 on one end side (left side in the figure), and the pixel driving shift register 1 sequentially supplies scanning signals to the gate signal lines GL. ing.

  Each drain signal line DL is connected to a D-A conversion circuit 2, a memory 3, an input data capturing circuit (INPut) 4, and an H-side address decoder 5 in this order from one end side (upper side in the figure). The memory is connected to a V-side address decoder 6 and a memory driving shift register 7.

  The liquid crystal display device thus configured receives information including a start pulse clock signal (CLK), pixel data (Data), a pixel address (H-add), and a pixel address (V-add). It is like that.

  The start pulse clock signal is sent to the memory drive shift register 7 and the pixel drive shift register 1, the pixel address (H) is sent to the H-side address decoder 5, the pixel data is sent to the input data fetch circuit 4, and the pixel address (V) is sent to V. Each is input to the side address decoder 6.

Here, the display area AR formed on the surface of the transparent substrate SUB1 and its peripheral circuits are laminated with a conductive layer, a semiconductor layer, an insulating layer, and the like formed in a predetermined pattern by selective etching using a photolithography technique. Thin film transistors (MISTFT), pixel electrodes, signal lines and the like are formed.
In this case, the semiconductor layer is made of, for example, polycrystalline silicon (p-SI).

《Pixel drive shift register》
FIG. 1A is a circuit diagram showing an embodiment of the pixel driving shift register. FIG. 1B shows a timing chart of the circuit shown in FIG. 1A and shows respective outputs VN1 to VN6 at nodes N1 to N6 with respect to the input pulse φIN and the synchronization pulses φ1 and φ2.

  In FIG. 1, there is an n-type MOS transistor NMT1. One of the source / drain terminals is connected to the input terminal φIN of the input pulse φIN, and the gate terminal is connected to the input terminal of the synchronization pulse φ1. . The MOS transistor NMT1 forms an input unit.

  The other terminal of the MOS transistor NMT1 is connected to the gate terminal of the n-type MOS transistor NMT2, one terminal of the n-type MOS transistor NMT4, and one terminal of the capacitor CS1.

  The other terminal of the capacitor CS1 is connected to the fixed voltage VBIAS, and one terminal of the MOS transistor NMT2 is connected to the input terminal of the synchronization pulse φ2 having a phase opposite to that of the synchronization pulse φ1.

  The other terminal of the MOS transistor NMT2 is connected to one terminal and a gate terminal of the n-type MOS transistor NMT3, and is connected to one terminal of the capacitor Cb1.

  The other terminal of the capacitor Cb1 is connected to the other terminal of the MOS transistor NMT1, the gate terminal of the MOS transistor NMT2, and one terminal of the n-type MOS transistor NMT4.

  The other terminal of the MOS transistor NMT3 is connected to the gate terminal of the n-type MOS transistor NMT5, one terminal of the MOS transistor NMT7, and is connected to one terminal of the capacitor CS2, and the first output terminal. Is configured.

  The other terminal of the capacitor CS2 is connected to the fixed voltage VBIAS, and the other terminal of the MOS transistor NMT5 is connected to the input terminal of the synchronization pulse φ1.

  The other terminal of the MOS transistor NMT5 is connected to one terminal and gate terminal of the n-type MOS transistor NMT6, to the gate terminal of the MOS transistor NMT4, and to one terminal of the capacitor Cb2, and the second terminal An output terminal is configured.

  The other terminal of the capacitor Cb2 is connected to the other input terminal of the MOS transistor NMT3, the gate terminal of the MOS transistor NMT5, and one terminal of the n-type MOS transistor NMT7.

  The other terminal of the MOS transistor NMT4 and the other terminal of the MOS transistor NMT7 are equal to the voltage that is the source voltage of the MOS transistor among the voltages of the synchronization pulses φ1 and φ2 (the lowest voltage for n-type and the highest voltage for p-type). Alternatively, it is connected to a fixed power supply or a ground potential (VSS / VDD) that is at least equal to or higher than the threshold voltage of the MOS transistor NMT4 and does not differ from the voltage that becomes the source voltage of the synchronization pulses φ1, φ2.

  Such connection is the same in the next stage and further in the next stage, and the gate terminal of the MOS transistor NMT7 is connected to the gate terminal of the MOS transistor NMT9 corresponding to the MOS transistor NMT4 in the next stage.

  In the shift register having such a configuration, in the configuration shown in FIG. 9A, one ends of the load capacitors CS1, CS2, CS3,... Are connected to the nodes N1, N3, N5,. .., And the other end of each of CS1, CS2, CS3,... Is connected to a fixed potential VBIAS.

  By doing in this way, said Formula (9) can be rewritten to following Formula (11).

[Equation 11]
VN3 = Vφ × (Cdg5 / (Cdg5 + CN3 + CS2))
(11)
Here, CS2 is a design parameter and can be formed with a direct parallel plate capacitance.

Even if CN3 is ignored, VN3 is expressed by the following equation (12).
[Equation 12]
VN3 = Vφ × (Cdg5 / (Cdg5 + CS2)) <Vth
(12)

Further, the following equation (13) obtained by adding CS (nodes N3 to CS2) to the equation (4) is satisfied.
[Equation 13]
VN1 = (Vφ−Vth) + Vφ (Cb / (Cb + CS + cs))> Vφ + Vth
(13)

  As a result, the design margin in a state where the above-described unstable elements are avoided is widened, and a stable dynamic ratioless shift register made of a thin film transistor made of polycrystalline silicon can be realized.

  FIG. 3A shows a cross-sectional view of the thin film transistor constituting the circuit when the above-described dynamic ratioless shift register is formed on the transparent substrate SUB1.

  As candidates for forming the load capacitor CS in this thin film transistor, the polysilicon thin film and the wiring material capacity Csl, the gate forming thin film and the wiring material capacity Cgl, the gate forming thin film and the pixel electrode capacity Ctg, the wiring material and the pixel Specific examples include electrode capacitance Ctl.

  With the above-described configuration, the added load capacitance CS plays an important role from the viewpoint of stable operation of the circuit, and can improve the degree of design freedom. However, from the standpoint of bootstrap efficiency, this is a completely parasitic capacitance.

  Therefore, a MOS capacitor is formed as the load capacitor CS as shown in FIGS. 3B and 3C, thereby improving bootstrap efficiency.

That is, VBIAS is set as shown in the following formula (14),
[Formula 14]
Vth <VBIAS <Vφ-2Vth (14)

  When the source side is connected to the floating node and the gate side is connected to the bias, when the floating node (N3, N5,...) Is 'L', an inversion layer is formed and the capacitance is large (CSL), 'H' In this case, a variable capacitor can be obtained in which the inversion layer is eliminated and the capacitance is small (CSS).

That is, the relationship shown in the following formula (15) is obtained.
[Equation 15]
CSL >> CSS (15)
As a result, the above equations (12) and (13) are changed to the following equations (16) and (17), respectively.
[Equation 16]
VN3 = Vφ × (Cdg5 / (Cdg5 + CSL)) <Vth (16)

[Equation 17]
VN1 = (Vφ−Vth) + (Cb / (Cb + CSS + Cs))> Vφ + Vth
(17)
Thus, the stabilization capacity is heavy and the bootstrap efficiency is improved.

FIG. 4 shows another embodiment in which the circuit of FIG. 1 is further improved.
In the figure, when the circuit that forms the first output of the next stage of the input unit and the circuit that forms the second output of the next stage are used as basic circuits, NMTr2 is incorporated in the basic circuit of the first stage. NMTr1 and NMTr2 are formed in the basic circuit of each subsequent stage.

  In each basic circuit, the NMTr2 has a first terminal connected to the seventh MOS transistor NMT4 or the first terminal of the corresponding MOS transistor, and a gate terminal connected to the input terminal of the input pulse φIN. .

  The second terminal of the NMTr2 is equal to the voltage that is the source voltage of the MOS transistor (the lowest voltage for the n-type and the highest voltage for the p-type) among the voltages of the synchronization pulses φ1 and φ2, or at least the fourth It is connected to a fixed power supply or ground potential that is not different from the voltage that becomes the source voltage of each synchronization pulse φ1, φ2 above the threshold voltage of the MOS transistor.

  The NMTr1 has a first terminal connected to the fourth MOS transistor NMT4 or the first terminal of the corresponding MOS transistor, and a gate terminal connected to the input terminal of the input pulse φIN.

  The second terminal of the NMTr2 is equal to the voltage that is the source voltage of the MOS transistor (the lowest voltage for the n-type and the highest voltage for the p-type) among the voltages of the synchronization pulses φ1 and φ2, or at least the fourth It is connected to a fixed power supply or ground potential that is not different from the voltage that becomes the source voltage of each synchronization pulse φ1, φ2 above the threshold voltage of the MOS transistor.

  The dynamic ratioless shift register configured as described above has an effect of resetting the situation when each node is unstable such as when the power is turned on.

  In each circuit described above, the input section is not limited to that shown in FIG. 1A. As shown in FIG. 5, the input pulse φIN is applied to one terminal and the gate terminal of the MOS transistor NMT1. It is good also as a structure connected to the input terminal. This is because the same effect can be obtained.

[Example 2]
FIG. 6A is a circuit diagram showing another embodiment of the shift register formed in the liquid crystal display device according to the present invention.

  Unlike the configuration in which the load level is added to maintain the OFF level as in the first embodiment, the present embodiment has a configuration in which a circuit for setting the input gate of an unselected shift register to 'L' is added. It has become.

  That is, as shown in FIG. 6A, first, the MOS transistor NMT1 has its first terminal and gate terminal connected to the input terminal of the input pulse φIN to form an input section.

  The second terminal of the MOS transistor NMT1 is connected to the gate terminal of the MOS transistor NMT4, the first terminal of the MOS transistor NMT2, and is connected to the first terminal of the capacitor CB1, and the second terminal of the capacitor CB1 is The second terminal of the MOS transistor NMT4, the first terminal of the MOS transistor NMT5, and the gate terminal are connected.

  The first terminal of the MOS transistor NMT2 is connected to the gate terminal of the MOS transistor NMT7, and the gate terminal of the MOS transistor NMT2 and the second terminal of the MOS transistor NMT3 are connected to the second terminal of the MOS transistor NMT10.

The second terminal of the MOS transistor NMT2 is equal to the voltage that becomes the source voltage of the MOSTFT among the voltages of the synchronization pulses φ1 and φ2, or at least the threshold voltage of the MOS transistor NMT4 and the source voltage of the synchronization pulses φ1 and φ2 Connected to a fixed power supply VSS or ground potential (VDD) that is not different from the voltage to be
The second terminal of the MOS transistor NMT3 is equal to the voltage that becomes the source voltage of the MOSTFT among the voltages of the synchronization pulses φ1 and φ2, or at least equal to or higher than the threshold voltage of the MOS transistor NMT4. Is connected to a fixed power supply VSS or a ground potential (VDD) which is not different from a voltage that becomes a source voltage of the power source.

The first terminal of the MOS transistor NMT4 is connected to the input terminal of the synchronization pulse φ2,
The second terminal of the MOS transistor NMT5 is connected to the gate terminal of the MOS transistor NMT6 and to the first terminal of the capacitor CB2.

  The second terminal of the capacitor CB2 is connected to the second terminal of the MOS transistor NMT8, the first terminal and gate terminal of the MOS transistor NMT9, and the first terminal and gate terminal of the MOS transistor NMT10. A second output terminal is formed.

  The first terminal of the MOS transistor NMT6 is connected to the gate terminal of the MOS transistor NMT11. The second terminal of the MOS transistor NMT11 is equal to the voltage that becomes the source voltage of the MOSTFT among the voltages of the synchronization pulses φ1 and φ2, or at least the threshold voltage of the MOS transistor NMT4 and the source voltage of the synchronization pulses φ1 and φ2 Is connected to a fixed power supply VSS or a ground potential (VDD) which is not different from the voltage to be.

  The first terminal of the MOS transistor NMT8 is connected to the input terminal of the synchronization pulse φ1, and the second terminal of the ninth MOS transistor NMT9 forms a second output terminal.

  The gate terminal of the MOS transistor NMT6 and the first terminal of the MOS transistor NMT7 are the second terminals of the other MOS transistors corresponding to the NOS transistor NMT10 of the next stage circuit having the same configuration as the circuit described above. It is connected to the.

  The operation of the shift register configured as described above will be described below with reference to the timing chart of FIG.

  When φIN changes from “L” to “H” at time t0, NMT3 is turned ON, N5 and VSS (= GND) are connected, VN5 = VSS, NMT2 having N5 as a gate is turned OFF, and N1 Enters a floating state.

  At the same time, the voltage VN1 of N1 becomes VN1 = Vφ−Vth due to the diode connection of NMT1. When Vφ−Vth> Vth is set, NMT7 is also turned on by VN1 = Vφ−Vth, N8 and VSS (= VSS) are connected, VN8 = VSS, and NMT6 having N8 as a gate Becomes OFF and N3 becomes floating.

  At this time, only the gates of NMT4 and NMT8 among the NMTs whose drains are connected to the synchronization pulses φ1 and φ2 are in a floating state.

  When φ2 changes from “L” to “H” at time t1, since NMT4 is in the ON state, the potential of N2 rises and VN2 = Vφ is satisfied by the bootstrap capacitor CB1 as described above.

  At this time, N1 is boosted to increase the voltage to VN1 = (Vφ−Vth) + Vφ (Cb / (Cb + Cs)), but φIN is “H”, and the gate of NMT2 is VSS (= GND). Therefore, forced OFF is maintained.

  Then, due to the diode-connected NMT5, VN3 = Vφ−Vth. As a result, NMT11 having N3 as a gate is turned on, N11 is changed from “H” to “L”, NMT15 is turned off, and N6 is brought into a floating state.

At time t2, φ1 changes from L → H and φ2 changes from “H” to “L”.
Since φ2 changes from “H” to “L”, VN2 changes from H to L, but VN3 maintains “H”. When φ1 changes from “L” to “H”, the voltage of N4 becomes VN4 = Vφ through the NMT 8 in the ON state.

  As a result, NMT16 having N6 as a gate is turned on, N14 is changed from “H” to “L”, NMT20 is turned off, and N9 is brought into a floating state.

  At the same time, VN5 = Vφ−Vth is obtained by the diode-connected NMT10. As a result, NMT2 having N5 as a gate is turned on, N1 and VSS are connected, and NMT4 is forcedly turned off with its gate connected to VSS. Since the NMT 10 is diode-connected, the VN5 remains in the “H” state even when VN4 = L (the element α is omitted for simplicity).

  That is, the forced OFF state in which the gate of NMT4 is connected to VSS is maintained until φIN becomes “H” again.

At time T3, φ2 changes from “L” to “H”, and φ1 changes from “H” to “L”.
When φ1 changes from “H” to “L”, VN4 changes from “H” to “L”, but VN6 maintains “H”. When φ2 changes from “L” to “H”, the voltage of N7 becomes VN7 = Vφ through the NMT 12 in the ON state.

  Due to the diode-connected NMT 13, VN9 = Vφ−Vth. As a result, NMT21 having N9 as a gate is turned on, N14 is changed from “H” to “L”, NMT25 is turned off, and N12 is brought into a floating state.

  At the same time, VN8 = Vφ−Vth is obtained by the diode-connected NMT 14. As a result, NMT6 having N8 as a gate is turned on, N3 and VSS are connected, and NMT8 is forcedly turned off with its gate connected to VSS. Since the NMT 14 is diode-connected, the VN 8 remains in the “H” state even when VN 7 = L (the element α is omitted for simplicity).

That is, the forced OFF state in which the gate of NMT4 is connected to VSS is maintained until VIN becomes H again.
Thereafter, the above operation is sequentially repeated to operate the shift register.

  The shift register configured as described above has a configuration in which all unnecessary gates of MOS transistors connected to the synchronization pulses φ1 and φ2 are connected to VSS. For this reason, since the MOS transistor can be forcedly turned off, the occurrence of unstable operation can be avoided.

  In the above-described embodiment, the input unit is not limited to that shown in FIG. 6A, and the first terminal of the MOS transistor NMT1 is input to the input pulse φIN as shown in FIG. Alternatively, the gate terminal may be connected to the input terminal of the synchronization pulse φ. This is because the same effect can be obtained.

[Example 3]
FIG. 7A is a circuit diagram showing another embodiment of the shift register formed in the liquid crystal display device according to the present invention.

  This figure shows the circuit shown in the second embodiment in which a diode-connected thin film transistor NMTR1, whose nodes N11, N14, N17,... Are the sources and the input pulse signal φIN is the drain and the gate, NMTR2, NMTR3,... Are connected.

  Each of these thin film transistors NMTR1, NMTR2, NMTR3,... Reinforces the “H” of each node in the floating state when the input pulse signal φIN becomes “H”, and the non-selected input gate. Can be made more reliable.

In addition, there is an effect that the same initialization as the normal operation state can be performed at the start of scanning immediately after the power is turned on.
In each of the above-described embodiments, an n-type thin film transistor has been described as a shift register. However, a p-type may be used as a matter of course.

This is because the effects of the present invention can be obtained in the same manner by reversing the absolute potentials of “H” and “L” of each signal.
In each of the above-described embodiments, the thin film transistor is shown as a MOS transistor whose gate insulating film is made of, for example, SiO ₂ , but the gate insulating film may be made of, for example, SiN. Not too long.

[Example 4]
FIG. 11 is a circuit diagram showing another embodiment of the ratioless type dynamic shift register used in the display device according to the present invention. That is, it is shown as a further improvement of the dynamic shift register shown in each of the embodiments described above. FIG. 12 shows an input pulse timing chart of the circuit shown in FIG.

  Here, in order to clarify the characteristic part of the ratioless type dynamic shift register used in the display device according to the present invention, a circuit diagram to be compared is shown in FIG. FIG. 14 shows an input pulse timing chart of the circuit shown in FIG.

  In such a circuit, an H1 clock jump is observed at the VSS (GND) level of the node 3 in FIG. FIG. 15A illustrates this phenomenon, and the H1 clock after the input signal Hin appears at the VSS (GND) level of the node 3 (lower side in the figure).

If the MIS transistor Mtr1 is turned on by a pulse that enters the node 5 from the node 4 in FIG. 13 and enters the node 5, there is no problem if the state continues for the next frame time (if the node 5 does not leak). As shown in FIG. 15D, the signal at the node 5 leaks.
For this reason, the Mtr1 is turned off, the node 1 is in a floating state and becomes unstable, and the same thing occurs in the node 2.
Therefore, the ratioless type dynamic shift register used in the display device according to the present invention shown in the present embodiment has a MIS transistor that is separate from the MIS transistor Mtr2 connected to the ground level of each output of each stage. Mtr3 is connected in parallel.

  That is, the MIS transistor Mtr1 shown in FIG. 13 in which the node 2 is dropped to VSS (GND) is composed of the MIS transistor Mtr2 and the MIS transistor Mtr3 connected in parallel with each other.

  Among them, the MIS transistor Mtr3 has a function similar to that of the MIS transistor Mtr1 shown in FIG. 13, and the MIS transistor Mtr2 is always at VSS except when the High signal is received at the node 1 shown in FIG. Has the ability to drop to level.

  Specifically, the gate of the MIS transistor Mtr2 is always in the high state at the potential charged by the H2 clock.

  Note that a MIS transistor Mtr9 is provided in order to prevent the charge charged in the node 7 from leaking to the node 6 as a diode backflow current when the potential of the node 6 falls below VSS.

The process of charging the node 7 in the ratioless type dynamic shift register configured as described above will be described.
First, since the node 6 is a floating node (a node not connected to the power source), the node 6 can swing at the timing of the clock H2 (see the waveform diagram of the node 6 in FIG. 12).
The node 7 is dropped to the VSS level while the node 1 is high, and becomes floating at the potential.

  After that, when the node 6 is lifted by the clock H2 for the first time, a current flows through the diode, and even if the potential of the node 6 drops, the charge is retained by the reverse connection of the diode (see the waveform diagram of the node 7 in FIG. 12).

  Even if the charge of the node 7 is lost due to some leakage current, the node 6 is swung at the timing of the clock H2 and is immediately charged again. For this reason, it is set so that it does not fall below (VSS− (Vth of Mtr8)) by Mtr9.

  The potential held at the node 7 is {(Amplitude High of the node 6) − (Vth of the diode)} when the potential of the node 6 is VSS. The amplitude of the node 6 is determined by C1 and other stray capacitance C0, and is represented by {(High of clock H2) × C1 / (C1 + C0)}.

  Further, in the ratioless type dynamic shift register shown in FIG. 11, the means for surely dropping the ground level to the ground level other than the high level signal at the output of each stage is MIS transistors Mtr4, Mtr5, It is composed of Mtr6, Mtr7, and Mtr8.

First, Mtr4 and Mtr5 will be described. The waveforms of the nodes 4 and 5 are as shown in the timing chart of FIG. 12 by the clocks H1 and H2, respectively.
When the clocks H1 and H2 are High, they are turned on and play the role of dropping the node to the gate signal line to the VSS level.

  In this case, when the node 2 is at a high level (when a high level signal is output to the gate signal line), Mtr6 and Mtr7 are turned on, and the nodes 4 and 5 are lowered to the VSS level, so that Mtr4 and Mtr5 are turned off. Become.

  MTr8 is connected so that the potential of node 4 does not become smaller than (VSS− (Vth of MTr8)). When the potential of this node is greatly lower than VSS, the amplitudes of the clocks H1 and H2 satisfy the Vth of Mtr4 and Mtr5 (the potential of VSS + Vth or more is required to turn on Mtr4 and Mtr5). This is because it is lost and meaningless.

  Further, in this embodiment, as shown in FIG. 11, the MIS transistor Mtr2 connected to the ground level of each output of each stage, the one operating at the output of the previous stage, one end having the ground level, and the other end having the capacitive element C1. And the other end of the MIS transistor Mtr2 is connected to the gate of the MIS transistor Mtr2. A capacitive element C2 is provided between the other end of the MIS transistor Mtr2 and the ground level.

  At the same time as node 3 falls to VSS level and node 7 becomes a floating node not connected to VSS level, node 2 is raised by the H1 clock.

At this time, the gate (node 7) may also be lifted by the gate-drain capacitance CG of the MIS transistor Mtr2, and the node 2 becomes conductive with VSS. In order to prevent this, a capacitor C2 is provided.
As a result, the potential increase of the node 7 becomes CG / (CG + C2 + other stray capacitance) times, and becomes a negligible value when C2 is larger than CG.

In each of the embodiments described above, for example, a dynamic ratioless shift register provided in a liquid crystal display device is shown. However, the present invention is not limited to this, and the present invention is also applicable to, for example, a dynamic ratioless shift register provided in an EL display device. Needless to say, it can be done.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a figure which shows the circuit diagram which shows one Example of the shift register formed on the board | substrate of the display apparatus by this invention, and its timing chart. It is a block diagram which shows one Example of the whole display apparatus by this invention. It is explanatory drawing which showed the capacity | capacitance etc. which the thin-film transistor which comprises the shift register formed on the board | substrate of the display apparatus by this invention produces. It is a circuit diagram which shows the other Example of the shift register formed on the board | substrate of the display apparatus by this invention. It is explanatory drawing which shows the other Example of the shift register formed on the board | substrate of the display apparatus by this invention. It is the figure which shows the circuit diagram which shows the other Example of the shift register formed on the board | substrate of the display apparatus by this invention, and its timing chart. It is the figure which shows the circuit diagram which shows the other Example of the shift register formed on the board | substrate of the display apparatus by this invention, and its timing chart. It is explanatory drawing which shows the other Example of the shift register formed on the board | substrate of the display apparatus by this invention. FIG. 4 is a circuit diagram showing an example of a dynamic ratioless shift register formed on a single crystal semiconductor layer and a timing chart thereof. It is explanatory drawing which showed the difference compared with a dynamic ratioless shift register on the case of forming a dynamic ratioless shift register on a glass substrate on a single crystal semiconductor layer. It is a circuit diagram which shows the other Example of the dynamic ratioless shift register used for the display apparatus by this invention. 12 is an input pulse timing chart of the circuit shown in FIG. FIG. 12 is a circuit diagram that is compared to clarify the features of the circuit shown in FIG. 11. It is an input pulse timing chart of the circuit shown in FIG. FIG. 14 is a waveform diagram for explaining disadvantages in the description of the circuit shown in FIG. 13 and the circuit shown in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel drive shift register 7 Memory drive shift register GL Gate signal line DL Drain signal line TFT Thin film transistor.

Claims (9)

Provided with a display drive circuit including a shift register on the substrate surface,
The shift register is composed of a transistor having a semiconductor layer,
The transistor includes a gate terminal, a first terminal, a second terminal, and a bootstrap capacitor provided between the gate terminal and the first terminal ,
A synchronization pulse is input to the first terminal,
A first switching element is provided between the gate terminal and the constant voltage power line, and the gate terminal is in a floating state when the first switching element is in an off state,
When the gate terminal is in a floating state due to a bootstrap effect, the voltage of the gate terminal rises as the synchronization pulse changes from a low level to a high level,
A second switching element is provided between the control terminal of the first switching element and the constant voltage power line;
When the second switching element is turned on, the voltage of the constant voltage power supply line is applied to the control terminal of the first switching element, and the first switching element is turned off.
By inputting a signal for turning on the transistor, the second switching element is turned on, and the first switching element is turned off, so that the gate terminal is in a floating state, and the gate terminal is booted. A display device characterized by improving strap efficiency.   The display device according to claim 1, wherein the transistor is formed on a glass substrate.   The display device according to claim 1, wherein the transistor is a thin film transistor formed on a glass substrate. Provided with a display drive circuit including a shift register on the substrate surface,
The shift register is composed of a transistor having a semiconductor layer,
The transistor includes a gate terminal, a first terminal, a second terminal, and a bootstrap capacitor provided between the gate terminal and the first terminal ,
A synchronization pulse is input to the first terminal,
A first switching element is provided between the gate terminal and the constant voltage power line, and the gate terminal is in a floating state when the first switching element is in an off state,
When the gate terminal is in a floating state due to bootstrap capacitance, the voltage of the gate terminal rises as the synchronization pulse changes from low level to high level,
A second switching element is provided between the control terminal of the first switching element and the constant voltage power line;
When the second switching element is turned on, the voltage of the constant voltage power supply line is applied to the control terminal of the first switching element, and the first switching element is turned off.
When the signal for turning on the transistor is input, the second switching element is turned on, and the first switching element is turned off, so that the gate terminal is in a floating state and is connected to the gate terminal . Display device characterized in that the bootstrap capacity increased .   The display device according to claim 4, wherein the transistor is formed on a glass substrate.   The display device according to claim 4, wherein the pre-transistor is a thin film transistor formed on a glass substrate. Provided with a display drive circuit including a shift register on the substrate surface,
The shift register includes a first transistor having a semiconductor layer, a second transistor, and a third transistor ,
The first transistor has a gate terminal, a first terminal, a second terminal, and a bootstrap capacitor provided between the gate terminal and the first terminal ;
A synchronization pulse is input to the first terminal of the first transistor,
The second transistor is provided between a gate terminal of the first transistor and a voltage line; the second transistor is in an off state; and the gate terminal of the first transistor is in a floating state;
When the gate terminal is in a floating state, the voltage of the gate terminal of the first transistor rises as the synchronization pulse changes from a low level to a high level,
The second transistor is in an on state to connect the gate terminal of the first transistor and a voltage line;
When the third transistor is turned on, the voltage of the voltage line is applied to the gate terminal of the second transistor, and the second transistor is turned off.
The display device is characterized in that the third transistor is turned on and the second transistor is turned off by the input of a signal for turning on the first transistor.   The display device according to claim 7, wherein the transistor is formed on a glass substrate.   The display device according to claim 7, wherein the transistor is a thin film transistor formed on a glass substrate.

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