JP2011039806A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce cost by not using a PIN type photodiode as a photosensor when installing the photosensor to a pixel, in a display panel using only single channel thin film transistors. <P>SOLUTION: A display device includes the display panel having a plurality of pixels, and at least one pixel of the plurality of pixels has the photosensor. The photosensor has a light reception part and a capacitance element, and has a light shield film shielding light emitted from the display panel on the opposite side of an observer side of the display panel of the light reception part. The light reception part is composed of an n type thin film transistor. In the photosensor, when Vg, Vs, and Vth respectively indicate a gate voltage, a source voltage, and a threshold voltage of the thin film transistor, an inverse bias voltage of Vg≤(Vth-2.0V+Vs) is inputted to a gate of the thin film transistor within a sensor light reception period, and a voltage of the capacitance element charged by a current flowing through the thin film transistor within the sensor light reception period is taken out as an output of the photosensor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device with a built-in optical sensor.

As with the resistive film system, the optical sensor type touch panel ranges from two touches that touch and not touch, to ones that can be used for scanners with tens or hundreds of tones depending on the light intensity. Possible uses.
In addition, the resolution of the sensor unit may be arranged in a necessary number only for a part touched as an icon on the screen, or may be arranged in each pixel (dot).
In any case, in the case where the optical sensor is built in the display panel, it is necessary to create a circuit necessary for display using a thin film transistor and also create an optical sensor. Thereby, unlike the resistive film method, a thin display panel can be realized.

FIG. 1 is a circuit diagram showing an equivalent circuit of a conventional liquid crystal display panel in which a photosensor is incorporated in one pixel.
As shown in FIG. 1, a conventional liquid crystal display panel in which an optical sensor is incorporated in one pixel includes a liquid crystal scanning line (also referred to as a gate line) GL and a video line (also referred to as a drain line or a source line) DL. In addition to the liquid crystal thin film transistor Tr1 and the storage capacitor element C, the optical sensor PS, the sensor control line (multiple cases) PSL, and the sensor output line OUT are included. In some cases, the sensor control line PSL and the sensor output line OUT can be shared with the scanning line GL for liquid crystal and the video line DL.
The output of the optical sensor PS is output outside the liquid crystal display panel and input to an external driver (liquid crystal data control IC or the like) DRV. Thereby, the output of the optical sensor PS is reflected on the liquid crystal display panel as liquid crystal data. In FIG. 1 and FIG. 11 described later, an arrow FA indicates the outside of the liquid crystal display panel.
FIG. 2 is a schematic cross-sectional view showing the cross-sectional structure of one pixel in which the photosensor shown in FIG. 1 is incorporated. FIG. 2A shows the cross-sectional structure of the thin film transistor Tr1, and FIG. 2B shows the photosensor PS. The cross-sectional structure of is shown.
In FIG. 2, S is a source, G is a gate, D is a drain, SM is a semiconductor layer, K is a cathode, and A is an anode. The optical sensor PS has a PIN structure, for example, and generates a current for light. Further, a light shielding film BPS is provided on the lower side of the optical sensor PS so that light from the backlight is not incident.

FIG. 3 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in which pixels in which photosensors are incorporated are arranged in an array.
The photosensor PS shown in FIG. 3 includes a PIN photodiode D1, a capacitive element C1 that converts the current of the PIN photodiode D1 into a voltage, and thin film transistors (Tr2, Tr3) of a readout circuit. Note that the thin film transistor Tr3 has one configuration for one vertical read line because it is used as a common use. CLK1 and CLK2 are clock lines, Vb is a bias line, and SGVD is a reference voltage line.
3 is extracted as shown in FIG. As shown in FIG. 4, the thin film transistors Tr2 and Tr3 form a source follower circuit, which impedance-converts a voltage change with respect to the light of the capacitive element C1 and outputs it as a sensor output SOUT.
In the circuit shown in FIG. 3, since the liquid crystal scanning line GL and the video line DL are not shared, the operation of the optical sensor can be performed asynchronously with the liquid crystal display.

FIG. 5 is a timing chart of the circuit shown in FIG. 4. Hereinafter, the operation of the circuit shown in FIG. 4 will be described with reference to FIG.
First, the voltage of the clock line CLK2 is set to a high level (hereinafter referred to as H level), and charges are accumulated in the capacitor C1. Then, the operation of the optical sensor (sense by light reception) starts from the time when the voltage of the clock line CLK2 becomes low level (hereinafter referred to as L level).
By irradiating the PIN photodiode D1 with light, the charge accumulated in the capacitor C1 is expelled to the clock line CLK2, and as a result, the voltage Vo of the capacitor C1 decreases. This is integrated by the sensor operating time, and the change in irradiation light is output as the voltage Vo of the capacitive element C1.
Next, when the clock line CLK1 becomes the H level voltage, the source follower circuit configured by the thin film transistors Tr2 and Tr3 starts to operate, and the voltage Vo of the capacitive element C1 at that time is supplied to the sensor output SOUT via the source follower circuit. It becomes.
Therefore, the sensor light receiving time is from the time when the voltage of the clock line CLK2 becomes L level to the time when the clock line CLK1 becomes H level.
Note that the wavy lines of the voltage Vo of the capacitive element C1 and the sensor output SOUT in FIG. 5 are outputs in a dark state where no light is irradiated, and this difference is a voltage change with respect to the irradiated light.

JP 2008-300530 A

In a liquid crystal display panel, as a pixel transistor of each pixel or a transistor of a peripheral circuit, a thin film transistor integrally formed on a substrate, that is, a thin film transistor using a polycrystalline silicon (polysilicon) layer as a semiconductor layer (hereinafter referred to as a polysilicon thin film transistor). Is known to use).
On the other hand, as shown in FIG. 2, a conventional photosensor built-in panel uses a PIN photodiode.
Therefore, if a liquid crystal display panel that uses only a single channel, for example, an n-type polysilicon thin film transistor, as a pixel transistor of each pixel or a peripheral circuit transistor, and a PIN photodiode is incorporated, the cost is increased. There was a problem.
That is, in order to create a P layer of a PIN type photodiode, “photo (exposure)” and “implantation” processes are essential. However, as a pixel transistor of each pixel or a transistor of a peripheral circuit, a single channel, for example, In a liquid crystal display panel using only an n-type polysilicon thin film transistor, it is necessary to newly add “photo (exposure)” and “implant” processes in order to create a PIN diode, resulting in an increase in cost. .
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide an optical sensor for a display panel that uses only a single-channel thin film transistor, when the optical sensor is incorporated into a pixel. An object of the present invention is to provide a technique that can reduce the cost without using a PIN photodiode.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A display device having a display panel having a plurality of pixels, at least one of the plurality of pixels having a photosensor, wherein the photosensor has a light receiving portion and a capacitive element. The light receiving portion is formed of an n-type thin film transistor, and when Vg, Vs, and Vth are respectively set to a gate voltage, a source voltage, and a threshold voltage of the thin film transistor, the gate of the thin film transistor is received within a sensor light receiving period. Is input with a reverse bias voltage of Vg <(Vth + Vs) (preferably a reverse bias voltage of Vg ≦ (Vth−2.0V + Vs)), and is charged by the current flowing through the thin film transistor during the sensor light receiving period. Is taken out as an output of the photosensor.
(2) When Vd is the drain voltage of the thin film transistor in (1), a voltage of (Vs + Vth + 1.0V) ≦ Vd ≦ (15.0V + Vs) is input to the drain of the thin film transistor within the sensor light receiving period. .

(3) A display device having a display panel having a plurality of pixels, wherein at least one of the plurality of pixels has a photosensor, and the photosensor has a light receiving portion and a capacitive element. The light receiving unit is composed of a p-type thin film transistor, and when Vg, Vs, and Vth are set to the gate voltage, the source voltage, and the threshold voltage of the thin film transistor, respectively, the gate of the thin film transistor is received within the sensor light receiving period. Is input with a reverse bias voltage of (Vth + Vs) <Vg (preferably a reverse bias voltage of (Vth + 2.0V + Vs) ≦ Vg), and the voltage of the capacitor element charged by the current flowing through the thin film transistor within the sensor light receiving period Is taken out as an output of the optical sensor.
(4) When Vd is the drain voltage of the thin film transistor in (3), (Vs-15.0V) ≦ Vd ≦ (Vs + Vth−1.0V) is applied to the drain of the thin film transistor within the sensor light receiving period. Input the voltage.
(5) In any one of (1) to (4), after the output of the photosensor is taken out after the sensor light receiving period has elapsed, the thin film transistor is turned on to reset the voltage charged in the capacitor.
(6) In any one of (1) to (5), the display panel includes a scanning line for inputting a scanning voltage to each pixel, and a gate of the thin film transistor is connected to the scanning line.

(7) A display device having a display panel having a plurality of pixels, wherein at least one of the plurality of pixels has a photosensor, and the photosensor has a light receiving portion and a capacitor. The light receiving unit is formed of a diode-connected thin film transistor, and when Vth is a threshold voltage of the thin film transistor, an absolute value of the threshold voltage of the thin film transistor satisfies 2.0 V ≦ | Vth | Then, the voltage of the capacitive element discharged by the current flowing through the thin film transistor within the sensor light receiving period is taken out as the output of the photosensor.
(8) In (7), after taking out the output of the photosensor after the sensor light receiving period has elapsed, the capacitive element is charged to a predetermined voltage.
(9) In any one of (1) to (8), the display panel has an output line for extracting the output of the photosensor, and the output of the photosensor is output from the output line after the sensor light receiving period has elapsed. Take out.

(10) In (9), a source follower circuit to which the voltage of the capacitive element is input is provided, and the output of the photosensor is output to the output line via the source follower circuit.
(11) In (9) or (10), the at least one pixel has a plurality of subpixels, and the display panel has a video line for inputting a video voltage to the subpixel, and the video line Also serves as the output line.
(12) In any one of (1) to (11), the thin film transistor is a thin film transistor whose semiconductor layer is a polycrystalline silicon layer.
(13) In any one of (1) to (12), the display panel is a liquid crystal display panel, the liquid crystal display panel is irradiated with backlight light emitted from a backlight, and the light receiving unit is A light shielding film for shielding backlight light is included.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, when a photosensor is incorporated in a pixel in a display panel that uses only a single channel thin film transistor, it is not necessary to use a PIN photodiode as the photosensor, so that the cost can be reduced.

It is a circuit diagram which shows the equivalent circuit of the liquid crystal display panel by which the photosensor was integrated in the conventional 1 pixel. It is a schematic cross section which shows the cross-section of 1 pixel incorporating the photosensor shown in FIG. It is a circuit diagram which shows the equivalent circuit of the liquid crystal display panel which has arrange | positioned the pixel incorporating an optical sensor in the array form. FIG. 4 is a circuit diagram showing the optical sensor unit and the readout circuit unit shown in FIG. 3 in an extracted manner. FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. 4. It is a graph which shows the relationship between the drain current (Id) and gate voltage (Vg) of a normal n-type polysilicon thin film transistor. It is a figure for demonstrating an example of the irradiation method of the light to an n-type polysilicon thin-film transistor. The relationship between the drain current (Id) and the gate voltage (Vg) of a normal n-type polysilicon thin film transistor and the drain current (Id) and the drain voltage (Vd) measured by changing the presence or absence of light irradiation and the drain voltage (Vd). It is a graph which shows the relationship. It is a circuit diagram which shows the optical sensor circuit of the Example of this invention. 10 is a timing chart of the photosensor circuit shown in FIG. 9. FIG. 10 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in which pixels in which the photosensor circuit shown in FIG. 12 is a timing chart of the photosensor circuit shown in FIG. 11. It is a figure for demonstrating the effect of the liquid crystal display panel of the Example of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Principle of the present invention]
As described above, in this specification, a thin film transistor using a polycrystalline silicon (polysilicon) layer as a semiconductor layer is referred to as a polysilicon thin film transistor.
FIG. 6 is a graph showing the relationship between the drain current (Id) and the gate voltage (Vg) of a normal n-type polysilicon thin film transistor.
In the n-type polysilicon thin film transistor, when light is applied from the outside in a state where a reverse bias voltage is input to the gate, the portion A in FIG. 6 changes depending on the amount of light. For example, the top gate is irradiated as shown in FIG. In FIG. 7, BPS is a light shielding film that blocks light incident from the backlight.

Actually, with respect to the portion A in FIG. 6, the presence or absence of light irradiation (illuminance is about 1000 lx) and the drain voltage (Vd) are changed (Vd = 1, 2, 3, 4, 5, 6 V), and the measured graph is shown in FIG. It is shown in a) and FIG.
FIG. 8A is a graph when the drain voltage (Vd) is fixed to 4.0 V (Vd = 4.0 V) and the gate voltage (Vg) is changed. The drain current (Id) shows a state in which light is irradiated and a state in which light is not irradiated (dark state).
FIG. 8B shows a state in which the gate voltage (Vg) is fixed at −5.0 (Vg = −5.0 V) and the drain voltage (Vd) is changed. The drain current (Id) is shown only in a state where light is irradiated.
The n-type polysilicon thin film transistor shown in FIG. 8 is a thin film transistor formed by a normal NMOS process described later, and the drain current (Id) changes due to light irradiation. Alternatively, the off-resistance (gate voltage Vg = negative resistance value) of the n-type polysilicon thin film transistor is lowered.
In the present invention, this change is used as an optical sensor. That is, in the present invention, the drain voltage (Vd) and the gate voltage (Vg) are set as follows from FIGS. 8 (a) and 8 (b).

(1) Gate voltage (Vg)
The portions B and C in FIG. 8A tend to increase the current value. This is probably because the gate voltage (Vg) approaches the threshold voltage (Vth) of the n-type polysilicon thin film transistor. If the threshold voltage (Vth) is defined as the gate voltage (Vg) at 1E-10A, the threshold voltage (Vth) is about 0.5 to 1 V, although not shown in FIG. It is.
As can be seen from FIG. 8A, when Vg ≦ −1.5 V, the drain current (Id) is constant without being influenced by the gate voltage (Vg). That is, when the gate voltage is 0 V (Vg = 0 V), there are electrons that cross the barrier under the gate, which deteriorates the light / plan ratio (S / N ratio) due to light reception, but the gate voltage (Vg) is further increased. By fixing to a negative voltage, the electrons that get over from the source can be suppressed, so that the drain current (Id) becomes constant without being influenced by the gate voltage (Vg).
This means that even if the threshold voltage (Vth) of the n-type polysilicon thin film transistor varies depending on the manufacturing process (size, film thickness, film quality, etc.), a large reverse bias voltage (negative voltage) is input to the gate voltage (Vg). This means that the drain current (Id) due to light is not affected.
Therefore, in the present invention, the gate voltage (Vg) is defined as the following equation (1).
Vg (V) ≦ Vth−2.0 + Vs (1)
Here, Vs is the source voltage of the n-type polysilicon thin film transistor, and when Vs = 0 V, equation (1) becomes equation (2).
Vg (V) ≦ Vth−2.0 (2)

(2) Drain voltage (Vd)
As can be seen from FIG. 8B, the change in the drain current (Id) is small even if the drain voltage (Vd) is changed regardless of the presence or absence of light irradiation. This means that the sensitivity does not change with respect to an unintended change in drain voltage (Vd) when an actual product is used.
Therefore, the drain voltage (Vd) may be larger than the threshold voltage (Vth) of the n-type polysilicon thin film transistor. However, in consideration of the stress on the n-type polysilicon thin film transistor, in the present invention, the drain voltage (Vd) is (3) It prescribes like a formula.
Vth + 1.0V + Vs ≦ Vd (V) ≦ 15V + Vs (3)
Further, when Vs = 0V, the expression (3) becomes the expression (4).
Vth + 1.0 ≦ Vd (V) ≦ 15V (4)

[Example 1]
FIG. 9 is a circuit diagram showing an optical sensor circuit according to an embodiment of the present invention. The optical sensor circuit of this embodiment is an optical circuit that uses an n-type polysilicon thin film transistor instead of a PIN diode.
In terms of circuit, only the n-type polysilicon thin film transistor (NMOS) is replaced in place of the PIN photodiode (D1) shown in FIG. 4, but the gate voltage (Vg) of the n-type polysilicon thin film transistor (NMOS) is externally applied. Must be entered.
In this embodiment, the drain current caused by light is voltage converted using the capacitive element C1 and then read by the source follower. However, the reading method is not limited to this, and other known examples are also used. It is also possible to use it.
FIG. 10 is a timing chart of the photosensor circuit of this embodiment. Hereinafter, the operation of the photosensor circuit of this embodiment will be described with reference to FIG.
[T1]
In order to set the capacitor C1 to the reference voltage (GND) in the initial state, the clock line CLK2 is set to the reference voltage (GND; L level) and the gate voltage (Vg) is set to VS. Accordingly, the n-type polysilicon thin film transistor (NMOS) is turned on, and the voltage (Vo) of the capacitive element C1 becomes the reference voltage (GND).

[T2]
Since the clock line CLK2 becomes Vd (H level) and the reverse bias voltage is input to the gate of the n-type polysilicon thin film transistor (NMOS), the capacitive element C1 holds the reference voltage (GND). Note that the voltage of Vd is the condition of the above-described equation (4). The gate voltage (Vg) is a voltage VL that is more negative than the reference voltage (GND). The voltage of VL is the condition of the above-mentioned formula (2).
From this point of time, the sensor light receiving period is started, and a leak current flows through the n-type polysilicon thin film transistor (NMOS) due to light irradiation. Due to this leakage current, charges are accumulated in the capacitive element C1, and a voltage of Vo is generated.
[T3]
When the clock line CLK1 is set to the voltage VD, the source follower including the thin film transistors Tr2 and Tr3 is activated, and the voltage Vo is read as an output.

FIG. 11 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in which pixels incorporating the photosensor circuit shown in FIG. 9 are arranged in an array.
In the liquid crystal display panel shown in FIG. 11, GL is a scanning line for liquid crystal (also referred to as a gate line), DL is a video line (also referred to as a drain line or a source line), Tr1 is a thin film transistor for liquid crystal, and C is a storage capacitor element. It is.
The photosensor circuit in one pixel has the above-described n-type polysilicon thin film transistor (NMOS). In order to drive the n-type polysilicon thin film transistor (NMOS), a clock line of CLK1 and CLK2, and a reference voltage of SGND A line is provided.
However, in the circuit shown in FIG. 11, the signal line for inputting the gate voltage Vg to the gate of the n-type polysilicon thin film transistor (NMOS) is shared with the scanning line GL for the liquid crystal writing thin film transistor (Tr1).
Normally, a signal line for inputting a gate voltage (Vg) to the gate of the n-type polysilicon thin film transistor (NMOS) is required by using an n-type polysilicon thin film transistor (NMOS) instead of the PIN photodiode (D1). As a result, the circuit area in the pixel increases and the aperture ratio decreases.
However, in the liquid crystal display panel shown in FIG. 11, the signal line for inputting the gate voltage Vg to the gate of the n-type polysilicon thin film transistor (NMOS) is shared with the scanning line GL for the liquid crystal writing thin film transistor (Tr1). It is possible to minimize the increase in the circuit area in the pixel and the decrease in the aperture ratio.

FIG. 12 is a timing chart of the photosensor circuit shown in FIG. Hereinafter, the operation of the photosensor circuit shown in FIG. 11 will be described with reference to FIG.
In a normal liquid crystal display panel, “the video voltage is about 0 to 5 V”, “the voltage of the scanning line GL connected to the gate of the thin film transistor Tr1 for writing liquid crystal is about −1.5 to 10 V” It is.
The reason why the voltage on the L level side of the scanning line GL is lower than 0 V is to prevent the video voltage for other pixels from being written to the unselected pixel via the thin film transistor Tr1 of the unselected pixel. The negative voltage lower than 0V is intentionally set for the purpose of surely turning off the unselected thin film transistor Tr1.
Therefore, the drain voltage (Vd) for the n-type polysilicon thin film transistor (NMOS), that is, the voltage of the clock line CLK2 may be a voltage having an amplitude of 0 to 4V.
For example, as an example, if the threshold voltage (Vth) of an n-type polysilicon thin film transistor (NMOS) is 0.5 V (Vth = 0.5 V), as shown in FIG. 12, “Vg = 10.5 V, Vd = 0 V The capacitor C1 is reset to 0V, and light can be received during the sensor light receiving period with “Vg = −1.5V, Vd = 4V”.
This is an operation satisfying the above-described equations (1) and (3).

FIG. 13 is a diagram for explaining the effect of the liquid crystal display panel of the present embodiment. Hereinafter, the effect of the liquid crystal display panel of the present embodiment will be described with reference to FIG.
FIG. 13A shows a standard process flow (gate process excerpt) of an n-type polysilicon thin film transistor (NMOS), and FIG. 13B shows a PIN type photodiode (D1) in the standard process shown in FIG. It is a figure which shows the process flow (gate process excerpt) of the photodiode (PIN) which added the creation process.
This will be described below along the procedure of FIG.
(A) Procedure (1)
In the process procedure (1) of FIG. 13A, the semiconductor layer polysilicon (SM) is formed / processed, the resist (RG) is removed, the gate oxide film (GI) is formed, and the N threshold ion implantation (arrow YA) is performed. Executed.
In the process procedure (1) of FIG. 13B, polysilicon (SM) formation / processing, resist (RG) removal, gate oxide film (GI) formation, N threshold exposure, N threshold ion implantation (arrow YA), Resist (RG) removal is performed.
In this way, in the procedure (1), two flows of “N threshold exposure” and “resist removal” are added in the photodiode (PIN) process shown in FIG. 13B. This is because ions are not implanted into the I layer portion of the photodiode (PIN).
(B) Procedure (2)
In step (2) of FIG. 13A, gate (G) formation / processing, N-electrode ion implantation (arrow YB), and resist (RG) removal are performed.
Similarly, in step (2) of FIG. 13B, gate (G) formation / processing, N electrode ion implantation (arrow YB), and resist (RG) removal are executed.

(C) Procedure (3)
In step (3) of FIG. 13A, NM region (region A in FIG. 13) ion implantation (arrow YC) is performed.
In step (3) of the process of FIG. 13B, NM region photo, NM region ion implantation (arrow YC), and resist (RG) removal are executed.
Thus, in the procedure (3), in the process of the photodiode (PIN) shown in FIG. 13B, two flows of “NM region photo” and “resist removal” are added.
The NM ion implantation is an ion implantation for a so-called LDD structure. The LDD structure is located in the middle (region B in FIG. 13) between the polysilicon under the thin film transistor gate and the N-electrode polysilicon, and the width is usually about 1 μm.
This LDD portion is generally used for implanting NM ions that are thinner than the N electrode (about 1 to 2 digits) to prevent reliability deterioration due to electric field concentration at the drain end.
In a photodiode (PIN), when an LDD is formed between an I layer and an N layer and between an I layer and a P layer, the sensitivity of the photodiode is reduced, which is not suitable for a diode. Therefore, a resist (RG) covering the photodiode (PIN) is required, and a process is added.
In addition, since the shadow of the area | region B of FIG. 13 which the N electrode ion of a procedure (2) does not implant is made, it becomes an area | region only of NM ion. The area A in FIG. 13 is the sum of N electrode ions and NM ions, but NM ions are almost N electrode ion areas because the implantation amount is one to two orders of magnitude smaller than N electrode ions.

(D) Procedure (4)
In procedure (4) of FIG. 13B, P electrode photo, P electrode ion implantation (arrow YD), and resist removal are executed.
As described above, in the procedure (4), in the process of the photodiode (PIN) shown in FIG. 13B, three flows of “P electrode photo”, “P electrode ion implantation”, and “resist removal” are added. . This is a process applied only to the P layer of the photodiode (PIN).
The region C in FIG. 13 is an N layer, and the region D is an I layer where no ion implantation is performed. The region E in FIG. 13 contains N electrode ions in step (2), but functions as a P electrode by adding more P electrode ions (for example, 3 to 10 times) than the N electrode ions. It is known to do.
Thus, in the photodiode (PIN) process shown in FIG. 13B, three exposure steps and one implantation step are added.
As described above, when the PIN photodiode (D1) is used for the light receiving portion of the optical sensor circuit, only a single channel, for example, an n-type polysilicon thin film transistor is used as a pixel transistor of each pixel or a peripheral circuit transistor. In such a liquid crystal display panel, a process for producing a PIN photodiode (D1) is added, which causes an increase in cost.
In contrast, in the present embodiment, an n-type polysilicon thin film transistor is used as a pixel transistor of each pixel, a transistor of a peripheral circuit, or a light receiving part of a photosensor circuit, so that a PIN type photodiode (D1) is formed. There is no need to do.
Therefore, in this embodiment, the cost can be reduced as compared with a liquid crystal display panel in which pixels in which a photosensor using a PIN photodiode (D1) is incorporated are arranged in an array.

For example, when the PIN diode is replaced by an n-type polysilicon thin film transistor, it is known that the n-type polysilicon thin film transistor is diode-connected, that is, the gate and drain of the n-type polysilicon thin film transistor are connected.
However, when the diode-connected n-type polysilicon thin film transistor is actually measured instead of the PIN photodiode, the operating point is a point of Vg = 0 V in FIG. This is a state in which the thin film transistor S has started to be turned on, and the threshold voltage (Vth) of the diode-connected n-type polysilicon thin film transistor in which the “bright / dark ratio (S / N ratio)” cannot be made large varies. In this case, there is a problem that a stable current value with respect to illuminance cannot be obtained.
However, by increasing the threshold voltage (Vth) of the diode-connected n-type polysilicon thin film transistor, it is possible to obtain the same effect as in this embodiment. That is, the threshold voltage (Vth) only needs to satisfy 2.0 ≦ Vth.
In this case, the method for increasing the threshold voltage (Vth) requires implantation into an n-type polysilicon thin film transistor, which increases the number of processes. However, a pixel in which a photosensor using a PIN photodiode (D1) is incorporated. The cost can be reduced as compared with the liquid crystal display panel arranged in an array.

In the above description, the embodiment using the n-type polysilicon thin film transistor as the thin film transistor for the optical sensor has been described. However, the liquid crystal using only the p-type polysilicon thin film transistor as the pixel transistor of each pixel or the transistor of the peripheral circuit. If it is a display panel, it is also possible to use a p-type polysilicon thin film transistor as a thin film transistor for an optical sensor.
However, when a p-type polysilicon thin film transistor is used as the thin film transistor for the photosensor, the gate voltage (Vg) and the drain voltage (Vd) must satisfy the following expressions (5) and (6).
Vg (V) ≧ Vth + 2.0 + Vs (5)
Vs-15.0 ≦ Vd (V) ≦ Vs + Vth−1.0 (6)
Similarly, the threshold voltage (Vth) satisfies Vth ≦ −2.0 when the same effect as in this embodiment is obtained by increasing the threshold voltage (Vth) of the diode-connected p-type polysilicon thin film transistor. do it.
In the above-described embodiment, the sensor control line PSL and the sensor output line OUT can be shared with the liquid crystal scanning line GL and the video line DL. For example, each pixel may have a plurality of subpixels, and a video line that inputs a video voltage to the subpixel may also serve as the sensor output line OUT.
Further, in the above description, the embodiment in which the present invention is applied to a liquid crystal display panel has been described. However, the present invention is not limited to this, and the present invention can also be applied to an organic EL display panel or the like. is there.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

GL scanning line (gate line)
DL video line (drain line or source line)
Tr1, Tr2, Tr3 Thin film transistor C Retention capacitance PS Photo sensor PSL Sensor control line OUT Sensor output line DRV driver S Source G Gate D Drain SM Semiconductor layer K Cathode A Anode BPS Light shielding film D1, PIN Photo diode C1 Capacitance element CLK1, CLK2 Clock line Vb bias line SGND reference voltage line NMOS n-type polysilicon thin film transistor RG resist

Claims (15)

A display panel having a plurality of pixels;
At least one of the plurality of pixels is a display device having a photosensor,
The optical sensor includes a light receiving unit,
A capacitive element;
The light receiving portion is composed of an n-type thin film transistor,
When Vg, Vs, and Vth are the gate voltage, source voltage, and threshold voltage of the thin film transistor, respectively, a reverse bias voltage of Vg <(Vth + Vs) is input to the gate of the thin film transistor within the sensor light receiving period,
A display device characterized in that a voltage of the capacitor element charged by a current flowing through the thin film transistor during the sensor light receiving period is taken out as an output of the photosensor.   2. The display device according to claim 1, wherein a reverse bias voltage of Vg ≦ (Vth−2.0 V + Vs) is input to the gate of the thin film transistor within the sensor light receiving period.   3. The voltage of (Vs + Vth + 1.0V) ≦ Vd ≦ (15.0V + Vs) is input to the drain of the thin film transistor within the light receiving period of sensor when Vd is the drain voltage of the thin film transistor. The display device described in 1. A display panel having a plurality of pixels;
At least one of the plurality of pixels is a display device having a photosensor,
The optical sensor includes a light receiving unit,
A capacitive element;
The light receiving portion is composed of a p-type thin film transistor,
When Vg, Vs, and Vth are the gate voltage, source voltage, and threshold voltage of the thin film transistor, respectively, a reverse bias voltage of (Vth + Vs) <Vg is input to the gate of the thin film transistor within the sensor light receiving period.
A display device characterized in that a voltage of the capacitor element charged by a current flowing through the thin film transistor during the sensor light receiving period is taken out as an output of the photosensor.   5. The display device according to claim 4, wherein a reverse bias voltage of (Vth + 2.0V + Vs) ≦ Vg is input to the gate of the thin film transistor within the sensor light receiving period.   When Vd is a drain voltage of the thin film transistor, a voltage of (Vs-15.0V) ≦ Vd ≦ (Vs + Vth−1.0V) is input to the drain of the thin film transistor within a light receiving period of the sensor. The display device according to claim 5.   The output of the optical sensor is taken out after the sensor light receiving period has elapsed, and then the thin film transistor is turned on to reset the voltage charged in the capacitor element. The display device described in the item. The display panel has a scanning line for inputting a scanning voltage to each pixel,
The display device according to claim 1, wherein a gate of the thin film transistor is connected to the scanning line. A display panel having a plurality of pixels;
At least one of the plurality of pixels is a display device having a photosensor,
The optical sensor includes a light receiving unit,
A capacitive element;
The light receiving unit is composed of a diode-connected thin film transistor,
When Vth is the threshold voltage of the thin film transistor, the absolute value of the threshold voltage of the thin film transistor satisfies 2.0V ≦ | Vth |
A display device characterized in that a voltage of the capacitor element discharged by a current flowing through the thin film transistor within the light receiving period of the sensor is taken out as an output of the photosensor.   The display device according to claim 9, wherein the capacitive element is charged to a predetermined voltage after the output of the optical sensor is taken out after the sensor light receiving period has elapsed. The display panel has an output line for extracting the output of the photosensor,
11. The display device according to claim 1, wherein an output of the photosensor is taken out from the output line after the sensor light receiving period has elapsed. A source follower circuit to which the voltage of the capacitive element is input;
The display device according to claim 11, wherein an output of the photosensor is output to the output line via the source follower circuit. The at least one pixel has a plurality of sub-pixels;
The display panel has a video line for inputting a video voltage to the sub-pixel,
The display device according to claim 11, wherein the video line also serves as the output line.   14. The display device according to claim 1, wherein the thin film transistor is a thin film transistor whose semiconductor layer is a polycrystalline silicon layer. The display panel is a liquid crystal display panel,
The liquid crystal display panel is irradiated with backlight light emitted from a backlight,
The display device according to claim 1, wherein the light receiving unit includes a light shielding film that shields the backlight light.

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