JP2004023364A - Internal signal observation method for prototyping system and programmable device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an internal signal observation method for a prototyping system and a programmable device, which can take out easily an internal signal of the programmable device and improve the quality of the internal signal observation. <P>SOLUTION: Switches between devices 9a and 9b are arranged between input/output terminals of FPGAs 51a-51c. A logic analyzer/vector sending control unit 4 supplies a sampling clock during concatenation of the switches between devices 9a and 9b, and a first emulation is conducted to store an output signal in a memory 2a. Thereafter, the switches between devices 9a and 9b are disconnected under the condition that the FPGAs 51a-51c output an internal signal, the data stored in memory 2a is supplied to the FPGAs 51a-51c as vector data, and a second emulation is conducted to store an output signal in a memory 2b. The original output signal and internal signal stored in the memories 2a and 2b are displayed in a composite fashion on a display screen of a host 8, and the quality of the observation is improved. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an emulator and a prototyping system for verifying the operation of a circuit used in an LSI development stage using a hardware device, and more particularly to a prototyping system capable of observing a signal inside a circuit without being limited to the number of terminals of the circuit. And a method for observing an internal signal of a programmable device.
[0002]
[Prior art]
In the conventional LSI development, at the stage of logic design, RTL (Register Transfer Level) description in HDL (Hardware Description Language) language, RTL simulation by software simulator, and bug extraction and correction are performed. However, in recent years, the circuit scale of the LSI has become large, and simulation using a software simulator has a heavy load on a computer device such as a workstation that executes this software, so that sufficient verification cannot be performed.
[0003]
Under such circumstances, operation verification has been performed by hardware devices called prototyping systems and emulators. These prototyping systems and emulators are very similar, with no clear separation criteria. Usually, a device that mounts a wiring control device (or wiring method) between a plurality of FPGAs and a logic analyzer module (or a connector for connecting a commercially available logic analyzer) is called a prototyping system, and the emulator further debugs the device. The one with enhanced functions. Hereinafter, a prototyping system including the emulator will be referred to.
[0004]
FIG. 13 is a configuration diagram showing a conventional prototyping system. The prototyping system 50 of this configuration example is configured by a plurality of modules of a plurality of FPGAs 51 (51a to 51c) as verification circuits, a user clock / reset signal generator 52, a logic analyzer 53, and a host interface (I / F) 54. I have.
[0005]
A software tool is incorporated in the host 55 composed of a personal computer or the like. This software tool divides and synthesizes the verification circuit for each of the FPGAs 51a to 51c, and creates circuit information that can be downloaded to the prototyping system 50.
[0006]
In the conventional method shown in this figure, the wiring between the FPGAs 51a to 51c is performed using fixed wiring on a printed wiring board without using a wiring control device, and the connection relationship between the FPGAs 51a to 51c is It is decided. Therefore, the circuit division by the prototyping system 50 is performed so as to satisfy the specifications defined by this connection relationship. In FIG. 13, wiring between the FPGA 51a and the FPGA 51c is omitted for simplification of description.
[0007]
The download of circuit information from the host 55 to the FPGAs 51 (51a to 51c), which are verification circuits, the setting of the frequency of the user clock for the user clock / reset signal generator 52, and the upload of logic analyzer data from the logic analyzer 53 to the host 55 are performed by the host. This is performed via the I / F 54.
[0008]
The logic analyzer 53 includes a memory 56 for storing observation waveforms, a sampling clock generator 57 for generating a sampling clock, a logic analyzer control unit 58, and a switching device 59. Although the illustrated switching device 59 is described as a physical switch, the switching device 59 is generally formed of an electrical switching device such as a transistor.
[0009]
As the sampling clock generated by the sampling clock generator 57, a clock much faster than the user clock is used. The upper limit of the user clock operating in the prototyping system 50 is about 10 MHz, whereas the sampling clock generated by the sampling clock generator 57 uses 100 MHz to 1 GHz. This high-speed clock enables timing analysis.
[0010]
The logic analyzer 53 assigns a signal to be observed to an unused terminal of each of the FPGAs 51a to 51c in order to observe a signal output to a terminal of the FPGA 51a to 51c, and observes an internal signal through the unused terminal. The unused terminals in the illustrated example are 51A in the FPGA 51a and 51B in the FPGA 51b.
[0011]
FIG. 14 is an internal configuration diagram of the verification circuit when performing the state analysis. A configuration example in which only state analysis, that is, state analysis of a signal for each user clock is performed is shown. Logic analyzer macro circuits 61a to 61c are arranged in advance in the user circuits 60a to 60c inside the FPGA 51, respectively. The output of each of the logic analyzer macro circuits 61a to 61c is converted into a serial signal by the logic analyzer control serial converter 62, and a signal is extracted from the unused terminal or the JTAG interface. According to this method, the number of observation signals inside the FPGA 51 is not limited to the number of unused terminals, and a larger number of observation signals than the number of unused terminals can be extracted.
[0012]
[Problems to be solved by the invention]
However, in the configuration shown in FIG. 13, the signals that can be observed by the logic analyzer 53 are limited to the signals output to the terminals of the FPGAs 51a to 51c. The signal could not be observed, making debugging difficult.
[0013]
Further, in the configuration shown in FIG. 14, since it is necessary to operate the logic analyzer macro circuits 61a to 61c inside the FPGA, it is impossible to input a high-speed sampling clock. That is, in the configuration shown in FIG. 14, state analysis is performed using a low-rate user clock as a sampling clock, and timing analysis cannot be realized.
[0014]
In the case of the prototyping system 50 that targets the FPGAs 51a to 51c as the verification circuit, the circuits are operated on the actual FPGAs 51a to 51c. Here, when there is a malfunction in the operation of the FPGAs 51a to 51c, it is highly likely that the malfunction is related to timing, such as clock racing or hazard. Therefore, in debugging such a system, the logic analyzer 53 needs to execute timing analysis. Therefore, with the configuration in which the state analysis is performed by the logic analyzer 53 shown in FIG. 14, the cause may not be able to be determined.
[0015]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a prototyping system capable of easily extracting an internal signal of a programmable device and improving observability of the internal signal, and an internal signal observation of the programmable device. The aim is to provide a method.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides mounting means for mounting a plurality of programmable devices such as an FPGA, a logic analyzer which supplies a sampling clock to the programmable device to obtain an operation waveform, and an operation of the programmable device. After the circuit information is created by dividing and synthesizing the design circuit of the programmable device for verification, the circuit information is downloaded to the programmable device, and the host is configured to execute and control the logic analyzer. When creating the circuit information, the host arranges the circuit information of the selector for selecting either the original output signal or the internal signal by correcting the circuit information of the design circuit. The mounting means includes an inter-device switch for connecting or disconnecting input / output terminals of a plurality of programmable devices, and the logic analyzer operates the device in the connected state when the inter-device switch is disconnected. Control means for emulating while supplying vector data to an input terminal of each programmable device via an inter-switch.
[0017]
According to the present invention, an original output signal and an internal signal are switched and output from an output terminal of a programmable device such as an FPGA, and the first and second emulation results are obtained. When outputting the internal signal, the connection between the input / output terminals of the plurality of FPGAs is disconnected, and the first emulation result is supplied to the FPGA as vector data, so that the second emulation result for obtaining the internal signal is obtained. Can be obtained exactly as in the connection. The first and second emulation results are displayed and output to the host. Since the host synthesizes and displays these waveforms, the host can observe the original output signal and the internal signal on the same screen, thereby facilitating the analysis work.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Preferred embodiments of a prototyping system and a method for observing an internal signal of a programmable device according to the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of the prototyping system of the present invention.
[0019]
The prototyping system 1 includes a memory 2 for storing observation waveforms, a sampling clock generator 3 for generating a sampling clock, a logic analyzer (logic analyzer) / vector transmission control unit 4, and a logic analyzer 10 including modules of a switching device 5, It comprises a user clock / reset signal generator 6 and a host interface (I / F) 7. The prototyping system 1 is connected to a host 8 via a host I / F7. The functions of the host 8 are the same as those of the host 55 described above, and control including start / stop of the operation of the prototyping system 1, creation of a netlist, display of a signal waveform on a screen, and the like are performed by a software tool.
[0020]
The memory 2 may be constituted by a plurality of memories 2a and 2b for respective functions as shown in the drawing, or may be constituted so that a storage area is divided into two and used within a single memory 2. The switching device 5 includes four (5a to 5d) in the illustrated configuration example.
[0021]
The switching device 5a mainly switches storage or upload of data in the memory 2b. The common contact is connected to the memory 2b, the contact 1 is connected to the host I / F 7, and the contact 2 is connected to the switching device 5b. It is connected to the. When switching to the second side, the output signals of the FPGAs 51a to 51c are stored in the memory 2b via the switching device 5b. By switching to the first side, the data (output signals of the FPGAs 51a to 51c) stored in the memory 2b is output (uploaded) to the host 8 side.
[0022]
The switching device 5b is mainly for switching the output signal of each of the FPGAs 51a to 51c to the memory 2a or the memory 2b and outputting the same, and has a common contact at an input / output terminal (line between the input / output terminal) of each of the FPGAs 51a to 51c. The contact 1 is connected to the contact 2 of the switching device 5a, and the contact 2 is connected to the contact 2 of the switching device 5c. When switching to the 1 side, the output signals of the respective FPGAs 51a to 51c are output to the switching device 5a (memory 2b) side. When switching to the second side, the output signals of the FPGAs 51a to 51c are output to the switching device 5c (memory 2a) side.
[0023]
The switching device 5c is mainly for switching data storage or upload to the memory 2a. The common contact is connected to the contact 1 of the switching device 5d, the contact 1 is connected to the host I / F 7, and the contact 2 Are connected to the contact 2 of the switching device 5b. When switching to the 1 side, the output signal of the switching device 5d (memory 2a) is uploaded to the host 8 side. When switching to the second side, the output signals of the FPGAs 51a to 51c are output to the switching device 5d (memory 2a) via the switching device 5b.
[0024]
The switching device 5d switches whether to supply data stored in the memory 2a as vector data to each of the FPGAs 51a to 51c, and a common contact is connected to the memory 2a, and a contact 1 is connected to the switching device. The contact 2 is connected to the common contact 5c, and the contact 2 is connected to each contact 1 of the inter-device switches 9a and 9b. This switching device 5d works in conjunction with the inter-device switches 9a and 9b. When switching to the 1 side, the output signals of the FPGAs 51a to 51c are stored in the memory 2a. Further, data stored in the memory 2a can be uploaded to the host 8. When switching to the second side, data stored in the memory 2a (output signals of the FPGAs 51a to 51c) can be output to the FPGAs 51a to 51c as vector data to the FPGAs 51a to 51c via the inter-device switches 9a and 9b. To
[0025]
The logic analyzer / vector transmission control unit 4 controls the output of the user clock by the user clock / reset signal generator 6, and selectively switches the switching devices 5a to 5d. By switching the switching devices 5a to 5d,
(1) The output signals of the FPGAs 51a, 51b, 51c are selectively stored in the memories 2a, 2b when the operation of the verification circuit is verified.
(2) The output signals stored in the memory 2a are input as vector data to the FPGAs 51a, 51b, and 51c again.
(3) The output signals stored in the memories 2a and 2b are uploaded to the host 8. These details will be described later.
[0026]
Output terminals and input terminals of the respective terminals of the FPGAs 51a, 51b, and 51c are fixedly determined. Switching devices (switches between devices) 9a, 9b for connecting / disconnecting input / output signals are arranged between output terminals and input terminals of the FPGAs 51a, 51b, 51c. The wiring from the FPGA 51b and the FPGAs 51a and 51c to the FPGAs 51a and 51b is omitted for convenience of explanation, but is actually wired via the same switching device as described above.
[0027]
FIG. 2 is a diagram illustrating a circuit configuration example of an FPGA as a verification circuit. FIG. 2 illustrates one output terminal F1_5 of the FPGA 51a. The output terminal F1_5 outputs an original output signal OUT1 defined for the FPGA via the plurality of FF instances 12a and 12b and the logic circuit 12c. The internal signal NET1 for observing the output of the preceding stage (the logic circuit 12c) of the FF instance 12b is connected to the selector 12d, and the output signal OUT1 or the output signal OUT1 based on the selection signal SEL for the selector 12d. Switching is performed such that the internal signal NET1 is selectively output from the output terminal F1_5.
[0028]
By the way, the logic analyzer / vector transmission control unit 4 outputs the above selection signal SEL to the FPGAs 51a to 51c, the switching devices 5a to 5d, and the switches 9a and 9b, and controls the switching in each of them. Next, the operation of the prototyping system 1 having the above configuration will be described for each process.
[0029]
(Step 1) First, the logic analyzer / vector transmission control unit 4 connects the FPGAs 51a to 51c in a connection relationship realizing the originally designed circuit operation according to an instruction from the host 8. Specifically, the state shown in FIG. 1 is set, that is, the switching device 5d is set to the contact 1 side, the switching devices 5b and 5c are set to the contact 2 side, and the inter-device switches 9a and 9b are set to the contact 2 side. . With this setting, the input / output terminals of the FPGAs 51a to 51c are connected via the inter-device switches 9a and 9b.
[0030]
(Step 2) Next, the logic analyzer / vector transmission control unit 4 enables the user clock / reset signal generator 6 according to an instruction from the host 8, and starts the circuit operation of the FPGAs 51a to 51c. At this time, the output signal OUT1 is output from the output terminal F1_5 shown in FIG. 2 as the output signal of each of the FPGAs 51a to 51c. This output signal OUT1 is stored in the memory 2a via the switching devices 5b → 5c → 5d.
[0031]
(Step 3) Next, the logic analyzer / vector transmission control unit 4 stops emulation according to an instruction from the host 8, sets the switching device 5d to the contact 2 side, switches the inter-device switches 9a and 9b to the contact 1 side, and switches -Switch the device 5b to the contact 1 side. As a result, the wiring between the FPGAs is disconnected by the inter-device switches 9a and 9b. FIG. 3 is a diagram illustrating a switching state (part 1) of each switch.
[0032]
(Step 4) Next, the logic analyzer / vector transmission controller 4 enables the user clock / reset signal generator 6 according to an instruction from the host 8 and restarts emulation. At this time, the selection signal SEL is input to the selector 12d (see FIG. 2) of each of the FPGAs 51a to 51c in addition to the switching device 5d and the inter-device switches 9a and 9b, and the output signals of the FPGAs 51a to 51c are internally The signal, that is, NET1 is output from the output terminal F1_5. This output signal is stored in the memory 2b via the switching device 5b → 5a.
[0033]
(Step 5) At the same time, the logic analyzer / vector transmission control unit 4 transmits the data at the time of the previous emulation stored in the memory 2a (the above step 2) from the switching device 5d to the inter-device switches 9a and 9b. This is supplied to the input terminals of the FPGAs 51a to 51c. The FPGA performs one circuit operation designed by the operation of all three FPGAs 51a to 51c. Here, by using the previous sampling data as an input vector, even if the wiring between the FPGAs 51a to 51c is disconnected at this time, it can be apparently operated as one circuit. it can.
[0034]
(Step 6) According to the instruction from the host 8, the logic analyzer / vector transmission control unit 4 sets the switching devices 5a, 5c, and 5d to the contact 1 side after the emulation is completed, and stores the data stored in the memories 2a and 2b into the host. Upload to 8. FIG. 4 is a diagram illustrating a switching state (part 2) of each switch.
[0035]
(Step 7) The host 8 treats the sampling data in the memories 2a and 2b as data sampled by the same emulation, and displays a waveform on a display screen. This allows the operator to observe the state of the internal signals of the FPGAs 51a to 51c in association with the original external output signals.
[0036]
By sequentially executing the processes based on the steps described above, it is possible to observe the internal signal even when there are no unused terminals in the FPGAs 51a to 51c.
[0037]
FIG. 5 is a flowchart showing a procedure for creating circuit information for download. As described above, according to the present invention, the selector is inserted into the FPGA, and the selector is inserted into a netlist that creates circuit information downloadable to the prototyping system 1. That is, the present invention is different from the conventional one in that a selector insertion process is added.
[0038]
First, the software tool (tool) incorporated in the host 8 executes a circuit dividing process (step S1) for creating an RTL 20 in which the RTL description in the HDL language is divided for each programmable device of the FPGA. Thereafter, the generated RTL 20 is synthesized, and a synthesis process (step S2) for obtaining a netlist 21 for each programmable device is executed. Thereafter, an internal signal to be observed as logic analyzer data is selected from the netlist 21 of the design circuit, and an original output signal (OUT1 described above) and a selected internal signal (OUT1 described above) are selected to realize the operation of the design circuit. NET1) is inserted (step S3).
[0039]
In this selector insertion processing, an input port for controlling a selection signal (SEL described above) for selecting which of an original output signal and an internal signal to output from the outside of the programmable device is inserted. Is used. As a result, the netlist created in step S2 is modified to create a netlist 23 having a function after the selector is inserted. In the first embodiment, by using the inter-FPGA wiring information 22, the placement and wiring processing (step S 4) is performed on the net list 23 after the selector insertion, and the net output information 24 and the download circuit of the prototyping system 1 are executed. Information 25 is obtained.
[0040]
The inter-FPGA wiring information 22 used in the arrangement and wiring processing in step S4 is a signal between the FPGAs 51a to 51c corresponding to the fact that the wiring between the FPGAs 51a to 51c in the prototyping system 1 of the present invention is fixed. Used to associate names. The pin assignment of the input / output terminals of each of the FPGAs 51a to 51c is performed based on the inter-FPGA wiring information 22.
[0041]
FIG. 6 is a flowchart showing the procedure of the selector insertion process (step S3). First, the input processing of the netlist 21 is performed (step S31), the circuit diagram is created based on the information of the netlist 21 (step S32), and the created circuit diagram is displayed on the display screen of the host 8 (step S33). . The operator selects a net of the internal signal to be observed from the displayed circuit diagram (Step S34). The tool of the host 8 stores the selected net. Thereafter, the tool of the host 8 automatically executes the following processing.
[0042]
After selecting the net of the internal signal to be observed, the tool searches the output port and the instance of the output source (step S35). According to the circuit configuration example shown in FIG. 2, at this stage, the output terminal F1_5 is connected to the FF instance 12b, and the output signal OUT1 does not exist.
[0043]
(1) Thereafter, a selector insertion process (step S36) is performed. First, the output instance is changed to a selector, and the net of the original instance output is changed to an arbitrary name. According to FIG. 2, the selector 12d is inserted, the net name of the output of the FF instance 12b is changed to OUT1, and the output of the selector 12d is set to the output terminal F1_5.
(2) Connect the net of the selected internal signal to the other selector input. According to FIG. 2, the internal signal NET1 is connected to the selector 12d.
[0044]
(3) The selector selection signal SEL is added to the input port of the netlist and connected to the selector terminal of the selector instance. According to FIG. 2, the selection signal SEL is connected to the selector 12d.
(4) The netlist 23 after the selector insertion is output as a file.
(5) At the same time, a file of net output information 24 describing which internal terminal is connected to which output terminal is output. The net output information 24 is used when displaying the sampling data of the logic analyzer.
[0045]
The selector insertion processing (step S36) returns to step S31 for all the input netlists 21 and is repeated (step S37: No), and when the processing of all the input netlists 21 is completed (step S37: Yes) ), And proceeds to the placement and wiring processing (step S4 shown in FIG. 5).
[0046]
The host 8 downloads the download circuit information 25 created by the above processing to the prototyping system 1 (FPGAs 51a to 51c that are programmable devices) of the present invention. At this time, the switching devices 5a to 5d and the switches 9a and 9b are switched so that the data (output signals) of the FPGAs 51a to 51c are input to the memory 2a and the wiring between the FPGAs 51a to 51c is connected.
[0047]
In addition, the logic analyzer / vector transmission controller 4 (see FIG. 1) enables the user clock / reset signal generator 6 to start emulation. As described above, the emulation is performed twice by changing the setting (storage of data in the memory 2a in step 2 and storage of data in the memory 2b in step 4). In the first and second emulations, it is necessary to completely match the sampling timing with the timing of the generation and reset release of the user clock, so that the user clock / reset signal generator 6 is controlled by the logic analyzer / vector transmission controller 4. Is to take over.
[0048]
FIG. 7 is a diagram showing waveforms during the first (step 2) emulation. The reset timing is omitted. Sampling is started from the rising edge of the first sampling clock after the user clock / reset signal generator 6 is enabled. In the parentheses of the signal names shown in FIG. 7, for example, the signal F1_3 (F2I1) is the same signal because the output terminal F1_3 of the FPGA 51a and the input terminal F2I1 of the FPGA 51b are connected at this stage (see FIG. 1). Will be displayed as In the emulation operation at this time, the user clock is also input to the memory 2a as sampling data.
[0049]
Then, in step 3, the emulation is stopped, and the switching devices 5b and 5d and the switches 9a and 9b are switched. As a result, the connection between the FPGAs 51a to 51c is disconnected as shown in FIG. 3, the output signals of the FPGAs 51a to 51c are input to the memory 2b as sampling data, and the sampling data of the memory 2a is input to the input terminals of the FPGAs 51a to 51c. It is supplied as vector data. At this time, the output terminals of the FPGAs 51a to 51c output the internal signal NET1 by the SEL signal.
[0050]
FIG. 8 is a diagram showing a waveform at the time of the second (step 4) emulation. In the drawing, only the output signal of the output terminal F1_5 of the FPGA 51a is shown as sampling data to be input to the memory 2b for convenience. At this time, the output terminal F1_5 outputs the internal signal NET1 (see FIG. 2). The waveforms of the signals F2I1 to F3_3 are vector data supplied from the memory 2a to the FPGAs 51b and 51c, respectively.
[0051]
The timing of generation of addresses in the memory 2a differs between the time of sampling and the time of vector transmission. In FIG. 7, the signal F1_3 (F2I1) is first sampled as the value 1 at the memory address 3. In order for the value to be "1" at the time of sampling, the value of the actual signal is "1" before the rise of the sampling clock. Therefore, if the value of "1" is transmitted at the same timing of the sampling clock at the time of transmitting the vector data, the value of "1" is actually supplied after the rise of the sampling clock. Input data will be supplied one sampling clock later than time. Therefore, when transmitting the vector in the second emulation, the logic analyzer / vector transmission control unit 4 changes the address of the memory 2a so as to transmit the data one sampling clock before the sampling, as shown in FIG. To set.
[0052]
After the emulation is completed, the sampling data in the memories 2a and 2b is uploaded to the host 8. The host 8 displays a waveform on a display screen using a logic analyzer waveform display tool which is a part of a software tool.
[0053]
FIG. 9 is a flowchart of a waveform display process executed by the logic analyzer waveform display tool. The host 8 uploads data from the memories 2a and 2b of the prototyping system 1 in the above-described step 7 (steps S11 and S12). At this time, for the data obtained by reading the memory 2a, the terminal names of the FPGAs 51a to 51c are displayed on the screen as signal names as they are.
[0054]
On the other hand, with respect to the data obtained by reading the memory 2b, the internal signal assigned to the terminal name is searched with reference to the net output information 24, and the obtained internal signal is converted into a signal name (step S13). A signal composite waveform file 26 is generated by combining the data obtained from the memories 2a and 2b with the signal names assigned. When displaying a waveform, the signal composite waveform file 26 is read (step S14) and displayed on the display screen of the host 8 (step S15).
[0055]
FIG. 10 is a diagram showing an example of a waveform display screen. The data uploaded from the memory 2a is displayed as signals F1_3, F1_4,..., F201,. In the illustrated example, the data uploaded from the memory 2b is the only data output from the output terminal F1_5 of the FPGA 51a. However, since the signal F1_5 is actually a waveform in which the internal signal NET1 is output, it is converted to NET1 and displayed.
[0056]
An example of the analysis of the waveform displayed on the screen will be described. For example, in the waveform shown in FIG. 10, the signal F1_5 changes to the value “1” at the first rising edge of the user clock, and then the signal F1_5 changes to the state of “1”. Has remained. However, it is assumed that it is abnormal (malfunction) that F1_5 originally changes to the value “1” at the timing when the user clock rises. Here, it can be confirmed that the internal signal NET1 synthesized and displayed on the same screen has a hazard near the rising edge of the user clock. Thus, it is possible to easily confirm that the cause of the malfunction of the signal F1_5 is "hazard of the internal signal NET1" by displaying the signal combination.
[0057]
Even if the cause of the operation failure is due to the timing, the same failure phenomenon generally occurs even if the same emulation is repeated many times. At this time, a similar problem occurs in the operation inside the FPGA.
[0058]
Focusing on this point, the present invention emulates the original output signal and the internal signal from the single output terminal of the verification circuit, respectively, and synthesizes and displays the signals on a single display screen, thereby facilitating signal analysis. It is something that can be done. In addition, since the selector is inserted inside the FPGA to switch the internal signal and output from a single output terminal, unlike a configuration in which a macro circuit or a serial conversion unit is provided inside the FPGA and state analysis is performed, a higher speed is achieved. Timing analysis using a simple clock can be performed, and debugging can be easily performed.
[0059]
In addition, since the internal signal can be observed without using the unused terminal of the FPGA which is a verification circuit, the number of observation of the internal signal is not limited to the number of unused terminals as in the related art. Internal signals for the number of output terminals can be observed.
[0060]
(Embodiment 2)
FIG. 11 is a block diagram showing the configuration of the second embodiment of the prototyping system according to the present invention. The second embodiment has a configuration in which the number of switching devices 5 (5a to 5d) used in the first embodiment is reduced to two.
[0061]
The switch 15a mainly switches the output signal of each of the FPGAs 51a to 51c to the memory 2a or the memory 2b and outputs the same. , Contact 1 is connected to the memory 2b, and contact 2 is connected to the memory 2a. When switching to the first side, the output signals of the FPGAs 51a to 51c are output to the memory 2b. When switching to the second side, the output signals of the FPGAs 51a to 51c are output to the memory 2a via the switch 15b.
[0062]
The switch 15b switches whether to supply data stored in the memory 2a as vector data to each of the FPGAs 51a to 51c or not. The common contact is connected to the memory 2a, and the contact 1 is connected to the contact 2 of the switch 15a. , And the host I / F 7, and the contact 2 is connected to each contact 1 of the inter-device switches 9a and 9b. This switch 15b is interlocked with the switches 9a and 9b between the devices. When switching to the 1 side, the output signals of the FPGAs 51a to 51c are stored in the memory 2a via the switch 15a. Further, data stored in the memory 2a can be uploaded to the host 8. When switching to the second side, data stored in the memory 2a (output signals of the FPGAs 51a to 51c) can be output to the FPGAs 51a to 51c as vector data to the FPGAs 51a to 51c via the inter-device switches 9a and 9b. To
[0063]
Note that the memory 2b is directly connected to the host I / F 7, and is configured to be able to upload data stored in the memory 2b. Hereinafter, steps of the prototyping system 1 according to the second embodiment will be described.
[0064]
(Step 1) First, the logic analyzer / vector transmission control unit 4 connects the FPGAs 51a to 51c in a connection relationship realizing the originally designed circuit operation according to an instruction from the host 8. Specifically, the state shown in FIG. 11 is set, that is, the switch 15a is set to the contact 2 side, the switch 15b is set to the contact 1 side, and the inter-device switches 9a and 9b are set to the contact 2 side. With this setting, the input / output terminals of the FPGAs 51a to 51c are connected via the inter-device switches 9a and 9b.
[0065]
(Step 2) Next, the logic analyzer / vector transmission control unit 4 enables the user clock / reset signal generator 6 according to an instruction from the host 8, and starts the circuit operation of the FPGAs 51a to 51c. At this time, the output signal OUT1 is output from the output terminal F1_5 shown in FIG. 2 as the output signal of each of the FPGAs 51a to 51c. This output signal OUT1 is stored in the memory 2a via the switches 15a → 15b.
[0066]
(Step 3) Next, the logic analyzer / vector transmission control unit 4 stops emulation according to an instruction from the host 8, sets the switch 15b to the contact 2 side, sets the switches 9a and 9b between the devices to the contact 1 side, and sets the switch 15a to Switch to contact 1 side. As a result, the wiring between the FPGAs is disconnected by the inter-device switches 9a and 9b. FIG. 12 is a diagram illustrating a switching state of each switch.
[0067]
(Step 4) Next, the logic analyzer / vector transmission controller 4 enables the user clock / reset signal generator 6 according to an instruction from the host 8 and restarts emulation. At this time, the selection signal SEL is input to the selector 12d (see FIG. 2) of each of the FPGAs 51a to 51c in addition to the switch 15b and the switches 9a and 9b between the devices. That is, NET1 is output from the output terminal F1_5. This output signal is stored in the memory 2b via the switch 15a.
[0068]
(Step 5) At the same time, the logic analyzer / vector transmission control unit 4 transmits the data at the time of the previous emulation stored in the memory 2a (the above-described step 2) from the switch 15b to the FPGAs 51a to It supplies to the input terminal of 51c. The FPGA performs one circuit operation designed by the operation of all three FPGAs 51a to 51c. Here, by using the previous sampling data as an input vector, even if the wiring between the FPGAs 51a to 51c is disconnected at this time, it can be apparently operated as one circuit. it can.
[0069]
(Step 6) In response to an instruction from the host 8, the logic analyzer / vector transmission control unit 4 returns to the switch state shown in FIG. 11 after emulation is completed, sets the switch 15a to the contact 2 side, and sets the switch 15b to the contact 1 side. Then, the data stored in the memories 2a and 2b is uploaded to the host 8.
[0070]
The sampling data is also input to the host I / F 7 during the emulation. However, in order for the host 8 to take in the data during the emulation, the host 8 needs to be capable of transferring data at a speed higher than the sampling speed. Realistically impossible. Therefore, after emulation is completed, the host 8 sets a sufficiently slow clock to the sampling clock generator 3 and reads (uploads) data via the host I / F 7.
[0071]
(Step 7) The host 8 treats the sampling data in the memories 2a and 2b as data sampled by the same emulation, and displays a waveform on a display screen. This allows the operator to observe the state of the internal signals of the FPGAs 51a to 51c in association with the original external output signals.
[0072]
According to the above configuration, the same processing can be executed by reducing the number of switches 15 compared to the first embodiment.
[0073]
Various processes executed by the software tool of the host for operation verification in the prototyping system described above can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This program is recorded on various recording media, and is executed by being read from the recording medium by a computer. The program may be a transmission medium that can be distributed via a network such as the Internet.
[0074]
(Appendix 1) In a prototyping system that verifies the operation of a programmable device,
The programmable device comprises a selector for selectively switching and outputting an original output signal defined from an output terminal of the programmable device and an internal signal of a desired internal circuit,
A prototyping system comprising a logic analyzer that controls the selector to perform emulation in a state where either the original output signal or the internal signal is output.
[0075]
(Supplementary Note 2) A mounting means for mounting a plurality of the programmable devices,
The logic analyzer according to claim 1, wherein the logic analyzer controls the selector to execute emulation in a state where either the original output signal or the internal signal of each of the plurality of programmable devices is output. Prototyping system as described.
[0076]
(Supplementary Note 3) Mounting means for mounting a plurality of programmable devices from which circuit information is downloaded, a logic analyzer that supplies a sampling clock to the programmable devices to obtain an operation waveform, and a host that controls execution of the logic analyzer In the prototyping system configured by
The programmable device comprises a selector for selectively switching and outputting an original output signal defined from an output terminal of the programmable device and an internal signal of a desired internal circuit,
The prototyping system, wherein the host corrects the circuit information by inserting selector information of the selector into the circuit information.
[0077]
(Supplementary Note 4) The host divides and synthesizes a design circuit of the programmable device to create circuit information for verifying operation of the programmable device, and downloads the created circuit information to the programmable device. The prototyping system according to claim 3, wherein:
[0078]
(Supplementary Note 5) The mounting means includes an inter-device switch for connecting or disconnecting input / output terminals of the plurality of programmable devices,
The logic analyzer further comprises control means for executing the emulation in a state where vector data is supplied to the input terminal of each of the programmable devices via the inter-device switch when the inter-device switch is disconnected. The prototyping system according to any one of Supplementary Notes 2 to 4.
[0079]
(Supplementary Note 6) The control means samples output signals of the plurality of programmable devices according to a sampling clock when the inter-device switch is connected and disconnected, and outputs each of the output signals at the time of connection and disconnection. The prototyping system according to Supplementary Note 5, wherein the prototyping system is stored separately.
[0080]
(Supplementary Note 7) The control means stores, as a first emulation result, output signals of the plurality of programmable devices obtained when the inter-device switch is connected,
When the inter-device switch is disconnected, the first emulation result is supplied as the vector data to the input terminal of each of the programmable devices through the inter-device switch, and the obtained outputs of the plurality of programmable devices are output. 7. The prototyping system according to claim 5, wherein the signal is stored as a result of the second emulation.
[0081]
(Supplementary Note 8) The logic analyzer includes a first storage unit that stores a result of the first emulation;
8. The prototyping system according to claim 7, further comprising a second storage unit that stores a result of the second emulation.
[0082]
(Supplementary Note 9) The control unit switches the selector of each of the programmable devices at the time of the second emulation for disconnecting the switch between the devices, and outputs an internal signal output from an output terminal of each of the programmable devices. Is obtained as the result of the second emulation.
[0083]
(Supplementary note 10) Any one of Supplementary notes 5 to 9, wherein the control unit changes the clock timing of the vector data to the input terminal of each of the programmable devices and supplies the same to the input terminal of the second emulation. A prototyping system as described in.
[0084]
(Supplementary Note 11) The logic analyzer uploads a plurality of executed emulation results to a host,
11. The prototyping system according to claim 1, wherein the host includes a waveform synthesizing unit that synthesizes and displays the plurality of uploaded emulation results on the same display screen.
[0085]
(Supplementary Note 12) The waveform synthesizing unit displays all output signals output from the output terminals of the programmable device based on the first emulation result, and displays the programmable device for the second emulation result. 12. The prototyping system according to claim 11, wherein only the internal signal output from the output terminal is extracted and synthesized and displayed together with all the output signals.
[0086]
(Supplementary Note 13) An emulation result from the programmable device to each of the first and second storage units is provided between the programmable device, the inter-device switch, and the first and second storage units. Flow, data flow for storing the vector data from the inter-device switch to the programmable device, and emulation results from the first and second storage means to the host. 13. The prototyping system according to any one of appendices 8 to 12, further comprising: a switch for switching a data flow for uploading the data to any one of the plurality of data streams, wherein the switch is controlled by the control unit.
[0087]
(Supplementary note 14) The host according to any of Supplementary notes 1 to 13, wherein the host assigns different signal names to the original output signal and the internal signal output from a single output terminal of the programmable device. A prototyping system according to any one of the preceding claims.
[0088]
(Supplementary Note 15) The host assigns a signal name of the original output signal to an output signal output from an output terminal of the programmable device by the first emulation,
The output signal output from the output terminal of the same output terminal of the programmable device by the second emulation is changed to the signal name of the internal signal. Prototyping system according to any one of the above.
[0089]
(Supplementary Note 16) A method of observing an internal signal of a programmable device in which a plurality of programmable devices are mounted and operation verification is performed,
A circuit information creating step of creating circuit information of the design circuit for each programmable device,
A selector insertion step of executing a process of inserting selector information for selectively outputting an internal signal of the programmable device into the circuit information to correct the circuit information created by the circuit information creation step;
A download step of downloading the selector-inserted circuit information obtained in the selector insertion step to the prototyping system,
Wherein the internal signal of the programmable device can be observed in the prototyping system.
[0090]
(Supplementary Note 17) In the selector inserting step, a selection is made to select which of an original output signal output from the same output terminal provided in the programmable device and an internal signal is output for the circuit information. 18. The method of observing an internal signal of a programmable device according to claim 16, wherein a process of arranging an input port for controlling a signal from outside the programmable device is performed.
[0091]
(Supplementary Note 18) A plurality of programmable devices having a selector for selectively switching and outputting an original output signal defined from an output terminal and an internal signal of a desired internal circuit are mounted, and the original output signal is provided. And a method for observing an internal signal of a programmable device for observing an internal signal,
Switching a selector of the programmable device to an output signal output side of the main body and supplying a sampling clock to the programmable device in a state where input / output terminals of the plurality of programmable devices are connected; A first emulation result obtaining step of obtaining an output signal of the device;
Switching the selector of the programmable device to an internal signal output side, and supplying the first emulation result as vector data to the programmable device in a state where input / output terminals of the plurality of programmable devices are disconnected; A second emulation result obtaining step of obtaining an internal signal of the programmable device;
A method for observing an internal signal of a programmable device, comprising:
[0092]
(Supplementary Note 19) A storing step of storing the first and second emulation results, respectively.
A display output step of displaying and outputting the first and second emulation results, respectively;
19. The method for observing an internal signal of a programmable device according to supplementary note 18, comprising:
[0093]
(Supplementary note 20) The method of observing an internal signal of a programmable device according to supplementary note 19, wherein the display output step includes a process of combining and displaying the first and second emulation results on the same display screen. .
[0094]
(Supplementary note 21) The display output step includes a process of assigning different signal names to the original output signal and the internal signal output from the same output terminal of the programmable device. 3. The method for observing an internal signal of a programmable device according to claim 1.
[0095]
【The invention's effect】
According to the present invention, internal signals for the number of output terminals of a verification circuit such as an FPGA can be observed, and an original output signal or an internal signal is output from an output terminal in an operation state in which a sampling clock is supplied to the verification circuit. As a result, timing analysis can be performed. Further, since the original output signal and the internal signal can be synthesized and displayed on the same display screen, it is possible to easily observe a defect of the verification circuit. As a result, there is an effect that the debugging efficiency can be remarkably improved, the debugging period can be shortened, and the development period of an LSI including a verification circuit can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a prototyping system according to the present invention.
FIG. 2 is a diagram illustrating a circuit configuration example of an FPGA as a verification circuit.
FIG. 3 is a diagram illustrating a switching state (part 1) of each switch.
FIG. 4 is a diagram illustrating a switching state (part 2) of each switch.
FIG. 5 is a flowchart showing a procedure for creating circuit information for download.
FIG. 6 is a flowchart illustrating a procedure of a selector insertion process.
FIG. 7 is a diagram showing a waveform at the time of a first emulation.
FIG. 8 is a diagram showing a waveform at the time of the second emulation.
FIG. 9 is a flowchart of a waveform display process executed by a logic analyzer waveform display tool.
FIG. 10 is a diagram showing an example of a waveform display screen.
FIG. 11 is a block diagram illustrating a configuration of a prototyping system according to a second embodiment of the present invention.
FIG. 12 is a diagram illustrating a switching state of each switch.
FIG. 13 is a configuration diagram showing a conventional prototyping system.
FIG. 14 is an internal configuration diagram of a verification circuit when performing state analysis.
[Explanation of symbols]
1 Prototyping system
2 (2a, 2b) memory
3 Sampling clock generator
4 Logic analyzer / vector transmission control unit
5 (5a-5d, 15a, 15b) switching device
6 User clock / reset signal generator
7 Host interface
8 Host
9a, 9b Switch between devices
10 Logic analyzer
12a, 12b FF instance
12c logic circuit
12d selector
20 RTL
21 Netlist
22 Wiring information between FPGA
23 Netlist after selector insertion
24 Net output information
25 Download circuit information
26 Signal synthesis waveform file
51a-51d FPGA

Claims (10)

In a prototyping system that verifies the operation of programmable devices,
The programmable device comprises a selector for selectively switching and outputting an original output signal defined from an output terminal of the programmable device and an internal signal of a desired internal circuit,
A prototyping system comprising a logic analyzer that controls the selector to perform emulation in a state where either the original output signal or the internal signal is output. It is constituted by mounting means for mounting a plurality of programmable devices from which circuit information is downloaded, a logic analyzer for supplying an operation waveform by supplying a sampling clock to the programmable device, and a host for controlling the execution of the logic analyzer. In a prototyping system,
The programmable device comprises a selector for selectively switching and outputting an original output signal defined from an output terminal of the programmable device and an internal signal of a desired internal circuit,
The prototyping system, wherein the host corrects the circuit information by inserting selector information of the selector into the circuit information. The mounting means includes an inter-device switch for connecting or disconnecting input / output terminals of the plurality of programmable devices,
The logic analyzer further comprises control means for executing the emulation while supplying vector data to the input terminals of the programmable devices via the inter-device switch when the inter-device switch is disconnected. The prototyping system according to claim 2. The control means samples output signals of the plurality of programmable devices at the time of connection and disconnection of the inter-device switch according to a sampling clock, and individually stores the output signals at the time of connection and at the time of disconnection. The prototyping system according to claim 3, wherein The control means stores, as a first emulation result, output signals of the plurality of programmable devices obtained when the inter-device switch is connected,
When the inter-device switch is disconnected, the first emulation result is supplied as the vector data to the input terminals of the programmable devices through the inter-device switch, and the obtained outputs of the plurality of programmable devices are obtained. The prototyping system according to claim 3, wherein the signal is stored as a result of the second emulation. The logic analyzer uploads the plurality of executed emulation results to a host,
The prototyping system according to any one of claims 1 to 5, wherein the host includes a waveform synthesizing unit that synthesizes and displays the plurality of uploaded emulation results on the same display screen. Between the programmable device, the inter-device switch, and the first and second storage units, emulation results are separately stored in the first and second storage units from the programmable device. A data flow for causing the vector data to be supplied from the inter-device switch to the programmable device; and a data flow for uploading an emulation result from the first and second storage means to the host. 7. The prototyping system according to claim 6, further comprising a switch for switching the flow of the prototyping to any one, and wherein the switch is controlled by the control unit. A method for observing an internal signal of a programmable device in which a plurality of programmable devices are mounted and operation verification is performed,
A circuit information creating step of creating circuit information of the design circuit for each programmable device,
A selector insertion step of executing a process of inserting selector information for selectively outputting an internal signal of the programmable device into the circuit information to correct the circuit information created by the circuit information creation step;
A download step of downloading the selector-inserted circuit information obtained in the selector insertion step to the prototyping system,
Wherein the internal signal of the programmable device can be observed in the prototyping system. A plurality of programmable devices having a selector for selectively switching and outputting an original output signal defined from an output terminal and an internal signal of a desired internal circuit are mounted, and the original output signal and the internal signal are output. A method for observing an internal signal of a programmable device for observing,
Switching a selector of the programmable device to an output signal output side of the main body and supplying a sampling clock to the programmable device in a state where input / output terminals of the plurality of programmable devices are connected; A first emulation result obtaining step of obtaining an output signal of the device;
Switching the selector of the programmable device to an internal signal output side, and supplying the first emulation result as vector data to the programmable device in a state where input / output terminals of the plurality of programmable devices are disconnected; A second emulation result obtaining step of obtaining an internal signal of the programmable device;
A method for observing an internal signal of a programmable device, comprising: A storage step of storing the first and second emulation results, respectively;
A display output step of displaying and outputting the first and second emulation results, respectively;
The method for observing an internal signal of a programmable device according to claim 9, comprising:

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