JP4890086B2 - Circuit verification apparatus and circuit verification method - Google Patents

Description

  The present invention includes a programmable element capable of reconfiguring a logic circuit such as a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD), and for verifying the operation of the circuit configured in the programmable element. The present invention relates to a circuit verification device and a circuit verification method.

  Conventionally, when designing a digital circuit, HDL (Hardware Description Language) such as VHDL or Verilog-HDL is used. A designer describes a digital circuit in HDL, verifies an RTL (Register Transfer Level) circuit using a simulator, and then performs logic synthesis to generate a gate level circuit. After that, the generated gate level circuit is verified again. If no error is found by the verification, a layout of the circuit is created using a placement and routing tool, and semiconductor ICs are manufactured based on this layout. Is called.

  When verifying a circuit, simulation is performed by giving an RTL or gate level circuit and a test pattern of the circuit to the simulator. However, recent digital circuits have become large-scale and require a huge amount of time for the simulation. There's a problem. For example, when performing a simulation for one second with an actual machine, a simulation time of several tens of hours to several days may be required. Therefore, there is a problem that test patterns that can be simulated are limited, and sufficient verification cannot be performed.

  In order to solve this problem, a circuit verification apparatus including a programmable element such as FPGA or CPLD can be used for circuit verification. An FPGA includes a large number of logic blocks and a storage element for connecting wiring between the logic blocks. An element using memory technology such as SRAM or flash memory is used as the storage element, and the designer can change the circuit configuration by changing the data stored in the storage element. When verifying using a programmable element, the circuit can be operated in real time, so the verification time can be shortened, and more test patterns can be input to operate the circuit. An error can be detected with certainty. When an error is discovered by performing circuit verification, the designer can correct the circuit and reconfigure the corrected circuit into a programmable element to perform verification. By using such a circuit verification apparatus, there is an advantage that work such as circuit verification and correction, that is, so-called debugging work can be speeded up and the circuit development period can be shortened.

  In Patent Document 1, a storage element for storing a logical value is provided in each node of a logic circuit configured in an FPGA, and according to designation of a node address from the outside and designation of a read timing from the outside. By reading the value from the storage element provided at the node of the specified node address at the specified read timing and outputting it to the outside, it is possible to freely select the node in the logic circuit and read the value A field programmable gate array that can improve the debugging efficiency of a logic circuit has been proposed.

  In Patent Document 2, a plurality of FPGAs are provided, and a predetermined number of terminals among the terminals of each FPGA are always secured as probe terminals, and the logic circuit is divided and divided according to the number of terminals. When logically synthesizing a logic circuit and creating data for each FPGA, a plurality of data for connecting the internal node of the divided logic circuit to the probe terminal is created in advance, and the internal node to be probed An emulation system has been proposed in which a circuit is configured in an FPGA by selecting data corresponding to the change in the circuit. In this emulation system, the time required for logic synthesis accompanying the change of the probed node can be shortened, and the work efficiency of circuit debugging can be improved.

In Patent Document 3, a target circuit and a trace macro unit that selects a group from an internal signal group in the target circuit by a select signal that can be controlled from the outside and outputs the selected group of signals to the outside in the FPGA. Configured and output signals are sent as data from the target board on which the FPGA is mounted to the slave board part, and between the slave board part and the pod box part connected to the PC (personal computer) by the high-speed receiver driver and transmitter driver Have proposed an internal signal monitoring device for transferring data. In this internal signal monitoring apparatus, even when the number of output terminals for monitoring the FPGA mounted on the target board is small, it is possible to monitor the internal signals more than the number of terminals from the PC at high speed.
JP-A-5-90949 Japanese Patent Laid-Open No. 10-312309 JP 2003-271812 A

  In the case of a circuit verification device having a conventional configuration, a node in the circuit is connected to an output terminal of the FPGA to output a signal to the outside, and the output signal is an observation device such as a logic analyzer (hereinafter referred to as logic analyzer) or an oscilloscope. By using this, the designer can verify by observing the internal signal of the circuit. However, since the number of nodes in the circuit is larger than the number of output terminals of the FPGA and signals of all nodes cannot be observed, when changing the connection between the nodes in the circuit and the output terminals of the FPGA, The logic synthesis of the HDL circuit described by the designer needs to be performed again. The larger the circuit scale, the longer the logic synthesis takes, and the problem is that the efficiency of circuit verification deteriorates.

  Patent Documents 1 to 3 propose an invention for improving the deterioration of the efficiency of circuit verification caused by performing the logic synthesis again as described above. However, in the field programmable gate array described in Patent Document 1, it is necessary to provide a storage element at each node of the logic circuit in the FPGA. Therefore, the number of necessary storage elements increases as the circuit scale increases and the number of nodes increases. There is a problem that increases. Therefore, when the circuit scale becomes large, an FPGA having a larger capacity is required or a plurality of FPGAs must be used, and the cost for performing verification increases.

  The emulation system described in Patent Document 2 generates data by performing logic synthesis of a plurality of patterns in advance so that an internal node of a circuit configured in the FPGA can be connected to a probe terminal of the FPGA. When changing a node for observing a signal, the change is made by reconfiguring the FPGA using data in which a desired node is connected to a probe terminal. For this reason, when the number of internal nodes is large and the number of probe terminals is small, it is necessary to prepare a lot of data in advance, and more EEPROM or the like for storing this data is required. Since more time is required to logically synthesize a lot of data, there is a problem that the verification efficiency is deteriorated.

  The internal signal monitoring device described in Patent Document 3 has an advantage that there is no need to perform logic synthesis when changing an observation node because the internal signal is selected by a multiplexer and output to the outside of the FPGA. Requires a lot of hardware, such as a target board on which an FPGA is mounted, a slave board connected to the target board, and a pod box unit that is connected to a PC operated by the designer and performs high-speed communication with the slave board There is a problem that the cost is high.

  Further, not only when the internal signal to be observed is changed, but also when the circuit is verified, there is a case where the designer must re-synthesize the logic of the RTL circuit described in HDL. For example, when a circuit to be designed is composed of a plurality of circuit blocks, and there are a plurality of candidate circuit blocks as one of the circuit blocks, the designer operates each circuit block to verify it. In some cases, it is desired to select and adopt one circuit block most suitable for the design conditions. In this case, it is necessary to perform logic synthesis for the number of candidate circuit blocks. For example, when there is a constant that defines the operation of the circuit and it is desired to change the constant, it is necessary to perform logic synthesis again. In Patent Documents 1 to 3, such a case is not mentioned, and logic synthesis must be performed again.

  In addition, when an error occurs by performing circuit verification, the designer needs to specify a circuit portion that generates an error from all the circuits. This is a more difficult task as the circuit scale becomes larger, and a circuit verification apparatus having programmable elements such as FPGAs should have a more advanced designer support function for narrowing down the circuit parts that generate errors from all circuits. desired.

  The present invention has been made in view of such circumstances, and its object is to provide a circuit to be verified in a programmable element, an auxiliary circuit for inputting and outputting signals to the circuit to be verified, and a circuit to be verified. And a specified value storage unit for storing a specified value that defines the operation of the auxiliary circuit, and the control unit changes the specified value in response to an instruction from an external device to operate the circuit to be verified and the auxiliary circuit. It is an object of the present invention to provide a circuit verification device that allows a designer to verify various circuit operations only by changing a specified value in a specified value storage unit via a control unit.

  Another object of the present invention is to provide a circuit block to be verified when the circuit to be verified has a plurality of circuit blocks such as a circuit block to be verified and an input side circuit block that provides an input signal to the circuit block to be verified. An input value to be input to and a specified value for determining whether or not to provide this input value to the circuit block to be verified are stored in the specified value storage unit, and either an input signal of the input side circuit block or an input value of the specified value storage unit Is a circuit verification device that can perform verification by giving an arbitrary input value determined by the designer to a specific circuit block of the circuit to be verified by selecting the signal according to the specified value and giving it to the circuit block to be verified Is to provide.

  Another object of the present invention is that the circuit to be verified has the same functions as the circuit block to be verified, the output side circuit block for obtaining the output signal from the circuit block to be verified, and the circuit block to be verified. When there are a plurality of circuit blocks such as alternative circuit blocks that can be substituted for the circuit block to be verified, the output signal of either the circuit block to be verified or the alternative circuit block depends on the specified value stored in the specified value storage unit It is an object of the present invention to provide a circuit verification apparatus that can perform verification by replacing circuit blocks without performing logic synthesis again by selecting and supplying the selected circuit block to an output side circuit block.

  Another object of the present invention is to provide an input signal from either the test pattern generation circuit in the programmable element or the input terminal of the programmable element to the circuit to be verified according to the stored specified value. Thus, the test pattern generation circuit can be used to provide various test patterns to the circuit to be verified, and the output signal from a device or device outside the programmable element can be supplied to the circuit to be verified for verification. It is an object of the present invention to provide a circuit verification device that can be used.

  In addition, another object of the present invention is to perform observation without performing logic synthesis again by selecting and outputting the internal signal of the circuit to be verified according to the specified value stored in the specified value storage unit. Another object of the present invention is to provide a circuit verification apparatus that can perform verification by changing an internal signal to be verified.

  Another object of the present invention is to change the specified value of the specified value storage unit using a clock signal faster than the clock signal for operating the circuit to be verified, and change the internal signal to be output. Accordingly, it is an object of the present invention to provide a circuit verification apparatus capable of observing more internal signals during the operation of one clock of the circuit to be verified.

  In addition, another object of the present invention is to provide an observation value storage unit for storing the value of the selected and output internal signal, so that a test can be performed without using an observation device such as a logic analyzer or an oscilloscope. An object of the present invention is to provide a circuit verification device that can read a value from an observation value storage unit and verify an internal signal after operating a circuit to be verified by a pattern.

  Another object of the present invention is to provide a counter that operates in response to a clock signal for operating the circuit to be verified, and to observe an observation value when the counter value matches the start counter value stored in the specified value storage unit. A circuit capable of automatically storing the value of an internal signal within a period required for verification by starting storage of a value in the storage unit and ending the storage when the value matches the end counter value It is to provide a verification device.

  Another object of the present invention is to store the expected value of the internal signal of the circuit to be verified in the expected value storage unit, and stop the operation of the circuit to be verified when the internal signal and the expected value do not match. It is an object of the present invention to provide a circuit verification device that allows a designer to easily grasp the timing at which an error occurs in a circuit to be verified.

  Another object of the present invention is to provide a counter that operates in response to a clock signal that operates the circuit to be verified, and to stop the operation of the circuit to be verified every predetermined value of the counter. An object of the present invention is to provide a circuit verification device that can perform so-called step execution by operating a circuit to be verified little by little.

  Another object of the present invention is to easily stop the circuit to be verified by stopping the supply of the clock signal to the circuit to be verified when the operation of the circuit to be verified is stopped. It is an object of the present invention to provide a circuit verification device that can be implemented with a configuration.

  Another object of the present invention is to provide a communication means on a circuit board provided with a programmable element and a control unit to communicate with an external device, and the control unit specifies a specified value storage unit by specifying an address and data. Therefore, the circuit verification device can be provided in which the designer can easily store the prescribed value in the prescribed value storage unit by operating the external device.

  Another object of the present invention is to use a circuit verification device including a programmable element capable of reconfiguring a logic circuit, to input a circuit to be verified to the programmable element and to input and output a signal to the circuit to be verified. An auxiliary circuit to perform, and a specified value storage unit for storing a specified value for specifying the operation of the circuit to be verified and the auxiliary circuit, and storing the specified value in the specified value storage unit; It is an object of the present invention to provide a circuit verification method in which various circuit operations can be easily verified by simply changing a specified value in a specified value storage unit by controlling an operation.

A circuit verification apparatus according to the present invention includes a programmable element capable of reconfiguring a logic circuit, and in the circuit verification apparatus for verifying the operation of a circuit to be verified configured in the programmable element, the programmable element includes the An auxiliary circuit having a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified, and a specified value that defines the operation of the circuit to be verified and / or the auxiliary circuit are stored. A specified value storage unit is configured to store the specified value in the specified value storage unit, and to control the operation of the circuit to be verified and / or the auxiliary circuit , the programmable element, and the a circuit board on which the control unit is provided, disposed on the circuit board, and a communication means for communicating with the control unit and an external device, wherein the circuit to be verified is more The plurality of circuit blocks include a circuit block to be verified and an input side circuit block that provides an input signal to the circuit block to be verified, and the specified value storage unit is provided by the input side circuit block An input value to be given to the circuit block to be verified instead of an input signal and a specified value for determining whether or not to apply the input value to the circuit to be verified are stored, and the auxiliary circuit is configured to store the specified value. A selection circuit that selects an input signal from the input-side circuit block or an input value stored in the specified value storage unit according to the specified value stored in the storage unit and applies the selected value to the circuit block to be verified; The control unit makes the storage of the specified value and the input value to the specified value storage unit of the programmable element accessible by designating an address and data by a common address space. And wherein the Rukoto.

In the circuit verification device according to the present invention, the auxiliary circuit includes a selection circuit that selects and outputs an internal signal of the circuit to be verified, and the specified value storage unit defines the selection of the selection circuit. The prescribed value is stored.

The circuit verification apparatus according to the present invention includes a programmable element capable of reconfiguring a logic circuit, and in the circuit verification apparatus that verifies the operation of the circuit to be verified configured in the programmable element, the programmable element includes An auxiliary circuit having a selection circuit that selects and outputs an internal signal of the circuit to be verified, and has a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified; A specified value storage unit that includes a specified value that defines the selection of the selection circuit and stores a defined value that defines the operation of the circuit to be verified and / or the auxiliary circuit. A control unit that stores a specified value in the value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit, and an observation value storage that stores the value of the internal signal output from the selection circuit And a counter that operates according to a clock signal input to the circuit to be verified, and the specified value storage unit starts a storage of an internal signal value in the observation value storage unit, and An end counter value for ending storage is stored, and the observed value storage unit starts storing when the counter value matches the start counter value, and the counter value is the end counter value. The storage is terminated when the two match .

The circuit verification apparatus according to the present invention further includes an observation clock signal output circuit that outputs an observation clock signal having a frequency higher than that of the clock signal input to the circuit to be verified, and the specified value storage unit includes the observation value The control unit can operate in synchronization with a clock signal, and the control unit changes a specified value in the specified value storage unit in synchronization with the observation clock signal, and outputs an internal signal output from the selection circuit. The observation value storage unit stores the data in synchronization with the observation clock signal.

The circuit verification apparatus according to the present invention includes a programmable element capable of reconfiguring a logic circuit, and in the circuit verification apparatus that verifies the operation of the circuit to be verified configured in the programmable element, the programmable element includes An auxiliary circuit having a selection circuit that selects and outputs an internal signal of the circuit to be verified, and has a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified; A specified value storage unit that includes a specified value that defines the selection of the selection circuit and stores a defined value that defines the operation of the circuit to be verified and / or the auxiliary circuit. A control unit that stores a specified value in the value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit, and an expected value storage that stores an expected value of an internal signal of the circuit to be verified A comparison means for comparing the internal signal output from the selection circuit and the expected value stored in the expected value storage unit, and if the internal signal and the expected value do not match as a result of comparison by the comparison means, And a stop means for stopping the operation of the verification circuit .

The circuit verification apparatus according to the present invention includes a programmable element capable of reconfiguring a logic circuit, and in the circuit verification apparatus that verifies the operation of the circuit to be verified configured in the programmable element, the programmable element includes An auxiliary circuit having a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified; and a specified value that defines an operation of the circuit to be verified and / or the auxiliary circuit. A control unit that stores a specified value in the specified value storage unit, and controls the operation of the circuit to be verified and / or the auxiliary circuit; A counter that operates in response to a clock signal input to the circuit; and a stopping unit that stops the operation of the circuit to be verified for each predetermined value of the counter. Value storage unit is characterized in that are provided to store the predetermined value.

The circuit verification apparatus according to the present invention is characterized in that the stopping means stops the operation of the circuit to be verified by stopping the supply of the clock signal to the circuit to be verified. .

In the circuit verification apparatus according to the present invention, the circuit to be verified includes a plurality of circuit blocks, and the circuit block to be verified and an input side circuit for supplying an input signal to the circuit block to be verified The specified value storage unit includes an input value given to the circuit block to be verified instead of an input signal given by the input side circuit block, and a rule that determines whether or not to give the input value to the circuit to be verified The auxiliary circuit is configured to store an input signal from the input-side circuit block or an input value stored in the specified value storage unit according to the specified value stored in the specified value storage unit. And a selection circuit that supplies the selected circuit block to the circuit block to be verified.

The circuit verification apparatus according to the present invention includes a circuit board on which the programmable element and the control unit are provided, and a communication unit that is provided on the circuit board and performs communication between the control unit and an external device. The control unit is characterized in that the storage of the specified value in the specified value storage unit of the programmable element is made accessible by designating an address and data in a common address space.
The circuit verification apparatus according to the present invention includes a storage unit provided on the circuit board, and the control unit is provided in the specified value storage unit of the programmable element, the communication unit, and the storage unit of the circuit board. On the other hand, access is made possible by designating addresses and data in a common address space.

In the circuit verification device according to the present invention, the circuit to be verified includes a plurality of circuit blocks, and the circuit blocks to be verified and outputs for acquiring output signals from the circuit blocks to be verified are included in the plurality of circuit blocks. A replacement circuit block that can replace the side circuit block and the circuit block to be verified; and the specified value storage unit stores a specified value that determines whether or not the circuit block to be verified is replaced by the replacement circuit block. The auxiliary circuit selects the output signal of the circuit block to be verified or the output signal of the alternative circuit block according to the specified value stored in the specified value storage unit, and outputs the circuit block on the output side. And a selection circuit for supplying to.

The circuit verification apparatus according to the present invention includes a test pattern generation circuit that generates an input signal that the auxiliary circuit supplies to the circuit to be verified, an input signal that is input from an input terminal provided in the programmable element, or the test A selection circuit that selects an input signal generated by the pattern generation circuit and applies the selected signal to the circuit to be verified, and the specified value storage unit stores a specified value that defines the selection of the selection circuit. It is characterized by.

The circuit verification apparatus according to the present invention further includes an observation clock signal output circuit that outputs an observation clock signal having a frequency higher than that of the clock signal input to the circuit to be verified, and the specified value storage unit includes the observation value The control unit can operate in synchronization with a clock signal, and the control unit changes a specified value in the specified value storage unit in synchronization with the observation clock signal, and outputs an internal signal output from the selection circuit. It is characterized by being changed.

The circuit verification apparatus according to the present invention further includes an observation value storage unit that stores a value of an internal signal output from the selection circuit in synchronization with the observation clock signal.

The circuit verification method according to the present invention is a circuit verification method in which a circuit to be verified is configured in the programmable element using the circuit verification apparatus described above, and the circuit to be verified is verified. Defines a verification circuit, an auxiliary circuit having a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified, and an operation of the circuit to be verified and / or the auxiliary circuit. A specified value storage unit that stores a specified value is configured, the specified value is stored in the specified value storage unit, and verification is performed by controlling operations of the circuit to be verified and the auxiliary circuit.
Further, the circuit verification method according to the present invention stops the operation of the circuit to be verified, changes the specified value stored in the specified value storage unit while the operation of the circuit to be verified is stopped, and The operation is resumed.

In the present invention, in the programmable element, a circuit to be verified, an auxiliary circuit for inputting / outputting signals to / from the circuit to be verified, and a specified value storage for storing specified values for defining the operation of the circuit to be verified and the auxiliary circuit Part. In addition, a control unit that changes the specified value of the specified value storage unit is provided. The designer can change the operation of the circuit to be verified and the auxiliary circuit only by changing the specified value of the specified value storage unit without performing the logic synthesis again.

Further, in the present invention, when the circuit to be verified has a plurality of circuit blocks such as a circuit block to be verified and an input side circuit block that supplies an input signal to the circuit block to be verified, the input signal of the input side circuit block is replaced. An input value to be given to the circuit block to be verified is stored in the specified value storage unit, and either an input signal of the input side circuit block or an input value of the specified value storage unit is selected and supplied to the circuit block to be verified. The selection at this time is performed according to the specified value stored in the specified value storage unit. Therefore, the designer can store an input value in the specified value storage unit, change the specified value, and give an arbitrary input value to the circuit block to be verified without performing logic synthesis again.

In the present invention, the circuit to be verified has the same function as the circuit block to be verified, the output side circuit block for acquiring the output signal from the circuit block to be verified, and the circuit block to be verified, and can be replaced with the circuit block to be verified. When there are a plurality of circuit blocks such as a substitute circuit block, the output signal of either the circuit block to be verified or the substitute circuit block is selected and supplied to the output side circuit block. That is, this is to replace a circuit block. The selection of which circuit block to use is performed according to the specified value stored in the specified value storage unit. For this reason, the designer can replace the circuit block without changing the logic synthesis only by changing the specified value in the specified value storage unit.

In the present invention, a test pattern generation circuit is provided in the programmable element, and either an input signal from the test pattern generation circuit or an input signal from the input terminal of the programmable element is selected and supplied to the circuit to be verified. The circuit to be verified can be operated by the input signal generated by the test pattern generation circuit, and another device is connected to the input terminal of the programmable element, and the output signal output from the other device is supplied to the circuit to be verified. Can be made. The selection of which input signal is supplied to the circuit to be verified is performed according to the specified value stored in the specified value storage unit. The designer can change the supply source of the input signal only by changing the specified value in the specified value storage unit without performing the logic synthesis again.

In the present invention, the internal signal of the circuit to be verified is selected and output according to the specified value stored in the specified value storage unit. Even if the number of internal signals of the circuit to be verified that needs to be observed is larger than the number of output terminals of the programmable element, it is not necessary to perform logic synthesis again to change the connection, and the specified value storage unit The internal signal to be output can be changed simply by changing the value.

In the present invention, the specified value for selection of the internal signal stored in the specified value storage unit is changed in synchronization with the clock signal for observation higher in frequency than the clock signal for operating the circuit to be verified. Thereby, during the operation of one clock of the circuit to be verified, the specified value of the specified value storage unit can be changed a plurality of times to output a plurality of internal signals, and the designer can simultaneously output more internal signals. Can be observed.

In the present invention, an observation value storage unit for storing the value of the selected internal signal is provided. The designer can verify the internal signal by reading the stored value. Therefore, without connecting an observation device such as a logic analyzer or an oscilloscope to the output terminal of the programmable element, the value read from the control unit to the external device can be transferred and displayed on the external device for verification.

In the present invention, a counter that operates according to a clock signal that operates the circuit to be verified is provided. In addition, the start counter value and the end counter value are stored in the specified value storage unit, and when the counter value matches the start counter value, the storage of the internal signal value to the observation value storage unit is started, and the end counter value is set. When they match, the storage in the observation value storage unit is terminated. By specifying a range in which the value of the internal signal is stored in advance, only a value within this range is stored, and a value outside the range is not stored. Therefore, the observation value storage unit can be used efficiently according to the storage capacity.

In the present invention, an expected value storage unit for storing the expected value of the internal signal of the circuit to be verified is provided. When the internal signal and the expected value do not match, the operation of the circuit to be verified is stopped. As a result, the occurrence of an error in the circuit to be verified can be reliably captured, and the designer can verify the operation of the circuit to be verified at this timing in detail, so that it is easy to find an error in the circuit to be verified.

In the present invention, a counter that operates according to a clock signal that operates the circuit to be verified is provided. Further, the predetermined value is stored in the specified value storage unit, and the operation of the circuit to be verified is stopped every time the counter value counts the predetermined value. As a result, the circuit to be verified can be executed in steps, and the designer can reliably verify the operation of the circuit to be verified every predetermined period.

In the present invention, when the operation of the circuit to be verified is stopped, the supply of the clock signal to the circuit to be verified is stopped. As a result, the circuit to be verified does not operate reliably. Further, it can be realized with a simple circuit configuration.
In the present invention, means for communicating with an external device is provided on the circuit board on which the programmable element and the control unit are provided. The designer operates the external device to verify the circuit to be verified configured in the programmable element. Further, the control unit accesses the specified value storage unit by designating an address and data, and changes the specified value. By storing the specified value storage unit in the address space of the control unit, the control unit can easily access the specified value storage unit.

In the present invention, a circuit verification device including a programmable element is used to define a circuit to be verified in the programmable element, an auxiliary circuit that inputs and outputs signals to the circuit to be verified, and operations of the circuit to be verified and the auxiliary circuit. And a specified value storage unit for storing specified values to be stored. Next, the specified value is stored in the specified value storage unit to control the operation of the circuit to be verified and the auxiliary circuit. The operation of the circuit to be verified and the auxiliary circuit can be changed by changing the specified value stored in the specified value storage unit.

In the case of the present invention, the circuit to be verified in the programmable element, the auxiliary circuit for inputting / outputting a signal to / from the circuit to be verified, and the specified value storage for storing the specified value for defining the operation of the verified circuit and the auxiliary circuit And the control unit changes the specified value to change the operation of the circuit to be verified and the auxiliary circuit, so that the designer only needs to change the specified value in the specified value storage unit. Since the operation of the circuit and the auxiliary circuit can be changed and there is no need to perform logic synthesis again, the verification period of the circuit to be verified can be shortened, and the designer can perform advanced circuit verification with a simple operation. .

Further, in the case of the present invention, when the circuit to be verified has a plurality of circuit blocks such as the circuit block to be verified and the input side circuit block that provides an input signal to the circuit block to be verified, the input to be input to the circuit block to be verified Value and a specified value for determining whether or not to provide the input value to the circuit block to be verified are stored in the specified value storage unit, and either the input signal of the input side circuit block or the input value of the specified value storage unit is set to the specified value. By selecting according to the configuration to be given to the circuit block to be verified, the designer stores the input value in the specified value storage unit, and gives the arbitrary input value to the circuit block to be verified only by changing the specified value. In addition, since it is not necessary to perform logic synthesis again, the verification period of the circuit to be verified can be shortened.

Further, according to the present invention, the circuit to be verified has the same function as the circuit block to be verified, the output side circuit block for obtaining the output signal from the circuit block to be verified, and the circuit block to be verified. When there are a plurality of circuit blocks such as alternative circuit blocks that can be replaced, the output signal of either the circuit block to be verified or the alternative circuit block is selected according to the specified value stored in the specified value storage unit By providing the configuration to the output side circuit block, the designer can replace the circuit block only by changing the specified value in the specified value storage unit, and there is no need to perform logic synthesis again, so that The circuit verification period can be shortened.

In the case of the present invention, the test is performed by providing an input signal from either the test pattern generation circuit in the programmable element or the input terminal of the programmable element to the circuit to be verified according to the stored specified value. The circuit to be verified can be operated by the input signal generated by the pattern generation circuit, and another device is connected to the input terminal of the programmable element, and the output signal output from the other device is supplied to the circuit to be verified for operation. Therefore, verification can be performed by applying various test patterns to the circuit to be verified, and verification accuracy can be improved. Moreover, the designer can change the supply source of the input signal only by changing the specified value in the specified value storage unit, and it is not necessary to perform the logic synthesis again, thereby shortening the verification period of the circuit to be verified. Can do.

In the case of the present invention, it is necessary to perform observation from the number of output terminals of the programmable element by selecting and outputting the internal signal of the circuit to be verified according to the specified value stored in the specified value storage unit. Even when the number of internal signals of a circuit to be verified is large, it is possible to change the internal signal to be output simply by changing the specified value in the specified value storage unit. Therefore, it is not necessary to perform the logic synthesis again to change the connection, and the verification period of the circuit to be verified can be shortened.

In the case of the present invention, the specified value for selecting the internal signal stored in the specified value storage unit is changed in synchronization with the clock signal for observation higher in frequency than the clock signal for operating the circuit to be verified. By doing so, it is possible to change the specified value of the specified value storage unit a plurality of times and output a plurality of internal signals during the operation of one clock of the circuit to be verified, and the designer can simultaneously output more internal signals. Therefore, the accuracy of verification can be improved and the convenience of the circuit verification apparatus can be improved.

Further, according to the present invention, an observation device such as a logic analyzer or an oscilloscope is connected to the output terminal of the programmable element by providing an observation value storage unit for storing the value of the selected and outputted internal signal. Instead, verification can be performed by transferring the read value from the control unit to the external device and displaying it on the external device. Therefore, it is possible to reduce the cost of measuring equipment necessary for verifying the circuit to be verified, and to improve the convenience of the circuit verification apparatus.

Further, according to the present invention, a counter that operates in response to a clock signal that operates the circuit to be verified is provided, and when the counter value matches the start counter value stored in the specified value storage unit, the counter is stored in the observation value storage unit. By starting the storage of the value and ending the storage when it matches the end counter value, the range for storing the internal signal value is specified in advance, and the internal signal value required for verification is automatically set. Therefore, the convenience of the circuit verification device can be improved. Since the observation value storage unit can be used efficiently according to the storage capacity, an increase in the cost of the circuit verification device can be suppressed.

Further, according to the present invention, the expected value of the internal signal of the circuit to be verified is stored in the expected value storage unit, and the operation of the circuit to be verified is stopped when the internal signal and the expected value do not match. Therefore, it is possible to reliably catch the error occurrence of the circuit to be verified, and the designer can verify the operation of the circuit to be verified at this timing in detail, so that the accuracy of the verification can be improved, and the circuit verification device Can improve convenience.

Further, in the case of the present invention, a circuit that operates in response to a clock signal that operates the circuit to be verified is provided, and the operation of the circuit to be verified is stopped for each predetermined value of the counter. Can be executed step by step, and the designer can reliably verify the operation of the circuit to be verified every predetermined period, thus improving the accuracy of verification and improving the convenience of the circuit verification device. it can.

Further, according to the present invention, when stopping the operation of the circuit to be verified, the circuit to be verified is stopped with a simple circuit configuration by stopping the supply of the clock signal to the circuit to be verified. Therefore, it is possible to suppress an increase in the cost of the circuit verification device by providing this function.

Further, in the case of the present invention, the circuit board provided with the programmable element and the control unit is equipped with a communication means to communicate with an external device, and the control unit can access the specified value storage unit by specifying an address and data. By doing so, the specified value storage unit can be stored in the address space of the control unit, and the specified value can be easily stored from the control unit to the specified value storage unit. Access to the specified value storage unit in the programmable element from the external device can be easily performed, and the convenience of the circuit verification device can be improved.

Further, according to the present invention, using a circuit verification device including a programmable element capable of reconfiguring a logic circuit, a circuit to be verified is connected to the programmable element, and an auxiliary circuit that inputs and outputs signals to the circuit to be verified And a specified value storage unit for storing specified values for defining the operation of the circuit to be verified and the auxiliary circuit, and storing the specified value in the specified value storage unit to control the operation of the circuit to be verified and the auxiliary circuit. As a result, the operation of the circuit to be verified and the auxiliary circuit can be easily changed simply by changing the specified value stored in the specified value storage unit, and there is no need to perform logic synthesis again, thereby shortening the verification period of the circuit to be verified. can do.

(Embodiment 1)
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing a configuration of a circuit verification apparatus according to Embodiment 1 of the present invention. In FIG. 1, the data bus is indicated by a solid arrow, and the address bus is indicated by a broken arrow. In the figure, reference numeral 1 denotes a circuit verification device on which an FPGA 2 that can constitute a digital circuit (target circuit) 20 designed by a designer is mounted. The PC (personal computer) 10 operated by the designer is connected to a USB cable or LAN. It is connected via a cable or the like, and verifies the operation of the target circuit 20 configured in the FPGA 2 in accordance with a command given from the PC 10 by a designer's operation.

  The circuit verification apparatus 1 includes an FPGA 2, a CPU 3, a memory 4, a memory 5, a communication device 6, and the like disposed on a circuit board, which are connected via a bus 7. The FPGA 2, the memory 4, the memory 5, the communication device 6, and the like are managed so as to be accessible from the CPU 3 or a program executed by the CPU 3 as resources in one address space.

  FIG. 2 is a schematic diagram showing a configuration example of the address space of the CPU 3 of the circuit verification device 1 according to the first embodiment of the present invention. In this figure, the case where the CPU 3 has a 32-bit address space is shown. The address space of the CPU 3 includes an address space for designating resources in the FPGA 2, an address space for designating a storage area of the memory 4, an address space for designating a storage area of the memory 5, and a communication And an address space for designating resources of the device 6. Further, the address space for designating resources in the FPGA 2 includes an address space for designating each storage area of the control register 30 and the internal memory 44 described later. Therefore, the CPU 3 can write data only by designating an address and data, and can read data only by designating an address.

  The memory 4 is used as a buffer for temporarily storing input data to be input to the FPGA 2, and the input data is given from the PC 10 via the communication device 6. The memory 5 is used as a buffer for temporarily storing the output data output from the FPGA 2, and the output data is provided to the PC 10 via the communication device 6. In FIG. 1, two memories, ie, the memory 4 and the memory 5, are provided. However, the memory 4 and the memory 5 can be replaced with one memory.

  The communication device 6 is connected to a USB cable, a LAN cable or the like, and transmits / receives data to / from the PC 10 based on a communication protocol. Data received from the PC 10 is stored in the memory 4, and when data is transmitted to the PC 10, data stored in the memory 5 is read and transmitted.

  The FPGA 2 is an FPGA including a storage element using SRAM technology, and a circuit configured in the FPGA 2 can be changed by changing circuit data stored in the storage element. Since the SRAM technology is used, each circuit block as illustrated is not configured in the FPGA 2 immediately after the circuit verification apparatus 1 is turned on, and circuit data is transmitted from the PC 10 to the circuit verification apparatus 1 after the power is turned on. Thus, each circuit block is configured in the FPGA 2. Note that a ROM storing circuit data may be provided in the circuit verification device 1 so that the circuit data is read from the ROM after the power is turned on.

  Based on circuit data from the PC 10, the FPGA 2 stores the target circuit 20 to be verified designed by the designer, the test pattern generation circuit 25 that provides an input signal to the target circuit 20, and the value of the output signal or internal signal of the target circuit 20. The memory switching unit 42 for switching the storage destination to one of the internal memory 44, the external memory 5 or the internal memory 44, and the control register 30 for storing setting values or input values for operating these units. Etc. are provided.

  The target circuit 20 is a circuit to be verified by using the circuit verification apparatus 1 and is designed by a designer, and after the verification is completed, a layout is created and manufactured as a semiconductor IC. The test pattern generation circuit 25 is a circuit for verification that generates an input signal of the target circuit 20, and is designed by the designer for each target circuit 20. As an example, FIG. 1 shows a test pattern generation circuit 25 that is supplied with input data stored in the memory 4 and supplies the input data to the target circuit 20 at a predetermined timing. At this time, when the number of input signals to the target circuit 20 is larger than the number of signals on the bus 7, the test pattern generation circuit 25 may be configured to temporarily store and output input data provided from the memory 4. However, in this case, it is desirable that the test pattern generation circuit 25 operates at a higher speed than the target circuit 20. Note that the specification of the test pattern generation circuit 25 may be different for each specification of the target circuit 20, and is not limited to that shown in the figure. Further, when the test pattern generation circuit 25 is not necessary, it may not be included in the FPGA 2.

  The output of the test pattern generation circuit 25 is given as an input signal to the target circuit 20 via a multiplexer (hereinafter referred to as MUX) 40. The MUX 40 selects either the input signal from the test pattern generation circuit 25 or the input signal input from the input terminal of the FPGA 2 according to the set value stored in the control register 30, and sends it to the target circuit 20. To give. For example, an output signal from another already completed IC can be input to the input terminal of the FPGA 2, and for example, a test pattern that cannot be generated by the test pattern generation circuit 25 is generated and input by a device such as a signal generator. can do.

  The output signal of the target circuit 20 that has been operated by receiving the input signal from the MUX 40 is output from the output terminal of the FPGA 2 and is stored in the external memory 5 or the internal memory 44 via the memory switching unit 42. is there. The internal signal of the target circuit 20 is given to the MUX 41. The MUX 41 selects and outputs 64 internal signals according to the set value stored in the control register 30 from 2048 internal signals given as signals for observation from the target circuit 20, for example, and a memory switching unit 42.

  The memory switching unit 42 is configured to supply a signal supplied from the target circuit 20 and the MUX 41 to either the memory 5 or the internal memory 44 according to the set value stored in the control register 30. Furthermore, the structure which can give the signal from the target circuit 20 to the memory mounted in PC10 via the communication device 6 may be sufficient. The internal memory 44 is constituted by SRAM resources or register resources in the FPGA 2, and stores the output signal of the target circuit 20 and the value of the internal signal given from the memory switching unit 42. The stored value is stored in the memory. 5 is transferred. The memory 5 desirably has a larger capacity than the internal memory 44. Further, since the internal memory 44 is in the address space of the CPU 3, the CPU 3 can directly access it, and the stored value can be transferred from the communication device 6 to the PC 10 without going through the memory 5. It is.

  Further, since the internal memory 44 provided in the FPGA 2 exists in the address space of the CPU 3 as shown in FIG. 2, it can be directly accessed from the CPU 3, and the logic configured in the FPGA 2 can be accessed. Access from the circuit is also possible. This is a configuration in which the logic circuit in the FPGA 2 and the CPU 3 share the internal memory 44. Similarly, the memory 4 and the memory 5 of the circuit verification apparatus 1 may have a configuration shared by the logic circuit in the FPGA 2 and the CPU 3. In this case, the large-capacity memory 4 that cannot be configured in the FPGA 2. And the memory 5 has an advantage that a logic circuit configured in the FPGA 2 can be used.

  Since the control register 30 is in the address space of the CPU 3, the CPU 3 can directly access and set the value, and the CPU 3 changes the value of the control register 30 to select the input signal by the MUX 40. Alternatively, the selection of the internal signal by the MUX 41 can be changed. FIG. 3 is a schematic diagram illustrating a configuration example of the control register 30 of the circuit verification device 1 according to the first embodiment of the present invention.

  The control register 30 is supplied to an observation signal selection register that stores a setting value related to selection of an internal signal of the target circuit 20 by the MUX 41, the target circuit 20, the test pattern generation circuit 25, the MUX 40, and the memory switching unit 42. A debug setting register that stores setting values relating to the operation of the circuit and an input data register that stores data directly input to the target circuit 20 are included. A circuit verification method using these registers will be described later.

  Although not shown in FIG. 1, the circuit inspection apparatus 1 includes a clock signal generation circuit that outputs a clock signal for operating the target circuit 20 and the test pattern generation circuit 25 in the FPGA 2, and a clock signal generation circuit. And a frequency multiplication circuit that generates and outputs a signal having a frequency that is an integral multiple of the clock signal based on the generated clock signal. The frequency multiplication circuit is a circuit that generates a signal having a frequency that is an integral multiple of the harmonic component of the input signal. For example, a signal having a frequency that is four times the clock signal (hereinafter referred to as a quadruple clock signal) is generated. Output. The control register 30 and the internal memory 44 in the FPGA 2 can operate in synchronization with the quadruple clock signal output from the frequency multiplication circuit.

  FIG. 4 is a flowchart showing an example of a digital circuit design flow using the circuit verification apparatus 1 according to the first embodiment of the present invention. In designing a digital circuit, first, a behavioral level design of the target circuit 20 is performed (step S1). In the behavior level design, the function, specification, architecture, and the like of the target circuit 20 are determined. The description may be performed by using a system level description language such as C language. Next, based on the determined function, specification, architecture, etc., the target circuit 20 is described in HDL, and RTL design is performed (step S2). Note that when description is made in a system level description language at the stage of behavior level design, an RTL circuit may be automatically generated based on this description. After creating the RTL circuit, an RTL simulation of the target circuit 20 is performed using a simulator (step S3). If no error is found in the RTL simulation, the process proceeds to the next step. When an error is found, it is necessary to identify the cause of the error and perform behavior level design or RTL design again.

  After completion of the RTL simulation, a circuit for the FPGA 2 is created (step S4). This circuit includes the target circuit 20 created in steps S1 to S3, to which a test pattern generation circuit 25, MUX 40, and the like are added, and is an RTL circuit described in HDL. In addition, this circuit described in HDL includes connection information between the target circuit 20, the test pattern generation circuit 25, and the like, and the control register 30, the MUX 41, the memory switching unit 42, the internal memory 44, and the like prepared in advance. It is. The connection information may be described by a designer or automatically generated using a dedicated tool.

  Next, using the logic synthesis tool for FPGA 2, the circuit created in step S4 is logically synthesized (step S5), and circuit data is created. At this time, the circuit configurations such as the control register 30, the MUX 41, the memory switching unit 42, and the internal memory 44 prepared in advance are automatically read and connected to the target circuit 20, the test pattern generation circuit 25, the MUX 40, and the like. Circuit data having the configuration shown in the FPGA 2 of FIG. 1 is created.

  After completion of the logic synthesis, the created circuit data is given from the PC 10 to the circuit verification apparatus 1 to configure the circuit in the FPGA 2, and the circuit verification by the circuit verification apparatus 1 is performed (step S6). If no error is found in this verification, logic synthesis of the target circuit 20 is performed under conditions suitable for the process of manufacturing the semiconductor IC (step S7), and a gate level circuit is created. When an error is found in the verification in step S6, it is necessary to identify the cause of the error and perform behavior level design or RTL design again. After creating a gate level circuit, a gate level simulation is performed using a simulator (step S8).

  After completion of the gate level simulation, a layout of the target circuit 20 is created using a placement and routing tool (step S9), delay information is extracted from the created layout, and back annotation is performed (step S10). After back annotation, a mask is created based on the layout of the target circuit 20 (step S11), and an IC is manufactured using the created mask (step S12).

In the circuit verification performed in step S6 of the above flow, various verifications are performed using the control register 30 without repeating the logic synthesis in step S5 by using the circuit verification apparatus 1 according to the present embodiment. It can be carried out. For example,
(1) Change of observed internal signal (2) Change of input signal (3) Operation verification in circuit block unit (4) Change of fixed value (5) Replacement of circuit block (6) Data input etc. it can.

(1) Change of the internal signal to be observed The designer can store the internal signal of each node in the target circuit 20 in the memory 5 or the internal memory 44 and read it to observe it. At this time, the designer can change the internal signal stored in the memory 5 or the internal memory 44 by changing the value of the observation signal selection register of the control register 30. FIG. 5 is a schematic diagram for explaining a method of changing the internal signal to be observed. As an example, 2048 internal signals that can be observed exist in the target circuit 20, and 32 of these internal signals are present. The case of selecting and observing is illustrated. FIG. 6 is a block diagram showing the supply relationship of the clock signal, and only the block relating to the observation of the internal signal is extracted and shown.

  The change of the internal signal to be observed is realized by the observation signal selection register of the control register 30 and the MUX 41. The MUX 41 includes 32 multiplexers that select and output one signal from 64 input signals (mux0 to mux31). Each of mux0 to mux31 is connected to the observation signal selection register of the control register 30 and outputs one of 64 internal signals as an observation signal according to the set value stored in the observation signal selection register. It is like that. The 32 observation signals 0 to 31 output from the MUX 41 are given to the memory 5 or the internal memory 44 by the memory switching unit 42, and the values are stored. Therefore, the internal signal to be observed can be changed only by changing the set value of the observation signal selection register.

  In addition, the clock signal output from the clock signal generation circuit 46 having a crystal resonator or the like is supplied to the target circuit 20 and also to the frequency multiplication circuit 47. A frequency multiplication circuit 47 is used to generate a quadruple clock signal having a frequency four times that of the clock signal for operating the target circuit 20, and the setting value of the control register 30 is changed in synchronization with the quadruple clock signal. By performing the operations of the memory 5 and the internal memory 44 in synchronization with the quadruple clock signal, the MUX 41 can be selected four times during the operation of one clock of the target circuit 20, so that 32 × 4 = 128 lines. The value of the internal signal can be stored in the memory 5 or the internal memory 44 and observed. Note that the switching of the memory switching unit 42 is performed in accordance with the value stored in the debug setting register of the control register 30.

(2) Change of input signal The designer selects an input signal to be supplied to the target circuit 20 from either an input signal generated by the test pattern generation circuit 25 or an input signal input from the input terminal of the FPGA 2. be able to. At this time, the designer can change the selection of the input signal by changing the value of the debug setting register of the control register 30. FIG. 7 is a schematic diagram for explaining a method of changing the input signal. As an example, a case where 32 input signals are input to the target circuit 20 is illustrated.

  The change of the input signal is realized by the debug setting register of the control register 30 and the MUX 40. The MUX 40 includes 32 multiplexers that select and output one of the two input signals (mux0 to mux31). The mux0 to mux31 are connected to the same debug setting register of the control register 30, and are selected according to the setting value stored in the debug setting register and supplied to the target circuit 20 as an input signal. Therefore, only by changing the value of the debug setting register, either the input signal generated by the test pattern generation circuit 25 (test patterns 0 to 31) or the input signal input from the input terminals 0 to 31 of the FPGA 2 is selected. It can be given to the target circuit 20 as an input signal.

(3) Operation verification in units of circuit blocks When designing a large-scale digital circuit, it is possible to design the circuit as a small circuit block by dividing the entire circuit by function, and to configure the entire circuit by connecting multiple circuit blocks. Many. Therefore, when the target circuit 20 includes a plurality of circuit blocks and an error occurs as a result of the verification of the target circuit 20, it is desirable to identify the circuit block that causes the error. Since the circuit verification apparatus 1 according to the present embodiment can give an arbitrary input signal to a specific circuit block and can observe an internal signal of the specific circuit block using the MUX 41 as described above. Operation verification can be performed on a circuit block basis.

  FIG. 8 is a schematic diagram for explaining a method of performing operation verification in units of circuit blocks. As an example, the case where the target circuit 20 has four circuit blocks (circuit blocks 0 to 3) is illustrated. For simplification of description, each circuit block is illustrated as a block with one input and one output, but is not limited thereto.

  The output signal of the circuit block 0 of the target circuit 20 is input to the circuit block 1 via mux1 (multiplexer), the output signal of the circuit block 1 is input to the circuit block 2 via mux2, and the output signal of the circuit block 2 is Mux 1 to 3 are inserted between the circuit blocks so as to be input to the circuit block 3 via mux 3. It should be noted that the mux 1 to 3 may be inserted into the target circuit 20 by a designer or automatically before performing logic synthesis.

  The mux 1 to 3 select and output one of the input signals input from the two input terminals. The output signal of each circuit block is input to one of the input terminals, and the MUX 41 is input to the other. Are connected so that a signal from the input terminal of the test pattern generation circuit 25 or the FPGA 2 can be input. Further, the selection of mux 1 to 3 is performed according to the set value stored in the debug setting register of the control register 30. By providing the test pattern generation circuit 25 with a configuration capable of generating not only the circuit block 0 of the target circuit 20 but also other circuit blocks, the generated input signals can be given to the circuit blocks 1 to 3. In addition, an input signal directly input from the input terminal of the FPGA 2 can be given.

  Note that the input data register of the control register 30 may be connected to the other of the input terminals of mux 1 to 3, and in this case, data stored in advance in the input data register can be input, and the value of the data register Each circuit block can be operated by changing. Alternatively, mux 1 to 3 may be a three-input multiplexer, and any one of the output signal of the circuit block, the output signal of MUX 40, or the value of the input data register may be selected.

  For example, when the operation verification of the circuit block 1 is performed, the setting value of the debug setting register 1 is changed so that the mux 1 supplies the output signal of the MUX 40 to the circuit block 1 and the observation signal selection register of the control register 30 The set value is changed and the output signal (internal signal 1) of the circuit block 1 is selected by the MUX 41. Further, the setting is changed so that the MUX 40 gives the output signal of the test pattern generation circuit 25 to the target circuit 20. As a result, the input data temporarily stored in the memory 4 can be given to the circuit block 1 via the test pattern generation circuit 25, and the internal signal 1 as the operation result at this time can be observed.

  By using this function, the following verification can be performed. When an error occurs in the output signal of the target circuit 20, first, the output signal (internal signal 0) of the circuit block 0 is observed to check whether there is an error. If no error has occurred in the output signal of the circuit block 0, then the output signal (internal signal 1) of the circuit block 1 is observed to check whether there is an error. In this way, after checking each block in order and specifying the circuit block in which an error has occurred in the output signal, various test patterns are input from the test pattern generation circuit 25 to the circuit block in which an error has occurred via the MUX 40. And investigate the cause of the error.

  Further, the circuit configuration of the target circuit 20 is not a simple configuration including four circuit blocks as shown in FIG. 8, but a complicated configuration in which a plurality of circuit blocks having a plurality of hierarchical structures are connected to each other. Even in such a case, the above-described verification can be performed by exchanging signals with a mux interposed between the circuit blocks. Further, by using this function, verification can be performed by regarding one circuit block as a target circuit, and all of the verification described above and verification described later can be performed on one circuit block. .

(4) Change of fixed value For example, when the target circuit 20 has a counter circuit, and this counter circuit is a circuit that loads a specific value and counts down until the value becomes 0, the designer Although the value is designed as a fixed value, there is a case where it is desired to change the fixed value during the verification stage. The same applies to cases other than the counter circuit, for example, where the offset value of the arithmetic circuit or the arithmetic table is given as a fixed value. The circuit verification apparatus 1 according to the present embodiment can change the fixed value without performing logic synthesis again by using the input data register of the control register 30.

  FIG. 9 is a schematic diagram for explaining a method of changing the fixed value, and illustrates a case where the fixed value of the counter circuit is changed as an example. By connecting the input data register of the control register 30 to the counter circuit and loading the setting value stored in the input data register instead of the fixed value, the designer can change the setting value of the input data register. It is possible to change the operation of the counter circuit simply by doing. The connection between the input data register and the counter circuit may be configured by a designer or may be configured automatically before performing logic synthesis.

(5) Replacement of circuit block When the target circuit 20 has a plurality of circuit blocks, one of which is a circuit block that performs a specific operation, and a plurality of algorithms can be selected as an algorithm for the operation In order to verify which algorithm is optimal, there is a case where it is desired to operate by replacing a circuit block. Further, even if the algorithm is the same, there are cases where it is desired to replace a plurality of circuit blocks having different circuit configurations due to differences in circuit scale, calculation speed, or error occurrence frequency. In such a case, the circuit verification apparatus 1 according to the present embodiment can replace the circuit block without performing logic synthesis again by using the debug setting register of the control register 30.

  FIG. 10 is a schematic diagram for explaining a method of replacing a circuit block. As an example, the target circuit 20 is operated by three circuit blocks, and one of these circuit blocks (circuit block 1a or The case of replacing 1b) is illustrated. For simplification of description, each circuit block is illustrated as a block with one input and one output, but is not limited thereto.

  The two circuit blocks 1a and 1b to be replaced have the same number of input terminals and output terminals (not necessarily the same), and the output terminal of the circuit block 0 is connected to the input terminals of the circuit blocks 1a and 1b, respectively. It is connected. Further, the output terminals of the circuit blocks 1a and 1b are connected to a mux (multiplexer), and an output signal from either one is selected by the mux and supplied to the circuit block 2. The mux is selected according to the set value stored in the debug setting register of the control register 30.

  Thereby, the designer can give the output signal of either the circuit block 1a or 1b to the circuit block 2 by changing the setting value of the debug setting register, and the circuit block without performing the logic synthesis again. It is possible to verify the operation of the target circuit 20 in the two cases of using 1a and using the circuit block 1b. The circuit blocks 1a and 1b need to be designed by the designer, but the circuit blocks 1a and 1b and other circuit blocks may be connected and the mux may be inserted by the designer. It may be configured to be automatically performed before performing logic synthesis.

(6) Data Input The circuit verification apparatus 1 according to the present embodiment uses the data stored in the data register of the control register 30 as another circuit instead of the input signal given from one circuit block to another circuit block. Can be given to the block. FIG. 11 is a schematic diagram for explaining a method of inputting data to a circuit block. As an example, a target circuit is operated by four circuit blocks, and three circuit blocks (circuit blocks 0 to 2) are illustrated. Is shown as an input signal to one circuit block (circuit block 3). As an example, the circuit block 3 is an arithmetic circuit that performs multiplication and addition of data given from the circuit blocks 0 to 2 and outputs the result. In addition, these structures are examples and are not restricted to this.

  The target circuit 20 is provided with three mux 0-2. The output of the circuit block 0 and the input data register 0 are connected to mux 0, and either the output signal of the circuit block 0 or the data stored in the input data register 0 is selected according to the value stored in the debug setting register 0. The signal is input to the circuit block 3. Similarly, the output and input data register 1 of the circuit block 1 is connected to mux 1, and the output signal of the circuit block 1 or the data stored in the input data register 1 depends on the value stored in the debug setting register 1. Either one is input to the circuit block 3, the output of the circuit block 2 and the input data register 2 are connected to the mux 2, and the output of the circuit block 2 according to the value stored in the debug setting register 2 Either the signal or the data stored in the input data register 2 is input to the circuit block 3.

  The circuit block 3 is a circuit block that multiplies the input signals given from the circuit blocks 0 and 1 and adds the multiplication result and the input signal given from the circuit block 2 and outputs the result. The setting values are stored in the debug setting registers 0 to 2 so that mux 0 to 2 output the data stored in the input data registers 0 to 2, so that they are stored in the input data registers 0 to 2 in the circuit block 3. Arbitrary data can be entered. At this time, if the operation of the target circuit 20 can be temporarily stopped as will be described later, the control register 30 can be simulated by changing the value of the input data register by stopping the operation. The circuit blocks 0 to 2 can be used. The mux 0 to 2 may be inserted into the target circuit 20 by a designer or may be automatically performed before performing logic synthesis.

  In the circuit verification device 1 having the above configuration, the control register 30 that can be directly accessed by the CPU 3 is provided in the FPGA 2, and the operation of the target circuit 20 and other circuits is changed using the control register 30. Various verifications as described in (1) to (6) above can be performed, and the verification accuracy of the target circuit 20 can be increased. In addition, since it is not necessary to perform logic synthesis again at this time, the verification period can be shortened.

  In addition, although the circuit verification apparatus 1 which concerns on this Embodiment was set as the structure provided with one FPGA2, it is not restricted to this, The structure provided with several FPGA may be sufficient. In addition, although the FPGA 2 and the CPU 3 are provided on the same substrate, the present invention is not limited to this, and each may be provided on a separate substrate and electrically connected to the substrate. The FPGA 2 is an SRAM-type FPGA, but is not limited to this, and a flash-type or anti-fuse-type FPGA may be used, or a programmable element other than the FPGA may be used. Moreover, although the circuit verification apparatus 1 was set as the structure provided with one CPU3, it is not restricted to this, The structure provided with two or more CPUs may be sufficient. Similarly, a configuration including a plurality of communication devices 6 may be used. In this case, more data can be transmitted and received between the PC 10 and the communication device 6, so that communication can be speeded up. In addition, there is an advantage that a plurality of PCs 10 can be connected to the circuit verification apparatus 1. Further, the CPU 3, the memory 4, the memory 5 and the communication device 6 are separately provided and connected via the bus 7. However, the present invention is not limited to this, and the CPU 3, the memory 4, the memory 5 or the communication device 6 is not limited thereto. It is also possible to configure some or all of these in the FPGA 2.

  Further, only the internal signal of the target circuit 20 is selected by the MUX 41 and applied to the memory switching unit 42, and the output signal of the target circuit 20 is directly applied to the memory switching unit 42. However, the present invention is not limited to this. The 20 output signals may be selected by the MUX 41 together with the internal signals and supplied to the memory switching unit 42. Moreover, it is good also as a structure which outputs the output signal of MUX41 from the output terminal of FPGA2. In addition, the control register 30 of the FPGA 2 is in the address space of the CPU 3 and can be directly accessed by the CPU 3. However, the present invention is not limited to this, and an interface circuit interposed between the CPU 3 and the control register 30 is installed in the FPGA 2. The configuration may be provided inside or outside the FPGA 2.

  The control register 30 has three types of registers, that is, an observation signal selection register, a debug setting register, and an input data register. Since these registers have the same hardware configuration, it is necessary to particularly distinguish them. Absent. The verification of the circuit using the control register 30 is not limited to the above (1) to (6), and the control register 30 can be used for various other purposes. By providing an area in the control register 30 that can be freely used by the designer, the designer can independently perform verification suitable for the target circuit 20.

(Modification 1)
FIG. 12 is a block diagram showing a configuration of the circuit verification apparatus according to the first modification of the first embodiment of the present invention. A circuit verification device 81 according to the first modification includes an internal memory 44, a memory 4, and a memory 5 that are provided in the circuit verification device 1 shown in FIG. The output signal of the target circuit 20 and the internal signal are directly transmitted from the communication device 6 to the PC 10. A signal given from the communication device 6 to the PC 10 is stored in a memory provided in the PC 10 (not shown). The circuit verification device 1 shown in FIG. 1 is provided with the CPU 3 to manage the memory elements. However, the circuit verification device 81 according to the modification does not need this, and therefore, the control chip is smaller than the CPU 3. It is only necessary to provide 3a. Therefore, the cost of the circuit verification device can be reduced by using the memory of the PC 10.

(Modification 2)
FIG. 13 is a block diagram showing a configuration of the circuit verification apparatus according to the second modification of the first embodiment of the present invention. The circuit verification device 91 according to the second modification includes four FPGAs 2a, 2b, 2c, and 2d that can configure a digital circuit designed by a designer. The four FPGAs 2a, 2b, 2c, and 2d are connected to the CPU 3, the memory 4, the memory 5, and the communication device 6 through the bus 7, and the CPU 3 together with the memory 4, the memory 5, and the communication device 6 has the FPGA 2a. 2b, 2c, and 2d can be accessed as resources in one address space.

  FIG. 14 is a schematic diagram showing a configuration example of the address space of the CPU 3 of the circuit verification device 91 according to the second modification of the first embodiment of the present invention. In the address space of the CPU 3, an address space for designating resources in the FPGAs 2 a, 2 b, 2 c, and 2 d is continuously provided, an address space for designating a storage area of the memory 4, and a storage in the memory 5 An address space for designating an area and an address space for designating resources of the communication device 6 are provided.

  As a result, the CPU 3 can treat the four FPGAs 2a, 2b, 2c, and 2d as one large FPGA, and can verify a large-scale digital circuit that does not fit in one FPGA. In Modification 2, the circuit verification device 91 includes four FPGAs 2a, 2b, 2c, and 2d. However, the configuration is not limited to this, and the number of FPGAs to be mounted may be two. There may be three, or five or more. In addition, the address for designating the resources in the FPGAs 2a, 2b, 2c, and 2d is continuously provided in the address space. However, the present invention is not limited to this, and the addresses may be discontinuous.

(Embodiment 2)
FIG. 15 is a block diagram showing a configuration of a circuit verification apparatus according to Embodiment 2 of the present invention. In the circuit verification apparatus 101 according to the second embodiment, an expected value memory 150 that stores an output value of the target circuit 20 and an expected value of an internal signal is connected via the bus 7, and the expected value memory 150 is in the address space of the CPU 3. The CPU 3 can be directly accessed. Further, the logic circuit configured in the FPGA 2 and the CPU 3 share the expected value memory 150, and the logic circuit in the FPGA 2 can directly access the expected value memory 150.

  In the FPGA 2, a comparison circuit 151 that compares the expected value stored in the expected value memory 150 with the value of the internal signal or output signal of the target circuit 20 output from the MUX 41 is provided. The comparison circuit 151 reads the expected value corresponding to the value of the internal signal or output signal output from the MUX 41 from the expected value memory 150 and compares it. For example, when all the values match, it outputs “1”. “0” is output when there is an unmatched value. Whether or not the comparison circuit 151 performs the comparison is determined according to the set value stored in the debug setting register of the control register 30, and “1” is output when the comparison is not performed. .

  A clock signal for operating the target circuit 20 is input to the clock supply unit 152 from the input terminal of the FPGA 2 and is supplied to the target circuit 20 through the clock supply unit 152. The clock supply unit 152 switches supply / non-supply of the clock signal to the target circuit 20 in accordance with the comparison result of the comparison circuit 151. In the simplest configuration, for example, the comparison circuit 151 performs comparison as described above. When outputting the result as “0” or “1”, it can be realized by using one AND element.

  In the circuit verification apparatus 101 configured as described above, the expected value of the internal signal or the output signal of the target circuit 20 is stored in the expected value memory 150 in advance, the comparison is performed by the comparison circuit 151, and the target circuit 20 is compared according to the comparison result. The clock supply unit 152 is configured to stop the supply of the clock signal to the target circuit 20. When an error occurs during the operation of the target circuit 20, the operation of the target circuit 20 can be automatically stopped. The addition of the comparison circuit 151 and the clock supply unit 152 and the connection with the expected value memory 150 may be performed by a designer, or may be performed automatically before performing logic synthesis. Good. The expected value memory 150 may be provided in the FPGA 2. Further, the value of the output signal of the MUX 41 and the expected value of the expected value memory 150 are compared. However, the present invention is not limited to this. For example, the internal signal or output signal of the target circuit 20 stored in the internal memory 44 is not limited thereto. The configuration may be such that the value and the expected value of the expected value memory 150 are compared.

  The other configuration of the circuit verification device 101 according to the second embodiment is the same as the configuration of the circuit verification device 1 according to the first embodiment, and accordingly, corresponding portions are denoted by the same reference numerals and detailed description is given. Is omitted.

(Embodiment 3)
FIG. 16 is a block diagram showing a configuration of a circuit verification apparatus according to Embodiment 3 of the present invention. In the circuit verification device 201 according to the third embodiment, a clock signal for operating the target circuit 20 is input from the input terminal of the FPGA 2 to the clock supply unit 252 in the FPGA 2, and the clock is supplied to the target circuit 20 via the clock supply unit 252. A signal is given. The clock supply unit 252 switches the supply / non-supply of the clock signal to the target circuit 20 in accordance with the clock stop signal supplied from the clock controller 251.

  The clock controller 251 operates in response to a clock signal that is an output signal of the clock supply unit 252, and clocks a clock stop signal based on a setting value that defines a clock stop condition stored in the debug setting register of the control register 230. The signal is supplied to the supply unit 252 and the supply of the clock signal to the target circuit 20 is stopped. Further, the clock supply of the clock supply unit 252 is restarted by a stop cancellation command given from the CPU 3. Therefore, the designer can stop the operation of the target circuit 20 at an arbitrary timing only by changing the setting value of the debug setting register of the control register 230. After the stop, the designer gives a stop release instruction. The operation of the circuit 20 can be resumed.

  FIG. 17 is a schematic diagram illustrating a configuration of the control register 230 of the circuit verification device 201 according to the third embodiment of the present invention. Although the control register 230 has the same hardware configuration as the control register 30 according to the first embodiment, the debug setting register stores a step execution start setting, a register that stores a step execution end setting, and a step And a register for storing the number setting. In these, the number of clock signals for operating the target circuit 20 is set.

  The circuit verification apparatus 201 according to the third embodiment is configured so that the target circuit 20 can perform so-called step execution by storing the set values in the three registers described above. After the operation of the target circuit 20 starts, when the number of clocks of the clock signal reaches the number of clocks set as the step execution start setting, the supply of the clock signal to the target circuit 20 is stopped, thereby The operation is stopped. Further, the operation of the target circuit 20 can be restarted by giving a stop release command after the operation is stopped, and then the operation of the target circuit 20 is stopped for each number of clocks set as the step number setting. . When the operation of the target circuit 20 is repeatedly stopped and restarted, and the number of clocks of the clock signal reaches the number of clocks set as the step execution end setting, the step execution is ended and the clock signal is supplied to the target circuit 20 The normal operation is performed without stopping.

  FIG. 18 is a block diagram showing a configuration example of the clock controller 251 of the circuit verification apparatus 201 according to Embodiment 3 of the present invention. The clock controller 251 includes a first counter 261 and a second counter 262 that increase the value according to the clock signal that is the output of the clock supply unit 252. The first counter 261 is for counting the number of clocks of the clock signal from the start of the operation of the target circuit 20, and the second counter 262 counts an interval at which the operation of the target circuit 20 is stopped, so-called step number. Is for. The second counter 262 can be reset by a determination unit 266 described later.

  Further, the clock controller 251 compares the value of the first counter 261 and the number of clocks set as the step execution start setting in the control register 230, and ends the step execution in the value of the first counter 261 and the control register 230. A comparison circuit 264 that compares the number of clocks set as the setting, and a comparison circuit 265 that compares the value of the second counter 262 and the number of clocks set as the step number setting in the control register 230. The comparison results of 263, 264, and 265 are given to the determination unit 266.

  The determination unit 266 stops the supply of the clock signal to the target circuit 20 by supplying a clock stop signal to the clock supply unit 252 according to the comparison results of the comparison circuits 263, 264, and 265, and stops the operation of the target circuit 20. I am trying to make it. Further, when a stop release command is given from the CPU 3, the supply of the clock signal from the clock supply unit 252 is resumed, and the operation of the target circuit 20 is resumed. For example, the clock supply unit 252 stops the supply of the clock signal to the target circuit 20 when the clock stop signal is “1”, and supplies the clock signal when the clock stop signal is “0”. .

  FIG. 19 is a flowchart illustrating a procedure of a clock signal supply stop process performed by the determination unit 266 of the clock controller 251 of the circuit verification device 201 according to the third embodiment of the present invention. After the operation of the target circuit 20 is started, the determination unit 266 acquires the comparison result of the comparison circuit 263 (step S31), and the value of the first counter 261 matches the number of clocks stored as the step execution start setting. It is checked whether or not to perform (step S32). If they do not match (S32: NO), the process returns to step S31 and waits until they match. If they match (S32: YES), “1” is output as the clock stop signal, the supply of the clock signal to the target circuit 20 by the clock supply unit 252 is stopped (step S33), and the operation of the target circuit 20 is stopped. Let

  After the supply of the clock signal is stopped, it is checked whether or not a stop release command is given from the CPU 3 (step S34). If no stop release command is given (S34: NO), the process returns to step S33 to stop. Wait until a release order is given. When the stop cancellation command is given (S34: YES), “0” is output as the clock stop signal, the supply stop of the clock signal to the target circuit 20 by the clock supply unit 252 is canceled (step S35), and the target circuit The operation of 20 is resumed.

  Next, the value of the second counter 262 is reset (step S36), the comparison result of the comparison circuit 264 is acquired (step S37), and the value of the first counter 261 and the number of clocks stored as the step execution end setting are obtained. It is checked whether or not they match (step S38). If they do not match (S38: NO), the comparison result of the comparison circuit 265 is further acquired (step S39), and it is checked whether or not the value of the second counter 262 matches the number of clocks stored as the step number setting. (Step S40) If they do not match (S40: NO), the process returns to Step S37, and the comparison result is continuously acquired until a matching comparison result is obtained from the comparison circuit 264 or the comparison circuit 265. If the comparison by the comparison circuit 265 matches in step S40 (S40: YES), the process returns to step S33 and the supply of the clock signal is stopped. If the comparison by the comparison circuit 264 matches in step S38 (S38: YES), the determination unit 266 ends the clock signal supply stop process. Thereafter, the target circuit 20 performs a normal operation without stopping.

  In the circuit verification device 201 according to the third embodiment having the above-described configuration, the control register 230 stores only three setting values of the step execution start setting, the step execution end setting, and the step number setting. Execution can be performed.

  For example, when the operation of the target circuit 20 is stopped, the designer changes all the setting values stored in the control register 230 and switches the selection of signals by the MUX 41 so that the designer can select all the internal signals and output signals of the target circuit 20. Furthermore, by setting the step number setting of the control register 230 to 1, it becomes possible to observe all internal signals and output signals at all timings, so that the debugging accuracy can be improved. Can be increased.

  Note that the circuit configuration of the clock controller 251 shown in FIG. 18 is an example, and the present invention is not limited to this. Moreover, it is good also as a structure which can set two or more timings of the start and completion | finish of step execution. Note that the addition and connection of the clock controller 251 and the clock supply unit 252 may be performed by a designer, or may be performed automatically before performing logic synthesis.

  In addition, since the other structure of the circuit verification apparatus 201 which concerns on Embodiment 3 is the same as that of the circuit verification apparatus 1 which concerns on Embodiment 1, it attaches | subjects the same code | symbol to a corresponding location, and is detailed description Is omitted.

(Embodiment 4)
FIG. 20 is a block diagram showing a configuration of a circuit verification apparatus according to Embodiment 4 of the present invention. The circuit verification device 301 according to the fourth embodiment includes a counter 351 in the FPGA 2 that operates in synchronization with a clock signal input from the input terminal of the FPGA 2 to the target circuit 20. The counter 351 is for counting the number of clock signals from the start of the operation of the target circuit 20, and the output of the counter 351 is given to the observation controller 352 in the FPGA 2.

  The observation controller 352 outputs the output signal of the target circuit 20 and the internal signal of the target circuit 20 supplied to the internal memory 44 via the MUX 41 according to the setting value stored in the debug setting register of the control register 330 and the value of the counter 351. Is stored in the internal memory 44, and the storage of the output signal of the target circuit 20 and the internal signal in the internal memory 44 is controlled.

  FIG. 21 is a schematic diagram showing a configuration of the control register 330 of the circuit verification device 301 according to the fourth embodiment of the present invention. The control register 330 has the same hardware configuration as the control register 30 according to the first embodiment, but the debug setting register is provided with a register for storing the observation start setting and a register for storing the observation end setting. Yes. In these, the number of clock signals for operating the target circuit 20 is set.

  When the value of the counter 351 coincides with the value of the observation start setting stored in the control register 330 after the operation of the target circuit 20 starts, the observation controller 352 sends the output signal of the target circuit 20 and the internal signal to the internal memory 44. The memory is started. When the value of the counter 351 matches the value of the observation end setting stored in the control register 330 after the start of storage in the internal memory 44, the output signal of the target circuit 20 and the internal signal to the internal memory 44 are stored. The memory is terminated.

  The circuit verification apparatus 301 having the above configuration is designed so that the designer stores the observation start setting and the observation end setting in the control register 330 in advance, and outputs only within a limited range when the target circuit 20 is operated. Signal and internal signal values can be stored automatically. Therefore, the internal memory 44 in the FPGA 2 can be used effectively. In the present embodiment, one set value related to the observation start setting and the observation end setting is stored in the control register 330. However, the present invention is not limited to this, and a plurality of set values are stored. It is good also as a structure which memorize | stores the value of an output signal and an internal signal within the range.

  In addition, since the other structure of the circuit verification apparatus 301 which concerns on Embodiment 4 is the same as that of the circuit verification apparatus 1 which concerns on Embodiment 1, the same code | symbol is attached | subjected to a corresponding location and detailed description is given. Is omitted.

(Embodiment 5)
FIG. 22 is a block diagram showing a configuration of a circuit verification apparatus according to Embodiment 5 of the present invention. The circuit verification apparatus 401 according to the fifth embodiment determines whether the output signal of the target circuit 20 output from the MUX 41 and the value of the internal signal match a condition set in the control register 430 in advance. A condition determination unit 450 that switches supply / non-supply of the clock signal of the clock supply unit 451 that supplies a signal to the target circuit 20 is provided.

  Although not shown, the control register 430 has set values (signal selection settings 0 to 3) for selecting any four signals from the output signals of the target circuit 20 output from the MUX 41 and the values of the internal signals. And a comparison result of whether or not the set values (expected value settings 0 to 3) for setting the expected values of the values of the four selected signals match the values of the four signals and the four expected values, respectively. Setting for selecting whether the four comparison results are all the same as the determination condition or the determination condition is the case where at least one of the four comparison results are the same A register for storing (condition setting) is provided.

  The clock supply unit 451 switches the supply / non-supply of the clock signal to the target circuit 20 according to the determination result of the condition determination unit 450. In the simplest configuration, for example, an AND element or an OR element is 1 This can be realized by using two.

  FIG. 23 is a block diagram showing a configuration of condition determination unit 450 of circuit verification device 401 according to Embodiment 5 of the present invention. The condition determination unit 450 selects any one value from the internal signal or output signal value of the target circuit 20 output by the MUX 41 according to the value of the signal selection setting 0 to 3 stored in the control register 430. Four multiplexers (mux 0 to 3) are provided. The four values selected by mux 0 to 3 are respectively supplied to four comparators (comparators 0 to 3). The comparators 0 to 3 are stored in the control register 430 with the four values given. The expected value settings 0 to 3 are respectively compared, and a comparison result indicating whether or not they match is given to the determination unit 452.

  The determination unit 452 is provided with the four comparison results from the comparators 0 to 3 and the condition setting stored in the control register 430, and the clock supply unit 451 performs the determination based on the given comparison result and condition setting. The supply / non-supply of the clock signal is switched. For example, when the condition setting is “0”, the clock signal is not supplied when all four comparison results match, and when the condition setting is “1”, at least one of the four comparison results matches The clock signal is not supplied. The simplest configuration of the determination unit 452 can be realized by using a 4-input AND element, a 4-input OR element, and a multiplexer that selects and outputs either the AND element or the output of the OR element. is there.

  As described above, by providing the condition determination unit 450, the supply of the clock signal is stopped and the operation of the target circuit 20 is stopped when the internal signal or the output signal of the target circuit 20 satisfies a predetermined condition. it can. At this time, the designer only has to store the signal selection settings 0 to 3, the expected value settings 0 to 3, and the setting values of the condition settings in the control register 430. FIG. 24 is a schematic diagram showing a display example of the setting screen of the circuit verification device according to the fifth embodiment of the present invention, which is displayed on a display device (not shown) provided in the PC 10.

  On the setting screen displayed on the display of the PC 10, an input box for inputting the signal name of the internal signal or output signal of the target circuit 20 and an expected value for this signal as a condition for stopping the operation of the target circuit 20. 461 is provided. In the input box 461, signal names and expected values of the four signals can be input as stop conditions. Also, an AND check button 462 for selecting to stop the operation of the target circuit 20 when all four stop conditions are satisfied under the input box 461, and any one of the four stop conditions is satisfied. In this case, an OR check button 463 for selecting to stop the operation of the target circuit 20 is provided. Only one of the selection by the AND check button 462 and the selection by the OR check button 463 is performed. I can do it.

  Settings by the input box 461, the AND check button 462, and the OR check button 463 are reflected by pressing a setting button 464 provided at the bottom of the setting screen. When the setting button 464 is pressed, the signal selection setting 0 to 3 is stored in the control register 430 so that the signal corresponding to the signal name input to the input box 461 is selected by the mux 0 to 3 of the condition determination unit 450. The signal name and the selection setting of mux 0 to 3 are associated with each other by referring to a setting file stored in, for example, a hard disk in the PC 10. When the setting button 464 is pressed, the four expected values input in the input box 461 are stored in the control register 430 as the expected value settings 0 to 3, and either the AND check button 462 or the OR check button 463 is selected. The selection is stored in the control register 430 as a condition setting.

  In the circuit verification device 401 according to the fifth embodiment having the above configuration, the operation of the target circuit 20 is stopped when the value of the internal signal or output signal of the target circuit 20 matches a predetermined expected value. Therefore, it is easy for the designer to perform debugging work, and the convenience of the circuit verification apparatus can be improved. Note that the setting screen shown in FIG. 24 is an example, and the present invention is not limited to this. In addition, although four signals can be designated as internal signals or output signals of the target circuit 20, the present invention is not limited to this, and three or less or five or more signals are designated and expected values are set. The operation of the target circuit 20 may be stopped. The addition and connection of the condition determination unit 450 and the clock supply unit 451 may be performed by a designer, or may be performed automatically before the logic synthesis tool performs logic synthesis. .

  The other configuration of the circuit verification device 401 according to the fifth embodiment is the same as the configuration of the circuit verification device 1 according to the first embodiment. Is omitted.

  Further, the circuit verification device may be configured to have all or some of the functions provided in the circuit verification devices of the first to fifth embodiments.

It is a block diagram which shows the structure of the circuit verification apparatus which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows one structural example of the address space of CPU of the circuit verification apparatus which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows one structural example of the control register of the circuit verification apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows an example of the design flow of the digital circuit using the circuit verification apparatus which concerns on Embodiment 1 of this invention. It is a schematic diagram for demonstrating the method of changing the internal signal to observe. It is a block diagram which shows the supply relationship of a clock signal. It is a schematic diagram for demonstrating the method of changing an input signal. It is a schematic diagram for demonstrating the method of performing operation | movement verification in a circuit block unit. It is a schematic diagram for demonstrating the method of changing a fixed value. It is a schematic diagram for demonstrating the method of replacing a circuit block. It is a schematic diagram for demonstrating the method of performing the data input to a circuit block. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on the modification 1 of Embodiment 1 of this invention. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on the modification 2 of Embodiment 1 of this invention. It is a schematic diagram which shows one structural example of the address space of CPU of the circuit verification apparatus which concerns on the modification 2 of Embodiment 1 of this invention. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on Embodiment 3 of this invention. It is a schematic diagram which shows the structure of the control register of the circuit verification apparatus concerning Embodiment 3 of this invention. It is a block diagram which shows the example of 1 structure of the clock controller of the circuit verification apparatus concerning Embodiment 3 of this invention. It is a flowchart which shows the procedure of the supply stop process of the clock signal which the determination part of the clock controller of the circuit verification apparatus concerning Embodiment 3 of this invention performs. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on Embodiment 4 of this invention. It is a schematic diagram which shows the structure of the control register of the circuit verification apparatus which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the circuit verification apparatus which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the condition determination part of the circuit verification apparatus which concerns on Embodiment 5 of this invention. It is a schematic diagram which shows one display example of the setting screen of the circuit verification apparatus which concerns on Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit verification apparatus 2, 2a, 2b, 2c, 2d FPGA (programmable element)
3 CPU (control unit)
3a Control chip 5 Memory (observation value storage)
6 Communication devices (communication means)
10 PC
20 Target circuit (circuit to be verified)
25 Test pattern generation circuit (auxiliary circuit)
30 Control register (specified value storage)
40, 41 MUX (auxiliary circuit, selection circuit)
42 Memory switching part (auxiliary circuit)
44 Internal memory (auxiliary circuit, observation value storage)
46 Clock signal generation circuit 47 Frequency multiplication circuit (observation clock signal output circuit)
81, 91 Circuit verification device 101 Circuit verification device 150 Expected value memory (expected value storage unit)
151 Comparison circuit (comparison means)
152 Clock supply unit (stopping means)
201 circuit verification device 230 control register (specified value storage unit)
251 clock controller 252 clock supply unit 261 first counter 262 second counter 263, 264, 265 comparison circuit 266 determination unit 301 circuit verification device 330 control register (specified value storage unit)
351 Counter 352 Observation controller 401 Circuit verification device 430 Control register (specified value storage unit)
450 Condition determination unit 451 Clock supply unit

Claims (16)

In a circuit verification apparatus comprising a programmable element capable of reconfiguring a logic circuit and verifying the operation of a circuit to be verified configured in the programmable element,
In the programmable element,
An auxiliary circuit having a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified;
A specified value storage unit that stores a specified value that defines the operation of the circuit to be verified and / or the auxiliary circuit; and
A control unit that stores a specified value in the specified value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit ;
A circuit board provided with the programmable element and the control unit;
A communication means provided on the circuit board for communicating between the control unit and an external device ;
The circuit to be verified has a plurality of circuit blocks,
The plurality of circuit blocks include a circuit block to be verified and an input side circuit block that supplies an input signal to the circuit block to be verified.
The specified value storage unit stores an input value supplied to the circuit block to be verified instead of an input signal supplied by the input side circuit block, and a specified value that determines whether the input value is supplied to the circuit to be verified. And
The auxiliary circuit selects an input signal from the input-side circuit block or an input value stored in the specified value storage unit according to the specified value stored in the specified value storage unit, and sends it to the circuit block to be verified. A selection circuit to give,
The circuit verification apparatus according to claim 1, wherein the control unit makes it possible to access the storage of the specified value and the input value to the specified value storage unit of the programmable element by designating an address and data in a common address space . The auxiliary circuit has a selection circuit that selects and outputs an internal signal of the circuit to be verified,
The circuit verification apparatus according to claim 1 , wherein the specified value storage unit stores a specified value that defines selection of the selection circuit. In a circuit verification apparatus comprising a programmable element capable of reconfiguring a logic circuit and verifying the operation of a circuit to be verified configured in the programmable element,
  In the programmable element,
  A selection circuit that selects and outputs an internal signal of the circuit to be verified, an auxiliary circuit having a function of providing an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified;
  A specified value storage unit that stores a specified value that defines the operation of the circuit to be verified and / or the auxiliary circuit, including a defined value that defines the selection of the selection circuit;
  Is configured, and
  A control unit that stores a specified value in the specified value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit;
  An observation value storage unit for storing the value of the internal signal output by the selection circuit;
  A counter that operates in response to a clock signal input to the circuit to be verified;
  With
  The specified value storage unit is configured to store a start counter value for starting storage of the value of the internal signal in the observation value storage unit and an end counter value for ending storage,
  The observed value storage unit starts storage when the counter value matches the start counter value, and ends storage when the counter value matches the end counter value.
  A circuit verification apparatus characterized by the above. An observation clock signal output circuit that outputs an observation clock signal having a frequency higher than that of the clock signal input to the circuit to be verified;
The specified value storage unit can operate in synchronization with the observation clock signal,
Wherein the control unit, in synchronization with the observation clock signal to change the specified value of the prescribed value storage unit, Ri Citea to change the internal signal the selection circuit outputs,
The circuit verification device according to claim 3 , wherein the observation value storage unit stores data in synchronization with the observation clock signal . In a circuit verification apparatus comprising a programmable element capable of reconfiguring a logic circuit and verifying the operation of a circuit to be verified configured in the programmable element,
  In the programmable element,
  A selection circuit that selects and outputs an internal signal of the circuit to be verified, an auxiliary circuit having a function of providing an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified;
  A specified value storage unit that stores a specified value that defines the operation of the circuit to be verified and / or the auxiliary circuit, including a defined value that defines the selection of the selection circuit;
  Is configured, and
  A control unit that stores a specified value in the specified value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit;
  An expected value storage unit for storing an expected value of an internal signal of the circuit to be verified;
  Comparison means for comparing the internal signal output by the selection circuit and the expected value stored in the expected value storage unit;
  Stop means for stopping the operation of the circuit to be verified if the internal signal and the expected value do not match as a result of comparison by the comparison means;
  Having
  A circuit verification apparatus characterized by the above. In a circuit verification apparatus comprising a programmable element capable of reconfiguring a logic circuit and verifying the operation of a circuit to be verified configured in the programmable element,
  In the programmable element,
  An auxiliary circuit having a function of supplying an input signal to the circuit to be verified and / or a function of acquiring an output signal from the circuit to be verified;
  A specified value storage unit that stores specified values that define the operation of the circuit to be verified and / or the auxiliary circuit;
  Is configured, and
  A control unit that stores a specified value in the specified value storage unit and controls the operation of the circuit to be verified and / or the auxiliary circuit;
  A counter that operates in response to a clock signal input to the circuit to be verified;
  Stop means for stopping the operation of the circuit to be verified every predetermined value of the counter;
  With
  The specified value storage unit stores the predetermined value.
  A circuit verification apparatus characterized by the above. Said stop means, said by stopping the supply of the clock signal to the circuit to be verified, the circuit verification apparatus according to claim 5 or claim 6 are so as to stop the operation of the circuit to be verified. The circuit to be verified has a plurality of circuit blocks,
The plurality of circuit blocks include a circuit block to be verified and an input side circuit block that supplies an input signal to the circuit block to be verified.
The specified value storage unit stores an input value supplied to the circuit block to be verified instead of an input signal supplied by the input side circuit block, and a specified value that determines whether the input value is supplied to the circuit to be verified. And
The auxiliary circuit selects an input signal from the input-side circuit block or an input value stored in the specified value storage unit according to the specified value stored in the specified value storage unit, and sends it to the circuit block to be verified. The circuit verification device according to claim 3 , further comprising a selection circuit that provides the selection circuit. A circuit board provided with the programmable element and the control unit;
A communication means provided on the circuit board for communicating between the control unit and an external device;
Wherein the control unit, the storage of the specified value to the specified value storage unit of the programmable elements, one of the common address space claims 3 to 8 that is to be accessed by designating the addresses and data by the The circuit verification apparatus described in 1. A storage unit provided on the circuit board;
The control unit is configured to be able to access the specified value storage unit of the programmable element, the communication unit, and the storage unit of the circuit board by specifying an address and data in a common address space. The circuit verification apparatus according to claim 2 or 9. The circuit to be verified has a plurality of circuit blocks,
The plurality of circuit blocks include a circuit block to be verified, an output side circuit block that acquires an output signal from the circuit block to be verified, and an alternative circuit block that can be substituted for the circuit block to be verified.
The specified value storage unit is configured to store a specified value that determines whether or not the verification target circuit block is replaced by the replacement circuit block.
The auxiliary circuit includes a selection circuit that selects an output signal of the circuit block to be verified or an output signal of the alternative circuit block according to the specified value stored in the specified value storage unit and supplies the selected signal to the output-side circuit block. circuit verification apparatus according to any one of claims 1 to 10 having. The auxiliary circuit selects a test pattern generation circuit that generates an input signal to be supplied to the circuit to be verified, and an input signal supplied from an input terminal provided in the programmable element or an input signal generated by the test pattern generation circuit. And a selection circuit for giving to the circuit to be verified.
The prescribed value storage unit, the circuit verification apparatus according to any one of claims 1 to 11 the specified value are provided to store defining a selection of the selection circuit. An observation clock signal output circuit that outputs an observation clock signal having a frequency higher than that of the clock signal input to the circuit to be verified;
The specified value storage unit can operate in synchronization with the observation clock signal,
6. The control unit according to claim 2 or 5, wherein the control unit changes a specified value of the specified value storage unit in synchronization with the observation clock signal, and changes an internal signal output by the selection circuit. Circuit verification equipment. The circuit verification device according to claim 13 , further comprising an observation value storage unit that stores a value of an internal signal output from the selection circuit in synchronization with the observation clock signal. A circuit verification method using the circuit verification device according to any one of claims 1 to 14 , wherein a circuit to be verified is configured in the programmable element, and the circuit to be verified is verified.
An auxiliary circuit having a function of giving an input signal to the circuit to be verified and / or an output signal from the circuit to be verified, and a circuit to be verified and / or the circuit to be verified. A specified value storage unit that stores a specified value that defines the operation of the auxiliary circuit, and
A circuit verification method characterized in that the specified value is stored in the specified value storage unit and the verification is performed by controlling the operation of the circuit to be verified and the auxiliary circuit. Stop the operation of the circuit to be verified,
Changing the specified value stored in the specified value storage unit during operation stop of the circuit to be verified;
Resuming the operation of the circuit to be verified;
The circuit verification method according to claim 15.

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