JP2004014574A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device into which ions are implanted without being shielded by a gate electrode, even in a device of high integration degree and high density. <P>SOLUTION: This method comprises a step for forming an insulating film 2 on a semiconductor substrate 1, a step for forming a conductive layer on the insulating film 2, a step for forming a hard mask 6 on the conductive layer, a step for forming the gate electrodes 8 and 8' by etching the insulating film 2 and the conductive layer by using the hard mask 6, a step for processing the hard mask 6 into a tapered shape, and a step for implanting the ions from a diagonally upward direction into the semiconductor substrate 1 with the gate electrodes 8 and 8' as masks. The conductive layer can have a structure in which a polysilicon layer 3, a tungsten nitride layer 4 and a tungsten layer 5 are laminated in this order. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a step of implanting ions into a semiconductor substrate from an obliquely upward direction of the semiconductor substrate using a gate electrode or the like as a mask.
[0002]
[Prior art]
In recent years, as the degree of integration of semiconductor devices has increased, the dimensions of individual devices have been miniaturized, and the dimensions of semiconductor regions constituting each device have also been miniaturized. As the miniaturization progresses, a short channel effect causes a problem of punch-through between the source and the drain. Therefore, a halo implantation method has been conventionally used as one of the techniques for solving this problem. In the halo implantation method, for example, as described in JP-A-11-214687, a high-concentration impurity region of the same type as a substrate (hereinafter, referred to as a pocket region) is formed so as to surround a source / drain portion. This is a method of suppressing punch-through between the source and the drain. As a method of forming a pocket region, there is a method of implanting impurity ions obliquely into a semiconductor substrate as described in Japanese Patent Application Laid-Open No. 9-246538.
[0003]
Incidentally, polysilicon is generally used as a gate electrode material. In addition, as a structure of the gate electrode, a high melting point metal such as tungsten (W), molybdenum (Mo), titanium (Ti) or a silicide of these metals is used in order to reduce the sheet resistance and increase the speed of the device. A laminated structure formed on polysilicon is taken. For forming such a gate electrode, an etching method using a hard mask is employed.
[0004]
FIG. 11 shows a conventional method for manufacturing a semiconductor device. First, after a gate insulating film 43 is formed on the main surface of the semiconductor substrate 42, a polysilicon layer 44 doped with impurities is formed. Subsequently, after a tungsten nitride (WN) layer 45 and a tungsten (W) layer 46 are deposited, silicon oxide (SiO 2) ₂ 11) A hard mask 47 made of a film or the like is formed, and the structure shown in FIG. Next, a resist film 48 is formed, and the resist film 48 is patterned by a photolithography method (FIG. 11B). After the hard mask 47 is etched using the patterned resist film 48 as a mask, the resist film 48 is removed (FIG. 11C). Using the hard mask 47, the tungsten film 46, the tungsten nitride film 45, the polysilicon film 44, and the gate insulating film 43 are etched to obtain the structure shown in FIG.
[0005]
[Problems to be solved by the invention]
By the way, since the hard mask is difficult to remove selectively like a resist film, when the hard mask is left on the gate electrode, the aspect ratio of the gate electrode increases by the thickness of the hard mask. Will do. On the other hand, in highly integrated and high density devices, the source / drain profile needs to be very shallow. Therefore, in FIG. 11, the angle θ (hereinafter, referred to as an implantation angle) between the incident direction (A direction) of the implanted ions by the halo implantation method and the direction (B direction) perpendicular to the main surface 42 a of the semiconductor substrate 42 is large. Is required. However, as the aspect ratio of the gate electrode increases, there is a problem that implanted ions having a large implantation angle θ are shielded by the gate electrodes 49 and 49 ′, and a desired pocket region cannot be formed. That is, in the case of a highly integrated and high-density device, ions need to be incident at an implantation angle of 30 ° or more, whereas in a conventional semiconductor device, the implantation angle is limited to about 30 °. When the size is increased, there is a problem that ions are shielded by the gate electrode.
[0006]
The present invention has been made in view of such a problem. That is, the present invention provides a method of manufacturing a semiconductor device capable of implanting ions without being shielded by a gate electrode even in a highly integrated and high density device.
[0007]
[Means for Solving the Problems]
A first method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of processing the gate electrode into a tapered shape. And a step of implanting ions into the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the gate electrode processed into the taper shape as a mask. The gate electrode may have a laminated structure including a polysilicon layer and a high melting point metal layer, and the processing of the gate electrode may be processing of only the high melting point metal layer. Further, the gate electrode may have a laminated structure including a polysilicon layer and a silicide layer, and the processing of the gate electrode may be processing of only the silicide layer.
[0008]
The gate electrode may have a structure in which a polysilicon layer, a tungsten nitride layer, and a tungsten layer are stacked in this order, and at least one of these layers may be processed into a tapered shape in order from the top. Here, “at least one layer in order from the top” means that the tungsten layer, which is the uppermost layer, is always included, and is not related to the processing order. For example, processing may be performed so that only the uppermost tungsten layer has a tapered shape, or the tungsten layer and the tungsten nitride layer may be processed so as to have a tapered shape. Further, the tungsten layer, the tungsten nitride layer, and the polysilicon layer may be processed so as to have a tapered shape. As long as these finally have a tapered shape, the processing order may be any one.
[0009]
The step of processing into a tapered shape can be performed by anisotropic etching using high-density plasma. Further, the semiconductor substrate may be an SOI substrate.
[0010]
According to a second method of manufacturing a semiconductor device of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a conductive layer on the insulating film, and forming a hard mask on the conductive layer Forming a gate electrode by etching the insulating film and the conductive layer using the hard mask, processing the hard mask into a tapered shape, and forming the semiconductor from an obliquely upward direction of the semiconductor substrate using the gate electrode as a mask. Implanting ions into the substrate. The step of processing the hard mask into a tapered shape may further include processing the conductive layer into a tapered shape.
[0011]
The conductive layer has a laminated structure including a polysilicon layer and a high-melting point metal layer, and a hard mask may be formed on the high-melting point metal layer. The refractory metal layer may be processed into a tapered shape. Further, the conductive layer has a laminated structure including a polysilicon layer and a silicide layer, and a hard mask may be formed on the silicide layer. May be processed into a tapered shape.
[0012]
The conductive layer may have a structure in which a polysilicon layer, a tungsten nitride layer, and a tungsten layer are stacked in this order. In addition to the hard mask, at least one of these layers is processed into a tapered shape in order from the top. May be. Here, “at least one layer in order from the top” means that the tungsten layer, which is the uppermost layer, is always included, and is not related to the processing order. For example, the tungsten layer may be processed to have a tapered shape, or the tungsten layer and the tungsten nitride layer may be processed to have a tapered shape. Further, the tungsten layer, the tungsten nitride layer, and the polysilicon layer may be processed so as to have a tapered shape. As long as these finally have a tapered shape, the processing order may be any one.
[0013]
The step of processing into a tapered shape can be performed by anisotropic etching using high-density plasma. Further, the semiconductor substrate may be an SOI substrate.
[0014]
In a third method of manufacturing a semiconductor device according to the present invention, a step of forming an oxide film on a semiconductor substrate, a step of forming a dummy gate pattern on the oxide film, and processing the dummy gate pattern into a tapered shape A step of implanting ions into the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the dummy gate pattern processed into the tapered shape as a mask, and a step of forming an interlayer insulating film on the oxide film and the dummy gate pattern Removing the interlayer insulating film until the upper surface of the dummy gate pattern is exposed, selectively removing the dummy gate pattern to form a groove, and removing the oxide film exposed at the bottom of the groove. Forming a gate insulating film on the bottom and side surfaces of the trench and on the interlayer insulating film, and filling the trench with a gate electrode material. The features. The step of processing into a tapered shape can be performed by anisotropic etching using high-density plasma.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
Embodiment 1
In this embodiment, an example in which the present invention is applied to a semiconductor device having a MOS (Metal Oxide Semiconductor) structure will be described with reference to FIGS.
[0017]
First, as shown in FIG. 1A, a gate insulating film 2 is formed on a main surface of a semiconductor substrate 1. As the semiconductor substrate 1, for example, a silicon substrate can be used. The gate insulating film 2 can be made of, for example, silicon oxide or silicon nitride, and can be formed by a chemical vapor deposition method (hereinafter, referred to as CVD) or the like. The thickness of the gate insulating film 2 is preferably 1 to 15 nm.
[0018]
Next, a conductive layer is formed. First, a polysilicon layer 3 is formed on the gate insulating film 2. Specifically, polysilicon is deposited on the gate insulating film 2 using, for example, a low pressure CVD furnace. The thickness of the polysilicon layer 3 is preferably 30 to 100 nm. Further, instead of the polysilicon layer, an amorphous silicon layer may be formed on the gate insulating film.
[0019]
When the polysilicon layer 3 is formed on the gate insulating film 2, an impurity is added to the source gas to form n + type or p + type polysilicon. For example, phosphine (PH ₃ ) Can be used as the doping material to form n + type polysilicon. The impurity concentration is 5 × 10 for both n + type and p + type. ¹⁹ cm ^-3 The above is preferable. In addition to the addition of impurities at the time of film formation, n + type or p + type polysilicon may be formed by ion implantation.
[0020]
Next, to reduce the sheet resistance, a tungsten nitride layer 4 is deposited on the polysilicon layer 3 by, for example, a sputtering method or a CVD method, and then a tungsten layer 5 is deposited. The thickness of the tungsten nitride layer 4 is preferably 3 to 10 nm, and the thickness of the tungsten layer 5 is preferably 30 to 100 nm. A conductive layer is formed by the polysilicon layer 3, the tungsten nitride layer 4, and the tungsten layer 5.
[0021]
The layer formed on the polysilicon layer 3 is not limited to the tungsten nitride layer or the tungsten layer, but may be another layer. For example, a silicide layer (WSi) of a refractory metal such as tungsten, molybdenum, titanium, tantalum (Ta), etc. ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ May be formed on the polysilicon layer 3 by a sputtering method or a CVD method.
[0022]
Next, a hard mask 6 is formed to obtain the structure shown in FIG. As the hard mask 6, for example, silicon oxide or silicon nitride can be used, and can be formed by a low-pressure CVD method or a plasma CVD method. The thickness of the hard mask 6 is preferably 50 to 200 nm.
[0023]
Next, after forming a resist film 7 on the hard mask 6, the resist film 7 is patterned by photolithography to form a desired pattern (FIG. 1B). Subsequently, the hard mask 6 is etched by a dry etching method using the resist film 7 as a mask, and then the resist film 7 is removed by, for example, an ashing process using plasma (FIG. 1C). Then, using the hard mask 6, the tungsten layer 5 and the tungsten nitride layer 4 are etched by a dry etching method to obtain a structure shown in FIG.
[0024]
Next, the hard mask 6 is processed into a tapered shape. Here, the tapered shape is, specifically, as shown in FIG. 2A, in the gap 9 between the gate electrode 8 and the gate electrode 8 ′, from the lower part of the cross section of the hard mask 6 to the upper part of the cross section. A shape whose opening size is enlarged. In the figure, the cross section of the hard mask 6 is processed so as to be substantially triangular, but the present invention is not limited to this. For example, the processing may be performed so that the cross section of the hard mask is trapezoidal. The processing is performed by anisotropically etching the hard mask using, for example, a CVD apparatus using a high density plasma (High Density Plasma) as a plasma source. For example, the semiconductor device shown in FIG. 1D is placed in a film forming chamber (not shown) of a CVD device. Next, after the inside of the film formation chamber is evacuated to a predetermined degree of vacuum, high-frequency AC bias power is applied to the semiconductor substrate, and etching is performed by introducing an appropriate etching gas into the film formation chamber. At this time, by controlling the plasma bias, the inclination (θ ′, hereinafter referred to as a taper angle) from a direction (direction C) parallel to the main surface 1 a of the semiconductor substrate 1 can be changed.
[0025]
By processing the hard mask 6 into a tapered shape, the opening diameter of the gap 9 is reduced to L in FIG. ₁ From L in FIG. ₂ To increase the opening area. Therefore, the ion implantation angle θ at the time of halo implantation can be increased. For example, in the conventional example, the implantation angle is limited to 30 °. If the angle is more than 30 °, ions are shielded by the gate electrode. On the other hand, according to the present embodiment, the implantation angle is made larger than 30 °. It becomes possible.
[0026]
Next, using the hard mask 6, the polysilicon layer 3 and the gate insulating film 2 are etched by a dry etching method to obtain a structure shown in FIG. Thereafter, for the purpose of recovering from damage caused by etching, avoiding electrolytic concentration due to gate edge rounding, and avoiding channeling of source / drain implantation, a selective oxidation process for oxidizing only the polysilicon 3 and the semiconductor substrate 1 is performed. 10 are formed (FIG. 2C). In the drawings, an oxide film formed on the semiconductor substrate 1 is omitted.
[0027]
Next, extension implantation and halo implantation for a punch-through stopper are performed on the semiconductor substrate 1 using the gate electrodes 8, 8 'as a mask to form source / drain regions. Specifically, for example, boron difluoride (BF ₂ ) Is ion-implanted from the direction perpendicular to the semiconductor substrate 1 to form the p − type semiconductor region 11. Subsequently, phosphorus (P) is ion-implanted into the semiconductor substrate 1 at a desired implantation angle θ to form an n + -type halo implanted layer 12. The ion implantation method may be any of a step rotation implantation method and a continuous rotation implantation method. By processing the hard mask 6 into a tapered shape, the opening diameter of the gap 9 formed between the gate electrode 8 and the gate electrode 8 'is increased. Ions incident from the gate electrode 8 and 8 'are not shielded.
[0028]
In the present embodiment, the hard mask 6 is processed into a tapered shape before etching the polysilicon layer 3 and the gate insulating film 2, but the present invention is not limited to this. The hard mask 6 may be processed after the tungsten film 5, the tungsten nitride film 4, the polysilicon layer 3, and the gate insulating film 2 are etched by dry etching using the hard mask 6 as a mask.
[0029]
In the present embodiment, the hard mask is processed into a tapered shape to increase the ion implantation angle θ, but the present invention is not limited to this. For example, as shown in FIG. 3, not only the hard mask 6 but also the tungsten layer 5 may be processed so as to have an entire tapered shape, and the hard mask 6, the tungsten layer 5, and the tungsten nitride layer 4 may be entirely processed. May be processed to have a tapered shape. Further, as shown in FIG. 4, the hard mask 6 may be completely eliminated by further etching, and the tungsten layer 5 or the tungsten layer 5 and the tungsten nitride layer 4 may be processed so as to have a tapered shape. Further, as shown in FIG. 5, by reducing the thickness of the gate electrodes 8, 8 ', the whole of the tungsten film 5, the tungsten nitride layer 4, and the polysilicon layer 3 is processed into a tapered shape. Is also good. By adopting the shapes shown in FIGS. 3 to 5, the ion implantation angle θ can be made larger than that shown in FIG. For example, according to the example of FIG. 3, the injection angle can be increased to about 45 °. Further, according to the example of FIG. 4, it is possible to increase the injection angle to about 60 °. Further, according to the example of FIG. 5, the injection angle can be made larger than 60 °.
[0030]
The taper angle θ ′ is preferably 7 to 85 °, and can be changed, for example, by controlling the plasma bias in a high-density plasma CVD apparatus during etching.
[0031]
Embodiment 2 FIG.
In this embodiment, an example in which the present invention is applied to a semiconductor device having an SOI (Silicon on Insulating Substrate) structure will be described with reference to FIGS.
[0032]
First, an SOI substrate is prepared. As shown in FIG. 6, the SOI substrate 13 includes, for example, a support substrate 14 made of single crystal silicon, an insulating layer 15 formed on the support substrate 14, and a single crystal silicon formed on the insulating layer 15. It is composed of the layer 16 and can be manufactured by, for example, a bonding method or SIMOX (Separation by Implanted Oxygen). Here, the bonding method is a method for preparing an SOI substrate by preparing two silicon substrates each having an insulating layer formed on the surface and bonding the insulating layers of these silicon substrates to each other. SIMOX is a method for manufacturing an SOI substrate by forming an oxide film in a silicon substrate by ion-implanting high-concentration oxygen into the silicon substrate.
[0033]
As in the first embodiment, a gate insulating film 17, a polysilicon layer 18, a tungsten nitride layer 19, a tungsten layer 20, and a hard mask 21 are formed on an SOI substrate 13.
[0034]
First, a gate insulating film 17 is formed on the main surface of the SOI substrate 13. As the gate insulating film 17, for example, silicon oxide or silicon nitride can be used, and can be formed by a chemical vapor deposition method (hereinafter, referred to as CVD) or the like. The thickness of the gate insulating film 17 is preferably 1 to 15 nm.
[0035]
Next, a conductive layer is formed. First, a polysilicon layer 18 is formed on the gate insulating film 17. Specifically, polysilicon is deposited on the gate insulating film 17 using, for example, a low pressure CVD furnace. The thickness of the polysilicon layer 18 is preferably 30 to 100 nm. Further, instead of the polysilicon layer, an amorphous silicon layer may be formed on the gate insulating film.
[0036]
When the polysilicon layer 18 is formed on the gate insulating film 17, an impurity is added to the source gas to form n + type or p + type polysilicon. For example, phosphine (PH ₃ ) Can be used as the doping material to form n + type polysilicon. The impurity concentration is 5 × 10 for both n + type and p + type. ¹⁹ cm ^-3 The above is preferable. In addition to the addition of impurities at the time of film formation, n + type or p + type polysilicon may be formed by ion implantation.
[0037]
Next, to reduce the sheet resistance, a tungsten nitride layer 19 is deposited on the polysilicon layer 18 by, for example, a sputtering method or a CVD method, and then a tungsten layer 20 is deposited. The thickness of the tungsten nitride layer 19 is preferably 3 to 10 nm, and the thickness of the tungsten layer 20 is preferably 30 to 100 nm. A conductive layer is formed by the polysilicon layer 18, the tungsten nitride layer 19, and the tungsten layer 20.
[0038]
The layer formed on the polysilicon layer 18 is not limited to the tungsten nitride layer or the tungsten layer, but may be another layer. For example, a silicide layer (WSi) of a refractory metal such as tungsten, molybdenum, titanium, tantalum (Ta), etc. ₂ , MoSi ₂ , TiSi ₂ , TaSi ₂ May be formed on the polysilicon layer 18 by a sputtering method or a CVD method.
[0039]
Next, a hard mask 21 is formed on the tungsten layer 20. As the hard mask 21, for example, silicon oxide or silicon nitride can be used, and can be formed by a low-pressure CVD method or a plasma CVD method. The thickness of the hard mask 21 is preferably 50 to 200 nm.
[0040]
Next, after patterning the hard mask 21 in the same manner as in the first embodiment, the hard mask 21 is processed into a tapered shape. Here, specifically, the tapered shape means that, as shown in FIG. 6, in the gap 23 between the gate electrode 22 and the gate electrode 22 ′, the opening dimension increases from the lower part of the cross section of the hard mask 21 to the upper part of the cross section. A shape that expands. In the drawing, the cross section of the hard mask 21 is processed so as to be substantially triangular, but the present invention is not limited to this. For example, the processing may be performed so that the cross section of the hard mask 21 is trapezoidal. The processing is performed by anisotropically etching the hard mask 21 using, for example, a CVD apparatus using high-density plasma as a plasma source. For example, the semiconductor device on which the tungsten nitride layer 19 and the tungsten layer 20 have been etched is placed in a deposition chamber (not shown) of a CVD apparatus. Next, after the inside of the film formation chamber is evacuated to a predetermined degree of vacuum, high-frequency AC bias power is applied to the SOI substrate 13 and an appropriate etching gas is introduced into the film formation chamber to perform etching. At this time, the taper angle θ ′ can be changed by controlling the plasma bias.
[0041]
By processing the hard mask 21 into a tapered shape, the opening diameter of the gap 23 can be changed, and the opening area can be increased. Therefore, the ion implantation angle θ at the time of halo implantation can be increased. For example, in the conventional example, the implantation angle is limited to 30 °. If the angle is more than 30 °, ions are shielded by the gate electrode. On the other hand, according to the present embodiment, the implantation angle is made larger than 30 °. It becomes possible.
[0042]
Next, using the hard mask 21, the polysilicon layer 18 and the gate insulating film 17 are etched by a dry etching method. Selective oxidation treatment for oxidizing only the polysilicon layer 18 and the single crystal silicon layer 16 of the SOI substrate 13 for the purpose of recovering from damage caused by etching, avoiding electrolytic concentration due to gate edge rounding, and avoiding channeling of source / drain implantation. To form an oxide film 24 (FIG. 6). In the figure, an oxide film formed on the single crystal silicon layer 16 is omitted.
[0043]
Next, using the gate electrodes 22, 22 'as a mask, extension implantation and halo implantation for a punch-through stopper are performed on the SOI substrate 13 to form source / drain regions. Specifically, for example, boron difluoride (BF ₂ ) Is ion-implanted from a direction perpendicular to the SOI substrate to form a p − type semiconductor region 25. Subsequently, phosphorus (P) is ion-implanted into the semiconductor substrate at a desired implantation angle θ to form an n + type halo implanted layer 26. The ion implantation method may be any of a step rotation implantation method and a continuous rotation implantation method.
[0044]
According to the present embodiment, the opening diameter of the gap 23 formed between the gate electrode 22 and the gate electrode 22 ′ is increased by processing the hard mask 21 into a tapered shape. On the other hand, ions incident from an oblique direction (A direction) are not blocked by the gate electrodes 22 and 22 '.
[0045]
In the present embodiment, the hard mask 21 is processed into a tapered shape before etching the polysilicon layer 18 and the gate insulating film 17, but the present invention is not limited to this. The hard mask 21 may be processed after the tungsten film 20, the tungsten nitride film 19, the polysilicon layer 18, and the gate insulating film 17 are etched by dry etching using the hard mask 21 as a mask.
[0046]
In the present embodiment, the hard mask is processed into a tapered shape to increase the ion implantation angle θ, but the present invention is not limited to this. For example, not only the hard mask 21 but also the tungsten layer 20 may be processed so that the whole thereof has a tapered shape. The whole of the hard mask 21, the tungsten layer 20 and the tungsten nitride layer 19 may be formed into a tapered shape. May be processed. Further, the hard mask 21 may be completely eliminated by performing the etching, and the tungsten layer 20 or the tungsten layer 20 and the tungsten nitride layer 19 may be processed to have a tapered shape. Further, by reducing the thickness of the gate electrodes 22 and 22 ', the whole of the tungsten film 20, the tungsten nitride film 19 and the polysilicon 18 may be processed to have a tapered shape. With such a shape, the ion implantation angle θ can be further increased.
[0047]
The taper angle θ ′ is preferably 7 to 85 °, and can be changed by controlling a plasma bias in a high-density plasma CVD apparatus during etching.
[0048]
Embodiment 3 FIG.
In this embodiment, a case where the present invention is applied to a damascene transistor will be described. The method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
[0049]
First, as shown in FIG. 7A, for example, a silicon substrate is used as the semiconductor substrate 27, and an oxide film 28 is formed thereon by a CVD method or the like. Next, a dummy gate layer 29 is formed on the oxide film 28. The dummy gate layer 29 can be formed using, for example, polysilicon, and can be deposited on the oxide film 28 using a low-pressure CVD furnace or the like.
[0050]
Next, after a resist film 30 is formed on the dummy gate layer 29, desired patterning is performed on the resist film 30 by a photolithography method to obtain a structure shown in FIG. Subsequently, using the resist film 30 as a mask, the dummy gate layer 29 is etched by dry etching to form a dummy gate pattern 31. Thereafter, the resist film 30 is removed by, for example, an ashing process using plasma (FIG. 7B).
[0051]
Next, as shown in FIG. 7C, the dummy gate pattern 31 is processed into a tapered shape. In the figure, the cross section of the dummy gate pattern 31 is processed to be trapezoidal, but may be triangular. The processing is performed by anisotropically etching the dummy gate pattern 31 using, for example, a CVD apparatus using high-density plasma as a plasma source. For example, the semiconductor device shown in FIG. 7B is placed in a film forming chamber (not shown) of a CVD device. Next, after the inside of the film forming chamber is evacuated to a predetermined degree of vacuum, high frequency AC bias power is applied to the semiconductor substrate 27, and an appropriate etching gas is introduced into the film forming chamber to perform etching. At this time, the taper angle θ ′ can be changed by controlling the plasma bias. The taper angle θ ′ is preferably 7 to 85 °.
[0052]
Next, using the dummy gate pattern 31 as a mask, extension implantation and halo implantation for a punch-through stopper are performed on the semiconductor substrate 27 to form source / drain regions to obtain the structure shown in FIG. More specifically, for example, boron difluoride is ion-implanted from a direction perpendicular to the semiconductor substrate 27 to form the p − type semiconductor region 32. Subsequently, while rotating the semiconductor substrate 27, phosphorus is ion-implanted into the semiconductor substrate 27 at a desired implantation angle θ to form an n + type halo implanted layer 33. The ion implantation method may be any of a step rotation implantation method and a continuous rotation implantation method. Since the dummy gate pattern 31 is processed into a tapered shape, it becomes possible to increase the ion implantation angle θ at the time of halo implantation, so that the light enters the semiconductor substrate 27 from an oblique direction (A direction). The ions are not shielded by the dummy gate pattern 31.
[0053]
Next, as shown in FIG. 8A, an interlayer insulating film 34 is formed on the gate insulating film 28 and the dummy gate pattern 31. As the interlayer insulating film 34, for example, a TEOS (Tetraethylorthosilicate) film, a BPSG (Borophosphosilicate glass) film, or the like can be used, and can be formed by a CVD method or the like.
[0054]
Next, the dummy gate pattern 31 is exposed on the surface of the interlayer insulating film 34 by flattening the interlayer insulating film 34 by a CMP (Chemical and Mechanical Polishing) method or the like (FIG. 8B), and then etched. The dummy gate pattern 31 is removed to form a groove 35 (FIG. 8C).
[0055]
Next, after removing the oxide film 28 exposed from the bottom 35a of the groove 35 by etching, the bottom surface 35a and the side surface 35b of the groove 35 and the gate insulating film 36 are formed so that the groove 35 is not filled. It is deposited on the interlayer insulating film 34 by a CVD method or the like. Subsequently, a gate electrode material 37 such as aluminum (Al) or tungsten is deposited by a CVD method or the like so as to fill the groove 35 (FIG. 9B). Thereafter, the gate electrode material 37 is polished by a CMP method or the like so as to have the same height as the gate insulating film 36 to form the gate electrode 38 (FIG. 9C).
[0056]
After removing the dummy gate pattern 31 by etching, as shown in FIG. 9A, the interlayer insulating film 34 is processed into a tapered shape so that the opening diameter increases from the lower part of the cross section to the upper part of the cross section. You may. The processing can be performed, for example, by anisotropic etching using a CVD apparatus using high-density plasma as a plasma source. By performing such processing, the gate electrode material 37 can be deposited so as to completely fill the groove 35, and defects such as generation of voids (voids) in the groove 35 can be eliminated.
[0057]
In the first to third embodiments, all the gate electrodes in the device are processed into a tapered shape. However, the present invention is not limited to this. According to the present invention, a gate electrode having a tapered shape and a gate electrode having no tapered shape can coexist in one device. FIG. 10 shows an example in which the gate electrodes 39 and 39 ′ obtained by processing a hard mask into a tapered shape and the gate electrodes 40 and 40 ′ that are not processed coexist. In the example shown, the gate electrodes 39, 39 'and the gate electrodes 40, 40' are electrically separated by a trench 41.
[0058]
【The invention's effect】
According to the present invention, by processing a gate electrode, a dummy gate pattern, or the like into a tapered shape, it becomes possible to increase the implantation angle of ions at the time of halo implantation, and the ions are obliquely incident on the semiconductor substrate. The problem that ions are blocked by the gate electrode and the dummy gate pattern can be solved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment.
FIG. 3 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 5 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device according to the second embodiment.
FIG. 7 is a diagram illustrating a method for manufacturing the semiconductor device according to the third embodiment.
FIG. 8 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment.
FIG. 9 is a diagram illustrating the method for manufacturing the semiconductor device according to the third embodiment.
FIG. 10 is a diagram illustrating a method of manufacturing another semiconductor device according to the present invention.
FIG. 11 is a diagram illustrating a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
1, 27, 42 semiconductor substrate, 2, 17, 36, 43 gate insulating film, 3, 18, 44 polysilicon layer, 4, 19, 45 tungsten nitride layer, 5, 20, 46 tungsten layer, 6, 21, 47 Hard mask, 7, 30, 48 resist film, 8, 22, 38, 39, 40, 49 gate electrode, 9, 23 gap, 10, 24, 28 oxide film, 11, 25, 32 p-type semiconductor region, 12 , 26, 33 n + type halo injection layer, 13 SOI substrate, 14 support substrate, 15 insulating layer, 16 single crystal silicon layer, 29 dummy gate layer, 31 dummy gate pattern, 34 interlayer insulating film, 35 groove, 37 gate electrode material , 41 trench.

Claims (8)

Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Processing the gate electrode into a tapered shape;
Implanting ions into the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the gate electrode processed into the taper shape as a mask. 2. The semiconductor device according to claim 1, wherein the gate electrode has a structure in which a polysilicon layer, a tungsten nitride layer, and a tungsten layer are stacked in this order, and at least one of these layers is tapered in order from the top. 3. Production method. Forming an insulating film on the semiconductor substrate;
Forming a conductive layer on the insulating film;
Forming a hard mask on the conductive layer;
Forming a gate electrode by etching the insulating film and the conductive layer using the hard mask;
Processing the hard mask into a tapered shape;
Implanting ions into the semiconductor substrate from obliquely above the semiconductor substrate using the gate electrode as a mask. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of processing the hard mask into a tapered shape further includes processing the conductive layer into a tapered shape. 5. The semiconductor device according to claim 4, wherein the conductive layer has a structure in which a polysilicon layer, a tungsten nitride layer, and a tungsten layer are stacked in this order, and at least one of these layers is tapered in order from the top. Production method. The method according to claim 1, wherein the semiconductor substrate is an SOI substrate. Forming an oxide film on the semiconductor substrate;
Forming a dummy gate pattern on the oxide film;
Processing the dummy gate pattern into a tapered shape;
Implanting ions into the semiconductor substrate from an obliquely upward direction of the semiconductor substrate using the tapered dummy gate pattern as a mask,
Forming an interlayer insulating film on the oxide film and the dummy gate pattern;
Removing the interlayer insulating film until the upper surface of the dummy gate pattern is exposed;
Forming a groove by selectively removing the dummy gate pattern;
Removing the oxide film exposed on the bottom surface of the groove;
Forming a gate insulating film on the bottom and side surfaces of the trench and on the interlayer insulating film;
Filling the groove with a gate electrode material. The method for manufacturing a semiconductor device according to claim 1, wherein the step of processing into a tapered shape is anisotropic etching using high-density plasma.

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