JP2003524225A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003524225A5 JP2003524225A5 JP2001526709A JP2001526709A JP2003524225A5 JP 2003524225 A5 JP2003524225 A5 JP 2003524225A5 JP 2001526709 A JP2001526709 A JP 2001526709A JP 2001526709 A JP2001526709 A JP 2001526709A JP 2003524225 A5 JP2003524225 A5 JP 2003524225A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/409,764 US6457146B1 (en) | 1999-09-30 | 1999-09-30 | Method and apparatus for processing errors in a computer system |
| US09/409,764 | 1999-09-30 | ||
| PCT/US2000/025845 WO2001024007A2 (en) | 1999-09-30 | 2000-09-20 | Method and apparatus for processing errors in a computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003524225A JP2003524225A (ja) | 2003-08-12 |
| JP2003524225A5 true JP2003524225A5 (enExample) | 2007-11-08 |
Family
ID=23621860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001526709A Pending JP2003524225A (ja) | 1999-09-30 | 2000-09-20 | コンピュータシステムのエラーを処理する方法及び装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6457146B1 (enExample) |
| EP (1) | EP1221229A2 (enExample) |
| JP (1) | JP2003524225A (enExample) |
| WO (1) | WO2001024007A2 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6751698B1 (en) * | 1999-09-29 | 2004-06-15 | Silicon Graphics, Inc. | Multiprocessor node controller circuit and method |
| US7539134B1 (en) * | 1999-11-16 | 2009-05-26 | Broadcom Corporation | High speed flow control methodology |
| US8024639B2 (en) | 2006-06-23 | 2011-09-20 | Schweitzer Engineering Laboratories, Inc. | Software and methods to detect and correct data structure |
| US20080155293A1 (en) * | 2006-09-29 | 2008-06-26 | Schweitzer Engineering Laboratories, Inc. | Apparatus, systems and methods for reliably detecting faults within a power distribution system |
| US20080080114A1 (en) * | 2006-09-29 | 2008-04-03 | Schweitzer Engineering Laboratories, Inc. | Apparatus, systems and methods for reliably detecting faults within a power distribution system |
| US7900093B2 (en) * | 2007-02-13 | 2011-03-01 | Siemens Aktiengesellschaft | Electronic data processing system and method for monitoring the functionality thereof |
| US8441768B2 (en) | 2010-09-08 | 2013-05-14 | Schweitzer Engineering Laboratories Inc | Systems and methods for independent self-monitoring |
| US9007731B2 (en) | 2012-03-26 | 2015-04-14 | Schweitzer Engineering Laboratories, Inc. | Leveraging inherent redundancy in a multifunction IED |
| CN108632142B (zh) * | 2018-03-28 | 2021-02-12 | 华为技术有限公司 | 节点控制器的路由管理方法和装置 |
| US11323362B2 (en) | 2020-08-07 | 2022-05-03 | Schweitzer Engineering Laboratories, Inc. | Resilience to single event upsets in software defined networks |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5121342A (en) | 1989-08-28 | 1992-06-09 | Network Communications Corporation | Apparatus for analyzing communication networks |
| US5414713A (en) | 1990-02-05 | 1995-05-09 | Synthesis Research, Inc. | Apparatus for testing digital electronic channels |
| JPH05241985A (ja) * | 1992-03-03 | 1993-09-21 | Mitsubishi Electric Corp | 入出力制御装置 |
| US5465250A (en) | 1993-06-24 | 1995-11-07 | National Semiconductor Corporation | Hybrid loopback for FDDI-II slave stations |
| US5446726A (en) * | 1993-10-20 | 1995-08-29 | Lsi Logic Corporation | Error detection and correction apparatus for an asynchronous transfer mode (ATM) network device |
| US5581705A (en) * | 1993-12-13 | 1996-12-03 | Cray Research, Inc. | Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system |
| JP3164996B2 (ja) * | 1995-03-15 | 2001-05-14 | 日本電気株式会社 | シリアルデータ受信装置 |
| JPH08272719A (ja) * | 1995-03-30 | 1996-10-18 | Mitsubishi Electric Corp | 通信インタフェース回路 |
| JP3936408B2 (ja) * | 1995-03-31 | 2007-06-27 | 富士通株式会社 | 情報処理方法及び情報処理装置 |
| US6012148A (en) * | 1997-01-29 | 2000-01-04 | Unisys Corporation | Programmable error detect/mask utilizing bus history stack |
| US20010042176A1 (en) * | 1997-09-05 | 2001-11-15 | Erik E. Hagersten | Skewed finite hashing function |
-
1999
- 1999-09-30 US US09/409,764 patent/US6457146B1/en not_active Expired - Lifetime
-
2000
- 2000-09-20 JP JP2001526709A patent/JP2003524225A/ja active Pending
- 2000-09-20 WO PCT/US2000/025845 patent/WO2001024007A2/en not_active Ceased
- 2000-09-20 EP EP00963680A patent/EP1221229A2/en not_active Withdrawn